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0e882def38
The cannonlake power state chipset code would fail to keep an accurate record of the chipset's power state. For example, the EC could claim that the AP was in G3, whereas the SLP_SUS_L signal was deasserted. This commit fixes a few issues with the chipset code. - First, don't have PP3300_DSW_EN enabled by default coming out of reset. The default chipset power state when the EC comes out of reset is G3, therefore we should not enable the PP33000 DSW rail until we decide to leave G3. This is usually triggered by a power button press. - Similarly, when we wish to enter G3, we should turn off the PP3300 DSW rail instead of the noop that was done before. - Lastly, turn on the 5V rail when entering S5 instead of S3 and turn it off when leaving S5 to G3. BUG=b:70184397,b:70244199 BRANCH=None TEST=Flash zoombini; Verify that AP boots to S0 and can shutdown to S5 and the EC tracks it. Verify that after the S5 inactivity timer, we fall to G3. Verify that SLP_SUS_L is asserted and DSWPWROK is low. Verify that we can still perform BC1.2 detection in G3. `reboot ap-off` and verify that the AP does indeed remain off and no port 80 codes are seen. TEST=Verify that 5V is off in G3, but can be turned on if needed. TEST=Verify that 5V is on in S5. TEST=With the exception of BC1.2, repeat the above tests for meowth. Change-Id: I444a8f29969ef6a68a83d1734912d239bad429a5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/813501 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>