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fa13ac76b1
- disable PP1800_PGOOD internal pullup - add PP3300_DSW_EN control on PF6, turned on in S5 and off in G3 - change PCH_WAKE_L and PCH_PWRBTN_L to open drain signals - add PCH_BL_EN interrupt on PM3 for rising edge to put backlight controller into PWM mode, remove 1 second hook - add samus-specific extpower handler for AC_PRESENT to buffer the AC_PRESENT input to the new PCH_ACOK output on PM6. this is driven high in S5/S3/S0 when AC_PRESENT is high, otherwise driven low. BUG=chrome-os-partner:23752 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: Ie8ab538610e41914212ee1f3a6287b63474fb85b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175281 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In the most general case, the flash layout looks something like this: +---------------------+ | Reserved for EC use | +---------------------+ +---------------------+ | Vblock B | +---------------------+ | RW firmware B | +---------------------+ +---------------------+ | Vblock A | +---------------------+ | RW firmware A | +---------------------+ +---------------------+ | FMAP | +---------------------+ | Public root key | +---------------------+ | Read-only firmware | +---------------------+ BIOS firmware (and kernel) put the vblock info at the start of each image where it's easy to find. The Blizzard EC expects the firmware vector table to come first, so we have to put the vblock at the end. This means we have to know where to look for it, but that's built into the FMAP and the RO firmware anyway, so that's not an issue. The RO firmware doesn't need a vblock of course, but it does need some reserved space for vboot-related things. Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If we reserve 4K at the top of each FW image, that should give us plenty of room for vboot-related stuff.