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qsdk-ssdk: update to ath11.5-cs

Browse Source 
Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
2022-05-12 14:30:21 +02:00
parent b35232ab4a
commit 93d93c7708
677 changed files with 206 additions and 534001 deletions
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112
feeds/ipq807x/qca-ssdk/Makefile
View File

@@ -3,11 +3,23 @@ include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=qca-ssdk
PKG_SOURCE_DATE:=2020-07-10
PKG_SOURCE_PROTO:=git
PKG_BRANCH:=master
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk
PKG_VERSION:=0d6d410637648b1bea0dede48d3fab791689cfce
PKG_MIRROR_HASH:=60a3f89c8d93eef1e21871a9ee9e0a4c8564a6499913695a17e3e481e80c8b63
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_VERSION:=$(PKG_VERSION)
subtarget:=$(SUBTARGET)
hal_arch:=$(subtarget)
include $(INCLUDE_DIR)/package.mk
define KernelPackage/qca-ssdk
define KernelPackage/qca-ssdk/default-nohnat
SECTION:=kernel
CATEGORY:=Kernel modules
SUBMENU:=Network Devices
@@ -17,13 +29,50 @@ define KernelPackage/qca-ssdk
PROVIDES:=qca-ssdk
endef
define KernelPackage/qca-ssdk
$(call KernelPackage/qca-ssdk/default-nohnat)
VARIANT:=nohnat
ifneq (, $(findstring $(hal_arch), "ipq50xx"))
ifeq (, $(CONFIG_LOWMEM_FLASH))
ifneq ($(LINUX_VERSION),$(filter 5.4%,$(LINUX_VERSION)))
DEPENDS+=kmod-ipt-filter +kmod-ppp
QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable
endif
endif
endif
endef
define KernelPackage/qca-ssdk/Description
This package contains a qca-ssdk driver for QCA chipset
endef
GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/')
define KernelPackage/qca-ssdk-hnat
$(call KernelPackage/qca-ssdk/default-nohnat)
DEPENDS:=@TARGET_ipq_ipq40xx||TARGET_ipq40xx||TARGET_ar71xx||TARGET_ipq806x +kmod-ipt-extra +kmod-ipt-filter +(TARGET_ipq806x||TARGET_ipq):kmod-qca-rfs +kmod-ppp
TITLE+= (hnat)
VARIANT:=hnat
endef
TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin
define KernelPackage/qca-ssdk-hnat/Description
This package contains a qca-ssdk-hnat driver for QCA chipset
endef
GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/')
ifeq ($(GCC_VERSION), 4.8)
GCC_VERSION=4.8.3
endif
ifdef CONFIG_TOOLCHAIN_BIN_PATH
TOOLCHAIN_BIN_PATH=$(CONFIG_TOOLCHAIN_BIN_PATH)
else
TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin
endif
ifdef CONFIG_TARGET_NAME
QCASSDK_CONFIG_OPTS+= \
TARGET_NAME=$(CONFIG_TARGET_NAME)
endif
QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \
SYS_PATH=$(LINUX_DIR) \
@@ -34,17 +83,45 @@ QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \
GCC_VERSION=$(GCC_VERSION) \
CFLAGS=-I$(STAGING_DIR)/usr/include
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable
ifeq ($(SUBTARGET),ipq807x))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE
else ifeq ($(SUBTARGET),ipq60xx))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE
ifeq ($(LOCAL_VARIANT),hnat)
QCASSDK_CONFIG_OPTS+= HNAT_FEATURE=enable
ifeq ($(CONFIG_TARGET_ar71xx),)
QCASSDK_CONFIG_OPTS+= RFS_FEATURE=enable
endif
endif
QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable
QCASSDK_CONFIG_OPTS+= HK_CHIP=enable
ifneq (, $(findstring $(hal_arch), "ipq95xx"))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=APPE
endif
ifneq (, $(findstring $(hal_arch), "ipq60xx" "ipq807x" "ipq95xx"))
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable
endif
ifneq (, $(findstring $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256 512)$(CONFIG_LOWMEM_FLASH))
QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable
ifneq (, $(findstring $(hal_arch), "ipq807x"))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE
else ifneq (, $(findstring $(hal_arch), "ipq60xx"))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE
else ifneq (, $(findstring $(hal_arch), "ipq50xx"))
QCASSDK_CONFIG_OPTS+= ISISC_ENABLE=enable
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=MP
ifeq (, $(CONFIG_LOWMEM_FLASH))
ifeq (, $(findstring $(CONFIG_KERNEL_IPQ_MEM_PROFILE), 256))
QCASSDK_CONFIG_OPTS+= MINI_SSDK=disable
endif
endif
endif
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable
endif
ifeq ($(CONFIG_TARGET_ipq806x_QSDK_Standard),)
QCASSDK_CONFIG_OPTS+= HK_CHIP=enable
endif
define Build/InstallDev
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk
@@ -66,6 +143,9 @@ define Build/InstallDev
if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \
fi
if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_netlink.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_netlink.h $(1)/usr/include/qca-ssdk/init/; \
fi
$(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk
$(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk
$(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk
@@ -82,4 +162,10 @@ define KernelPackage/qca-ssdk/install
$(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk
endef
define KernelPackage/qca-ssdk-hnat/install
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk
endef
$(eval $(call KernelPackage,qca-ssdk))
$(eval $(call KernelPackage,qca-ssdk-hnat))

94
feeds/ipq807x/qca-ssdk/Makefile.orig Executable file
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@@ -0,0 +1,94 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=qca-ssdk
PKG_SOURCE_PROTO:=git
PKG_BRANCH:=master
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk
PKG_VERSION:=0d6d410637648b1bea0dede48d3fab791689cfce
PKG_MIRROR_HASH:=60a3f89c8d93eef1e21871a9ee9e0a4c8564a6499913695a17e3e481e80c8b63
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
PKG_SOURCE_VERSION:=$(PKG_VERSION)
include $(INCLUDE_DIR)/package.mk
define KernelPackage/qca-ssdk
SECTION:=kernel
CATEGORY:=Kernel modules
SUBMENU:=Network Devices
TITLE:=Kernel driver for QCA SSDK
FILES:=$(PKG_BUILD_DIR)/build/bin/qca-ssdk.ko
AUTOLOAD:=$(call AutoLoad,30,qca-ssdk)
PROVIDES:=qca-ssdk
endef
define KernelPackage/qca-ssdk/Description
This package contains a qca-ssdk driver for QCA chipset
endef
GCC_VERSION=$(shell echo "$(CONFIG_GCC_VERSION)" | sed 's/[^0-9.]*\([0-9.]*\).*/\1/')
TOOLCHAIN_BIN_PATH=$(TOOLCHAIN_DIR)/bin
QCASSDK_CONFIG_OPTS+= TOOL_PATH=$(TOOLCHAIN_BIN_PATH) \
SYS_PATH=$(LINUX_DIR) \
TOOLPREFIX=$(TARGET_CROSS) \
KVER=$(LINUX_VERSION) \
ARCH=$(LINUX_KARCH) \
TARGET_SUFFIX=$(CONFIG_TARGET_SUFFIX) \
GCC_VERSION=$(GCC_VERSION) \
CFLAGS=-I$(STAGING_DIR)/usr/include
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=enable
ifeq ($(SUBTARGET),ipq807x))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=HPPE
else ifeq ($(SUBTARGET),ipq60xx))
QCASSDK_CONFIG_OPTS+= CHIP_TYPE=CPPE
endif
QCASSDK_CONFIG_OPTS+= MINI_SSDK=enable
QCASSDK_CONFIG_OPTS+= PTP_FEATURE=disable
QCASSDK_CONFIG_OPTS+= HK_CHIP=enable
define Build/InstallDev
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/api
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/ref
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/fal
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/sal
$(INSTALL_DIR) $(1)/usr/include/qca-ssdk/init
$(CP) -rf $(PKG_BUILD_DIR)/include/api/sw_ioctl.h $(1)/usr/include/qca-ssdk/api
if [ -f $(PKG_BUILD_DIR)/include/ref/ref_vsi.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_vsi.h $(1)/usr/include/qca-ssdk/ref/; \
fi
if [ -f $(PKG_BUILD_DIR)/include/ref/ref_fdb.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_fdb.h $(1)/usr/include/qca-ssdk/ref/; \
fi
if [ -f $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/ref/ref_port_ctrl.h $(1)/usr/include/qca-ssdk/ref/; \
fi
if [ -f $(PKG_BUILD_DIR)/include/init/ssdk_init.h ]; then \
$(CP) -rf $(PKG_BUILD_DIR)/include/init/ssdk_init.h $(1)/usr/include/qca-ssdk/init/; \
fi
$(CP) -rf $(PKG_BUILD_DIR)/include/fal $(1)/usr/include/qca-ssdk
$(CP) -rf $(PKG_BUILD_DIR)/include/common/*.h $(1)/usr/include/qca-ssdk
$(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/linux/*.h $(1)/usr/include/qca-ssdk
$(CP) -rf $(PKG_BUILD_DIR)/include/sal/os/*.h $(1)/usr/include/qca-ssdk
endef
define Build/Compile
$(MAKE) -C $(PKG_BUILD_DIR) $(strip $(QCASSDK_CONFIG_OPTS))
endef
define KernelPackage/qca-ssdk/install
$(INSTALL_DIR) $(1)/etc/init.d
$(INSTALL_BIN) ./files/qca-ssdk $(1)/etc/init.d/qca-ssdk
endef
$(eval $(call KernelPackage,qca-ssdk))

26
feeds/ipq807x/qca-ssdk/patches/100-aq.patch
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@@ -1,8 +1,8 @@
Index: qca-ssdk/include/hsl/phy/hsl_phy.h
Index: qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/include/hsl/phy/hsl_phy.h
===================================================================
--- qca-ssdk.orig/include/hsl/phy/hsl_phy.h
+++ qca-ssdk/include/hsl/phy/hsl_phy.h
@@ -562,6 +562,7 @@ typedef struct {
--- qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce.orig/include/hsl/phy/hsl_phy.h
+++ qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/include/hsl/phy/hsl_phy.h
@@ -567,6 +567,7 @@ typedef struct {
#define QCA8033_PHY 0x004DD074
#define QCA8035_PHY 0x004DD072
/*qca808x_start*/
@@ -10,7 +10,7 @@ Index: qca-ssdk/include/hsl/phy/hsl_phy.h
#define QCA8081_PHY_V1_1 0x004DD101
#define INVALID_PHY_ID 0xFFFFFFFF
@@ -576,11 +577,14 @@ typedef struct {
@@ -581,12 +582,14 @@ typedef struct {
#define AQUANTIA_PHY_109 0x03a1b502
#define AQUANTIA_PHY_111 0x03a1b610
#define AQUANTIA_PHY_111B0 0x03a1b612
@@ -18,18 +18,18 @@ Index: qca-ssdk/include/hsl/phy/hsl_phy.h
#define AQUANTIA_PHY_112 0x03a1b660
#define AQUANTIA_PHY_113C_A0 0x31c31C10
#define AQUANTIA_PHY_113C_A1 0x31c31C11
#define AQUANTIA_PHY_113C_B0 0x31c31C12
#define AQUANTIA_PHY_113C_B1 0x31c31C13
#define AQUANTIA_PHY_112C 0x03a1b792
+#define AQUANTIA_PHY_114C 0x31c31C22
+
#define PHY_805XV2 0x004DD082
#define PHY_805XV1 0x004DD081
/*qca808x_start*/
Index: qca-ssdk/src/hsl/phy/hsl_phy.c
Index: qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/src/hsl/phy/hsl_phy.c
===================================================================
--- qca-ssdk.orig/src/hsl/phy/hsl_phy.c
+++ qca-ssdk/src/hsl/phy/hsl_phy.c
@@ -231,6 +231,8 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
--- qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce.orig/src/hsl/phy/hsl_phy.c
+++ qca-ssdk-0d6d410637648b1bea0dede48d3fab791689cfce/src/hsl/phy/hsl_phy.c
@@ -244,6 +244,8 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
case AQUANTIA_PHY_108:
case AQUANTIA_PHY_109:
case AQUANTIA_PHY_111:
@@ -38,7 +38,7 @@ Index: qca-ssdk/src/hsl/phy/hsl_phy.c
case AQUANTIA_PHY_111B0:
case AQUANTIA_PHY_112:
case AQUANTIA_PHY_113C_A0:
@@ -250,6 +252,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
@@ -265,6 +267,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
phytype = MPGE_PHY_CHIP;
break;
/*qca808x_start*/

129
feeds/ipq807x/qca-ssdk/src/ChangeLog
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@@ -1,129 +0,0 @@
============================================================
Changes for SSDK 1.0.3:
============================================================
* Support HORUS:
- Add chip type HORUS and related source code.
============================================================
Changes for SSDK 1.0.4:
============================================================
* Support ISIS:
- Add chip type ISIS and related source code.
============================================================
Changes for SSDK 1.0.5:
============================================================
* Speed up FDB entry next operation.
* Support linux 2.6.31 version.
============================================================
Changes for SSDK 1.0.6:
============================================================
* New APIs pppoe_session_id_set/get are supported for ISIS chip.
* Fix parameter speed check bug in API isis_port_speed_set.
============================================================
Changes for SSDK 1.0.7:
============================================================
* Fix address bytes order bug in API _isis_ip6_base_addr_set/get.
* Change the socket call for user space and kernel communication to nonblocking way.
* Remove force routing function for ISIS acl action.
* Add configuration for ISIS register accessing speed up feature in ./config file.
* Add configuration for ISIS NAT helper feature in ./config.file.
============================================================
Changes for SSDK 1.0.8:
============================================================
* Offer ioctl based method for linux kernel&user space communication
* Remove some port property logic limitation for ISIS.
* Remove FDB CRC mode setting in ISIS init.
* Add some operation mode flag for ISIS NAPT entry next operation.
* Add some operation mode flag for ISIS NAPT del opertion.
* Fix one bug for fdb entry extendnext command parsing when shell works at slient mode.
* Fix one bug in ISIS ACL rule delete operation(isis_acl_rule_delete).
* Fix one bug in ISIS queue shapper get operation(isis_rate_queue_shaper_get).
* Add new API for ISIS MAC based VLAN translation.(isis_port_mac_vlan_xlt_set/isis_port_mac_vlan_xlt_get).
* Add new API for ISIS add/delete port to/from an exist FDB entry.(isis_fdb_port_add/isis_fdb_port_del).
* Add new API for ISIS ACL rules active/deactive. (isis_acl_rule_active/isis_acl_rule_deactive).
* Add new API for ISIS wcmp hash mode setting. (isis_ip_wcmp_hash_mode_set/isis_ip_wcmp_hash_mode_get).
* Add new API for ISIS host entry aging time setting. (isis_ip_age_time_set/isis_ip_age_time_get).
* Add new API for ISIS interrupt operation. (isis_intr_mask_set/isis_intr_mask_get/isis_intr_status_get/
isis_intr_status_clear/isis_intr_port_link_mask_set/isis_intr_port_link_mask_get/isis_intr_port_link_status_get).
* Add new API for ISIS port MAC mode setting. (isis_interface_mac_mode_set/isis_interface_mac_mode_get).
* Add new API for ISIS port PHY mode setting. (isis_interface_phy_mode_set/isis_interface_phy_mode_get).
* Add new API for ISIS 802.3az setting. (isis_port_3az_status_set/isis_port_3az_status_get).
* Add new API for ISIS link status getting. (isis_port_link_status_get).
* Add new API for ISIS MAC TX status setting. (isis_port_txmac_status_set/isis_port_txmac_status_get).
* Add new API for ISIS MAC RX status setting. (isis_port_rxmac_status_set/isis_port_rxmac_status_get).
* Add new API for ISIS MAC TX flow control setting. (isis_port_txfc_status_set/isis_port_txfc_status_get).
* Add new API for ISIS MAC RX flow control setting. (isis_port_rxfc_status_set/isis_port_rxfc_status_get).
* Add new API for ISIS MAC back pressure setting. (isis_port_bp_status_set/isis_port_bp_status_get).
* Add new API for ISIS link force mode setting. (isis_port_link_forcemode_set/isis_port_link_forcemode_get).
* Fix one bug in Giga PHY device autoneg ability setting operation.
* Makefile change for ISIS NAT helper refactoring.
============================================================
Changes for SSDK 1.1.x:
============================================================
* Add support for QCA833x family (ISISC, S17c).
* Add support for out-of-band register access through ethernet packets with Atheros header. (S17/S17c)
* Add IPV6 Hardware Routing (ISISC, S17c).
* Add new API for set/get status of one ACL rule source filter. (S17c only)
* Add new API for set/get arl search mode as ivl or svl when vlan invalid. (S17c only)
* Add new API for interface control:
fal_interface_fx100_ctrl_set/fal_interface_fx100_ctrl_get/fal_interface_fx100_status_get/fal_interface_fx100_status_set/fal_interface_mac06_exch_get/fal_interface_mac06_exch_set. (S17c only)
* Add new API for MIB counter:
fal_mib_port_flush_counters/fal_mib_cpukeep_set/fal_mib_cpukeep_get. (S17c only)
*Add new API for Misc:
fal_intr_mask_mac_linkchg_set/fal_intr_mask_mac_linkchg_get/fal_intr_status_mac_linkchg_get/fal_cpu_vid_en_set/fal_cpu_vid_en_get/fal_rtd_pppoe_en_set/fal_rtd_pppoe_en_get/fal_intr_status_mac_linkchg_clear (S17c only)
* Add new API for nat: nat_prv_base_mask_set/nat_prv_base_mask_get. (S17c only)
* Add new API for port ctrl:
fal_port_mac_loopback_set/fal_port_mac_loopback_set. (S17c only)
* Add new API for port vlan:
fal_netisolate_set/fal_netisolate_get/fal_eg_trans_filter_bypass_en_set/fal_eg_trans_filter_bypass_en_get. (S17c only)
* Add new API for QoS:
fal_qos_port_force_spri_status_set/fal_qos_port_force_spri_status_get/fal_qos_port_force_cpri_status_set/fal_qos_port_force_cpri_status_get. (S17c only)
* Add new API for Rate limit:
fal_rate_port_add_rate_byte_set/fal_rate_port_add_rate_byte_get/fal_rate_port_gol_flow_en_set/fal_rate_port_gol_flow_en_get.
============================================================
Changes for SSDK 1.1.1:
============================================================
* Add IGMP mldv2 support
============================================================
Changes for SSDK 1.1.2:
============================================================
* Add API for Trunk support
* Add API for MAC loopback support
============================================================
Changes for SSDK 1.1.3:
============================================================
* Support CHIP_TYPE=ALL_CHIP
============================================================
Changes for SSDK 1.1.3.2:
============================================================
* Add hsl_shared_api.h (sync from Perforce server)
* Add support for Linux Kernel 3.2.0
* Add support for LITTLE ENDIAN (especially for HNAT)
* Add support for ARM CPU

52
feeds/ipq807x/qca-ssdk/src/Makefile
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@@ -1,52 +0,0 @@
include ./config
ifndef PRJ_PATH
PRJ_PATH=$(shell pwd)
endif
export PRJ_PATH
include ./make/config.mk
include ./make/tools.mk
include ./make/$(OS)_opt.mk
SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile)))
SUB_LIB=$(subst src/, , $(SUB_DIR))
all: $(BIN_DIR) kslib
mkdir -p ./temp/;cd ./temp;cp ../build/bin/ssdk_ks_km.a ./;ar -x ssdk_ks_km.a; cp ../ko_Makefile ./Makefile;
make -C $(SYS_PATH) M=$(PRJ_PATH)/temp/ CROSS_COMPILE=$(TOOLPREFIX) modules
cp $(PRJ_PATH)/temp/Module.symvers $(PRJ_PATH)/Module.symvers;
cp temp/*.ko build/bin;
rm -Rf ./temp/*.o ./temp/*.ko ./temp/*.a
@echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished."
kslib:kslib_o
$(AR) -r $(BIN_DIR)/$(KS_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/KSLIB/*.o)
kslib_o:
$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=KSLIB -C src/$i all || exit 1;)
uslib:uslib_o
$(AR) -r $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o)
uslib_o:
$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=USLIB -C src/$i all || exit 1;)
shell:uslib shell_o
$(CP) $(BLD_DIR)/SHELL/$(SHELLOBJ) $(BIN_DIR)/$(SHELLOBJ)
$(STRIP) $(BIN_DIR)/$(SHELLOBJ)
shell_o:
$(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=SHELL -C src/$i all || exit 1;)
$(BIN_DIR):
$(MKDIR) -p $@
release:
@cd make; ./release.sh $(VER)
clean:
$(RM) -f $(BLD_DIR)/KSLIB/*
$(RM) -f $(BLD_DIR)/USLIB/*
$(RM) -f $(BLD_DIR)/SHELL/*
$(RM) -f $(BIN_DIR)/*

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feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/host_helper.c
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feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.c
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22
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_dt.h
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@@ -1,22 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NAT_HELPER_DT_H
#define _NAT_HELPER_DT_H
extern void host_check_aging(void);
void napt_ct_counter_decrease(void);
#endif /*_NAT_HELPER_DT_H*/

879
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.c
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/*
* Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef KVER32
#include <linux/kconfig.h>
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/if_arp.h>
#include <linux/netdevice.h>
#include <linux/netfilter_arp.h>
#include <linux/netfilter_ipv4/ip_tables.h>
#include <net/netfilter/nf_conntrack.h>
#include "fal_nat.h"
#include "fal_ip.h"
#include "hsl_api.h"
#include "hsl.h"
#include "hsl_shared_api.h"
#include "../nat_helper.h"
#include "nat_helper_dt.h"
#include "nat_helper_hsl.h"
#include "../napt_acl.h"
int nat_chip_ver = 0;
a_bool_t napt_add_bypass_check = A_TRUE;
/* support 4 different interfaces (or 4 VLANs) */
static fal_intf_mac_entry_t global_if_mac_entry[MAX_INTF_NUM] = {{0}};
static a_uint8_t if_mac_count = 0;
extern int setup_wan_if;
extern int setup_lan_if;
#define DESS_CHIP(ver) ((((ver)&0xffff)>>8) == NAT_CHIP_VER_DESS)
#define ARP_HW_COUNTER_OFFSET 8
static a_uint8_t
nat_hw_debug_counter_get(void)
{
static a_uint32_t nat_debug_counter = 0;
return ((nat_debug_counter++) & 0x7);
}
static a_uint8_t
arp_hw_debug_counter_get(void)
{
static a_uint32_t ip_debug_counter = 0;
return ((ip_debug_counter++) & 0x7) + ARP_HW_COUNTER_OFFSET;
}
a_int32_t
nat_hw_add(nat_entry_t *nat)
{
fal_nat_entry_t hw_nat = {0};
hw_nat.flags = nat->flags;
hw_nat.src_addr = nat->src_addr;
hw_nat.trans_addr = nat->trans_addr;
hw_nat.port_num = nat->port_num;
hw_nat.port_range = nat->port_range;
hw_nat.counter_en = 1;
hw_nat.counter_id = nat_hw_debug_counter_get();
if(NAT_ADD(0, &hw_nat) != 0)
{
return -1;
}
nat->entry_id = hw_nat.entry_id;
return 0;
}
a_int32_t
nat_hw_del_by_index(a_uint32_t index)
{
fal_nat_entry_t nat_entry = {0};
HNAT_PRINTK("NAT_DEL(1) index=%d########\n", index);
nat_entry.entry_id = index;
if(NAT_DEL(0, FAL_NAT_ENTRY_ID_EN, &nat_entry)!= 0)
{
return -1;
}
return 0;
}
a_int32_t
nat_hw_flush(void)
{
if(NAT_DEL(0, 0, 0)!= 0)
{
return -1;
}
return 0;
}
a_int32_t
napt_hw_flush(void)
{
if(NAPT_DEL(0, 0, 0)!= 0)
{
return -1;
}
return 0;
}
static a_uint32_t private_ip_can_update = 1;
a_int32_t
nat_hw_prv_base_can_update(void)
{
return private_ip_can_update;
}
void
nat_hw_prv_base_update_enable(void)
{
private_ip_can_update = 1;
}
void
nat_hw_prv_base_update_disable(void)
{
private_ip_can_update = 0;
}
static a_uint32_t private_ip_base = 0xc0a80000;
static a_uint32_t private_net_mask = 0xffffff00;
a_int32_t
nat_hw_prv_base_set(a_uint32_t ip)
{
#define PRIVATE_IP_MASK 0xffffff00
ip = ntohl(ip);
if (((nat_chip_ver & 0xffff) >> 8) == NAT_CHIP_VER_8327)
private_ip_base = ip & PRIVATE_IP_MASK;
else
private_ip_base = ip & nat_hw_prv_mask_get();
if(DESS_CHIP(nat_chip_ver)) {
if (IP_PRV_BASE_ADDR_SET(0, 0, (fal_ip4_addr_t)ip) != 0)
{
return -1;
}
} else {
if (NAT_PRV_BASE_ADDR_SET(0, (fal_ip4_addr_t)ip) != 0)
{
return -1;
}
}
HNAT_PRINTK("%s: private_ip_base:%x private_ip_can_update:%d\n",
__func__, private_ip_base, private_ip_can_update);
return 0;
}
a_uint32_t
nat_hw_prv_base_get(void)
{
return private_ip_base;
}
a_int32_t
nat_hw_prv_mask_set(a_uint32_t ipmask)
{
ipmask = ntohl(ipmask);
if(DESS_CHIP(nat_chip_ver)) {
if (IP_PRV_BASE_MASK_SET(0, 0, (fal_ip4_addr_t)ipmask) != 0)
{
return -1;
}
} else if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8337) {
if (NAT_PRV_BASE_MASK_SET(0, (fal_ip4_addr_t)ipmask) != 0)
{
return -1;
}
}
private_net_mask = ipmask;
HNAT_PRINTK("%s: 0x%08x\n", __FUNCTION__, private_net_mask);
return 0;
}
a_uint32_t
nat_hw_prv_mask_get(void)
{
return private_net_mask;
}
a_int32_t
nat_hw_prv_base_is_match(a_uint32_t ip)
{
#define PRIVATE_IP_MASK 0xffffff00
a_uint32_t prv_base = private_ip_base;
a_uint32_t prv_mask;
if (((nat_chip_ver & 0xffff)>>8) == NAT_CHIP_VER_8327) {
if((prv_base & PRIVATE_IP_MASK) == (ip & PRIVATE_IP_MASK))
return 1;
} else {
prv_mask = nat_hw_prv_mask_get();
if((prv_base & prv_mask) == (ip & prv_mask))
return 1;
}
HNAT_PRINTK("%s: private_ip_base:%x usaddr:%x mismatch\n",
__func__, prv_base, ip);
return 0;
}
static a_int32_t
_arp_hw_if_mac_add(fal_intf_mac_entry_t *if_mac_entry)
{
return IP_INTF_ENTRY_ADD(0, if_mac_entry);
}
static a_int32_t
_arp_hw_if_mac_del(fal_intf_mac_entry_t *if_mac_entry)
{
return IP_INTF_ENTRY_DEL(0, FAL_IP_ENTRY_ID_EN, if_mac_entry);
}
a_int32_t
if_mac_cleanup(void)
{
a_uint8_t i = 0;
if_mac_count = 0;
for(i = 0; i < MAX_INTF_NUM; i++)
{
if(_arp_hw_if_mac_del(&global_if_mac_entry[i]) != 0) {
printk("mac del fail!\n");
return -1;
}
memset(&global_if_mac_entry[i], 0, sizeof(fal_intf_mac_entry_t));
}
setup_wan_if = 0;
setup_lan_if = 0;
return 0;
}
#define MACADDR_LEN 6
a_int32_t
if_mac_add(a_uint8_t *mac, a_uint32_t vid, uint32_t ipv6)
{
a_uint8_t i = 0;
a_uint8_t zero_mac[MACADDR_LEN] = {0};
if (!memcmp(mac, zero_mac, MACADDR_LEN))
return 0;
if(if_mac_count > MAX_INTF_NUM)
return -1;
for(i = 0; i < if_mac_count; i++)
{
if((!memcmp(global_if_mac_entry[i].mac_addr.uc, mac, 6)) &&
(global_if_mac_entry[i].vid_low == vid))
{
HNAT_PRINTK("%s: mac exist id:%d\n", __func__,
global_if_mac_entry[i].entry_id);
return 0;
}
}
if(if_mac_count == MAX_INTF_NUM)
{
HNAT_ERR_PRINTK("%s: reach mac count max\n", __func__);
return -1;
}
memset(&global_if_mac_entry[if_mac_count], 0, sizeof(fal_intf_mac_entry_t));
memcpy(global_if_mac_entry[if_mac_count].mac_addr.uc, mac, 6);
global_if_mac_entry[if_mac_count].entry_id = if_mac_count;
if (1 == ipv6)
{
global_if_mac_entry[if_mac_count].ip6_route = 1;
}
else
{
global_if_mac_entry[if_mac_count].ip6_route = 0;
}
global_if_mac_entry[if_mac_count].ip4_route = 1;
if (vid == 0)
{
global_if_mac_entry[if_mac_count].vid_low = 0;
global_if_mac_entry[if_mac_count].vid_high = 511;
}
else
{
global_if_mac_entry[if_mac_count].vid_low = vid;
global_if_mac_entry[if_mac_count].vid_high = vid;
}
if(_arp_hw_if_mac_add(&global_if_mac_entry[if_mac_count])!= 0)
{
return -1;
}
HNAT_PRINTK("%s: count:%d index:%d vid:%d mac:%02x-%02x-%02x-%02x-%02x-%02x\n",
__func__, if_mac_count, global_if_mac_entry[if_mac_count].entry_id, vid,
mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]);
if_mac_count ++;
return 0;
}
static a_int32_t
_arp_hw_add(fal_host_entry_t *arp_entry)
{
return IP_HOST_ADD(0, arp_entry);
}
a_int32_t
arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry)
{
fal_host_entry_t arp_entry;
#ifdef ISIS /* Only for AR8337(S17) */
if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type)
{
memset(&arp_entry,0,sizeof(arp_entry));
memcpy(&arp_entry.ip4_addr, ip, 4);
memcpy(arp_entry.mac_addr.uc, mac, 6);
arp_entry.status = ARP_AGE_NEVER;
if (port == S17_WAN_PORT)
{
arp_entry.port_id = port;
}
else
{
arp_entry.port_id = 6; /* always assigned to MAC 6 */
}
arp_entry.flags = FAL_IP_IP4_ADDR;
}
else
#endif /* not ISIS */
{
memset(&arp_entry,0,sizeof(arp_entry));
if (0 == is_ipv6_entry)
{
memcpy(&arp_entry.ip4_addr, ip, 4);
arp_entry.ip4_addr = ntohl(arp_entry.ip4_addr);
arp_entry.flags = FAL_IP_IP4_ADDR;
}
else
{
memcpy(&arp_entry.ip6_addr, ip, 16);
arp_entry.flags = FAL_IP_IP6_ADDR;
}
memcpy(arp_entry.mac_addr.uc, mac, 6);
if ((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && \
(S17_WAN_PORT == port))
{
arp_entry.status = ARP_AGE_NEVER;
}
else
{
arp_entry.status = ARP_AGE;
}
arp_entry.port_id = port;
}
arp_entry.intf_id = intf_id;
arp_entry.counter_en = 1;
if (S17_WAN_PORT == port)
{
arp_entry.counter_id = 0xf;
}
else
{
arp_entry.counter_id = arp_hw_debug_counter_get();
}
if (IP_HOST_GET(0, 0x10, &arp_entry)) {
HNAT_PRINTK("new arp for 0x%x\n", arp_entry.ip4_addr);
if(_arp_hw_add(&arp_entry) != 0)
{
HNAT_ERR_PRINTK("%s: fail\n", __func__);
return -1;
}
}
if (0 == is_ipv6_entry)
{
HNAT_PRINTK("%s: index:%x port:%d ip:%d.%d.%d.%d\n",
__func__, arp_entry.entry_id, port,
*(ip), *(ip+1), *(ip+2), *(ip+3));
}
if (0 != (arp_entry.entry_id & 0xFFFFFC00))
{
printk("Warning: arp_entry id should be only 10 bits!\n");
}
return arp_entry.entry_id;
}
#define AOS_HEADER_MAGIC 0xC0DE
a_int32_t
arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid)
{
aos_header_t *athr_header = NULL;
if((data==0) || (sport==0) || (vid==0))
{
return -1;
}
athr_header = (aos_header_t *)data;
#if 0
/*atheros header magic check*/
if(athr_header->magic != AOS_HEADER_MAGIC)
{
return -1;
}
#endif
*sport = athr_header->sport;
*vid = athr_header->vid;
return 0;
}
#define MAX_PUBLIC_IP_CNT 16
struct public_ip_shadow
{
a_uint32_t ip;
a_uint32_t use_cnt;
};
static struct public_ip_shadow public_ip_shadow[MAX_PUBLIC_IP_CNT]= {{0}};
static a_uint32_t public_ip_cnt = 0;
a_int32_t
nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index)
{
sw_error_t rv;
a_uint32_t hw_index;
a_uint32_t i;
fal_nat_pub_addr_t ip_entry;
for(i=0; i<MAX_PUBLIC_IP_CNT; i++)
{
if((ip == public_ip_shadow[i].ip) && (public_ip_shadow[i].use_cnt))
{
public_ip_shadow[i].use_cnt++;
*index = i;
return 0;
}
}
if(public_ip_cnt >= MAX_PUBLIC_IP_CNT)
{
return -1;
}
memset(&ip_entry, 0, sizeof(ip_entry));
ip_entry.pub_addr = ip;
rv = NAT_PUB_ADDR_ADD(0,&ip_entry);
if(rv != 0)
{
return -1;
}
public_ip_cnt++;
hw_index = ip_entry.entry_id;
public_ip_shadow[hw_index].ip = ip;
public_ip_shadow[hw_index].use_cnt++;
*index = hw_index;
HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
__func__, public_ip_cnt, hw_index, public_ip_shadow[hw_index].ip);
return 0;
}
void
napt_hw_mode_init(void)
{
sw_error_t rv;
/* age_speedup+age_thres_1/4+age_step_4+age_timer_28s*1+
stop_age_when1+overwrite_disable */
/* Also set NAT mode Port strict mode/symmetric mode */
a_uint32_t entry = 0x15F01CB;
HSL_REG_ENTRY_SET(rv, 0, NAT_CTRL, 0, (a_uint8_t *) (&entry),
sizeof (a_uint32_t));
HSL_REG_ENTRY_GET(rv, 0, ROUTER_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
/*set locktime 100us*/
SW_SET_REG_BY_FIELD(ROUTER_CTRL, GLB_LOCKTIME, 1, entry);
SW_SET_REG_BY_FIELD(ROUTER_CTRL, ARP_AGE_MODE, 1, entry);
HSL_REG_ENTRY_SET(rv, 0, ROUTER_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
HSL_REG_ENTRY_GET(rv, 0, MOD_ENABLE, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(MOD_ENABLE, L3_EN, 1, entry);
HSL_REG_ENTRY_SET(rv, 0, MOD_ENABLE, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
ACL_STATUS_SET(0, A_TRUE);
}
void
napt_hw_mode_cleanup(void)
{
a_uint32_t entry;
sw_error_t rv;
if (!DESS_CHIP(nat_chip_ver)) {
IP_ROUTE_STATUS_SET(0, A_FALSE);
entry = 0;
} else {
HSL_REG_ENTRY_GET(rv, 0, NAT_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_SET_REG_BY_FIELD(NAT_CTRL, NAT_EN, 0, entry);
}
HSL_REG_ENTRY_SET(rv, 0, NAT_CTRL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
ACL_STATUS_SET(0, A_FALSE);
}
a_int32_t
nat_hw_pub_ip_del(a_uint32_t index)
{
sw_error_t rv;
if(public_ip_shadow[index].use_cnt>0)
{
public_ip_shadow[index].use_cnt--;
if(public_ip_shadow[index].use_cnt == 0)
{
fal_nat_pub_addr_t ip_entry;
HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
__func__, public_ip_cnt, index, public_ip_shadow[index].ip);
memset(&ip_entry,0,sizeof(ip_entry));
ip_entry.pub_addr = public_ip_shadow[index].ip;
rv = NAT_PUB_ADDR_DEL(0, 1, &ip_entry);
if(rv != 0)
{
return -1;
}
public_ip_cnt--;
}
return 0;
}
return -1;
}
#define napt_entry_cp(to, from) \
{ \
(to)->entry_id = (from)->entry_id; \
(to)->status = (from)->status; \
(to)->flags = (from)->flags; \
(to)->src_addr = (from)->src_addr; \
(to)->src_port = (from)->src_port; \
(to)->dst_addr = (from)->dst_addr; \
(to)->dst_port = (from)->dst_port; \
(to)->trans_addr = (from)->trans_addr; \
(to)->trans_port = (from)->trans_port; \
(to)->ingress_packet = (from)->ingress_packet; \
(to)->ingress_byte = (from)->ingress_byte; \
(to)->egress_packet = (from)->egress_packet; \
(to)->egress_byte = (from)->egress_byte; \
}
a_int32_t
napt_hw_add(napt_entry_t *napt)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
fal_host_entry_t host_entry = {0};
a_uint32_t next_hop = 0;
napt_entry_cp(&fal_napt, napt);
fal_napt.flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
fal_napt.counter_en = 1;
fal_napt.counter_id = nat_hw_debug_counter_get();
fal_napt.action = FAL_MAC_FRWRD;
if (!napt_add_bypass_check) {
/*check arp entry*/
host_entry.flags = FAL_IP_IP4_ADDR;
host_entry.ip4_addr = fal_napt.src_addr;
ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry);
if (ret) {
HNAT_ERR_PRINTK("can not find src host entry!\n");
return ret;
}
if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) {
next_hop = get_next_hop(fal_napt.dst_addr, fal_napt.src_addr);
host_entry.ip4_addr = next_hop ? next_hop : fal_napt.dst_addr;
ret = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &host_entry);
if (ret) {
HNAT_ERR_PRINTK("can not find dst host entry!\n");
return ret;
}
}
}
ret = NAPT_ADD(0, &fal_napt);
napt->entry_id = fal_napt.entry_id;
return ret;
}
a_int32_t
napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
napt_entry_cp(&fal_napt, napt);
ret = NAPT_GET(0, 0, &fal_napt);
if(!ret)
*entry = fal_napt;
return ret;
}
a_int32_t
napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
fal_napt.flags = napt->flags | 0x10;
fal_napt.status = 0xf;
fal_napt.dst_addr = napt->dst_addr;
fal_napt.dst_port = napt->dst_port;
fal_napt.trans_addr = napt->trans_addr;
fal_napt.trans_port = napt->trans_port;
fal_napt.src_port = napt->src_port;
fal_napt.action = FAL_MAC_RDT_TO_CPU;
fal_napt.flow_cookie = cookie;
ret = NAPT_ADD(0, &fal_napt);
return ret;
}
a_int32_t
napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
fal_napt.flags = napt->flags | 0x10;
fal_napt.status = 0xf;
fal_napt.dst_addr = napt->dst_addr;
fal_napt.dst_port = napt->dst_port;
fal_napt.src_addr = napt->src_addr;
fal_napt.src_port = napt->src_port;
fal_napt.trans_port = napt->trans_port;
fal_napt.action = FAL_MAC_RDT_TO_CPU;
fal_napt.flow_cookie = cookie;
ret = NAPT_ADD(0, &fal_napt);
return ret;
}
a_int32_t
napt_hw_del(napt_entry_t *napt)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
napt_entry_cp(&fal_napt, napt);
napt_ct_counter_decrease();
ret = NAPT_DEL(0, FAL_NAT_ENTRY_KEY_EN, &fal_napt);
if(ret != 0)
{
return -1;
}
else
{
return 0;
}
}
a_int32_t
napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
fal_napt.status = age;
if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
{
ret = -1;
}
napt_entry_cp(napt, &fal_napt);
return ret;
}
a_int32_t
napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age)
{
a_int32_t ret = 0;
fal_napt_entry_t fal_napt = {0};
fal_napt.entry_id = napt->entry_id;
fal_napt.status = age;
if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
{
ret = -1;
}
napt_entry_cp(napt, &fal_napt);
return ret;
}
a_int32_t
napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index)
{
fal_napt_entry_t fal_napt = {0};
sw_error_t rv;
if(hw_index == 0)
{
fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
}
else
{
fal_napt.entry_id = hw_index - 1;
}
if((rv = NAPT_NEXT(0, 0, &fal_napt)) != 0)
{
HNAT_ERR_PRINTK("<napt_hw_get_by_index>[rv:%d] error hw:%x sw:%x\n",
rv, napt->entry_id, hw_index);
return -1;
}
napt_entry_cp(napt, &fal_napt);
if(napt->entry_id != hw_index)
{
HNAT_ERR_PRINTK("<napt_hw_get_by_index>hw_index error hw:%x sw:%x\n",
napt->entry_id, hw_index);
return -1;
}
return 0;
}
a_int32_t napt_hw_get_by_sip(a_uint32_t sip)
{
fal_napt_entry_t napt;
memset(&napt, 0, sizeof(fal_napt_entry_t));
napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
napt.src_addr = sip;
if (fal_napt_next(0, FAL_NAT_ENTRY_SOURCE_IP_EN, &napt) == SW_OK) {
return 0;
}
return -1;
}
a_uint32_t
napt_hw_used_count_get(void)
{
#define NAPT_USED_COUNT
#define NAPT_USED_COUNT_OFFSET 0x0e44 /*was:0x0e38*/
#define NAPT_USED_COUNT_E_LENGTH 11
#define NAPT_USED_COUNT_E_OFFSET 0x0
#define NAPT_USED_COUNT_NR_E 1
sw_error_t rv;
a_uint32_t count = 0;
HSL_REG_ENTRY_GET(rv, 0, NAPT_USED_COUNT, 0, (a_uint8_t *) (&count),
sizeof (a_uint32_t));
return count;
}
sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable)
{
sw_error_t rv;
a_uint32_t val;
if (A_TRUE == enable)
{
val = 1;
}
else if (A_FALSE == enable)
{
val = 0;
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
return rv;
}
sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable)
{
sw_error_t rv;
a_uint32_t val;
HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (val)
{
*enable = A_TRUE;
}
else
{
*enable = A_FALSE;
}
return SW_OK;
}
sw_error_t napt_helper_hsl_init()
{
return SW_OK;
}

257
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/lib/nat_helper_hsl.h
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@@ -1,257 +0,0 @@
/*
* Copyright (c) 2012, 2015, 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NAT_HELPER_HSL_H
#define _NAT_HELPER_HSL_H
#ifdef KVER32
#include <linux/kconfig.h>
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/if_ether.h>
#include "fal_nat.h"
#define NAT_HW_NUM 32
#define NAT_HW_PORT_RANGE_MAX 255
#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1
#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2
#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4
#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8
#define FAL_NAT_ENTRY_PORT_CHECK 0x20
#define MAX_INTF_NUM 4
/* WAN connection types */
#define NF_S17_WAN_TYPE_IP 0 /* DHCP, static IP connection */
#define NF_S17_WAN_TYPE_PPPOE 1 /* PPPoE connection */
#define NF_S17_WAN_TYPE_GRE 2 /* GRE connections, ex: PPTP */
#define NF_S17_WAN_TYPE_PPPOEV6 3 /* IPv6 PPPoE connection using the same session as IPv4 connection */
#define NF_S17_WAN_TYPE_PPPOES0 4 /* PPPoE connection but not yet connected */
/* define the H/W Age mode for NAPT entries */
#define ARP_AGE_NEVER 7
#define ARP_AGE 6
#if !defined (HSL_STANDALONG)
/*NAT API*/
#define NAPT_ADD fal_napt_add
#define NAPT_GET fal_napt_get
#define NAT_PUB_ADDR_ADD fal_nat_pub_addr_add
#define NAPT_NEXT fal_napt_next
#define NAT_PRV_BASE_ADDR_SET fal_nat_prv_base_addr_set
#define NAT_PRV_BASE_MASK_SET fal_nat_prv_base_mask_set
#define NAPT_DEL fal_napt_del
#define NAT_DEL fal_nat_del
#define NAT_PUB_ADDR_DEL fal_nat_pub_addr_del
#define NAT_ADD fal_nat_add
#define NAT_PRV_ADDR_MODE_GET fal_nat_prv_addr_mode_get
/*IP API*/
#define IP_INTF_ENTRY_ADD fal_ip_intf_entry_add
#define IP_HOST_ADD fal_ip_host_add
#define IP_HOST_DEL fal_ip_host_del
#define IP_HOST_GET fal_ip_host_get
#define IP_HOST_NEXT fal_ip_host_next
#define IP_INTF_ENTRY_DEL fal_ip_intf_entry_del
#define IP_HOST_PPPOE_BIND fal_ip_host_pppoe_bind
#define IP_ROUTE_STATUS_SET fal_ip_route_status_set
#define IP_HOST_ROUTE_ADD fal_ip_host_route_set
#define IP_PRV_BASE_ADDR_SET fal_ip_vrf_base_addr_set
#define IP_PRV_BASE_MASK_SET fal_ip_vrf_base_mask_set
/* PPPOE */
#define PPPOE_STATUS_GET fal_pppoe_status_get
#define PPPOE_STATUS_SET fal_pppoe_status_set
#define PPPOE_SESSION_ID_SET fal_pppoe_session_id_set
#define PPPOE_SESSION_TABLE_ADD fal_pppoe_session_table_add
#define PPPOE_SESSION_TABLE_DEL fal_pppoe_session_table_del
#define RTD_PPPOE_EN_SET fal_rtd_pppoe_en_set
/*MISC API*/
#define MISC_ARP_CMD_SET fal_arp_cmd_set
#define CPU_VID_EN_SET fal_cpu_vid_en_set
#define PORT_ARP_ACK_STATUS_SET fal_port_arp_ack_status_set
#define CPU_PORT_STATUS_SET fal_cpu_port_status_set
/*ACL API*/
#define ACL_RULE_ADD fal_acl_rule_add
#define ACL_RULE_DEL fal_acl_rule_delete
#define ACL_LIST_CREATE fal_acl_list_creat
#define ACL_LIST_DESTROY fal_acl_list_destroy
#define ACL_LIST_BIND fal_acl_list_bind
#define ACL_LIST_UNBIND fal_acl_list_unbind
#define ACL_STATUS_GET fal_acl_status_get
#define ACL_STATUS_SET fal_acl_status_set
#define ACL_PORT_UDF_PROFILE_SET fal_acl_port_udf_profile_set
/*VLAN API */
#define VLAN_NEXT fal_vlan_next
/* PORTVLAN API */
#define PORTVLAN_ROUTE_DEFV_SET(dev_id, port_id)
#define NETISOLATE_SET fal_netisolate_set
/* PORT_CTRL API */
#define HEADER_TYPE_SET fal_header_type_set
#define PORT_TXHDR_MODE_SET fal_port_txhdr_mode_set
/* REG ACCESS API */
#define REG_GET fal_reg_get
#endif
extern int nf_athrs17_hnat;
extern int nf_athrs17_hnat_wan_type;
extern int nf_athrs17_hnat_ppp_id;
extern int nf_athrs17_hnat_udp_thresh;
extern a_uint32_t nf_athrs17_hnat_wan_ip;
extern a_uint32_t nf_athrs17_hnat_ppp_peer_ip;
extern unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN];
extern unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN];
extern int nf_athrs17_hnat_sync_counter_en;
extern int nf_athrs17_hnat_ppp_id2;
extern unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN];
enum {
NAT_CHIP_VER_8327 = 0x12,
NAT_CHIP_VER_8337 = 0x13,
NAT_CHIP_VER_DESS = 0x14,
};
typedef struct
{
a_uint32_t entry_id;
a_uint32_t flags;
a_uint32_t src_addr;
a_uint32_t trans_addr;
a_uint16_t port_num;
a_uint16_t port_range;
} nat_entry_t;
typedef struct
{
a_uint32_t entry_id;
a_uint32_t flags;
a_uint32_t status;
a_uint32_t src_addr;
a_uint32_t dst_addr;
a_uint16_t src_port;
a_uint16_t dst_port;
a_uint32_t trans_addr;
a_uint16_t trans_port;
a_uint32_t ingress_packet;
a_uint32_t ingress_byte;
a_uint32_t egress_packet;
a_uint32_t egress_byte;
} napt_entry_t;
#if defined (__BIG_ENDIAN)
typedef struct
{
a_uint16_t ver:2;
a_uint16_t pri:3;
a_uint16_t type:5;
a_uint16_t rev:2;
a_uint16_t with_tag:1;
a_uint16_t sport:3;
a_uint16_t vid;
a_uint16_t magic;
} aos_header_t;
#elif defined (__LITTLE_ENDIAN)
typedef struct
{
a_uint16_t vid;
a_uint16_t sport:3;
a_uint16_t with_tag:1;
a_uint16_t rev:2;
a_uint16_t type:5;
a_uint16_t pri:3;
a_uint16_t ver:2;
} aos_header_t;
#else
#error "no ENDIAN"
#endif
a_int32_t
nat_hw_add(nat_entry_t *nat);
a_int32_t
nat_hw_del_by_index(a_uint32_t index);
a_int32_t
nat_hw_flush(void);
a_int32_t
napt_hw_flush(void);
a_int32_t
nat_hw_prv_base_can_update(void);
void
nat_hw_prv_base_update_enable(void);
void
nat_hw_prv_base_update_disable(void);
a_int32_t
nat_hw_prv_base_set(a_uint32_t ip);
a_uint32_t
nat_hw_prv_base_get(void);
a_int32_t
nat_hw_prv_mask_set(a_uint32_t ipmask);
a_uint32_t
nat_hw_prv_mask_get(void);
a_int32_t
nat_hw_prv_base_is_match(a_uint32_t ip);
a_int32_t
if_mac_add(uint8_t *mac, uint32_t vid, uint32_t ipv6);
a_int32_t
if_mac_cleanup(void);
a_int32_t
arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry);
a_int32_t
arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid);
a_int32_t
nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index);
void
napt_hw_mode_init(void);
void
napt_hw_mode_cleanup(void);
a_int32_t
nat_hw_pub_ip_del(a_uint32_t index);
a_int32_t
napt_hw_add(napt_entry_t *napt_entry);
a_int32_t
napt_hw_get(napt_entry_t *napt, fal_napt_entry_t *entry);
a_int32_t
napt_hw_dnat_cookie_add(napt_entry_t *napt, a_uint32_t cookie);
a_int32_t
napt_hw_snat_cookie_add(napt_entry_t *napt, a_uint32_t cookie);
a_int32_t
napt_hw_del(napt_entry_t *napt_entry);
a_int32_t
napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age);
a_int32_t
napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age);
a_int32_t
napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index);
a_int32_t napt_hw_get_by_sip(a_uint32_t sip);
a_uint32_t
napt_hw_used_count_get(void);
sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t napt_helper_hsl_init(void);
#endif /*_NAT_HELPER_HSL_H*/

1622
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_acl.c
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94
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_acl.h
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@@ -1,94 +0,0 @@
/*
* Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "fal_nat.h"
#include "fal_ip.h"
#include "hsl_api.h"
#include "hsl.h"
#if defined(DESS)
#include "dess_acl.h"
#include "dess_reg.h"
#elif defined(ISISC)
#include "isisc_acl.h"
#include "isisc_reg.h"
#else
#include "isis_acl.h"
#include "isis_reg.h"
#endif
#define MAX_PPPOE_PASSTHROUGH_NUM 4
/* ACL list priority */
#define S17_ACL_LIST_PRIO_HIGH 0
#define S17_ACL_LIST_PRIO_MID 1
#define S17_ACL_LIST_PRIO_LOW 2
#define S17_ACL_LIST_PRIO_LOWEST 3
#define S17_ACL_LIST_IPCONF 0
#define S17_ACL_LIST_UDP0 1
#define S17_ACL_LIST_DROUTE 2
#define S17_ACL_LIST_PPPOE 3
#define S17_ACL_LIST_IPV6MLD 5
#define S17_ACL_LIST_IPV6_SOLICITED_NODE 7
#define S17_ACL_LIST_IPV6_NODEINFO_QUERY 9
#define S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP 11
#define S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP 13
#define S17_ACL_LIST_UPNP_SSDP 15
#define S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN 17
#define S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN 19
#define S17_ACL_LIST_PLC_FILTER 22
#define S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN 26
#define S17_ACL_ICMP_FROM_WAN 27
#define S17_ACL_LIST_IPV6DROUTE 28
#define S17_ACL_LIST_DSCP_REMAP 29
/* port # of WAN, 1 for DB120 demo board */
//#define S17_WAN_PORT 5
#define S17_CPU_PORT 0
#define S17_CPU_PORT_W 6
#define S17_LAN_PORT0 1
#define S17_LAN_PORT1 2
#define S17_LAN_PORT2 3
#define S17_LAN_PORT3 4
#define S17_LAN_PORT4 5
uint32_t get_aclrulemask(void);
void set_aclrulemask(uint32_t acl_list);
void droute_add_acl_rules(uint32_t local_ip, uint32_t local_ip_mask, uint32_t gw_entry_id);
void droute_del_acl_rules(void);
void ipv6_droute_del_acl_rules(void);
void ipv6_droute_add_acl_rules(struct in6_addr *local_ip, uint32_t gw_entry_id);
void pppoe_add_acl_rules(
uint32_t wan_ip, uint32_t local_ip,
uint32_t local_ip_mask, uint32_t gw_entry_id);
void pppoe_del_acl_rules(void);
void ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id);
void ipv6_snooping_solicted_node_add_acl_rules(void);
void ipv6_snooping_nodeinfo_query_add_acl_rules(void);
void ipv6_snooping_sextuple0_group_add_acl_rules(void);
void ipv6_snooping_quintruple0_1_group_add_acl_rules ( void );
void ip_conflict_del_acl_rules(void);
void upnp_ssdp_add_acl_rules(void);
unsigned int isis_set_pppoe_passthrough(int enable);
unsigned int isis_enable_pppoe_discovery_acl(void);
int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac);

406
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_helper.c
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@@ -1,406 +0,0 @@
/*
* Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef KVER32
#include <linux/kconfig.h>
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/kthread.h>
#include <linux/udp.h>
#include <linux/rculist_nulls.h>
#ifdef KVER32
#include <linux/rcupdate.h>
#endif
#include <linux/if_arp.h>
#include <linux/if_vlan.h>
#include <linux/inetdevice.h>
#include <linux/string.h>
#include <net/netfilter/nf_conntrack_acct.h>
#include <net/netfilter/nf_conntrack_helper.h>
#include <net/netfilter/nf_conntrack.h>
#include "nat_helper.h"
#include "napt_acl.h"
#include "lib/nat_helper_hsl.h"
extern struct net init_net;
static struct task_struct *ct_task;
/*#undef HNAT_PRINTK
#define HNAT_PRINTK(x...) aos_printk(x)*/
#ifdef KVER32
extern void __rcu_read_lock(void);
extern void __rcu_read_unlock(void);
extern unsigned int nf_conntrack_htable_size;
#endif
a_bool_t napt_aging_ctrl_en = 0;
void
napt_ct_aging_disable(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
return;
if(!ct_addr)
{
return;
}
ct = (struct nf_conn *)ct_addr;
if (timer_pending(&ct->timeout))
{
del_timer(&ct->timeout);
}
}
int
napt_ct_aging_is_enable(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
if(!ct_addr)
{
return 0;
}
if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
return 0;
ct = (struct nf_conn *)ct_addr;
return timer_pending(&(((struct nf_conn *)ct)->timeout));
}
void
napt_ct_aging_enable(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
uint16_t l3num = 0;
uint8_t protonum = 0;
if(nf_athrs17_hnat_sync_counter_en || !napt_aging_ctrl_en)
return;
if(!ct_addr)
{
return;
}
if(napt_ct_aging_is_enable(ct_addr))
{
return;
}
ct = (struct nf_conn *)ct_addr;
l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
ct->timeout.expires = jiffies+10*HZ;
if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
{
if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
{
ct->timeout.expires = jiffies+(5*24*60*60*HZ);
}
}
HNAT_PRINTK("<aging> ct:[%x] add timeout again\n", ct_addr);
add_timer(&ct->timeout);
}
void
napt_ct_to_hw_entry(uint32_t ct_addr, napt_entry_t *napt)
{
struct nf_conn *ct = NULL;
struct nf_conntrack_tuple *org_tuple, *rep_tuple;
uint8_t protonum = 0;
if(!ct_addr)
{
return;
}
#define NAPT_AGE 0xe
ct = (struct nf_conn *)ct_addr;
if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat
{
org_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
}
else //dnat
{
org_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
}
protonum = org_tuple->dst.protonum;
if(org_tuple->src.l3num == AF_INET)
{
if(protonum == IPPROTO_TCP)
{
napt->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
}
else if(protonum == IPPROTO_UDP)
{
napt->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
}
}
napt->src_addr = ntohl(org_tuple->src.u3.ip);
napt->src_port = ntohs(org_tuple->src.u.all);
napt->dst_addr = ntohl(org_tuple->dst.u3.ip);
napt->dst_port = ntohs(org_tuple->dst.u.all);
napt->trans_addr = ntohl(rep_tuple->dst.u3.ip);
napt->trans_port = ntohs(rep_tuple->dst.u.all);
napt->status = NAPT_AGE;
return;
}
uint64_t
napt_ct_pkts_get(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
struct nf_conn_counter *cct = NULL;
if(!ct_addr)
{
return 0;
}
ct = (struct nf_conn *)ct_addr;
cct = (struct nf_conn_counter *)nf_conn_acct_find(ct);
if(cct)
{
return (atomic64_read(&cct[IP_CT_DIR_ORIGINAL].packets) +
atomic64_read(&cct[IP_CT_DIR_REPLY].packets));
}
else
{
return 0;
}
}
int
napt_ct_type_is_nat(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
if(!ct_addr)
{
return 0;
}
ct = (struct nf_conn *)ct_addr;
return ((IPS_NAT_MASK & (ct)->status)?1:0);
}
int
napt_ct_type_is_nat_alg(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
if(!ct_addr)
{
return 0;
}
ct = (struct nf_conn *)ct_addr;
return ((nfct_help(ct))?1:0);
}
int
napt_ct_intf_is_expected(uint32_t ct_addr)
{
struct nf_conn *ct = (struct nf_conn *)ct_addr;
struct nf_conntrack_tuple *rep_tuple;
uint32_t dst_ip;
struct net_device *dev = NULL;
if(!ct_addr)
{
return 0;
}
if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT)
rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
else
rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
dst_ip = rep_tuple->dst.u3.ip;
dev = ip_dev_find(&init_net, dst_ip);
if(dev) {
if(dev->type == ARPHRD_ETHER) {
if(strstr(dev->name, "eth0") || strstr(dev->name, "erouter0") ||
strstr(dev->name, "br-wan")) {
dev_put(dev);
return 1;
}
} else if (dev->type == ARPHRD_PPP) {
dev_put(dev);
return 1;
}
dev_put(dev);
}
return 0;
}
int
napt_ct_status_is_estab(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
uint16_t l3num = 0;
uint8_t protonum = 0;
if(!ct_addr)
{
return 0;
}
ct = (struct nf_conn *)ct_addr;
l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
{
if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
{
return 1;
}
}
else if ((l3num == AF_INET) && (protonum == IPPROTO_UDP))
{
return 1;
}
return 0;
}
uint32_t
napt_ct_priv_ip_get(uint32_t ct_addr)
{
struct nf_conn *ct = NULL;
uint32_t usaddr = 0;
if(!ct_addr)
{
return 0;
}
ct = (struct nf_conn *)ct_addr;
if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat
{
usaddr = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip;
}
else
{
usaddr = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip;
}
usaddr = ntohl(usaddr);
return usaddr;
}
void
napt_ct_list_lock(void)
{
rcu_read_lock();
}
void
napt_ct_list_unlock(void)
{
rcu_read_unlock();
}
uint32_t
napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate)
{
struct net *net = &init_net;
struct nf_conntrack_tuple_hash *h = NULL;
struct nf_conn *ct = NULL;
struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate);
while(*hash < nf_conntrack_htable_size)
{
if(pos == 0)
{
/*get head for list*/
pos = rcu_dereference((&net->ct.hash[*hash])->first);
}
hlist_nulls_for_each_entry_from(h, pos, hnnode)
{
(*iterate) = (uint32_t)(pos->next);
ct = nf_ct_tuplehash_to_ctrack(h);
return (uint32_t) ct;
}
++(*hash);
pos = 0;
}
*hash = 0;
return 0;
}
int
napt_ct_task_should_stop(void)
{
return kthread_should_stop();
}
void
napt_ct_task_start(int (*task)(void*), const char *task_name)
{
ct_task = kthread_create(task, NULL, task_name);
if(IS_ERR(ct_task))
{
aos_printk("thread: %s create fail\n", task_name);
return;
}
wake_up_process(ct_task);
HNAT_PRINTK("thread: %s create success pid:%d\n",
task_name, ct_task->pid);
}
void
napt_ct_task_stop(void)
{
if(ct_task)
{
kthread_stop(ct_task);
}
}
void
napt_ct_task_sleep(int secs)
{
msleep_interruptible(secs*1000);
}

91
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_helper.h
View File

@@ -1,91 +0,0 @@
/*
* Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NAPT_HELPER_H
#define _NAPT_HELPER_H
#define USING_LINUX2631 1
#ifdef USING_LINUX2631
void
napt_ct_task_start(int (*task)(void*), const char *task_name);
void
napt_ct_task_stop(void);
int
napt_ct_task_should_stop(void);
void
napt_ct_task_sleep(int secs);
void
napt_ct_list_lock(void);
void
napt_ct_list_unlock(void);
uint32_t
napt_ct_list_iterate(uint32_t *hash, uint32_t *pos) ;
void
napt_ct_to_hw_entry(uint32_t ct_addr, void *napt);
void
napt_ct_aging_enable(uint32_t ct_addr);
void
napt_ct_aging_disable(uint32_t ct_addr);
int
napt_ct_aging_is_enable(uint32_t ct_addr);
uint64_t
napt_ct_pkts_get(uint32_t ct_addr);
int
napt_ct_type_is_nat(uint32_t ct_addr);
int
napt_ct_type_is_nat_alg(uint32_t ct_addr);
int
napt_ct_status_is_estab(uint32_t ct_addr);
uint32_t
napt_ct_priv_ip_get(uint32_t ct_addr);
int
napt_ct_intf_is_expected(uint32_t ct_addr);
#define NAPT_CT_TASK_START napt_ct_task_start
#define NAPT_CT_TASK_STOP napt_ct_task_stop
#define NAPT_CT_TASK_SHOULD_STOP napt_ct_task_should_stop
#define NAPT_CT_TASK_SLEEP napt_ct_task_sleep
#define NAPT_CT_LIST_LOCK napt_ct_list_lock
#define NAPT_CT_LIST_UNLOCK napt_ct_list_unlock
#define NAPT_CT_LIST_ITERATE napt_ct_list_iterate
#define NAPT_CT_AGING_IS_ENABLE napt_ct_aging_is_enable
#define NAPT_CT_AGING_ENABLE napt_ct_aging_enable
#define NAPT_CT_AGING_DISABLE napt_ct_aging_disable
#define NAPT_CT_TYPE_IS_NAT napt_ct_type_is_nat
#define NAPT_CT_STATUS_IS_ESTAB napt_ct_status_is_estab
#define NAPT_CT_PRIV_IP_GET napt_ct_priv_ip_get
#define NAPT_CT_PKTS_GET napt_ct_pkts_get
#define NAPT_CT_TO_HW_ENTRY napt_ct_to_hw_entry
#define NAPT_CT_TYPE_IS_NAT_ALG napt_ct_type_is_nat_alg
#define NAPT_CT_INTF_EXPECTED napt_ct_intf_is_expected
#else
#endif
#endif

1316
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/napt_procfs.c
View File

File diff suppressed because it is too large Load Diff

69
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.c
View File

@@ -1,69 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef KVER32
#include <linux/kconfig.h>
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/string.h>
#include "nat_helper.h"
char hnat_log_en = HNAT_LOG_LEVEL_DISABLE;
char hnat_log_buffer[NAT_LOG_MAX_SIZE];
void hnat_log_msg(int level, char *string, ...)
{
va_list ptr;
if(level < hnat_log_en)
return;
memset(hnat_log_buffer, 0, sizeof(hnat_log_buffer));
va_start(ptr,string);
vsnprintf(hnat_log_buffer,sizeof(hnat_log_buffer), string, ptr);
va_end(ptr);
aos_printk("%s\n", hnat_log_buffer);
}
sw_error_t
nat_helper_init(uint32_t dev_id, uint32_t portbmp)
{
nat_helper_bg_task_init();
host_helper_init(portbmp);
napt_helper_init();
nat_ipt_helper_init();
aos_printk("Hello, nat helper module for 1.1!\n");
return SW_OK;
}
sw_error_t
nat_helper_cleanup(uint32_t dev_id)
{
host_helper_exit();
napt_helper_exit();
nat_ipt_helper_exit();
nat_helper_bg_task_exit();
aos_printk("Goodbye, nat helper module!\n");
return SW_OK;
}

54
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_helper.h
View File

@@ -1,54 +0,0 @@
/*
* Copyright (c) 2012, 2015, 2017, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NAT_HELPER_H
#define _NAT_HELPER_H
#include "sw.h"
#define NAPT_TABLE_SIZE 1024
#define S17_WAN_PORT nat_helper_wan_port_get()
void host_helper_init(a_uint32_t portbmp);
void host_helper_exit(void);
void napt_helper_init(void);
void napt_helper_exit(void);
void nat_ipt_helper_init(void);
void nat_ipt_helper_exit(void);
void nat_helper_bg_task_init(void);
void nat_helper_bg_task_exit(void);
a_uint32_t nat_helper_wan_port_get(void);
uint32_t get_next_hop(uint32_t daddr, uint32_t saddr);
void hnat_log_msg(int level, char *string, ...);
#define NAT_LOG_MAX_SIZE 1024
enum {
HNAT_LOG_LEVEL_DEBUG = 0,
HNAT_LOG_LEVEL_INFO,
HNAT_LOG_LEVEL_ERR,
HNAT_LOG_LEVEL_DISABLE
};
#define HNAT_PRINTK(arg...) \
hnat_log_msg(HNAT_LOG_LEVEL_DEBUG, arg)
#define HNAT_INFO_PRINTK(arg...) \
hnat_log_msg(HNAT_LOG_LEVEL_INFO, arg)
#define HNAT_ERR_PRINTK(arg...) \
hnat_log_msg(HNAT_LOG_LEVEL_ERR, arg)
#endif

761
feeds/ipq807x/qca-ssdk/src/app/nathelper/linux/nat_ipt_helper.c
View File

@@ -1,761 +0,0 @@
/*
* Copyright (c) 2012, 2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifdef KVER32
#include <linux/kconfig.h>
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#include <linux/netfilter_ipv4/ip_tables.h>
#include <net/netfilter/nf_nat.h>
#include <linux/netfilter/nf_nat.h>
#include <linux/netfilter/xt_multiport.h>
#include <linux/netfilter/xt_tcpudp.h>
#include <linux/netfilter/x_tables.h>
#include "nat_helper.h"
#include "lib/nat_helper_hsl.h"
#include "lib/nat_helper_dt.h"
#define nf_nat_ipv4_multi_range_compat \
nf_nat_ipv4_multi_range_compat
#define nf_nat_range nf_nat_ipv4_range
#define ipt_entry_target xt_entry_target
#define ipt_entry_match xt_entry_match
#define IPT_MATCH_ITERATE(e, fun, args...) \
({ \
unsigned int i; \
int ret = 0; \
struct xt_entry_match *m; \
\
for (i = sizeof(struct ipt_entry); \
i < (e)->target_offset; \
i += m->u.match_size) { \
m = (void *)e + i; \
ret = fun(m , ##args); \
if (ret != 0) \
break; \
} \
ret; \
})
#define IPT_ENTRY_ITERATE(entries, size, fun, args...) \
({ \
unsigned int k, j; \
int ret = 0; \
struct ipt_entry *e; \
\
for (k = 0, j = 0; k < (size); \
k += (e)->next_offset, j++) { \
e = (void *)(entries) + k; \
if (j < 0) \
continue; \
\
ret = fun(e , ##args); \
if (ret != 0) \
break; \
} \
ret; \
})
#define IPT_BUFFER_INIT_LEN 1000
#define NF_NAT_INIT_ENTRIES_NUM 5
static int
nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len);
static int
nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len);
int nat_sockopts_init = 0;
/*those initial value will be overwrited by orignal iptables sockopts*/
static struct nf_sockopt_ops orgi_ipt_sockopts;
static struct nf_sockopt_ops tmp_ipt_sockopts =
{
/*pls check linux/in.h*/
#define IPT_TEMP_BASE_CTL 60
#define IPT_TEMP_SET_MAX (IPT_TEMP_BASE_CTL+1)
#define IPT_TEMP_GET_MAX (IPT_TEMP_BASE_CTL+2)
.pf = PF_INET,
.set_optmin = IPT_TEMP_BASE_CTL,
.set_optmax = IPT_TEMP_SET_MAX,
.set = nat_ipt_set_ctl,
.get_optmin = IPT_TEMP_BASE_CTL,
.get_optmax = IPT_TEMP_GET_MAX,
.get = nat_ipt_get_ctl
};
static struct nf_sockopt_ops *ipt_sockopts = NULL;
static uint32_t snat_seq = 0;
static uint32_t hw_nat_ipt_seq[NAT_HW_NUM] = {0};
static uint32_t hw_nat_pip_idx[NAT_HW_NUM] = {0};
static uint8_t *gbuffer, *sbuffer;
static unsigned int glen, slen;
static struct ipt_replace old_replace;
static void
nat_ipt_del(struct ipt_replace ireplace)
{
int i, j;
struct ipt_entry *gentry = NULL;
struct ipt_entry *sentry = NULL;
struct xt_entry_target *gtarget = NULL;
struct xt_entry_target *starget = NULL;
struct nf_nat_ipv4_multi_range_compat *grange = NULL;
struct nf_nat_ipv4_multi_range_compat *srange = NULL;
uint8_t *gptr, *sptr;
unsigned int oldnum = ireplace.num_counters;
unsigned int seq = 1;
gptr = gbuffer;
sptr = sbuffer;
HNAT_PRINTK("into nat_ipt_del\n");
for (i = oldnum; i >= 0; i--)//NF_NAT_INIT_ENTRIES_NUM; i--)
{
gentry = (struct ipt_entry *)gptr;
sentry = (struct ipt_entry *)sptr;
gtarget = (struct xt_entry_target *)((uint8_t *) gentry + gentry->target_offset);
starget = (struct xt_entry_target *)((uint8_t *) sentry + sentry->target_offset);
grange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) gtarget + sizeof (*gtarget));
srange = (struct nf_nat_ipv4_multi_range_compat *)((uint8_t *) starget + sizeof (*starget));
HNAT_PRINTK("(%d)isis_nat_del name %s:%s#####(%x:%x %x)###\n",
i, gtarget->u.user.name, starget->u.user.name,
gentry->ip.src.s_addr, gentry->ip.dst.s_addr,
grange->range[0].min.all);
if (strcmp(gtarget->u.user.name, starget->u.user.name))
{
/*if (!strcmp(gtarget->u.user.name, "DNAT")) {
if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
|| grange->range[0].min.all)
return;
goto delete;
} else */
if (!strcmp(gtarget->u.user.name, "SNAT"))
{
if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
|| grange->range[0].min.all)
return;
goto delete;
}
return;
} /*else if (!strcmp(gtarget->u.user.name, "DNAT")) {
if (memcmp(gentry, sentry, gentry->next_offset)) {
if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
|| grange->range[0].min.all)
return;
goto delete;
}
} */else if (!strcmp(gtarget->u.user.name, "SNAT"))
{
if (memcmp(gentry, sentry, gentry->next_offset))
{
if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
|| grange->range[0].min.all)
return;
goto delete;
}
}
gptr += gentry->next_offset;
sptr += gentry->next_offset;
if(!strcmp(gtarget->u.user.name, "SNAT"))
{
seq++;
}
}
HNAT_PRINTK("NONE to delete\n");
return;
delete:
HNAT_PRINTK("READY to delete one\n");
for (j = 0; j < NAT_HW_NUM; j++)
{
HNAT_PRINTK("ready [%d] (hw)%x:(sw)%x######\n",
j, hw_nat_ipt_seq[j], seq);
if (hw_nat_ipt_seq[j] == seq)
{
if(nat_hw_del_by_index(j) != 0)
{
return;
}
//public_ip_del(hw_nat_pip_idx[j]);
}
}
for(i = 0; i < NAT_HW_NUM; i++)
{
if(hw_nat_ipt_seq[i] > seq)
{
hw_nat_ipt_seq[i]--;
}
else if(hw_nat_ipt_seq[i] == seq)
{
hw_nat_ipt_seq[i]=0;
}
}
return;
}
static void
nat_ipt_to_hw_entry(struct ipt_entry *e,
nat_entry_t *nat)
{
#define P_ANY 0
#define P_TCP 6
#define P_UDP 17
struct ipt_entry_target *t = (struct ipt_entry_target *)ipt_get_target(e);
const struct nf_nat_ipv4_multi_range_compat *mr =
(struct nf_nat_ipv4_multi_range_compat *)(t->data);
const struct nf_nat_range *range = &mr->range[0];
uint32_t sip = ntohl(e->ip.src.s_addr);
uint32_t pip = ntohl(range->min_ip);
uint16_t proto = e->ip.proto;
memset((void *) nat, 0, sizeof (nat_entry_t));
nat->src_addr = sip;
nat->trans_addr = pip;
if (proto == P_TCP)
{
nat->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
}
else if (proto == P_UDP)
{
nat->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
}
else if (proto == P_ANY)
{
nat->flags = FAL_NAT_ENTRY_PROTOCOL_ANY;
}
}
static int
nat_ipt_hw_add(nat_entry_t *nat)
{
uint32_t index = 0;
if(nat_hw_add(nat) != 0)
{
return -1;
}
hw_nat_ipt_seq[nat->entry_id] = snat_seq;
HNAT_PRINTK("###nat_ipt_hw_add hw_nat_ipt_seq[%d]:%d###\n",
nat->entry_id, snat_seq);
hw_nat_pip_idx[nat->entry_id] = nat->trans_addr;
if(nat_hw_prv_base_can_update())
{
nat_hw_prv_base_set(nat->src_addr);
nat_hw_prv_base_update_disable();
}
if(nat_hw_pub_ip_add(nat->trans_addr, &index)!= 0)
{
return -1;
}
return 0;
}
static int
nat_ipt_hw_port_range_add(nat_entry_t *nat,
uint16_t port_start, uint16_t port_end,
struct xt_multiport *xport)
{
unsigned int i;
nat->flags |= FAL_NAT_ENTRY_PORT_CHECK;
if(xport)
{
//some discontinuous ports
for (i = 0; i < xport->count; i++)
{
nat->port_num = xport->ports[i];
nat->port_range = 1;
if(nat_ipt_hw_add(nat))
{
HNAT_PRINTK("isis_nat_add(xport:%d) fail!\n", nat->port_num);
return -1;
}
HNAT_PRINTK("(1)isis_nat_add(xport:%d) success\n", nat->port_num);
}
}
else
{
//one port or port range
uint16_t port_min, port_max;
for (i = port_start; i <= port_end; i+= NAT_HW_PORT_RANGE_MAX)
{
port_min = i;
if((port_end-port_min)>(NAT_HW_PORT_RANGE_MAX-1))
{
port_max = port_min+(NAT_HW_PORT_RANGE_MAX-1);
}
else
{
port_max = port_end;
}
nat->port_num = port_min;
nat->port_range = (port_max - port_min + 1);
if(nat_ipt_hw_add(nat))
{
HNAT_PRINTK("isis_nat_add(range port:%d~%d) fail!\n",
port_min, port_max);
return -1;
}
HNAT_PRINTK("(2)isis_nat_add(range port:%d~%d) success\n", port_min, port_max);
}
}
return 0;
}
static int
nat_ipt_check_none_matches(struct ipt_entry *e)
{
nat_entry_t nat = {0};
nat_ipt_to_hw_entry(e, &nat);
if(nat_ipt_hw_add(&nat) != 0)
{
HNAT_PRINTK("(1)isis_nat_add(none port)fail!\n");
return -1;
}
HNAT_PRINTK("(1)isis_nat_add(none port) success\n");
return 0;
}
static int
nat_ipt_check_matches(struct ipt_entry_match *m,
struct ipt_entry *e,
unsigned int *j)
{
int ret = 0;
nat_entry_t nat = {0};
uint16_t port_start = 0, port_end = 0;
struct xt_multiport *xport = NULL;
if(strcmp(m->u.user.name, "udp") == 0)
{
struct xt_udp *udpinfo = (struct xt_udp *)m->data;
port_start = udpinfo->spts[0];
port_end = udpinfo->spts[1];
}
else if(strcmp(m->u.user.name, "tcp") == 0)
{
struct xt_tcp *tcpinfo = (struct xt_tcp *)m->data;
port_start = tcpinfo->spts[0];
port_end = tcpinfo->spts[1];
}
else if(strcmp(m->u.user.name, "multiport") == 0)
{
struct xt_multiport xport_data = {0};
struct ipt_entry_target *t = ipt_get_target(e);
xport = &xport_data;
if(t->u.user.revision == 0)
{
xport = (struct xt_multiport *)m->data;
}
else if(t->u.user.revision == 1)
{
const struct xt_multiport_v1 *xportv1 =
(struct xt_multiport_v1 *)m->data;
memcpy(xport->ports, xportv1->ports, sizeof(xportv1->ports));
xport->count = xportv1->count;
}
if(xport->flags != XT_MULTIPORT_SOURCE)
{
memset(xport->ports, 0, sizeof(xport->ports));
}
}
else
{
(*j)++ ;
HNAT_PRINTK("###no support matches m->u.user.name:%s\n",
m->u.user.name);
return -1;
}
nat_ipt_to_hw_entry(e, &nat);
ret = nat_ipt_hw_port_range_add(&nat, port_start, port_end, xport);
(*j)++ ;
return ret;
}
//check netmask !=32
#define NAT_IPT_RULE_IS_FOR_NAPT(e) (((e)->ip.smsk.s_addr) != 0xffffffff)
#define NAT_IPT_RULE_IS_NONE_MATCHES(e) (((e)->target_offset) == \
(sizeof(struct ipt_entry)))
static int
nat_ipt_find_check_entry(struct ipt_entry *e, unsigned int underflow,
unsigned int *i)
{
int ret = 0;
static uint16_t next_offset = 0;
struct ipt_entry_target *t = ipt_get_target(e);
if(*i == 0)
{
snat_seq = 0;
next_offset = e->next_offset;
}
else
{
next_offset += e->next_offset;
}
if (!strcmp(t->u.user.name, "SNAT"))
{
++snat_seq;
if(NAT_IPT_RULE_IS_FOR_NAPT(e))
{
HNAT_PRINTK("this ipt rule only for HW napt offload\n");
}
else
{
/*for basic nat offload*/
HNAT_PRINTK("[%d]next_offset:%d underflow:%d\n",
*i, next_offset, underflow);
if(next_offset == underflow) //new one
{
if(NAT_IPT_RULE_IS_NONE_MATCHES(e))
{
/*none matches*/
ret = nat_ipt_check_none_matches(e);
}
else
{
unsigned int j = 0;
/*iterate matches*/
ret = IPT_MATCH_ITERATE(e, nat_ipt_check_matches, e, &j);
}
}
}
}
(*i)++ ;
return ret;
}
static void
nat_ipt_data_cleanup(void)
{
if (gbuffer)
kfree(gbuffer);
gbuffer = NULL;
if (sbuffer)
kfree(sbuffer);
sbuffer = NULL;
}
static void
nat_ipt_data_init(void)
{
/*alloc initial set buffer*/
sbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
if(sbuffer)
{
memset(sbuffer, 0, IPT_BUFFER_INIT_LEN);
slen = IPT_BUFFER_INIT_LEN;
}
else
{
HNAT_PRINTK("%s sbuffer memory allocate fail\n", __func__);
}
/*alloc initial get buffer*/
gbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
if(gbuffer)
{
memset(gbuffer, 0, IPT_BUFFER_INIT_LEN);
glen = IPT_BUFFER_INIT_LEN;
}
else
{
HNAT_PRINTK("%s gbuffer memory allocate fail\n", __func__);
}
/*set initial underflow: nf_nat_rule.c*/
memset(&old_replace, 0, sizeof (old_replace));
/*record ipt rule(SNAT) sequence for hw nat*/
memset(hw_nat_ipt_seq, 0, NAT_HW_NUM);
/*record ipt rule(SNAT) pubip index for hw nat*/
memset(hw_nat_pip_idx, 0, NAT_HW_NUM);
}
static void
nat_ipt_flush(void)
{
napt_hw_flush();
nat_hw_flush();
nat_ipt_data_cleanup();
nat_ipt_data_init();
HNAT_PRINTK("------(nat flush done)------\n");
}
static void
nat_ipt_add(struct ipt_replace ireplace)
{
unsigned int i = 0;
IPT_ENTRY_ITERATE(sbuffer,
ireplace.size,
nat_ipt_find_check_entry,
ireplace.underflow[NF_INET_POST_ROUTING],
&i);
}
static int
nat_ipt_hook_type_check(struct ipt_replace ireplace)
{
int ret = -1;
HNAT_PRINTK("------we only support SNAT-----\n");
if((old_replace.underflow[NF_INET_POST_ROUTING]-
old_replace.hook_entry[NF_INET_POST_ROUTING]) !=
(ireplace.underflow[NF_INET_POST_ROUTING]-
ireplace.hook_entry[NF_INET_POST_ROUTING]))
{
HNAT_PRINTK("------this is POSTROUTING(SNAT):yes!------\n");
ret = 0;
}
else if ((old_replace.underflow[NF_INET_PRE_ROUTING]-
old_replace.hook_entry[NF_INET_PRE_ROUTING]) !=
(ireplace.underflow[NF_INET_PRE_ROUTING]-
ireplace.hook_entry[NF_INET_PRE_ROUTING]))
{
HNAT_PRINTK("------this is PREROUTING(DNAT):no!------\n");
}
else if((old_replace.underflow[NF_INET_LOCAL_OUT]-
old_replace.hook_entry[NF_INET_LOCAL_OUT]) !=
(ireplace.underflow[NF_INET_LOCAL_OUT]-
ireplace.hook_entry[NF_INET_LOCAL_OUT]))
{
HNAT_PRINTK("------this is OUTPUT:no!------\n");
}
else
{
HNAT_PRINTK("------this is UNKNOW:no!------\n");
}
return ret;
}
static void
nat_ipt_rules_cp_from_user(void **buf, unsigned int *buf_len,
void __user *user, unsigned int user_len)
{
if((*buf == 0) || (user == 0))
{
return;
}
if (*buf_len < user_len)
{
if(*buf)
{
kfree(*buf);
*buf = kmalloc(user_len, GFP_ATOMIC);
if(*buf == NULL)
{
HNAT_PRINTK("%s memory allocate fail\n", __func__);
return;
}
*buf_len = user_len;
}
}
HNAT_PRINTK("(2)nat_ipt_rules_cp_from_user *buf:%x user:%x user_len:%d\n",
(unsigned int)*buf, (unsigned int)user, user_len);
copy_from_user(*buf, user, user_len);
return;
}
static int
nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len)
{
struct ipt_replace ireplace;
memset(&ireplace, 0, sizeof(ireplace));
HNAT_PRINTK("NAT set hook\n");
if (cmd != IPT_SO_SET_REPLACE)
goto normal;
copy_from_user(&ireplace, user, sizeof (ireplace));
if (strcmp(ireplace.name, "nat")
|| (ireplace.num_entries == ireplace.num_counters))
{
HNAT_PRINTK("none NAT or no new entry %d", ireplace.num_entries);
goto normal;
}
if (ireplace.num_entries == NF_NAT_INIT_ENTRIES_NUM)
{
nat_ipt_flush();
goto normal;
}
if (nat_ipt_hook_type_check(ireplace) != 0)
{
goto normal;
}
nat_ipt_rules_cp_from_user((void **)&sbuffer, &slen,
(user + sizeof (ireplace)),
ireplace.size);
if (ireplace.num_entries > ireplace.num_counters)
{
nat_ipt_add(ireplace);
}
else
{
nat_ipt_del(ireplace);
}
normal:
/*save old_replace for next hook type check*/
old_replace = ireplace;
return orgi_ipt_sockopts.set(sk, cmd, user, len);
}
static int
nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len)
{
int k = orgi_ipt_sockopts.get(sk, cmd, user, len);
if (cmd == IPT_SO_GET_ENTRIES)
{
struct ipt_get_entries entries;
copy_from_user(&entries, user, sizeof (entries));
nat_ipt_rules_cp_from_user((void **)&gbuffer, &glen,
(user + sizeof (struct ipt_get_entries)),
(*len - sizeof (entries)));
}
return k;
}
void
nat_ipt_sockopts_replace(void)
{
int ret = 0;
/*register an temp sockopts to find ipt_sockopts*/
if((ret = nf_register_sockopt(&tmp_ipt_sockopts)) < 0) {
return;
}
list_for_each_entry(ipt_sockopts, tmp_ipt_sockopts.list.next, list)
{
if (ipt_sockopts->set_optmin == IPT_BASE_CTL)
{
nat_sockopts_init = 1;
break;
}
}
nf_unregister_sockopt(&tmp_ipt_sockopts);
if(!nat_sockopts_init)
return;
/*save orginal ipt_sockopts*/
orgi_ipt_sockopts = *ipt_sockopts;
/*replace ipt_sockopts with our opts*/
ipt_sockopts->set = nat_ipt_set_ctl;
ipt_sockopts->get = nat_ipt_get_ctl;
}
static void
nat_ipt_sockopts_restore(void)
{
ipt_sockopts->set = orgi_ipt_sockopts.set;
ipt_sockopts->get = orgi_ipt_sockopts.get;
}
void
nat_ipt_helper_init(void)
{
nat_ipt_sockopts_replace();
nat_ipt_data_init();
}
void
nat_ipt_helper_exit(void)
{
nat_ipt_sockopts_restore();
nat_ipt_data_cleanup();
nat_hw_flush();
}

347
feeds/ipq807x/qca-ssdk/src/config
View File

@@ -1,347 +0,0 @@
#CPU=mips
OS=linux
ifeq ($(KVER),$(filter 3.14%,$(KVER)))
OS_VER=3_14
endif
ifeq ($(KVER),$(filter 4.4%,$(KVER)))
OS_VER=4_4
endif
ifeq ($(KVER),$(filter 4.1%,$(KVER)))
OS_VER=4_1
endif
ifeq ($(KVER),$(filter 4.9%,$(KVER)))
OS_VER=4_9
endif
ifeq ($(KVER),$(filter 5.4%,$(KVER)))
OS_VER=5_4
endif
ifeq ($(KVER), 3.4.0)
OS_VER=3_4
endif
ifeq ($(KVER), 3.18)
OS_VER=3_18
endif
ifeq ($(KVER), 3.18.21)
OS_VER=3_18
endif
ifeq ($(KVER), 3.4.103)
OS_VER=3_4
endif
ifeq ($(KVER), 3.3.8)
OS_VER=3_2
endif
ifeq ($(ARCH), arm)
BOARD=ipq806x
endif
ifeq ($(ARCH), mips)
BOARD=ar71xx
endif
ifeq ($(BOARD), ar71xx)
BOARD_NAME=BOARD_AR71XX
endif
ifeq ($(BOARD), ipq806x)
BOARD_NAME=BOARD_IPQ806X
endif
OS_SUB=31
ifndef OS_VER
OS_VER=2_6
endif
# OS subversion, 2.6.31 for WASP (db120)
#OS_SUB=31
# GCC version, 3 or 4
#GCC_VER=4
#For MIPS Linux2.6
#pb45
#TOOL_PATH=/disk/pb45/sw/build/gcc-3.4.4-2.16.1/build_mips_nofpu/bin
#SYS_PATH=/disk/pb45/sw/linux/kernels/mips-linux-2.6.15
#ap81
# compatiable with OpenWRT
ifndef TOOL_PATH
TOOL_PATH=/disk/ap81fus/sw/build/gcc-3.4.4-2.16.1/build_mips/bin
endif
ifndef SYS_PATH
SYS_PATH=/disk/ap81fus/sw/linux/kernels/mips-linux-2.6.15
endif
ifeq ($(ARCH), mips)
CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-common -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB -D$(BOARD_NAME)
endif
#db120
ifeq ($(BOARD_TYPE),db12x)
OS_SUB=31
GCC_VER=4
TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
endif
ifeq ($(ARCH), arm)
ifeq ($(KVER), 3.4.0)
CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
endif
ifeq ($(KVER), 3.4.103)
CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
endif
ifeq ($(KVER), 3.18.21)
CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
endif
ifeq ($(KVER),$(filter 4.4% 5.4%,$(KVER)))
CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU -D$(BOARD_NAME)
endif
ifeq ($(KVER),$(filter 3.14%,$(KVER)))
CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
endif
ifeq ($(KVER),$(filter 4.9% 4.4% 5.4%,$(KVER)))
CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=2048 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
endif
ifeq ($(KVER),$(filter 3.18%,$(KVER)))
CPU_CFLAG= -DMODULE -nostdinc -D$(BOARD_NAME) -mlittle-endian -Wundef -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -Wno-format-security -fno-delete-null-pointer-checks -O2 -fno-dwarf2-cfi-asm -mabi=aapcs-linux -mno-thumb-interwork -mfpu=vfp -funwind-tables -marm -D__LINUX_ARM_ARCH__=7 -march=armv7-a -msoft-float -Uarm -Wframe-larger-than=1024 -fno-stack-protector -Wno-unused-but-set-variable -fomit-frame-pointer -g -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-overflow -fconserve-stack -Werror=implicit-int -DCC_HAVE_ASM_GOTO -D"KBUILD_STR(s)=\#s" -D"KBUILD_BASENAME=KBUILD_STR(mem)"
endif
endif
ifeq ($(ARCH), arm64)
ifeq ($(KVER),$(filter 4.1% 4.4% 4.9% 5.4%,$(KVER)))
CPU_CFLAG= -DMODULE -Os -pipe -march=armv8-a -mcpu=cortex-a53+crypto -fno-caller-saves -fno-strict-aliasing -Werror -fno-common -Wno-format-security -Wno-pointer-sign -Wno-unused-but-set-variable -Wno-error=unused-result -mcmodel=large
endif
endif
ifeq ($(BOARD_TYPE), ap136)
OS_SUB=31
GCC_VER=4
TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
endif
#For MIPS Linux2.4
#TOOL_PATH=/home/perforce/kernel2.4/5.3.1.20/tools/gcc-3.3.3-2.4.25/toolchain_mips/bin
#SYS_PATH=/home/perforce/kernel2.4/5.3.1.20/src/kernels/mips-linux-2.4.25
#TOOLPREFIX=$(CPU)-$(OS)-
#CPU_CFLAG=-Wstrict-prototypes -Wundef -fomit-frame-pointer -G 0 -mno-abicalls -Wno-trigraphs -fno-strict-aliasing -fno-common -ffreestanding -O2 -fno-pic -pipe -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,--trap -DMODULE -mlong-calls -DEXPORT_SYMTAB
ifeq ($(SWCONFIG_FEATURE), disable)
SWCONFIG=FALSE
else
SWCONFIG=TRUE
endif
KERNEL_MODE=TRUE
#compatiable with OpenWRT
ifeq ($(SWITCH_SSDK_MODE),user)
KERNEL_MODE=FLASE
endif
#FAL=FALSE or not define FAL, FAL will not be included in SSDK
FAL=TRUE
#CHIP_TYPE can be defined as ATHENA, GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS, HPPE, CPPE, MP and ALL_CHIP(ALL_CHIP means GARUDA, SHIVA, HORUS, ISIS, ISISC, DESS and HPPE CPPE MP)
ifndef CHIP_TYPE
CHIP_TYPE=ALL_CHIP
endif
#UK_IF=FALSE or not define UK_IF, UK_IF will not be included in SSDK
#when UK_IF=TRUE one of UK_NETLINK,UK_IOCTL must be defined as TRUE
UK_IF=TRUE
#UK_IOCTL=TRUE define user-kernel space communication based on ioctl
UK_IOCTL=TRUE
UK_MINOR_DEV=254
#API_LOCK=FALSE or not define API_LOCK, API_LOCK will not be included in SSDK
API_LOCK=FALSE
#REG_ACCESS_SPEEDUP=FALSE or not define REG_ACCESS_SPEEDUP, REG_ACCESS_SPEEDUP will not be enabled, now only ISIS supports
REG_ACCESS_SPEEDUP=FALSE
#ALL supported features:
#ACL FDB IGMP LEAKY LED MIB MIRROR MISC PORTCONTROL PORTVLAN QOS RATE STP VLAN
#IN_X=FALSE or not define IN_X, X will not be included in SSDK
IN_ACL=TRUE
IN_FDB=TRUE
IN_IGMP=TRUE
IN_LEAKY=TRUE
IN_LED=TRUE
IN_MIB=TRUE
IN_MIRROR=TRUE
IN_MISC=TRUE
IN_PORTCONTROL=TRUE
IN_PORTVLAN=TRUE
IN_QOS=TRUE
IN_RATE=TRUE
IN_STP=TRUE
IN_VLAN=TRUE
IN_REDUCED_ACL=FALSE
IN_COSMAP=TRUE
IN_IP=TRUE
IN_NAT=TRUE
IN_TRUNK=TRUE
IN_SEC=TRUE
IN_PPPOE=TRUE
ifeq ($(HNAT_FEATURE), enable)
IN_NAT_HELPER=TRUE
else
IN_NAT_HELPER=FALSE
endif
ifeq ($(RFS_FEATURE), enable)
IN_RFS=TRUE
else
IN_RFS=FALSE
endif
IN_INTERFACECONTROL=TRUE
IN_MACBLOCK=FALSE
#The PHY CHIP defined according to the switch CHIP
ifeq (ALL_CHIP, $(CHIP_TYPE))
IN_AQUANTIA_PHY=TRUE
IN_QCA803X_PHY=TRUE
IN_QCA808X_PHY=TRUE
IN_PHY_I2C_MODE=TRUE
IN_MALIBU_PHY=TRUE
IN_SFP_PHY=TRUE
IN_SFP=TRUE
else ifeq (HPPE, $(CHIP_TYPE))
IN_AQUANTIA_PHY=TRUE
IN_QCA803X_PHY=TRUE
IN_QCA808X_PHY=TRUE
IN_PHY_I2C_MODE=TRUE
IN_SFP_PHY=TRUE
IN_MALIBU_PHY=TRUE
else ifeq (CPPE, $(CHIP_TYPE))
IN_QCA808X_PHY=TRUE
IN_QCA803X_PHY=TRUE
IN_SFP_PHY=TRUE
IN_PHY_I2C_MODE=TRUE
IN_MALIBU_PHY=TRUE
else ifeq (DESS, $(CHIP_TYPE))
IN_MALIBU_PHY=TRUE
else ifeq (MP, $(CHIP_TYPE))
IN_QCA803X_PHY=TRUE
IN_QCA808X_PHY=TRUE
else
IN_QCA803X_PHY=FALSE
IN_QCA808X_PHY=FALSE
IN_AQUANTIA_PHY=FALSE
IN_MALIBU_PHY=FALSE
IN_SFP_PHY=FALSE
IN_SFP=FALSE
endif
ifeq ($(SFE_FEATURE), enable)
IN_SFE=TRUE
else
IN_SFE=FALSE
endif
#QCA808X PHY features
ifeq ($(IN_QCA808X_PHY), TRUE)
ifeq ($(PTP_FEATURE), enable)
IN_PTP=TRUE
else
IN_PTP=FALSE
endif
endif
#IN_PHY_I2C_MODE depends on IN_SFP_PHY
ifeq ($(IN_PHY_I2C_MODE), TRUE)
IN_SFP_PHY=TRUE
endif
ifneq (, $(filter HPPE CPPE ALL_CHIP, $(CHIP_TYPE)))
IN_FLOW=TRUE
IN_RSS_HASH=TRUE
IN_QM=TRUE
IN_VSI=TRUE
IN_CTRLPKT=TRUE
IN_SERVCODE=TRUE
IN_BM=TRUE
IN_SHAPER=TRUE
IN_POLICER=TRUE
endif
ifneq (, $(filter HPPE CPPE MP ALL_CHIP, $(CHIP_TYPE)))
IN_UNIPHY=TRUE
endif
#MINI SSDK enabled
ifeq ($(MINI_SSDK), enable)
IN_FDB_MINI=TRUE
IN_MISC_MINI=TRUE
IN_PORTCONTROL_MINI=TRUE
IN_QOS_MINI=TRUE
IN_COSMAP_MINI=TRUE
IN_PORTVLAN_MINI=TRUE
IN_VLAN_MINI=TRUE
IN_VSI_MINI=TRUE
IN_BM_MINI=TRUE
IN_SHAPER_MINI=TRUE
IN_POLICER_MINI=TRUE
IN_FLOW_MINI=TRUE
IN_QM_MINI=TRUE
IN_UNIPHY_MINI=TRUE
IN_IP_MINI=TRUE
IN_SFP=FALSE
#disable modules for MINI HPPE/CPPE
ifneq (, $(filter HPPE CPPE, $(CHIP_TYPE)))
IN_SERVCODE=FALSE
IN_PPPOE=FALSE
IN_NAT=FALSE
IN_COSMAP=FALSE
IN_RATE=FALSE
IN_IGMP=FALSE
IN_LEAKY=FALSE
IN_LED=FALSE
IN_INTERFACECONTROL=FALSE
endif
endif
ifneq ($(HK_CHIP), enable)
CHIP_TYPE=NONHK_CHIP
endif
ifeq (MP, $(CHIP_TYPE))
ifeq (disable, $(ISISC_ENABLE))
IN_ACL=FALSE
IN_FDB=FALSE
IN_IGMP=FALSE
IN_LEAKY=FALSE
IN_LED=FALSE
IN_MIRROR=FALSE
IN_MISC=FALSE
IN_PORTVLAN=FALSE
IN_QOS=FALSE
IN_RATE=FALSE
IN_STP=FALSE
IN_VLAN=FALSE
IN_REDUCED_ACL=FALSE
IN_COSMAP=FALSE
IN_IP=FALSE
IN_NAT=FALSE
IN_FLOW=FALSE
IN_TRUNK=FALSE
IN_RSS_HASH=FALSE
IN_SEC=FALSE
IN_QM=FALSE
IN_PPPOE=FALSE
IN_VSI=FALSE
IN_CTRLPKT=FALSE
IN_SERVCODE=FALSE
IN_BM=FALSE
IN_SHAPER=FALSE
IN_POLICER=FALSE
endif
endif

1604
feeds/ipq807x/qca-ssdk/src/include/adpt/adpt.h
View File

File diff suppressed because it is too large Load Diff

38
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_flow.h
View File

@@ -1,38 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_FLOW_
#define _ADPT_CPPE_FLOW_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifndef IN_FLOW_MINI
sw_error_t
adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

52
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_mib.h
View File

@@ -1,52 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_MIB_H_
#define _ADPT_CPPE_MIB_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_error_t
adpt_cppe_lpbk_mib_cpukeep_get(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t *enable);
sw_error_t
adpt_cppe_lpbk_mib_cpukeep_set(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t enable);
sw_error_t
adpt_hppe_lpbk_mib_status_get(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t *enable);
sw_error_t
adpt_cppe_lpbk_mib_status_set(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t enable);
sw_error_t
adpt_cppe_lpbk_mib_flush_counters(a_uint32_t dev_id,
fal_port_t port_id);
sw_error_t
adpt_cppe_lpbk_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info );
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

37
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_misc.h
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@@ -1,37 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_MISC_
#define _ADPT_CPPE_MISC_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_error_t
adpt_cppe_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id,
fal_counter_en_t *cnt_en);
sw_error_t
adpt_cppe_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id,
fal_counter_en_t *cnt_en);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

103
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_portctrl.h
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@@ -1,103 +0,0 @@
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_PORTCTRLH_
#define _ADPT_CPPE_PORTCTRLH_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0x0
#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 0x1
#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0x0
#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 0x1
#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0x0
#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 0x1
#define CPPE_PORT5_GMAC_SEL_GMAC 0x0
#define CPPE_PORT5_GMAC_SEL_XGMAC 0x1
#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0
#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1
#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0
#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1
#define CPPE_DETECTION_PHY_FAILURE 0xFFFF
#define CPPE_LOOPBACK_PORT_RATE_FREQUENCY 300 /* 300MHZ*/
#define CPPE_LOOPBACK_PORT_NUM 0x1
sw_error_t
_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t port_type);
sw_error_t
adpt_cppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
fal_mru_ctrl_t *ctrl);
sw_error_t
adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mru_ctrl_t *ctrl);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
fal_mtu_ctrl_t *ctrl);
sw_error_t
adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mtu_ctrl_t *ctrl);
sw_error_t
adpt_cppe_port_source_filter_set(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t enable);
sw_error_t
adpt_cppe_port_source_filter_get(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t * enable);
sw_error_t
adpt_cppe_port_source_filter_config_set(
a_uint32_t dev_id, fal_port_t port_id,
fal_src_filter_config_t *src_filter_config);
sw_error_t
adpt_cppe_port_source_filter_config_get
(a_uint32_t dev_id, fal_port_t port_id,
fal_src_filter_config_t* src_filter_config);
#endif
sw_error_t
adpt_cppe_port_to_channel_convert(a_uint32_t dev_id,
a_uint32_t port_id, a_uint32_t *channel_id);
sw_error_t
adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id,
fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
sw_error_t
adpt_cppe_switch_port_loopback_get(a_uint32_t dev_id,
fal_port_t port_id, fal_loopback_config_t *loopback_cfg);
sw_error_t
adpt_cppe_switch_port_loopback_flowctrl_set(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t enable);
sw_error_t
adpt_cppe_switch_port_loopback_flowctrl_get(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t *enable);
sw_error_t
adpt_cppe_lpbk_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t *max_frame);
sw_error_t
adpt_cppe_lpbk_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t max_frame);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

41
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qm.h
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@@ -1,41 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_QM_H_
#define _ADPT_CPPE_QM_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifndef IN_QM_MINI
sw_error_t
adpt_cppe_qm_port_source_profile_set(
a_uint32_t dev_id, fal_port_t port, a_uint32_t src_profile);
sw_error_t
adpt_cppe_qm_port_source_profile_get(
a_uint32_t dev_id, fal_port_t port, a_uint32_t *src_profile);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

68
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_qos.h
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@@ -1,68 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_QOS_H_
#define _ADPT_CPPE_QOS_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_error_t
adpt_cppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_pri_precedence_t *pri);
sw_error_t
adpt_cppe_qos_port_pri_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_pri_precedence_t *pri);
sw_error_t
adpt_cppe_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t pcp,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t pcp,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t dscp,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint16_t flow,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_group_t *group);
sw_error_t
adpt_cppe_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t dscp,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint16_t flow,
fal_qos_cosmap_t *cosmap);
sw_error_t
adpt_cppe_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_group_t *group);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

47
feeds/ipq807x/qca-ssdk/src/include/adpt/cppe/adpt_cppe_uniphy.h
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@@ -1,47 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_CPPE_UNIPHYH_
#define _ADPT_CPPE_UNIPHYH_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_error_t
__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id,
a_uint32_t ch0_selection, a_uint32_t ch4_selection);
void
__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
a_bool_t enable);
sw_error_t
__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index);
void
__adpt_cppe_gcc_uniphy_software_reset(a_uint32_t dev_id,
a_uint32_t uniphy_index);
sw_error_t
__adpt_cppe_uniphy_mode_set(a_uint32_t dev_id,
a_uint32_t uniphy_index, a_uint32_t mode);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

112
feeds/ipq807x/qca-ssdk/src/include/adpt/hppe/adpt_hppe.h
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@@ -1,112 +0,0 @@
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_HPPE_H_
#define _ADPT_HPPE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
void adpt_hppe_fdb_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_fdb_init(a_uint32_t dev_id);
void adpt_hppe_portvlan_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_portvlan_init(a_uint32_t dev_id);
void adpt_hppe_ctrlpkt_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_ctrlpkt_init(a_uint32_t dev_id);
void adpt_hppe_servcode_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_servcode_init(a_uint32_t dev_id);
void adpt_hppe_rss_hash_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_rss_hash_init(a_uint32_t dev_id);
void adpt_hppe_mib_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_mib_init(a_uint32_t dev_id);
void adpt_hppe_stp_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_stp_init(a_uint32_t dev_id);
void adpt_hppe_vsi_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_vsi_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_port_ctrl_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id);
void adpt_hppe_mirror_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_mirror_init(a_uint32_t dev_id);
void adpt_hppe_trunk_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_trunk_init(a_uint32_t dev_id);
void adpt_hppe_ip_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_ip_init(a_uint32_t dev_id);
void adpt_hppe_qm_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_qm_init(a_uint32_t dev_id);
void adpt_hppe_flow_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_flow_init(a_uint32_t dev_id);
void adpt_hppe_pppoe_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_pppoe_init(a_uint32_t dev_id);
void adpt_hppe_sec_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_sec_init(a_uint32_t dev_id);
void adpt_hppe_acl_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_acl_init(a_uint32_t dev_id);
void adpt_hppe_qos_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_qos_init(a_uint32_t dev_id);
void adpt_hppe_bm_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_bm_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_shaper_init(a_uint32_t dev_id);
void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id);
void adpt_hppe_shaper_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_policer_init(a_uint32_t dev_id);
void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id);
/*shaper*/
#define HPPE_MAX_C_TOKEN_NUM 0x3fffffff
#define HPPE_MAX_E_TOKEN_NUM 0x3fffffff
#define HPPE_POLICER_TIMESLOT_DFT 600
#define HPPE_PORT_SHAPER_TIMESLOT_DFT 8
#define HPPE_FLOW_SHAPER_TIMESLOT_DFT 64
#define HPPE_QUEUE_SHAPER_TIMESLOT_DFT 300
#define HPPE_SHAPER_IPG_PREAMBLE_LEN_DFT 20
/*BM*/
#define HPPE_BM_PORT_NUM 15
#define HPPE_BM_PHY_PORT_OFFSET 8
void adpt_hppe_ptp_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id);
#define HPPE_REVISION 0x0
#define CPPE_REVISION 0x1
#define UNKNOWN_REVISION 0xff
a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id);
#ifdef IN_FDB
sw_error_t
adpt_hppe_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

43
feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp.h
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@@ -1,43 +0,0 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ADPT_MP_H_
#define _ADPT_MP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define MP_PORT_TO_GMAC_ID(port_id) (port_id -1)
#define MP_MAX_PORT 2
#define MP_GMAC0 0
#define MP_GMAC1 1
#define MP_PORT_ID_CHECK(port_id) \
do { \
if (port_id > MP_MAX_PORT) \
return SW_OUT_OF_RANGE; \
} while (0)
sw_error_t adpt_mp_intr_init(a_uint32_t dev_id);
sw_error_t adpt_mp_mib_init(a_uint32_t dev_id);
sw_error_t adpt_mp_portctrl_init(a_uint32_t dev_id);
sw_error_t adpt_mp_uniphy_init(a_uint32_t dev_id);
sw_error_t adpt_mp_led_init(a_uint32_t dev_id);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

63
feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_portctrl.h
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@@ -1,63 +0,0 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ADPT_PORTCTRL_H_
#define _ADPT_PORTCTRL_H_
#define GMAC_SPEED_10M 0x0
#define GMAC_SPEED_100M 0x1
#define GMAC_SPEED_1000M 0x0
#define GMAC_FULL_DUPLEX 0x1
#define GMAC_HALF_DUPLEX 0x0
#define GMAC_PAUSE_TIME 0xffff
#define GMAC_PAUSE_ZERO_QUANTA_ENABLE 0x0
#define GMAC_JD_ENABLE 0x1
#define GMAC_WD_DISABLE 0x0
#define GMAC_FRAME_BURST_ENABLE 0x1
#define GMAC_JUMBO_FRAME_ENABLE 0x1
#define GMAC_MAX_FRAME_CTRL_ENABLE 0x1
#define GMAC_LPI_LINK_UP 0x1
#define GMAC_LPI_AUTO_MODE 0x1
#define GMAC_TX_STORE_FORWAD_ENABLE 0x1
#define GMAC_RX_STORE_FORWAD_ENABLE 0x1
#define GMAC_FORWARD_ERROR_FRAME_DISABLE 0x0
#define GMAC_DROP_GAINT_FRAME_DISABLE 0x0
#define GMAC_FLUSH_RECEIVED_FRAMES_DISABLE 0x1
#define GMAC_HW_FLOWCTRL_ENABLE 0x1
#define GMAC_ACTIVATE_FLOWCTRL_MASK 0x800600
#define GMAC_ACTIVATE_FLOWCTRL_WITH_1KB 0x0
#define GMAC_ACTIVATE_FLOWCTRL_WITH_2KB 0x200
#define GMAC_ACTIVATE_FLOWCTRL_WITH_3KB 0x400
#define GMAC_ACTIVATE_FLOWCTRL_WITH_4KB 0x600
#define GMAC_ACTIVATE_FLOWCTRL_WITH_5KB 0x800000
#define GMAC_ACTIVATE_FLOWCTRL_WITH_6KB 0x800200
#define GMAC_ACTIVATE_FLOWCTRL_WITH_7KB 0x800400
#define GMAC_DACTIVATE_FLOWCTRL_MASK 0x401800
#define GMAC_DACTIVATE_FLOWCTRL_WITH_1KB 0x0
#define GMAC_DACTIVATE_FLOWCTRL_WITH_2KB 0x800
#define GMAC_DACTIVATE_FLOWCTRL_WITH_3KB 0x1000
#define GMAC_DACTIVATE_FLOWCTRL_WITH_4KB 0x1800
#define GMAC_DACTIVATE_FLOWCTRL_WITH_5KB 0x400000
#define GMAC_DACTIVATE_FLOWCTRL_WITH_6KB 0x400800
#define GMAC_DACTIVATE_FLOWCTRL_WITH_7KB 0x401000
#define GMAC_HW_FLOWCTRL_DISABLE 0x0
#define PORT_LPI_ENABLE_STATUS 0x3
#define PORT_LPI_TASK_RUNNING 0x10000
#define PORT_LPI_TASK_START 0x20000
#endif

45
feeds/ipq807x/qca-ssdk/src/include/adpt/mp/adpt_mp_uniphy.h
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@@ -1,45 +0,0 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_MP_UNIPHY_H_
#define _ADPT_MP_UNIPHY_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
void
adpt_mp_gcc_uniphy_port_reset(a_uint32_t dev_id, a_uint32_t port_id);
sw_error_t
adpt_mp_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t enable);
sw_error_t
adpt_mp_uniphy_adapter_port_reset(a_uint32_t dev_id, a_uint32_t port_id);
sw_error_t
adpt_mp_uniphy_mode_configure(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

32
feeds/ipq807x/qca-ssdk/src/include/adpt/sfp/adpt_sfp.h
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/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _ADPT_SFP_H_
#define _ADPT_SFP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_error_t adpt_sfp_init(a_uint32_t dev_id);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

39
feeds/ipq807x/qca-ssdk/src/include/api/api_access.h
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/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _API_ACCESS_H
#define _API_ACCESS_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
sw_api_func_t *
sw_api_func_find(a_uint32_t api_id);
sw_api_param_t *
sw_api_param_find(a_uint32_t api_id);
a_uint32_t
sw_api_param_nums(a_uint32_t api_id);
sw_error_t
sw_api_get(sw_api_t *sw_api);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _API_ACCESS_H */

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feeds/ipq807x/qca-ssdk/src/include/api/api_desc.h
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276
feeds/ipq807x/qca-ssdk/src/include/api/sw_api.h
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/*
* Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SW_API_H
#define _SW_API_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "sw_ioctl.h"
#define SW_MAX_API_BUF 2048
#define SW_MAX_API_PARAM 12 /* cmd type + return value + ten parameters */
#define SW_MAX_PAYLOAD (SW_MAX_API_PARAM << 2) /* maximum payload size for netlink msg*/
#define SW_PARAM_IN 0x1
#define SW_PARAM_OUT 0x2
#define SW_PARAM_PTR 0x4
#define SW_API_DEF(ioctl, name) {ioctl, name}
#define SW_PARAM_DEF(ioctl, data, size, type, name) {ioctl, size, data, type}
typedef enum
{
SW_UINT8 = 1,
SW_INT8,
SW_UINT16,
SW_INT16,
SW_UINT32,
SW_INT32,
SW_UINT64,
SW_INT64,
SW_ENABLE,
SW_SPEED,
SW_DUPLEX,
SW_1QMODE,
SW_EGMODE,
SW_CAP,
SW_VLAN,
SW_LAN_WAN_CFG,
SW_PBMP,
SW_MIB,
SW_MIB_CNTR,
SW_XGMIB,
SW_MACADDR,
SW_FDBENTRY,
SW_MACLIMIT_CTRL,
SW_SCH,
SW_QOS,
SW_STORM,
SW_STP,
SW_LEAKY,
SW_MACCMD,
SW_FLOWTYPE,
SW_FLOWCMD,
SW_UINT_A,
SW_ACLRULE,
SW_LEDPATTERN,
SW_INVLAN,
SW_VLANPROPAGATION,
SW_VLANTRANSLATION,
SW_QINQMODE,
SW_QINQROLE,
SW_CABLESTATUS,
SW_CABLELEN,
SW_SSDK_CFG,
SW_HDRMODE,
SW_FDBOPRATION,
SW_PPPOE,
SW_PPPOE_LESS,
SW_ACL_UDF_TYPE,
SW_IP_HOSTENTRY,
SW_ARP_LEARNMODE,
SW_IP_GUARDMODE,
SW_NATENTRY,
SW_NAPTENTRY,
SW_FLOWENTRY,
SW_NAPTMODE,
SW_IP4ADDR,
SW_IP6ADDR,
SW_INTFMACENTRY,
SW_PUBADDRENTRY,
SW_INGPOLICER,
SW_EGSHAPER,
SW_ACLPOLICER,
SW_MACCONFIG,
SW_PHYCONFIG,
SW_DATA_MAX,
SW_FDBSMODE,
SW_FX100CONFIG,
SW_SGENTRY,
SW_SEC_MAC,
SW_SEC_IP,
SW_SEC_IP4,
SW_SEC_IP6,
SW_SEC_TCP,
SW_SEC_UDP,
SW_SEC_ICMP4,
SW_SEC_ICMP6,
SW_REMARKENTRY,
SW_SGINFOENTRY,
SW_DEFAULT_ROUTE_ENTRY,
SW_HOST_ROUTE_ENTRY,
SW_IP_WCMP_ENTRY,
SW_IP_RFS_IP4,
SW_IP_RFS_IP6,
SW_FLOWCOOKIE,
SW_FDB_RFS,
SW_FLOWRFS,
SW_CROSSOVER_MODE,
SW_CROSSOVER_STATUS,
SW_PREFER_MEDIUM,
SW_FIBER_MODE,
SW_INTERFACE_MODE,
SW_COUNTER_INFO,
SW_REG_DUMP,
SW_DBG_REG_DUMP,
SW_VSI_NEWADDR_LRN,
SW_VSI_STAMOVE,
SW_VSI_MEMBER,
SW_VSI_COUNTER,
SW_MTU_INFO,
SW_MRU_INFO,
SW_MTU_ENTRY,
SW_MRU_ENTRY,
SW_FRAME_MAX_SIZE,
SW_SOURCE_FILTER,
SW_ARP_SG_CFG,
SW_IP_NETWORK_ROUTE,
SW_IP_INTF,
SW_IP_VSI_INTF,
SW_IP_NEXTHOP,
SW_UCAST_QUEUE_MAP,
SW_UCAST_PRI_CLASS,
SW_MCAST_PRI_CLASS,
SW_IP_SG,
SW_IP_PUB,
SW_IP_PORTMAC,
SW_IP_MCMODE,
SW_FLOW_AGE,
SW_FLOW_CTRL,
SW_AC_CTRL,
SW_AC_OBJ,
SW_STATIC_THRESH,
SW_DYNAMIC_THRESH,
SW_GROUP_BUFFER,
SW_FLOW_ENTRY,
SW_FLOW_HOST,
SW_IP_GLOBAL,
SW_FLOW_GLOBAL,
SW_GLOBAL_QINQMODE,
SW_PT_QINQMODE,
SW_TPID,
SW_INGRESS_FILTER,
SW_PT_DEF_VID_EN,
SW_PT_VLAN_TAG,
SW_PT_VLAN_DIRECTION,
SW_PT_VLAN_TRANS_ADV_RULE,
SW_PT_VLAN_TRANS_ADV_ACTION,
SW_PT_VLAN_COUNTER,
SW_DEBUG_COUNTER_EN,
SW_TAG_PROPAGATION,
SW_EGRESS_DEFAULT_VID,
SW_EGRESS_MODE,
SW_CTRLPKT_PROFILE,
SW_SERVCODE_CONFIG,
SW_RSS_HASH_MODE,
SW_RSS_HASH_CONFIG,
SW_MIRR_ANALYSIS_CONFIG,
SW_MIRR_DIRECTION,
SW_L3_PARSER,
SW_L4_PARSER,
SW_EXP_CTRL,
SW_ACL_UDF_PKT_TYPE,
SW_PORTGROUP,
SW_PORTPRI,
SW_PORTREMARK,
SW_COSMAP,
SW_SCHEDULER,
SW_QUEUEBMP,
SW_BMSTHRESH,
SW_BMDTHRESH,
SW_BMPORTCNT,
SW_PORT_SHAPER_TOKEN_CONFIG,
SW_SHAPER_TOKEN_CONFIG,
SW_PORT_SHAPER_CONFIG,
SW_SHAPER_CONFIG,
SW_MODULE,
SW_FUNC_CTRL,
SW_QM_CNT,
SW_POLICER_COUNTER,
SW_POLICER_PORT_CONFIG,
SW_POLICER_ACL_CONFIG,
SW_POLICER_CMD_CONFIG,
SW_POLICER_GLOBAL_COUNTER,
SW_PHY_DUMP,
SW_RESOURCE_SCHE,
SW_PTP_CONFIG,
SW_PTP_REFERENCE_CLOCK,
SW_PTP_RX_TIMESTAMP_MODE,
SW_PTP_DIRECTION,
SW_PTP_PKT_INFO,
SW_PTP_TIME,
SW_PTP_GRANDMASTER_MODE,
SW_PTP_SECURITY,
SW_PTP_PPS_SIGNAL_CONTROL,
SW_PTP_ASYM_CORRECTION,
SW_PTP_OUTPUT_WAVEFORM,
SW_PTP_TOD_UART,
SW_PTP_ENHANCED_TS_ENGINE,
SW_PTP_TRIGGER,
SW_PTP_CAPTURE,
SW_PTP_INTERRUPT,
SW_PORT_EEE_CONFIG,
SW_SRC_FILTER_CONFIG,
SW_PORT_LOOPBACK_CONFIG,
SW_SFP_DATA,
SW_SFP_DEV_TYPE,
SW_SFP_TRANSC_CODE,
SW_SFP_RATE_ENCODE,
SW_SFP_LINK_LENGTH,
SW_SFP_VENDOR_INFO,
SW_SFP_LASER_WAVELENGTH,
SW_SFP_OPTION,
SW_SFP_CTRL_RATE,
SW_SFP_ENHANCED_CFG,
SW_SFP_DIAG_THRESHOLD,
SW_SFP_DIAG_CAL_CONST,
SW_SFP_DIAG_REALTIME,
SW_SFP_CTRL_STATUS,
SW_SFP_ALARM_WARN_FLAG,
SW_SFP_CCODE_TYPE,
} sw_data_type_e;
typedef struct
{
a_uint32_t api_id;
void *func;
} sw_api_func_t;
typedef struct
{
a_uint32_t api_id;
a_uint16_t data_size;
a_uint8_t data_type;
a_uint8_t param_type;
} sw_api_param_t;
typedef struct
{
a_uint32_t api_id;
sw_api_func_t *api_fp;
sw_api_param_t *api_pp;
a_uint32_t api_nr;
} sw_api_t;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _SW_API_H */

989
feeds/ipq807x/qca-ssdk/src/include/api/sw_ioctl.h
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@@ -1,989 +0,0 @@
/*
* Copyright (c) 2012, 2015-2019, 2021, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*qca808x_start*/
#ifndef _SW_IOCTL_H_
#define _SW_IOCTL_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/*init*/
#define SW_API_INIT_OFFSET 10
#define SW_API_SWITCH_INIT (0 + SW_API_INIT_OFFSET)
#define SW_API_SWITCH_RESET (1 + SW_API_INIT_OFFSET)
#define SW_API_SSDK_CFG (2 + SW_API_INIT_OFFSET)
#define SW_API_MODULE_FUNC_CTRL_SET (3 + SW_API_INIT_OFFSET)
#define SW_API_MODULE_FUNC_CTRL_GET (4 + SW_API_INIT_OFFSET)
/*port ctrl*/
#define SW_API_PORT_OFFSET 30
#define SW_API_PT_DUPLEX_GET (0 + SW_API_PORT_OFFSET)
#define SW_API_PT_DUPLEX_SET (1 + SW_API_PORT_OFFSET)
#define SW_API_PT_SPEED_GET (2 + SW_API_PORT_OFFSET)
#define SW_API_PT_SPEED_SET (3 + SW_API_PORT_OFFSET)
#define SW_API_PT_AN_ADV_GET (4 + SW_API_PORT_OFFSET)
#define SW_API_PT_AN_ADV_SET (5 + SW_API_PORT_OFFSET)
#define SW_API_PT_AN_GET (6 + SW_API_PORT_OFFSET)
#define SW_API_PT_AN_ENABLE (7 + SW_API_PORT_OFFSET)
#define SW_API_PT_AN_RESTART (8 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_HDR_SET (9 + SW_API_PORT_OFFSET)
#define SW_API_PT_HDR_GET (10 + SW_API_PORT_OFFSET)
#define SW_API_PT_FLOWCTRL_SET (11 + SW_API_PORT_OFFSET)
#define SW_API_PT_FLOWCTRL_GET (12 + SW_API_PORT_OFFSET)
#define SW_API_PT_FLOWCTRL_MODE_SET (13 + SW_API_PORT_OFFSET)
#define SW_API_PT_FLOWCTRL_MODE_GET (14 + SW_API_PORT_OFFSET)
#define SW_API_PT_POWERSAVE_SET (15 + SW_API_PORT_OFFSET)
#define SW_API_PT_POWERSAVE_GET (16 + SW_API_PORT_OFFSET)
/*qca808x_start*/
#define SW_API_PT_HIBERNATE_SET (17 + SW_API_PORT_OFFSET)
#define SW_API_PT_HIBERNATE_GET (18 + SW_API_PORT_OFFSET)
#define SW_API_PT_CDT (19 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_TXHDR_SET (20 + SW_API_PORT_OFFSET)
#define SW_API_PT_TXHDR_GET (21 + SW_API_PORT_OFFSET)
#define SW_API_PT_RXHDR_SET (22 + SW_API_PORT_OFFSET)
#define SW_API_PT_RXHDR_GET (23 + SW_API_PORT_OFFSET)
#define SW_API_HEADER_TYPE_SET (24 + SW_API_PORT_OFFSET)
#define SW_API_HEADER_TYPE_GET (25 + SW_API_PORT_OFFSET)
#define SW_API_TXMAC_STATUS_SET (26 + SW_API_PORT_OFFSET)
#define SW_API_TXMAC_STATUS_GET (27 + SW_API_PORT_OFFSET)
#define SW_API_RXMAC_STATUS_SET (28 + SW_API_PORT_OFFSET)
#define SW_API_RXMAC_STATUS_GET (29 + SW_API_PORT_OFFSET)
#define SW_API_TXFC_STATUS_SET (30 + SW_API_PORT_OFFSET)
#define SW_API_TXFC_STATUS_GET (31 + SW_API_PORT_OFFSET)
#define SW_API_RXFC_STATUS_SET (32 + SW_API_PORT_OFFSET)
#define SW_API_RXFC_STATUS_GET (33 + SW_API_PORT_OFFSET)
#define SW_API_BP_STATUS_SET (34 + SW_API_PORT_OFFSET)
#define SW_API_BP_STATUS_GET (35 + SW_API_PORT_OFFSET)
#define SW_API_PT_LINK_MODE_SET (36 + SW_API_PORT_OFFSET)
#define SW_API_PT_LINK_MODE_GET (37 + SW_API_PORT_OFFSET)
/*qca808x_start*/
#define SW_API_PT_LINK_STATUS_GET (38 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_MAC_LOOPBACK_SET (39+ SW_API_PORT_OFFSET)
#define SW_API_PT_MAC_LOOPBACK_GET (40+ SW_API_PORT_OFFSET)
#define SW_API_PTS_LINK_STATUS_GET (41 + SW_API_PORT_OFFSET)
#define SW_API_PT_CONGESTION_DROP_SET (42+ SW_API_PORT_OFFSET)
#define SW_API_PT_CONGESTION_DROP_GET (43+ SW_API_PORT_OFFSET)
#define SW_API_PT_RING_FLOW_CTRL_THRES_SET (44+ SW_API_PORT_OFFSET)
#define SW_API_PT_RING_FLOW_CTRL_THRES_GET (45+ SW_API_PORT_OFFSET)
/*qca808x_start*/
#define SW_API_PT_8023AZ_SET (46 + SW_API_PORT_OFFSET)
#define SW_API_PT_8023AZ_GET (47 + SW_API_PORT_OFFSET)
#define SW_API_PT_MDIX_SET (48 + SW_API_PORT_OFFSET)
#define SW_API_PT_MDIX_GET (49 + SW_API_PORT_OFFSET)
#define SW_API_PT_MDIX_STATUS_GET (50 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_COMBO_PREFER_MEDIUM_SET (51 + SW_API_PORT_OFFSET)
#define SW_API_PT_COMBO_PREFER_MEDIUM_GET (52 + SW_API_PORT_OFFSET)
#define SW_API_PT_COMBO_MEDIUM_STATUS_GET (53 + SW_API_PORT_OFFSET)
#define SW_API_PT_COMBO_FIBER_MODE_SET (54 + SW_API_PORT_OFFSET)
#define SW_API_PT_COMBO_FIBER_MODE_GET (55 + SW_API_PORT_OFFSET)
/*qca808x_start*/
#define SW_API_PT_LOCAL_LOOPBACK_SET (56 + SW_API_PORT_OFFSET)
#define SW_API_PT_LOCAL_LOOPBACK_GET (57 + SW_API_PORT_OFFSET)
#define SW_API_PT_REMOTE_LOOPBACK_SET (58 + SW_API_PORT_OFFSET)
#define SW_API_PT_REMOTE_LOOPBACK_GET (59 + SW_API_PORT_OFFSET)
#define SW_API_PT_RESET (60 + SW_API_PORT_OFFSET)
#define SW_API_PT_POWER_OFF (61 + SW_API_PORT_OFFSET)
#define SW_API_PT_POWER_ON (62 + SW_API_PORT_OFFSET)
#define SW_API_PT_MAGIC_FRAME_MAC_SET (63 + SW_API_PORT_OFFSET)
#define SW_API_PT_MAGIC_FRAME_MAC_GET (64 + SW_API_PORT_OFFSET)
#define SW_API_PT_PHY_ID_GET (65 + SW_API_PORT_OFFSET)
#define SW_API_PT_WOL_STATUS_SET (66 + SW_API_PORT_OFFSET)
#define SW_API_PT_WOL_STATUS_GET (67 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_INTERFACE_MODE_SET (68 + SW_API_PORT_OFFSET)
#define SW_API_PT_INTERFACE_MODE_GET (69 + SW_API_PORT_OFFSET)
/*qca808x_start*/
#define SW_API_PT_INTERFACE_MODE_STATUS_GET (70 + SW_API_PORT_OFFSET)
#define SW_API_DEBUG_PHYCOUNTER_SET (71 + SW_API_PORT_OFFSET)
#define SW_API_DEBUG_PHYCOUNTER_GET (72 + SW_API_PORT_OFFSET)
#define SW_API_DEBUG_PHYCOUNTER_SHOW (73 + SW_API_PORT_OFFSET)
/*qca808x_end*/
#define SW_API_PT_INTERFACE_MODE_APPLY (74 + SW_API_PORT_OFFSET)
#define SW_API_PT_INTERFACE_3AZ_STATUS_SET (75 + SW_API_PORT_OFFSET)
#define SW_API_PT_INTERFACE_3AZ_STATUS_GET (76 + SW_API_PORT_OFFSET)
#define SW_API_PT_PROMISC_MODE_SET (77 + SW_API_PORT_OFFSET)
#define SW_API_PT_PROMISC_MODE_GET (78 + SW_API_PORT_OFFSET)
#define SW_API_PT_INTERFACE_EEE_CFG_SET (79 + SW_API_PORT_OFFSET)
#define SW_API_PT_INTERFACE_EEE_CFG_GET (80 + SW_API_PORT_OFFSET)
#define SW_API_PT_SWITCH_PORT_LOOPBACK_SET (81 + SW_API_PORT_OFFSET)
#define SW_API_PT_SWITCH_PORT_LOOPBACK_GET (82 + SW_API_PORT_OFFSET)
/*vlan*/
#define SW_API_VLAN_OFFSET 130
#define SW_API_VLAN_ADD (0 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_DEL (1 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_MEM_UPDATE (2 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_FIND (3 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_NEXT (4 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_APPEND (5 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_FLUSH (6 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_FID_SET (7 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_FID_GET (8 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_MEMBER_ADD (9 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_MEMBER_DEL (10 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_LEARN_STATE_SET (11 + SW_API_VLAN_OFFSET)
#define SW_API_VLAN_LEARN_STATE_GET (12 + SW_API_VLAN_OFFSET)
#define SW_API_LAN_WAN_CFG_SET (13 + SW_API_VLAN_OFFSET)
#define SW_API_LAN_WAN_CFG_GET (14 + SW_API_VLAN_OFFSET)
/*port ctrl extend*/
#define SW_API_PORT_EXT_OFFSET 160
#define SW_API_PT_MTU_SET (0 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_MTU_GET (1 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_MRU_SET (2 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_MRU_GET (3 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_SOURCE_FILTER_GET (4 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_SOURCE_FILTER_SET (5 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_FRAME_MAX_SIZE_GET (6 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_FRAME_MAX_SIZE_SET (7 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_SOURCE_FILTER_CONFIG_GET (8 + SW_API_PORT_EXT_OFFSET)
#define SW_API_PT_SOURCE_FILTER_CONFIG_SET (9 + SW_API_PORT_EXT_OFFSET)
/*portvlan*/
#define SW_API_PORTVLAN_OFFSET 200
#define SW_API_PT_ING_MODE_GET (0 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_ING_MODE_SET (1 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_EG_MODE_GET (2 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_EG_MODE_SET (3 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_MEM_ADD (4 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_MEM_DEL (5 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_MEM_UPDATE (6 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_MEM_GET (7 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_VID_GET (8 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_VID_SET (9 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_FORCE_DEF_VID_SET (10 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_FORCE_DEF_VID_GET (11 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_FORCE_PORTVLAN_SET (12 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_FORCE_PORTVLAN_GET (13 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_NESTVLAN_SET (14 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_NESTVLAN_GET (15 + SW_API_PORTVLAN_OFFSET)
#define SW_API_NESTVLAN_TPID_SET (16 + SW_API_PORTVLAN_OFFSET)
#define SW_API_NESTVLAN_TPID_GET (17 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_IN_VLAN_MODE_SET (18 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_IN_VLAN_MODE_GET (19 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_TLS_SET (20 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_TLS_GET (21 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_PRI_PROPAGATION_SET (22 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_PRI_PROPAGATION_GET (23 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_SVID_SET (24 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_SVID_GET (25 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_CVID_SET (26 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEF_CVID_GET (27 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_PROPAGATION_SET (28 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_PROPAGATION_GET (29 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ADD (30 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_DEL (31 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_GET (32 + SW_API_PORTVLAN_OFFSET)
#define SW_API_QINQ_MODE_SET (33 + SW_API_PORTVLAN_OFFSET)
#define SW_API_QINQ_MODE_GET (34 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_QINQ_ROLE_SET (35 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_QINQ_ROLE_GET (36 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ITERATE (37 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_MAC_VLAN_XLT_SET (38 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_MAC_VLAN_XLT_GET (39 + SW_API_PORTVLAN_OFFSET)
#define SW_API_NETISOLATE_SET (40 + SW_API_PORTVLAN_OFFSET)
#define SW_API_NETISOLATE_GET (41 + SW_API_PORTVLAN_OFFSET)
#define SW_API_EG_FLTR_BYPASS_EN_SET (42 + SW_API_PORTVLAN_OFFSET)
#define SW_API_EG_FLTR_BYPASS_EN_GET (43 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VRF_ID_SET (44 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VRF_ID_GET (45 + SW_API_PORTVLAN_OFFSET)
#define SW_API_GLOBAL_QINQ_MODE_SET (46 + SW_API_PORTVLAN_OFFSET)
#define SW_API_GLOBAL_QINQ_MODE_GET (47 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PORT_QINQ_MODE_SET (48 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PORT_QINQ_MODE_GET (49 + SW_API_PORTVLAN_OFFSET)
#define SW_API_TPID_SET (50 + SW_API_PORTVLAN_OFFSET)
#define SW_API_TPID_GET (51 + SW_API_PORTVLAN_OFFSET)
#define SW_API_EGRESS_TPID_SET (52 + SW_API_PORTVLAN_OFFSET)
#define SW_API_EGRESS_TPID_GET (53 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_INGRESS_VLAN_FILTER_SET (54 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_INGRESS_VLAN_FILTER_GET (55 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEFAULT_VLANTAG_SET (56 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_DEFAULT_VLANTAG_GET (57 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_TAG_PROPAGATION_SET (58 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_TAG_PROPAGATION_GET (59 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLANTAG_EGMODE_SET (60 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLANTAG_EGMODE_GET (61 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_XLT_MISS_CMD_SET (62 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_XLT_MISS_CMD_GET (63 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VSI_EGMODE_SET (64 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VSI_EGMODE_GET (65 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_SET (66 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLANTAG_VSI_EGMODE_EN_GET (67 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ADV_ADD (68 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ADV_DEL (69 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ADV_GETFIRST (70 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_TRANS_ADV_GETNEXT (71 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_COUNTER_GET (72 + SW_API_PORTVLAN_OFFSET)
#define SW_API_PT_VLAN_COUNTER_CLEANUP (73 + SW_API_PORTVLAN_OFFSET)
/*fdb*/
#define SW_API_FDB_OFFSET 300
#define SW_API_FDB_ADD (0 + SW_API_FDB_OFFSET)
#define SW_API_FDB_DELALL (1 + SW_API_FDB_OFFSET)
#define SW_API_FDB_DELPORT (2 + SW_API_FDB_OFFSET)
#define SW_API_FDB_DELMAC (3 + SW_API_FDB_OFFSET)
#define SW_API_FDB_FIRST (4 + SW_API_FDB_OFFSET)
#define SW_API_FDB_NEXT (5 + SW_API_FDB_OFFSET)
#define SW_API_FDB_FIND (6 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_LEARN_SET (7 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_LEARN_GET (8 + SW_API_FDB_OFFSET)
#define SW_API_FDB_AGE_CTRL_SET (9 + SW_API_FDB_OFFSET)
#define SW_API_FDB_AGE_CTRL_GET (10 + SW_API_FDB_OFFSET)
#define SW_API_FDB_AGE_TIME_SET (11 + SW_API_FDB_OFFSET)
#define SW_API_FDB_AGE_TIME_GET (12 + SW_API_FDB_OFFSET)
#define SW_API_FDB_ITERATE (13 + SW_API_FDB_OFFSET)
#define SW_API_FDB_EXTEND_NEXT (14 + SW_API_FDB_OFFSET)
#define SW_API_PT_FDB_LEARN_LIMIT_SET (15 + SW_API_FDB_OFFSET)
#define SW_API_PT_FDB_LEARN_LIMIT_GET (16 + SW_API_FDB_OFFSET)
#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET (17 + SW_API_FDB_OFFSET)
#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET (18 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_LIMIT_SET (19 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_LIMIT_GET (20 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_EXCEED_CMD_SET (21 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_EXCEED_CMD_GET (22 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RESV_ADD (23 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RESV_DEL (24 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RESV_FIND (25 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RESV_ITERATE (26 + SW_API_FDB_OFFSET)
#define SW_API_FDB_EXTEND_FIRST (27 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_LEARN_STATIC_SET (28 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_LEARN_STATIC_GET (29 + SW_API_FDB_OFFSET)
#define SW_API_FDB_TRANSFER (30 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PORT_ADD (31 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PORT_DEL (32 + SW_API_FDB_OFFSET)
#define SW_API_FDB_VLAN_IVL_SVL_SET (33 + SW_API_FDB_OFFSET)
#define SW_API_FDB_VLAN_IVL_SVL_GET (34 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RFS_SET (35 + SW_API_FDB_OFFSET)
#define SW_API_FDB_RFS_DEL (36 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_CTRL_SET (37 + SW_API_FDB_OFFSET)
#define SW_API_FDB_LEARN_CTRL_GET (38 + SW_API_FDB_OFFSET)
#define SW_API_PT_FDB_LEARN_COUNTER_GET (39 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_NEWADDR_LEARN_SET (40 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_NEWADDR_LEARN_GET (41 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_STAMOVE_SET (42 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_STAMOVE_GET (43 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_MACLIMIT_CTRL_SET (44 + SW_API_FDB_OFFSET)
#define SW_API_FDB_PT_MACLIMIT_CTRL_GET (45 + SW_API_FDB_OFFSET)
#define SW_API_FDB_DEL_BY_FID (46 + SW_API_FDB_OFFSET)
/*acl*/
#define SW_API_ACL_OFFSET 400
#define SW_API_ACL_LIST_CREAT (0 + SW_API_ACL_OFFSET)
#define SW_API_ACL_LIST_DESTROY (1 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_ADD (2 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_DELETE (3 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_QUERY (4 + SW_API_ACL_OFFSET)
#define SW_API_ACL_LIST_BIND (5 + SW_API_ACL_OFFSET)
#define SW_API_ACL_LIST_UNBIND (6 + SW_API_ACL_OFFSET)
#define SW_API_ACL_STATUS_SET (7 + SW_API_ACL_OFFSET)
#define SW_API_ACL_STATUS_GET (8 + SW_API_ACL_OFFSET)
#define SW_API_ACL_LIST_DUMP (9 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_DUMP (10 + SW_API_ACL_OFFSET)
#define SW_API_ACL_PT_UDF_PROFILE_SET (11 + SW_API_ACL_OFFSET)
#define SW_API_ACL_PT_UDF_PROFILE_GET (12 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_ACTIVE (13 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_DEACTIVE (14 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_SRC_FILTER_STS_SET (15 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_SRC_FILTER_STS_GET (16 + SW_API_ACL_OFFSET)
#define SW_API_ACL_RULE_GET_OFFSET (17 + SW_API_ACL_OFFSET)
#define SW_API_ACL_UDF_SET (18 + SW_API_ACL_OFFSET)
#define SW_API_ACL_UDF_GET (19 + SW_API_ACL_OFFSET)
/*qos*/
#define SW_API_QOS_OFFSET 500
#define SW_API_QOS_SCH_MODE_SET (0 + SW_API_QOS_OFFSET)
#define SW_API_QOS_SCH_MODE_GET (1 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QU_TX_BUF_ST_SET (2 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QU_TX_BUF_ST_GET (3 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QU_TX_BUF_NR_SET (4 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QU_TX_BUF_NR_GET (5 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_TX_BUF_ST_SET (6 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_TX_BUF_ST_GET (7 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_TX_BUF_NR_SET (8 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_TX_BUF_NR_GET (9 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_RX_BUF_NR_SET (10 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_RX_BUF_NR_GET (11 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_MODE_SET (12 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_MODE_GET (13 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_MODE_PRI_SET (14 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_MODE_PRI_GET (15 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_DEF_UP_SET (16 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_DEF_UP_GET (17 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_SCH_MODE_SET (18 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_SCH_MODE_GET (19 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_DEF_SPRI_SET (20 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_DEF_SPRI_GET (21 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_DEF_CPRI_SET (22 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_DEF_CPRI_GET (23 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_FORCE_SPRI_ST_SET (24 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_FORCE_SPRI_ST_GET (25 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_FORCE_CPRI_ST_SET (26 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_FORCE_CPRI_ST_GET (27 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QUEUE_REMARK_SET (28 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QUEUE_REMARK_GET (29 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_RED_EN_SET (30 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PT_RED_EN_GET (31 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_GROUP_GET (32 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_GROUP_SET (33 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_PRI_GET (34 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_PRI_SET (35 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_REMARK_GET (36 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_REMARK_SET (37 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PCP_MAP_GET (38 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PCP_MAP_SET (39 + SW_API_QOS_OFFSET)
#define SW_API_QOS_FLOW_MAP_GET (40 + SW_API_QOS_OFFSET)
#define SW_API_QOS_FLOW_MAP_SET (41 + SW_API_QOS_OFFSET)
#define SW_API_QOS_DSCP_MAP_GET (42 + SW_API_QOS_OFFSET)
#define SW_API_QOS_DSCP_MAP_SET (43 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QUEUE_SCHEDULER_GET (44 + SW_API_QOS_OFFSET)
#define SW_API_QOS_QUEUE_SCHEDULER_SET (45 + SW_API_QOS_OFFSET)
#define SW_API_QOS_RING_QUEUE_MAP_GET (46 + SW_API_QOS_OFFSET)
#define SW_API_QOS_RING_QUEUE_MAP_SET (47 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_QUEUES_GET (48 + SW_API_QOS_OFFSET)
#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_GET (49 + SW_API_QOS_OFFSET)
#define SW_API_QOS_SCHEDULER_DEQUEU_CTRL_SET (50 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_SCHEDULER_CFG_RESET (51 + SW_API_QOS_OFFSET)
#define SW_API_QOS_PORT_SCHEDULER_RESOURCE_GET (52 + SW_API_QOS_OFFSET)
/* igmp */
#define SW_API_IGMP_OFFSET 600
#define SW_API_PT_IGMPS_MODE_SET (0 + SW_API_IGMP_OFFSET)
#define SW_API_PT_IGMPS_MODE_GET (1 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_MLD_CMD_SET (2 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_MLD_CMD_GET (3 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_PT_JOIN_SET (4 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_PT_JOIN_GET (5 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_PT_LEAVE_SET (6 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_PT_LEAVE_GET (7 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_RP_SET (8 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_RP_GET (9 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_CREAT_SET (10 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_CREAT_GET (11 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_STATIC_SET (12 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_STATIC_GET (13 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_LEAKY_SET (14 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_LEAKY_GET (15 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_V3_SET (16 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_V3_GET (17 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_QUEUE_SET (18 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_ENTRY_QUEUE_GET (19 + SW_API_IGMP_OFFSET)
#define SW_API_PT_IGMP_LEARN_LIMIT_SET (20 + SW_API_IGMP_OFFSET)
#define SW_API_PT_IGMP_LEARN_LIMIT_GET (21 + SW_API_IGMP_OFFSET)
#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET (22 + SW_API_IGMP_OFFSET)
#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET (23 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_SG_ENTRY_SET (24 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_SG_ENTRY_CLEAR (25 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_SG_ENTRY_SHOW (26 + SW_API_IGMP_OFFSET)
#define SW_API_IGMP_SG_ENTRY_QUERY (27 + SW_API_IGMP_OFFSET)
/* leaky */
#define SW_API_LEAKY_OFFSET 700
#define SW_API_UC_LEAKY_MODE_SET (0 + SW_API_LEAKY_OFFSET)
#define SW_API_UC_LEAKY_MODE_GET (1 + SW_API_LEAKY_OFFSET)
#define SW_API_MC_LEAKY_MODE_SET (2 + SW_API_LEAKY_OFFSET)
#define SW_API_MC_LEAKY_MODE_GET (3 + SW_API_LEAKY_OFFSET)
#define SW_API_ARP_LEAKY_MODE_SET (4 + SW_API_LEAKY_OFFSET)
#define SW_API_ARP_LEAKY_MODE_GET (5 + SW_API_LEAKY_OFFSET)
#define SW_API_PT_UC_LEAKY_MODE_SET (6 + SW_API_LEAKY_OFFSET)
#define SW_API_PT_UC_LEAKY_MODE_GET (7 + SW_API_LEAKY_OFFSET)
#define SW_API_PT_MC_LEAKY_MODE_SET (8 + SW_API_LEAKY_OFFSET)
#define SW_API_PT_MC_LEAKY_MODE_GET (9 + SW_API_LEAKY_OFFSET)
/*mirror*/
#define SW_API_MIR_OFFSET 800
#define SW_API_MIRROR_ANALY_PT_SET (0 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_ANALY_PT_GET (1 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_IN_PT_SET (2 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_IN_PT_GET (3 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_EG_PT_SET (4 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_EG_PT_GET (5 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_ANALYSIS_CONFIG_SET (6 + SW_API_MIR_OFFSET)
#define SW_API_MIRROR_ANALYSIS_CONFIG_GET (7 + SW_API_MIR_OFFSET)
/*rate*/
#define SW_API_RATE_OFFSET 900
#define SW_API_RATE_QU_EGRL_SET (0 + SW_API_RATE_OFFSET)
#define SW_API_RATE_QU_EGRL_GET (1 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_EGRL_SET (2 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_EGRL_GET (3 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_INRL_SET (4 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_INRL_GET (5 + SW_API_RATE_OFFSET)
#define SW_API_STORM_CTRL_FRAME_SET (6 + SW_API_RATE_OFFSET)
#define SW_API_STORM_CTRL_FRAME_GET (7 + SW_API_RATE_OFFSET)
#define SW_API_STORM_CTRL_RATE_SET (8 + SW_API_RATE_OFFSET)
#define SW_API_STORM_CTRL_RATE_GET (9 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PORT_POLICER_SET (10 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PORT_POLICER_GET (11 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PORT_SHAPER_SET (12 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PORT_SHAPER_GET (13 + SW_API_RATE_OFFSET)
#define SW_API_RATE_QUEUE_SHAPER_SET (14 + SW_API_RATE_OFFSET)
#define SW_API_RATE_QUEUE_SHAPER_GET (15 + SW_API_RATE_OFFSET)
#define SW_API_RATE_ACL_POLICER_SET (16 + SW_API_RATE_OFFSET)
#define SW_API_RATE_ACL_POLICER_GET (17 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_ADDRATEBYTE_SET (18 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_ADDRATEBYTE_GET (19 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_GOL_FLOW_EN_SET (20 + SW_API_RATE_OFFSET)
#define SW_API_RATE_PT_GOL_FLOW_EN_GET (21 + SW_API_RATE_OFFSET)
/*stp*/
#define SW_API_STP_OFFSET 1000
#define SW_API_STP_PT_STATE_SET (0 + SW_API_STP_OFFSET)
#define SW_API_STP_PT_STATE_GET (1 + SW_API_STP_OFFSET)
/*mib*/
#define SW_API_MIB_OFFSET 1100
#define SW_API_PT_MIB_GET (0 + SW_API_MIB_OFFSET)
#define SW_API_MIB_STATUS_SET (1 + SW_API_MIB_OFFSET)
#define SW_API_MIB_STATUS_GET (2 + SW_API_MIB_OFFSET)
#define SW_API_PT_MIB_FLUSH_COUNTERS (3+ SW_API_MIB_OFFSET)
#define SW_API_MIB_CPU_KEEP_SET (4+ SW_API_MIB_OFFSET)
#define SW_API_MIB_CPU_KEEP_GET (5+ SW_API_MIB_OFFSET)
#define SW_API_PT_XGMIB_GET (6+ SW_API_MIB_OFFSET)
#define SW_API_PT_MIB_COUNTER_GET (7+ SW_API_MIB_OFFSET)
/*misc*/
#define SW_API_MISC_OFFSET 1200
#define SW_API_ARP_STATUS_SET (0 + SW_API_MISC_OFFSET)
#define SW_API_ARP_STATUS_GET (1 + SW_API_MISC_OFFSET)
#define SW_API_FRAME_MAX_SIZE_SET (2 + SW_API_MISC_OFFSET)
#define SW_API_FRAME_MAX_SIZE_GET (3 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_SA_CMD_SET (4 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_SA_CMD_GET (5 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_UC_FILTER_SET (6 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_UC_FILTER_GET (7 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_MC_FILTER_SET (8 + SW_API_MISC_OFFSET)
#define SW_API_PT_UNK_MC_FILTER_GET (9 + SW_API_MISC_OFFSET)
#define SW_API_PT_BC_FILTER_SET (10 + SW_API_MISC_OFFSET)
#define SW_API_PT_BC_FILTER_GET (11 + SW_API_MISC_OFFSET)
#define SW_API_CPU_PORT_STATUS_SET (12 + SW_API_MISC_OFFSET)
#define SW_API_CPU_PORT_STATUS_GET (13 + SW_API_MISC_OFFSET)
#define SW_API_BC_TO_CPU_PORT_SET (14 + SW_API_MISC_OFFSET)
#define SW_API_BC_TO_CPU_PORT_GET (15 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_CMD_SET (16 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_CMD_GET (17 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_STATUS_SET (18 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_STATUS_GET (19 + SW_API_MISC_OFFSET)
#define SW_API_PT_DHCP_SET (20 + SW_API_MISC_OFFSET)
#define SW_API_PT_DHCP_GET (21 + SW_API_MISC_OFFSET)
#define SW_API_ARP_CMD_SET (22 + SW_API_MISC_OFFSET)
#define SW_API_ARP_CMD_GET (23 + SW_API_MISC_OFFSET)
#define SW_API_EAPOL_CMD_SET (24 + SW_API_MISC_OFFSET)
#define SW_API_EAPOL_CMD_GET (25 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_ADD (26 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_DEL (27 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_GET (28 + SW_API_MISC_OFFSET)
#define SW_API_EAPOL_STATUS_SET (29 + SW_API_MISC_OFFSET)
#define SW_API_EAPOL_STATUS_GET (30 + SW_API_MISC_OFFSET)
#define SW_API_RIPV1_STATUS_SET (31 + SW_API_MISC_OFFSET)
#define SW_API_RIPV1_STATUS_GET (32 + SW_API_MISC_OFFSET)
#define SW_API_PT_ARP_REQ_STATUS_SET (33 + SW_API_MISC_OFFSET)
#define SW_API_PT_ARP_REQ_STATUS_GET (34 + SW_API_MISC_OFFSET)
#define SW_API_PT_ARP_ACK_STATUS_SET (35 + SW_API_MISC_OFFSET)
#define SW_API_PT_ARP_ACK_STATUS_GET (36 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_TABLE_ADD (37 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_TABLE_DEL (38 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_TABLE_GET (39 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_ID_SET (40 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_SESSION_ID_GET (41 + SW_API_MISC_OFFSET)
#define SW_API_INTR_MASK_SET (42 + SW_API_MISC_OFFSET)
#define SW_API_INTR_MASK_GET (43 + SW_API_MISC_OFFSET)
#define SW_API_INTR_STATUS_GET (44 + SW_API_MISC_OFFSET)
#define SW_API_INTR_STATUS_CLEAR (45 + SW_API_MISC_OFFSET)
#define SW_API_INTR_PORT_LINK_MASK_SET (46 + SW_API_MISC_OFFSET)
#define SW_API_INTR_PORT_LINK_MASK_GET (47 + SW_API_MISC_OFFSET)
#define SW_API_INTR_PORT_LINK_STATUS_GET (48 + SW_API_MISC_OFFSET)
#define SW_API_INTR_MASK_MAC_LINKCHG_SET (49 + SW_API_MISC_OFFSET)
#define SW_API_INTR_MASK_MAC_LINKCHG_GET (50 + SW_API_MISC_OFFSET)
#define SW_API_INTR_STATUS_MAC_LINKCHG_GET (51 + SW_API_MISC_OFFSET)
#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR (52 + SW_API_MISC_OFFSET)
#define SW_API_CPU_VID_EN_SET (53 + SW_API_MISC_OFFSET)
#define SW_API_CPU_VID_EN_GET (54 + SW_API_MISC_OFFSET)
#define SW_API_RTD_PPPOE_EN_SET (55 + SW_API_MISC_OFFSET)
#define SW_API_RTD_PPPOE_EN_GET (56 + SW_API_MISC_OFFSET)
#define SW_API_GLOBAL_MACADDR_SET (57 + SW_API_MISC_OFFSET)
#define SW_API_GLOBAL_MACADDR_GET (58 + SW_API_MISC_OFFSET)
#define SW_API_LLDP_STATUS_SET (59 + SW_API_MISC_OFFSET)
#define SW_API_LLDP_STATUS_GET (60 + SW_API_MISC_OFFSET)
#define SW_API_FRAME_CRC_RESERVE_SET (61 + SW_API_MISC_OFFSET)
#define SW_API_FRAME_CRC_RESERVE_GET (62 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_EN_SET (63 + SW_API_MISC_OFFSET)
#define SW_API_PPPOE_EN_GET (64 + SW_API_MISC_OFFSET)
#define SW_API_DEBUG_PORT_COUNTER_ENABLE (65 + SW_API_MISC_OFFSET)
#define SW_API_DEBUG_PORT_COUNTER_STATUS_GET (66 + SW_API_MISC_OFFSET)
/*led*/
#define SW_API_LED_OFFSET 1300
#define SW_API_LED_PATTERN_SET (0 + SW_API_LED_OFFSET)
#define SW_API_LED_PATTERN_GET (1 + SW_API_LED_OFFSET)
/* cosmap */
#define SW_API_COSMAP_OFFSET 1400
#define SW_API_COSMAP_UP_QU_SET (0 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_QU_GET (1 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_QU_SET (2 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_QU_GET (3 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_PRI_SET (4 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_PRI_GET (5 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_DP_SET (6 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_DP_GET (7 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_PRI_SET (8 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_PRI_GET (9 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_DP_SET (10 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_DP_GET (11 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_PRI_TO_QU_SET (12 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_PRI_TO_QU_GET (13 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_PRI_TO_EHQU_SET (14 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_PRI_TO_EHQU_GET (15 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_EG_REMARK_SET (16 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_EG_REMARK_GET (17 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_EHPRI_SET (18 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_EHPRI_GET (19 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_EHDP_SET (20 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_DSCP_TO_EHDP_GET (21 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_EHPRI_SET (22 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_EHPRI_GET (23 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_EHDP_SET (24 + SW_API_COSMAP_OFFSET)
#define SW_API_COSMAP_UP_TO_EHDP_GET (25 + SW_API_COSMAP_OFFSET)
/* sec */
#define SW_API_SEC_OFFSET 1500
#define SW_API_SEC_NORM_SET (0 + SW_API_SEC_OFFSET)
#define SW_API_SEC_NORM_GET (1 + SW_API_SEC_OFFSET)
#define SW_API_SEC_MAC_SET (2 + SW_API_SEC_OFFSET)
#define SW_API_SEC_MAC_GET (3 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP_SET (4 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP_GET (5 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP4_SET (6 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP4_GET (7 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP6_SET (8 + SW_API_SEC_OFFSET)
#define SW_API_SEC_IP6_GET (9 + SW_API_SEC_OFFSET)
#define SW_API_SEC_TCP_SET (10 + SW_API_SEC_OFFSET)
#define SW_API_SEC_TCP_GET (11 + SW_API_SEC_OFFSET)
#define SW_API_SEC_UDP_SET (12 + SW_API_SEC_OFFSET)
#define SW_API_SEC_UDP_GET (13 + SW_API_SEC_OFFSET)
#define SW_API_SEC_ICMP4_SET (14 + SW_API_SEC_OFFSET)
#define SW_API_SEC_ICMP4_GET (15 + SW_API_SEC_OFFSET)
#define SW_API_SEC_ICMP6_SET (16 + SW_API_SEC_OFFSET)
#define SW_API_SEC_ICMP6_GET (17 + SW_API_SEC_OFFSET)
#define SW_API_SEC_L3_PARSER_CTRL_GET (18 + SW_API_SEC_OFFSET)
#define SW_API_SEC_L3_PARSER_CTRL_SET (19 + SW_API_SEC_OFFSET)
#define SW_API_SEC_L4_PARSER_CTRL_GET (20 + SW_API_SEC_OFFSET)
#define SW_API_SEC_L4_PARSER_CTRL_SET (21 + SW_API_SEC_OFFSET)
#define SW_API_SEC_EXP_CTRL_GET (22 + SW_API_SEC_OFFSET)
#define SW_API_SEC_EXP_CTRL_SET (23 + SW_API_SEC_OFFSET)
/* ip */
#define SW_API_IP_OFFSET 1600
#define SW_API_IP_HOST_ADD (0 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_DEL (1 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_GET (2 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_NEXT (3 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_COUNTER_BIND (4 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_PPPOE_BIND (5 + SW_API_IP_OFFSET)
#define SW_API_IP_PT_ARP_LEARN_SET (6 + SW_API_IP_OFFSET)
#define SW_API_IP_PT_ARP_LEARN_GET (7 + SW_API_IP_OFFSET)
#define SW_API_IP_ARP_LEARN_SET (8 + SW_API_IP_OFFSET)
#define SW_API_IP_ARP_LEARN_GET (9 + SW_API_IP_OFFSET)
#define SW_API_IP_SOURCE_GUARD_SET (10 + SW_API_IP_OFFSET)
#define SW_API_IP_SOURCE_GUARD_GET (11 + SW_API_IP_OFFSET)
#define SW_API_IP_ARP_GUARD_SET (12 + SW_API_IP_OFFSET)
#define SW_API_IP_ARP_GUARD_GET (13 + SW_API_IP_OFFSET)
#define SW_API_IP_ROUTE_STATUS_SET (14 + SW_API_IP_OFFSET)
#define SW_API_IP_ROUTE_STATUS_GET (15 + SW_API_IP_OFFSET)
#define SW_API_IP_INTF_ENTRY_ADD (16 + SW_API_IP_OFFSET)
#define SW_API_IP_INTF_ENTRY_DEL (17 + SW_API_IP_OFFSET)
#define SW_API_IP_INTF_ENTRY_NEXT (18 + SW_API_IP_OFFSET)
#define SW_API_IP_UNK_SOURCE_CMD_SET (19 + SW_API_IP_OFFSET)
#define SW_API_IP_UNK_SOURCE_CMD_GET (20 + SW_API_IP_OFFSET)
#define SW_API_ARP_UNK_SOURCE_CMD_SET (21 + SW_API_IP_OFFSET)
#define SW_API_ARP_UNK_SOURCE_CMD_GET (22 + SW_API_IP_OFFSET)
#define SW_API_IP_AGE_TIME_SET (23 + SW_API_IP_OFFSET)
#define SW_API_IP_AGE_TIME_GET (24 + SW_API_IP_OFFSET)
#define SW_API_WCMP_HASH_MODE_SET (25 + SW_API_IP_OFFSET)
#define SW_API_WCMP_HASH_MODE_GET (26 + SW_API_IP_OFFSET)
#define SW_API_IP_VRF_BASE_ADDR_SET (27 + SW_API_IP_OFFSET)
#define SW_API_IP_VRF_BASE_ADDR_GET (28 + SW_API_IP_OFFSET)
#define SW_API_IP_VRF_BASE_MASK_SET (29 + SW_API_IP_OFFSET)
#define SW_API_IP_VRF_BASE_MASK_GET (30 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_ROUTE_SET (31 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_ROUTE_GET (32 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_ROUTE_SET (33 + SW_API_IP_OFFSET)
#define SW_API_IP_HOST_ROUTE_GET (34 + SW_API_IP_OFFSET)
#define SW_API_IP_WCMP_ENTRY_SET (35 + SW_API_IP_OFFSET)
#define SW_API_IP_WCMP_ENTRY_GET (36 + SW_API_IP_OFFSET)
#define SW_API_IP_RFS_IP4_SET (37 + SW_API_IP_OFFSET)
#define SW_API_IP_RFS_IP6_SET (38 + SW_API_IP_OFFSET)
#define SW_API_IP_RFS_IP4_DEL (39 + SW_API_IP_OFFSET)
#define SW_API_IP_RFS_IP6_DEL (40 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_FLOW_CMD_SET (41 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_FLOW_CMD_GET (42 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_RT_FLOW_CMD_SET (43 + SW_API_IP_OFFSET)
#define SW_API_IP_DEFAULT_RT_FLOW_CMD_GET (44 + SW_API_IP_OFFSET)
#define SW_API_IP_VIS_ARP_SG_CFG_GET (45 + SW_API_IP_OFFSET)
#define SW_API_IP_VIS_ARP_SG_CFG_SET (46 + SW_API_IP_OFFSET)
#define SW_API_IP_NETWORK_ROUTE_GET (47 + SW_API_IP_OFFSET)
#define SW_API_IP_NETWORK_ROUTE_ADD (48 + SW_API_IP_OFFSET)
#define SW_API_IP_INTF_GET (49 + SW_API_IP_OFFSET)
#define SW_API_IP_INTF_SET (50 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_INTF_GET (51 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_INTF_SET (52 + SW_API_IP_OFFSET)
#define SW_API_IP_NEXTHOP_GET (53 + SW_API_IP_OFFSET)
#define SW_API_IP_NEXTHOP_SET (54 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_SG_SET (55 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_SG_GET (56 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_SG_SET (57 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_SG_GET (58 + SW_API_IP_OFFSET)
#define SW_API_IP_PUB_IP_SET (59 + SW_API_IP_OFFSET)
#define SW_API_IP_PUB_IP_GET (60 + SW_API_IP_OFFSET)
#define SW_API_IP_NETWORK_ROUTE_DEL (61 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_INTF_GET (62 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_INTF_SET (63 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_MAC_GET (64 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_MAC_SET (65 + SW_API_IP_OFFSET)
#define SW_API_IP_ROUTE_MISS_GET (66 + SW_API_IP_OFFSET)
#define SW_API_IP_ROUTE_MISS_SET (67 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_ARP_SG_GET (68 + SW_API_IP_OFFSET)
#define SW_API_IP_PORT_ARP_SG_SET (69 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_MC_MODE_GET (70 + SW_API_IP_OFFSET)
#define SW_API_IP_VSI_MC_MODE_SET (71 + SW_API_IP_OFFSET)
#define SW_API_GLOBAL_CTRL_GET (72 + SW_API_IP_OFFSET)
#define SW_API_GLOBAL_CTRL_SET (73 + SW_API_IP_OFFSET)
/* nat */
#define SW_API_NAT_OFFSET 1700
#define SW_API_NAT_ADD (0 + SW_API_NAT_OFFSET)
#define SW_API_NAT_DEL (1 + SW_API_NAT_OFFSET)
#define SW_API_NAT_GET (2 + SW_API_NAT_OFFSET)
#define SW_API_NAT_NEXT (3 + SW_API_NAT_OFFSET)
#define SW_API_NAT_COUNTER_BIND (4 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_ADD (5 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_DEL (6 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_GET (7 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_NEXT (8 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_COUNTER_BIND (9 + SW_API_NAT_OFFSET)
#define SW_API_NAT_STATUS_SET (10 + SW_API_NAT_OFFSET)
#define SW_API_NAT_STATUS_GET (11 + SW_API_NAT_OFFSET)
#define SW_API_NAT_HASH_MODE_SET (12 + SW_API_NAT_OFFSET)
#define SW_API_NAT_HASH_MODE_GET (13 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_STATUS_SET (14 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_STATUS_GET (15 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_MODE_SET (16 + SW_API_NAT_OFFSET)
#define SW_API_NAPT_MODE_GET (17 + SW_API_NAT_OFFSET)
#define SW_API_PRV_BASE_ADDR_SET (18 + SW_API_NAT_OFFSET)
#define SW_API_PRV_BASE_ADDR_GET (19 + SW_API_NAT_OFFSET)
#define SW_API_PRV_ADDR_MODE_SET (20 + SW_API_NAT_OFFSET)
#define SW_API_PRV_ADDR_MODE_GET (21 + SW_API_NAT_OFFSET)
#define SW_API_PUB_ADDR_ENTRY_ADD (22 + SW_API_NAT_OFFSET)
#define SW_API_PUB_ADDR_ENTRY_DEL (23 + SW_API_NAT_OFFSET)
#define SW_API_PUB_ADDR_ENTRY_NEXT (24 + SW_API_NAT_OFFSET)
#define SW_API_NAT_UNK_SESSION_CMD_SET (25 + SW_API_NAT_OFFSET)
#define SW_API_NAT_UNK_SESSION_CMD_GET (26 + SW_API_NAT_OFFSET)
#define SW_API_PRV_BASE_MASK_SET (27 + SW_API_NAT_OFFSET)
#define SW_API_PRV_BASE_MASK_GET (28 + SW_API_NAT_OFFSET)
#define SW_API_NAT_GLOBAL_SET (29 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_ADD (30 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_DEL (31 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_GET (32 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_NEXT (33 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_COUNTER_BIND (34 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_COOKIE_SET (35 + SW_API_NAT_OFFSET)
#define SW_API_FLOW_RFS_SET (36 + SW_API_NAT_OFFSET)
/* trunk */
#define SW_API_TRUNK_OFFSET 1800
#define SW_API_TRUNK_GROUP_SET (0 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_GROUP_GET (1 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_HASH_SET (2 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_HASH_GET (3 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_MAN_SA_SET (4 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_MAN_SA_GET (5 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_FAILOVER_EN_SET (6 + SW_API_TRUNK_OFFSET)
#define SW_API_TRUNK_FAILOVER_EN_GET (7 + SW_API_TRUNK_OFFSET)
/* Interface Control */
#define SW_API_INTERFACE_OFFSET 1900
#define SW_API_MAC_MODE_SET (0 + SW_API_INTERFACE_OFFSET)
#define SW_API_MAC_MODE_GET (1 + SW_API_INTERFACE_OFFSET)
#define SW_API_PORT_3AZ_STATUS_SET (2 + SW_API_INTERFACE_OFFSET)
#define SW_API_PORT_3AZ_STATUS_GET (3 + SW_API_INTERFACE_OFFSET)
#define SW_API_PHY_MODE_SET (4 + SW_API_INTERFACE_OFFSET)
#define SW_API_PHY_MODE_GET (5 + SW_API_INTERFACE_OFFSET)
#define SW_API_FX100_CTRL_SET (6 + SW_API_INTERFACE_OFFSET)
#define SW_API_FX100_CTRL_GET (7 + SW_API_INTERFACE_OFFSET)
#define SW_API_FX100_STATUS_GET (8 + SW_API_INTERFACE_OFFSET)
#define SW_API_MAC06_EXCH_SET (9 + SW_API_INTERFACE_OFFSET)
#define SW_API_MAC06_EXCH_GET (10 + SW_API_INTERFACE_OFFSET)
/* VSI */
#define SW_API_VSI_OFFSET 2000
#define SW_API_VSI_ALLOC (0 + SW_API_VSI_OFFSET)
#define SW_API_VSI_FREE (1 + SW_API_VSI_OFFSET)
#define SW_API_PORT_VSI_SET (2 + SW_API_VSI_OFFSET)
#define SW_API_PORT_VSI_GET (3 + SW_API_VSI_OFFSET)
#define SW_API_PORT_VLAN_VSI_SET (4 + SW_API_VSI_OFFSET)
#define SW_API_PORT_VLAN_VSI_GET (5 + SW_API_VSI_OFFSET)
#define SW_API_VSI_TBL_DUMP (6 + SW_API_VSI_OFFSET)
#define SW_API_VSI_NEWADDR_LRN_SET (7 + SW_API_VSI_OFFSET)
#define SW_API_VSI_NEWADDR_LRN_GET (8 + SW_API_VSI_OFFSET)
#define SW_API_VSI_STAMOVE_SET (9 + SW_API_VSI_OFFSET)
#define SW_API_VSI_STAMOVE_GET (10 + SW_API_VSI_OFFSET)
#define SW_API_VSI_MEMBER_SET (11 + SW_API_VSI_OFFSET)
#define SW_API_VSI_MEMBER_GET (12 + SW_API_VSI_OFFSET)
#define SW_API_VSI_COUNTER_GET (13 + SW_API_VSI_OFFSET)
#define SW_API_VSI_COUNTER_CLEANUP (14 + SW_API_VSI_OFFSET)
/* qm */
#define SW_API_QM_OFFSET 2100
#define SW_API_UCAST_QUEUE_BASE_PROFILE_SET (0 + SW_API_QM_OFFSET)
#define SW_API_UCAST_QUEUE_BASE_PROFILE_GET (1 + SW_API_QM_OFFSET)
#define SW_API_UCAST_PRIORITY_CLASS_SET (2 + SW_API_QM_OFFSET)
#define SW_API_UCAST_PRIORITY_CLASS_GET (3 + SW_API_QM_OFFSET)
#define SW_API_MCAST_PRIORITY_CLASS_SET (4 + SW_API_QM_OFFSET)
#define SW_API_MCAST_PRIORITY_CLASS_GET (5 + SW_API_QM_OFFSET)
#define SW_API_UCAST_HASH_MAP_SET (6 + SW_API_QM_OFFSET)
#define SW_API_UCAST_HASH_MAP_GET (7 + SW_API_QM_OFFSET)
#define SW_API_UCAST_DFLT_HASH_MAP_SET (8 + SW_API_QM_OFFSET)
#define SW_API_UCAST_DFLT_HASH_MAP_GET (9 + SW_API_QM_OFFSET)
#define SW_API_MCAST_CPUCODE_CLASS_SET (10 + SW_API_QM_OFFSET)
#define SW_API_MCAST_CPUCODE_CLASS_GET (11 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_FLUSH (12 + SW_API_QM_OFFSET)
#define SW_API_AC_CTRL_SET (13 + SW_API_QM_OFFSET)
#define SW_API_AC_CTRL_GET (14 + SW_API_QM_OFFSET)
#define SW_API_AC_PRE_BUFFER_SET (15 + SW_API_QM_OFFSET)
#define SW_API_AC_PRE_BUFFER_GET (16 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_GROUP_SET (17 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_GROUP_GET (18 + SW_API_QM_OFFSET)
#define SW_API_STATIC_THRESH_SET (19 + SW_API_QM_OFFSET)
#define SW_API_STATIC_THRESH_GET (20 + SW_API_QM_OFFSET)
#define SW_API_DYNAMIC_THRESH_SET (21 + SW_API_QM_OFFSET)
#define SW_API_DYNAMIC_THRESH_GET (22 + SW_API_QM_OFFSET)
#define SW_API_GOURP_BUFFER_SET (23 + SW_API_QM_OFFSET)
#define SW_API_GOURP_BUFFER_GET (24 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_CNT_CTRL_GET (25 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_CNT_CTRL_SET (26 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_CNT_GET (27 + SW_API_QM_OFFSET)
#define SW_API_QUEUE_CNT_CLEANUP (28 + SW_API_QM_OFFSET)
#define SW_API_QM_ENQUEUE_CTRL_SET (29 + SW_API_QM_OFFSET)
#define SW_API_QM_ENQUEUE_CTRL_GET (30 + SW_API_QM_OFFSET)
#define SW_API_QM_SOURCE_PROFILE_SET (31 + SW_API_QM_OFFSET)
#define SW_API_QM_SOURCE_PROFILE_GET (32 + SW_API_QM_OFFSET)
/* flow */
#define SW_API_FLOW_OFFSET 2200
#define SW_API_FLOW_STATUS_SET (0 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_STATUS_GET (1 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_AGE_TIMER_SET (2 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_AGE_TIMER_GET (3 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_CTRL_SET (4 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_CTRL_GET (5 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_ENTRY_ADD (6 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_ENTRY_DEL (7 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_ENTRY_GET (8 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_GLOBAL_CFG_GET (9 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_GLOBAL_CFG_SET (10 + SW_API_FLOW_OFFSET)
#define SW_API_FLOWENTRY_NEXT (11 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_HOST_ADD (20 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_HOST_DEL (21 + SW_API_FLOW_OFFSET)
#define SW_API_FLOW_HOST_GET (22 + SW_API_FLOW_OFFSET)
/* rss hash */
#define SW_API_RSS_HASH_OFFSET 2400
#define SW_API_RSS_HASH_CONFIG_SET (0 + SW_API_RSS_HASH_OFFSET)
#define SW_API_RSS_HASH_CONFIG_GET (1 + SW_API_RSS_HASH_OFFSET)
/* Ctrlpkt Control */
#define SW_API_CTRLPKT_OFFSET 2500
#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_SET (0 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_ETHTYPE_PROFILE_GET (1 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_RFDB_PROFILE_SET (2 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_RFDB_PROFILE_GET (3 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_ADD (4 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_DEL (5 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST (6 + SW_API_CTRLPKT_OFFSET)
#define SW_API_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT (7 + SW_API_CTRLPKT_OFFSET)
/* Service Code */
#define SW_API_SERVCODE_OFFSET 2600
#define SW_API_SERVCODE_CONFIG_SET (0 + SW_API_SERVCODE_OFFSET)
#define SW_API_SERVCODE_CONFIG_GET (1 + SW_API_SERVCODE_OFFSET)
#define SW_API_SERVCODE_LOOPCHECK_EN (2 + SW_API_SERVCODE_OFFSET)
#define SW_API_SERVCODE_LOOPCHECK_STATUS_GET (3 + SW_API_SERVCODE_OFFSET)
/* POLICER */
#define SW_API_POLICER_OFFSET 2800
#define SW_API_POLICER_TIMESLOT_SET (0 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_TIMESLOT_GET (1 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_PORT_COUNTER_GET (2 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_ACL_COUNTER_GET (3 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_COMPENSATION_SET (4 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_COMPENSATION_GET (5 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_PORT_ENTRY_SET (6 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_PORT_ENTRY_GET (7 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_ACL_ENTRY_SET (8 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_ACL_ENTRY_GET (9 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_GLOBAL_COUNTER_GET (10 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_BYPASS_EN_SET (11 + SW_API_POLICER_OFFSET)
#define SW_API_POLICER_BYPASS_EN_GET (12 + SW_API_POLICER_OFFSET)
/* SHAPER */
#define SW_API_SHAPER_OFFSET 2900
#define SW_API_PORT_SHAPER_TIMESLOT_SET (0 + SW_API_SHAPER_OFFSET)
#define SW_API_PORT_SHAPER_TIMESLOT_GET (1 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_TIMESLOT_SET (2 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_TIMESLOT_GET (3 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_TIMESLOT_SET (4 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_TIMESLOT_GET (5 + SW_API_SHAPER_OFFSET)
#define SW_API_PORT_SHAPER_TOKEN_NUMBER_SET (6 + SW_API_SHAPER_OFFSET)
#define SW_API_PORT_SHAPER_TOKEN_NUMBER_GET (7 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_SET (8 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_TOKEN_NUMBER_GET (9 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_SET (10 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_TOKEN_NUMBER_GET (11 + SW_API_SHAPER_OFFSET)
#define SW_API_PORT_SHAPER_SET (12 + SW_API_SHAPER_OFFSET)
#define SW_API_PORT_SHAPER_GET (13 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_SET (14 + SW_API_SHAPER_OFFSET)
#define SW_API_FLOW_SHAPER_GET (15 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_SET (16 + SW_API_SHAPER_OFFSET)
#define SW_API_QUEUE_SHAPER_GET (17 + SW_API_SHAPER_OFFSET)
#define SW_API_SHAPER_IPG_PRE_SET (18 + SW_API_SHAPER_OFFSET)
#define SW_API_SHAPER_IPG_PRE_GET (19 + SW_API_SHAPER_OFFSET)
/* bm */
#define SW_API_BM_OFFSET 3000
#define SW_API_BM_CTRL_SET (0 + SW_API_BM_OFFSET)
#define SW_API_BM_CTRL_GET (1 + SW_API_BM_OFFSET)
#define SW_API_BM_PORTGROUP_MAP_SET (2 + SW_API_BM_OFFSET)
#define SW_API_BM_PORTGROUP_MAP_GET (3 + SW_API_BM_OFFSET)
#define SW_API_BM_GROUP_BUFFER_SET (4 + SW_API_BM_OFFSET)
#define SW_API_BM_GROUP_BUFFER_GET (5 + SW_API_BM_OFFSET)
#define SW_API_BM_PORT_RSVBUFFER_SET (6 + SW_API_BM_OFFSET)
#define SW_API_BM_PORT_RSVBUFFER_GET (7 + SW_API_BM_OFFSET)
#define SW_API_BM_STATIC_THRESH_SET (8 + SW_API_BM_OFFSET)
#define SW_API_BM_STATIC_THRESH_GET (9 + SW_API_BM_OFFSET)
#define SW_API_BM_DYNAMIC_THRESH_SET (10 + SW_API_BM_OFFSET)
#define SW_API_BM_DYNAMIC_THRESH_GET (11 + SW_API_BM_OFFSET)
#define SW_API_BM_PORT_COUNTER_GET (12 + SW_API_BM_OFFSET)
/* ptp */
#define SW_API_PTP_OFFSET 3100
#define SW_API_PTP_CONFIG_SET (0 + SW_API_PTP_OFFSET)
#define SW_API_PTP_CONFIG_GET (1 + SW_API_PTP_OFFSET)
#define SW_API_PTP_REFERENCE_CLOCK_SET (2 + SW_API_PTP_OFFSET)
#define SW_API_PTP_REFERENCE_CLOCK_GET (3 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RX_TIMESTAMP_MODE_SET (4 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RX_TIMESTAMP_MODE_GET (5 + SW_API_PTP_OFFSET)
#define SW_API_PTP_TIMESTAMP_GET (6 + SW_API_PTP_OFFSET)
#define SW_API_PTP_PKT_TIMESTAMP_SET (7 + SW_API_PTP_OFFSET)
#define SW_API_PTP_PKT_TIMESTAMP_GET (8 + SW_API_PTP_OFFSET)
#define SW_API_PTP_GRANDMASTER_MODE_SET (9 + SW_API_PTP_OFFSET)
#define SW_API_PTP_GRANDMASTER_MODE_GET (10 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_TIME_SET (11 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_TIME_GET (12 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_TIME_CLEAR (13 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_ADJTIME_SET (14 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_ADJFREQ_SET (15 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_ADJFREQ_GET (16 + SW_API_PTP_OFFSET)
#define SW_API_PTP_LINK_DELAY_SET (17 + SW_API_PTP_OFFSET)
#define SW_API_PTP_LINK_DELAY_GET (18 + SW_API_PTP_OFFSET)
#define SW_API_PTP_SECURITY_SET (19 + SW_API_PTP_OFFSET)
#define SW_API_PTP_SECURITY_GET (20 + SW_API_PTP_OFFSET)
#define SW_API_PTP_PPS_SIGNAL_CONTROL_SET (21 + SW_API_PTP_OFFSET)
#define SW_API_PTP_PPS_SIGNAL_CONTROL_GET (22 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RX_CRC_RECALC_SET (23 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RX_CRC_RECALC_GET (24 + SW_API_PTP_OFFSET)
#define SW_API_PTP_ASYM_CORRECTION_SET (25 + SW_API_PTP_OFFSET)
#define SW_API_PTP_ASYM_CORRECTION_GET (26 + SW_API_PTP_OFFSET)
#define SW_API_PTP_OUTPUT_WAVEFORM_SET (27 + SW_API_PTP_OFFSET)
#define SW_API_PTP_OUTPUT_WAVEFORM_GET (28 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_TIME_SNAPSHOT_SET (29 + SW_API_PTP_OFFSET)
#define SW_API_PTP_RTC_TIME_SNAPSHOT_GET (30 + SW_API_PTP_OFFSET)
#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_SET (31 + SW_API_PTP_OFFSET)
#define SW_API_PTP_INCREMENT_SYNC_FROM_CLOCK_GET (32 + SW_API_PTP_OFFSET)
#define SW_API_PTP_TOD_UART_SET (33 + SW_API_PTP_OFFSET)
#define SW_API_PTP_TOD_UART_GET (34 + SW_API_PTP_OFFSET)
#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_SET (35 + SW_API_PTP_OFFSET)
#define SW_API_PTP_ENHANCED_TIMESTAMP_ENGINE_GET (36 + SW_API_PTP_OFFSET)
#define SW_API_PTP_TRIGGER_SET (37 + SW_API_PTP_OFFSET)
#define SW_API_PTP_TRIGGER_GET (38 + SW_API_PTP_OFFSET)
#define SW_API_PTP_CAPTURE_SET (39 + SW_API_PTP_OFFSET)
#define SW_API_PTP_CAPTURE_GET (40 + SW_API_PTP_OFFSET)
#define SW_API_PTP_INTERRUPT_SET (41 + SW_API_PTP_OFFSET)
#define SW_API_PTP_INTERRUPT_GET (42 + SW_API_PTP_OFFSET)
/* sfp */
#define SW_API_SFP_OFFSET 3200
#define SW_API_SFP_DATA_GET (0 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DATA_SET (1 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DEV_TYPE_GET (2 + SW_API_SFP_OFFSET)
#define SW_API_SFP_TRANSC_CODE_GET (3 + SW_API_SFP_OFFSET)
#define SW_API_SFP_RATE_ENCODE_GET (4 + SW_API_SFP_OFFSET)
#define SW_API_SFP_LINK_LENGTH_GET (5 + SW_API_SFP_OFFSET)
#define SW_API_SFP_VENDOR_INFO_GET (6 + SW_API_SFP_OFFSET)
#define SW_API_SFP_LASER_WAVELENGTH_GET (7 + SW_API_SFP_OFFSET)
#define SW_API_SFP_OPTION_GET (8 + SW_API_SFP_OFFSET)
#define SW_API_SFP_CTRL_RATE_GET (9 + SW_API_SFP_OFFSET)
#define SW_API_SFP_ENHANCED_CFG_GET (10 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DIAG_THRESHOLD_GET (11 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DIAG_CAL_CONST_GET (12 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DIAG_REALTIME_GET (13 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DIAG_CTRL_STATUS_GET (14 + SW_API_SFP_OFFSET)
#define SW_API_SFP_DIAG_ALARM_WARN_FLAG_GET (15 + SW_API_SFP_OFFSET)
#define SW_API_SFP_CHECKCODE_GET (16 + SW_API_SFP_OFFSET)
/*qca808x_start*/
/*debug*/
#define SW_API_DEBUG_OFFSET 10000
#define SW_API_PHY_GET (0 + SW_API_DEBUG_OFFSET)
#define SW_API_PHY_SET (1 + SW_API_DEBUG_OFFSET)
/*qca808x_end*/
#define SW_API_REG_GET (2 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_SET (3 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_ENTRY_GET (4 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_ENTRY_SET (5 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_FIELD_GET (6 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_FIELD_SET (7 + SW_API_DEBUG_OFFSET)
#define SW_API_PSGMII_REG_GET (8 + SW_API_DEBUG_OFFSET)
#define SW_API_PSGMII_REG_SET (9 + SW_API_DEBUG_OFFSET)
#define SW_API_REG_DUMP (10 + SW_API_DEBUG_OFFSET)
#define SW_API_DBG_REG_DUMP (11 + SW_API_DEBUG_OFFSET)
#define SW_API_DBG_PSGMII_SELF_TEST (12 + SW_API_DEBUG_OFFSET)
#define SW_API_PHY_DUMP (13 + SW_API_DEBUG_OFFSET)
#define SW_API_UNIPHY_REG_GET (20 + SW_API_DEBUG_OFFSET)
#define SW_API_UNIPHY_REG_SET (21 + SW_API_DEBUG_OFFSET)
/*qca808x_start*/
#define SW_API_PHY_I2C_GET (22 + SW_API_DEBUG_OFFSET)
#define SW_API_PHY_I2C_SET (23 + SW_API_DEBUG_OFFSET)
#define SW_API_MAX 0xffff
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _SW_IOCTL_H_ */
/*qca808x_end*/

19
feeds/ipq807x/qca-ssdk/src/include/common/aos_head.h
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@@ -1,19 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "aos_mem.h"
#include "aos_timer.h"
#include "aos_lock.h"
#include "aos_types.h"

120
feeds/ipq807x/qca-ssdk/src/include/common/shared_func.h
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@@ -1,120 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SHARED_FUNC_H
#define _SHARED_FUNC_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define SW_RTN_ON_ERROR(rtn) \
do { if (rtn != SW_OK) return(rtn); } while(0);
#define SW_OUT_ON_ERROR(rtn) \
do { \
if (rtn != SW_OK) { \
rv = rtn; \
goto out;\
} \
} while(0);
#define SW_CNTU_ON_ERROR_AND_COND1_OR_GOTO_OUT(rtn, cond1) \
{ \
if ((rtn != SW_OK)) { \
if (rtn == cond1) \
continue; \
else \
goto out; \
} \
}
#define SW_RTN_ON_ERROR_EXCEPT_COND1(rtn, cond1) \
do { \
if ((rtn != SW_OK) && (rtn != cond1)) \
return rtn; \
}while(0);
#define SW_RTN_ON_NULL(op) \
do { \
if ((op) == NULL) \
return SW_NOT_INITIALIZED;\
}while(0);
/* register functions */
#define SW_BIT_MASK_U32(nr) (~(0xFFFFFFFF << (nr)))
#define SW_FIELD_MASK_U32(offset, len) \
((SW_BIT_MASK_U32(len) << (offset)))
#define SW_FIELD_MASK_NOT_U32(offset,len) \
(~(SW_BIT_MASK_U32(len) << (offset)))
#define SW_FIELD_2_REG(field_val, bit_offset) \
(field_val << (bit_offset) )
#define SW_REG_2_FIELD(reg_val, bit_offset, field_len) \
(((reg_val) >> (bit_offset)) & ((1 << (field_len)) - 1))
#define SW_REG_SET_BY_FIELD_U32(reg_value, field_value, bit_offset, field_len)\
do { \
(reg_value) = \
(((reg_value) & SW_FIELD_MASK_NOT_U32((bit_offset),(field_len))) \
| (((field_value) & SW_BIT_MASK_U32(field_len)) << (bit_offset)));\
} while (0)
#define SW_FIELD_GET_BY_REG_U32(reg_value, field_value, bit_offset, field_len)\
do { \
(field_value) = \
(((reg_value) >> (bit_offset)) & SW_BIT_MASK_U32(field_len)); \
} while (0)
#define SW_SWAP_BITS_U8(x) \
((((x)&0x80)>>7) | (((x)&0x40)>>5) | (((x)&0x20)>>3) | (((x)&0x10)>>1) \
|(((x)&0x1)<<7) | (((x)&0x2)<<5) | (((x)&0x4)<<3) |(((x)&0x8)<<1) )
#define SW_OFFSET_U8_2_U16(byte_offset) ((byte_offset) >> 1)
#define SW_OFFSET_U16_2_U8(word16_offset) ((word16_offset) << 1)
#define SW_OFFSET_BIT_2_U8_ALIGN16(bit_offset) (((bit_offset) / 16) * 2)
#define SW_SET_REG_BY_FIELD(reg, field, field_value, reg_value) \
SW_REG_SET_BY_FIELD_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
reg##_##field##_BLEN)
#define SW_GET_FIELD_BY_REG(reg, field, field_value, reg_value) \
SW_FIELD_GET_BY_REG_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
reg##_##field##_BLEN)
/* port bitmap functions */
#define SW_IS_PBMP_MEMBER(pbm, port) ((pbm & (1 << port)) ? A_TRUE: A_FALSE)
#define SW_IS_PBMP_EQ(pbm0, pbm1) ((pbm0 == pbm1) ? A_TRUE: A_FALSE)
#define SW_PBMP_AND(pbm0, pbm1) ((pbm0) &= (pbm1))
#define SW_PBMP_OR(pbm0, pbm1) ((pbm0) |= (pbm1))
#define SW_IS_PBMP_INCLUDE(pbm0, pbm1) \
((pbm1 == SW_PBMP_AND(pbm0, pbm1)) ? A_TRUE: A_FALSE)
#define SW_PBMP_CLEAR(pbm) ((pbm) = 0)
#define SW_PBMP_ADD_PORT(pbm, port) ((pbm) |= (1U << (port)))
#define SW_PBMP_DEL_PORT(pbm,port) ((pbm) &= ~(1U << (port)))
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _SHARED_FUNC_H */

33
feeds/ipq807x/qca-ssdk/src/include/common/sw.h
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@@ -1,33 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SW_H_
#define _SW_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw_config.h"
#include "aos_head.h"
#include "sw_error.h"
#include "shared_func.h"
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _SW_H_ */

37
feeds/ipq807x/qca-ssdk/src/include/common/sw_config.h
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@@ -1,37 +0,0 @@
/*
* Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SW_CONFIG_H
#define _SW_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define SW_MAX_NR_DEV 3
#define SW_MAX_NR_PORT 16
#ifdef HSL_STANDALONG
#define HSL_LOCAL
#else
#define HSL_LOCAL static
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

62
feeds/ipq807x/qca-ssdk/src/include/common/sw_error.h
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@@ -1,62 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SW_ERROR_H
#define _SW_ERROR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
typedef enum {
SW_OK = 0, /* Operation succeeded */
SW_FAIL = -1, /* Operation failed */
SW_BAD_VALUE = -2, /* Illegal value */
SW_OUT_OF_RANGE = -3, /* Value is out of range */
SW_BAD_PARAM = -4, /* Illegal parameter(s) */
SW_BAD_PTR = -5, /* Illegal pointer value */
SW_BAD_LEN = -6, /* Wrong length */
SW_BAD_STATE = -7, /* Wrong state of state machine */
SW_READ_ERROR = -8, /* Read operation failed */
SW_WRITE_ERROR = -9, /* Write operation failed */
SW_CREATE_ERROR = -10, /* Fail in creating an entry */
SW_DELETE_ERROR = -11, /* Fail in deleteing an entry */
SW_NOT_FOUND = -12, /* Entry not found */
SW_NO_CHANGE = -13, /* The parameter(s) is the same */
SW_NO_MORE = -14, /* No more entry found */
SW_NO_SUCH = -15, /* No such entry */
SW_ALREADY_EXIST = -16, /* Tried to create existing entry */
SW_FULL = -17, /* Table is full */
SW_EMPTY = -18, /* Table is empty */
SW_NOT_SUPPORTED = -19, /* This request is not support */
SW_NOT_IMPLEMENTED = -20, /* This request is not implemented */
SW_NOT_INITIALIZED = -21, /* The item is not initialized */
SW_BUSY = -22, /* Operation is still running */
SW_TIMEOUT = -23, /* Operation Time Out */
SW_DISABLE = -24, /* Operation is disabled */
SW_NO_RESOURCE = -25, /* Resource not available (memory ...) */
SW_INIT_ERROR = -26, /* Error occured while INIT process */
SW_NOT_READY = -27, /* The other side is not ready yet */
SW_OUT_OF_MEM = -28, /* Cpu memory allocation failed. */
SW_ABORTED = -29 /* Operation has been aborted. */
} sw_error_t;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _SW_ERROR_H */

92
feeds/ipq807x/qca-ssdk/src/include/common/util.h
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@@ -1,92 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _UTIL_H_
#define _UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define LL_IN_ORDER 0x1
#define LL_FIX_NDNR 0x2
typedef enum {
LL_CMP_EQUAL = 0,
LL_CMP_GREATER = 1,
LL_CMP_SMALLER = 2
}
ll_cmp_rslt_t;
typedef ll_cmp_rslt_t(*ll_nd_cmp) (void *src, void *dest);
typedef void (*ll_nd_dump) (void *data);
typedef struct _sll_node_t
{
struct _sll_node_t *next;
void *data;
} sll_node_t;
typedef struct
{
sll_node_t *fst_nd;
a_uint32_t nd_nr;
a_uint32_t flag;
ll_nd_cmp nd_cmp;
ll_nd_dump nd_dump;
sll_node_t *free_nd;
} sll_head_t;
sll_head_t *sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func,
a_uint32_t flag, a_uint32_t nd_nr);
void sll_destroy(sll_head_t * sll);
void sll_lock(sll_head_t * sll);
void sll_unlock(sll_head_t * sll);
void *sll_nd_find(const sll_head_t * sll, void *data,
a_ulong_t *iterator);
void *sll_nd_next(const sll_head_t *sll, a_ulong_t *iterator);
sw_error_t sll_nd_insert(sll_head_t * sll, void *data);
sw_error_t sll_nd_delete(sll_head_t * sll, void *data);
typedef struct
{
a_uint32_t id_ptr;
a_uint32_t id_nr;
a_uint32_t id_min;
a_uint32_t id_size;
void *id_pool;
} sid_pool_t;
sid_pool_t *sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id);
void sid_pool_destroy(sid_pool_t * pool);
sw_error_t sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id);
sw_error_t sid_pool_id_free(sid_pool_t * pool, a_uint32_t id);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _UTIL_H_ */

68
feeds/ipq807x/qca-ssdk/src/include/fal/fal.h
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@@ -1,68 +0,0 @@
/*
* Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*qca808x_start*/
#ifndef _FAL_H
#define _FAL_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal_port_ctrl.h"
/*qca808x_end*/
#include "fal_misc.h"
#include "fal_vlan.h"
#include "fal_fdb.h"
#include "fal_portvlan.h"
#include "fal_qos.h"
#include "fal_stp.h"
#include "fal_rate.h"
#include "fal_mirror.h"
#include "fal_leaky.h"
#include "fal_igmp.h"
#include "fal_mib.h"
#include "fal_acl.h"
#include "fal_led.h"
/*qca808x_start*/
#include "fal_reg_access.h"
#include "fal_init.h"
/*qca808x_end*/
#include "fal_cosmap.h"
#include "fal_ip.h"
#include "fal_nat.h"
#include "fal_flow.h"
#include "fal_qm.h"
#include "fal_sec.h"
#include "fal_trunk.h"
#include "fal_interface_ctrl.h"
#include "fal_fdb.h"
#include "fal_multi.h"
#include "fal_ctrlpkt.h"
#include "fal_servcode.h"
#include "fal_rss_hash.h"
#include "fal_vsi.h"
#include "fal_pppoe.h"
#include "fal_bm.h"
#include "fal_shaper.h"
#include "fal_policer.h"
#include "fal_ptp.h"
#include "fal_sfp.h"
/*qca808x_start*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_H */
/*qca808x_end*/

616
feeds/ipq807x/qca-ssdk/src/include/fal/fal_acl.h
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@@ -1,616 +0,0 @@
/*
* Copyright (c) 2014, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_acl FAL_ACL
* @{
*/
#ifndef _FAL_ACL_H_
#define _FAL_ACL_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This enum defines the ACL rule type.
*/
typedef enum {
FAL_ACL_RULE_MAC = 0, /**< include MAC, udf fields*/
FAL_ACL_RULE_IP4, /**< include MAC, IP4 and Tcp/Udp udf fields*/
FAL_ACL_RULE_IP6, /**< include MAC, IP6 and Tcp/Udp udf fields*/
FAL_ACL_RULE_UDF, /**< only include user defined fields*/
FAL_ACL_RULE_BUTT,
}
fal_acl_rule_type_t;
/**
@brief This enum defines the ACL field operation type.
*/
typedef enum
{
FAL_ACL_FIELD_MASK = 0, /**< match operation is mask*/
FAL_ACL_FIELD_RANGE, /**< match operation is range*/
FAL_ACL_FIELD_LE, /**< match operation is less than equal*/
FAL_ACL_FIELD_GE, /**< match operation is greater than equal*/
FAL_ACL_FIELD_NE, /**<- match operation is not equal*/
FAL_ACL_FIELD_OP_BUTT,
} fal_acl_field_op_t;
typedef enum
{
FAL_ACL_POLICY_ROUTE = 0,
FAL_ACL_POLICY_SNAT,
FAL_ACL_POLICY_DNAT,
FAL_ACL_POLICY_RESERVE,
} fal_policy_forward_t;
typedef enum
{
FAL_ACL_COMBINED_NONE = 0,
FAL_ACL_COMBINED_START,
FAL_ACL_COMBINED_CONTINUE,
FAL_ACL_COMBINED_END,
} fal_combined_t;
/**
@brief This enum defines the ACL field operation type.
*/
typedef enum
{
FAL_ACL_UDF_TYPE_L2 = 0, /*start from L2 */
FAL_ACL_UDF_TYPE_L3, /*start from L3 */
FAL_ACL_UDF_TYPE_L4, /*start from L4 */
FAL_ACL_UDF_TYPE_L2_SNAP, /*start from SNAP L2 */
FAL_ACL_UDF_TYPE_L3_PLUS, /*start from SNAP L3 */
FAL_ACL_UDF_TYPE_BUTT,
} fal_acl_udf_type_t;
/**
@brief This enum defines the ACL rule type.
*/
typedef enum {
FAL_ACL_UDF_NON_IP = 0, /*UDF for non-ip packets*/
FAL_ACL_UDF_IP4, /*UDF for IPv4 packets*/
FAL_ACL_UDF_IP6, /*UDF for IPv6 packets*/
FAL_ACL_UDF_BUTT,
}fal_acl_udf_pkt_type_t;
typedef enum {
FAL_ACL_DEST_PORT_BMP = 0, /*dest info is bitmap*/
FAL_ACL_DEST_NEXTHOP, /*dest info is nexthop*/
FAL_ACL_DEST_PORT_ID, /*dest info is port id*/
}fal_acl_dest_type_t;
#define FAL_ACL_DEST_OFFSET(type,value) (((type)<<24)|(value))
#define FAL_ACL_DEST_TYPE(dest) (((dest)>>24)&0xff)
#define FAL_ACL_DEST_VALUE(dest) ((dest)&0xffffff)
#define FAL_ACL_FIELD_MAC_DA 0
#define FAL_ACL_FIELD_MAC_SA 1
#define FAL_ACL_FIELD_MAC_ETHTYPE 2
#define FAL_ACL_FIELD_MAC_TAGGED 3
#define FAL_ACL_FIELD_MAC_UP 4
#define FAL_ACL_FIELD_MAC_VID 5
#define FAL_ACL_FIELD_IP4_SIP 6
#define FAL_ACL_FIELD_IP4_DIP 7
#define FAL_ACL_FIELD_IP6_LABEL 8
#define FAL_ACL_FIELD_IP6_SIP 9
#define FAL_ACL_FIELD_IP6_DIP 10
#define FAL_ACL_FIELD_IP_PROTO 11
#define FAL_ACL_FIELD_IP_DSCP 12
#define FAL_ACL_FIELD_L4_SPORT 13
#define FAL_ACL_FIELD_L4_DPORT 14
#define FAL_ACL_FIELD_UDF 15
#define FAL_ACL_FIELD_MAC_CFI 16
#define FAL_ACL_FIELD_ICMP_TYPE 17
#define FAL_ACL_FIELD_ICMP_CODE 18
#define FAL_ACL_FIELD_TCP_FLAG 19
#define FAL_ACL_FIELD_RIPV1 20
#define FAL_ACL_FIELD_DHCPV4 21
#define FAL_ACL_FIELD_DHCPV6 22
#define FAL_ACL_FIELD_MAC_STAG_VID 23
#define FAL_ACL_FIELD_MAC_STAG_PRI 24
#define FAL_ACL_FIELD_MAC_STAG_DEI 25
#define FAL_ACL_FIELD_MAC_STAGGED 26
#define FAL_ACL_FIELD_MAC_CTAG_VID 27
#define FAL_ACL_FIELD_MAC_CTAG_PRI 28
#define FAL_ACL_FIELD_MAC_CTAG_CFI 29
#define FAL_ACL_FIELD_MAC_CTAGGED 30
#define FAL_ACL_FIELD_INVERSE_ALL 31
/*new add for hawkeye*/
#define FAL_ACL_FIELD_POST_ROURING_EN 32
#define FAL_ACL_FIELD_RES_CHAIN 33
#define FAL_ACL_FIELD_FAKE_MAC_HEADER 34
#define FAL_ACL_FIELD_SNAP 35
#define FAL_ACL_FIELD_ETHERNET 36
#define FAL_ACL_FIELD_IPV6 37
#define FAL_ACL_FIELD_IP 38
#define FAL_ACL_FIELD_VSI 39
#define FAL_ACL_FIELD_PPPOE_SESSIONID 40
#define FAL_ACL_FIELD_L3_FRAGMENT 41
#define FAL_ACL_FIELD_AH_HEADER 42
#define FAL_ACL_FIELD_ESP_HEADER 43
#define FAL_ACL_FIELD_MOBILITY_HEADER 44
#define FAL_ACL_FIELD_FRAGMENT_HEADER 45
#define FAL_ACL_FIELD_OTHER_EXT_HEADER 46
#define FAL_ACL_FIELD_L3_TTL 47
#define FAL_ACL_FIELD_IPV4_OPTION 48
#define FAL_ACL_FIELD_FIRST_FRAGMENT 49
#define FAL_ACL_FIELD_L3_LENGTH 50
#define FAL_ACL_FIELD_VSI_VALID 51
#define FAL_ACL_FIELD_IP_PKT_TYPE 52
#define FAL_ACL_FIELD_UDF0 53
#define FAL_ACL_FIELD_UDF1 54
#define FAL_ACL_FIELD_UDF2 55
#define FAL_ACL_FIELD_UDF3 56
#define FAL_ACL_FIELD_NUM 57
#define FAL_ACL_ACTION_PERMIT 0
#define FAL_ACL_ACTION_DENY 1
#define FAL_ACL_ACTION_REDPT 2
#define FAL_ACL_ACTION_RDTCPU 3
#define FAL_ACL_ACTION_CPYCPU 4
#define FAL_ACL_ACTION_MIRROR 5
#define FAL_ACL_ACTION_MODIFY_VLAN 6
#define FAL_ACL_ACTION_NEST_VLAN 7
#define FAL_ACL_ACTION_REMARK_UP 8
#define FAL_ACL_ACTION_REMARK_QUEUE 9
#define FAL_ACL_ACTION_REMARK_STAG_VID 10
#define FAL_ACL_ACTION_REMARK_STAG_PRI 11
#define FAL_ACL_ACTION_REMARK_STAG_DEI 12
#define FAL_ACL_ACTION_REMARK_CTAG_VID 13
#define FAL_ACL_ACTION_REMARK_CTAG_PRI 14
#define FAL_ACL_ACTION_REMARK_CTAG_CFI 15
#define FAL_ACL_ACTION_REMARK_LOOKUP_VID 16
#define FAL_ACL_ACTION_REMARK_DSCP 17
#define FAL_ACL_ACTION_POLICER_EN 18
#define FAL_ACL_ACTION_WCMP_EN 19
#define FAL_ACL_ACTION_ARP_EN 20
#define FAL_ACL_ACTION_POLICY_FORWARD_EN 21
#define FAL_ACL_ACTION_BYPASS_EGRESS_TRANS 22
#define FAL_ACL_ACTION_MATCH_TRIGGER_INTR 23
/*new add for hawkeye*/
#define FAL_ACL_ACTION_ENQUEUE_PRI 25
#define FAL_ACL_ACTION_INT_DP 26
#define FAL_ACL_ACTION_SERVICE_CODE 27
#define FAL_ACL_ACTION_CPU_CODE 28
#define FAL_ACL_ACTION_SYN_TOGGLE 29
#define FAL_ACL_ACTION_METADATA_EN 30
enum{
FAL_ACL_BYPASS_IN_VLAN_MISS = 0,
FAL_ACL_BYPASS_SOUCE_GUARD,
FAL_ACL_BYPASS_MRU_MTU_CHECK,
FAL_ACL_BYPASS_EG_VSI_MEMBER_CHECK = 8,
FAL_ACL_BYPASS_EG_VLAN_TRANSLATION,
FAL_ACL_BYPASS_EG_VLAN_TAG_CTRL = 10,
FAL_ACL_BYPASS_FDB_LEARNING,
FAL_ACL_BYPASS_FDB_REFRESH,
FAL_ACL_BYPASS_L2_SECURITY,/*new address, station move, learn limit, hash full*/
FAL_ACL_BYPASS_MANAGEMENT_FWD,
FAL_ACL_BYPASS_L2_FWD = 15,
FAL_ACL_BYPASS_IN_STP_CHECK,
FAL_ACL_BYPASS_EG_STP_CHECK,
FAL_ACL_BYPASS_SOURCE_FILTER,
FAL_ACL_BYPASS_POLICYER,
FAL_ACL_BYPASS_L2_EDIT = 20,/*VLAN tag edit*/
FAL_ACL_BYPASS_L3_EDIT,/*Edit MAC address, PPPoE, IP address, TTL, DSCP, L4 port*/
FAL_ACL_BYPASS_POST_ACL_CHECK_ROUTING,
FAL_ACL_BYPASS_PORT_ISOLATION,
};
/**
* @brief This type defines the action in Acl rule.
* @details Comments:
* It's a bit map type, we can access it through macro FAL_ACTION_FLG_SET,
* FAL_ACTION_FLG_CLR and FAL_ACTION_FLG_TST.
*/
typedef a_uint32_t fal_acl_action_map_t;
#define FAL_ACTION_FLG_SET(flag, action) \
(flag) |= (0x1UL << (action))
#define FAL_ACTION_FLG_CLR(flag, action) \
(flag) &= (~(0x1UL << (action)))
#define FAL_ACTION_FLG_TST(flag, action) \
((flag) & (0x1UL << (action))) ? 1 : 0
/**
* @brief This type defines the field in Acl rule.
* @details Comments:
* It's a bit map type, we can access it through macro FAL_FIELD_FLG_SET,
* FAL_FIELD_FLG_CLR and FAL_FIELD_FLG_TST.
*/
typedef a_uint32_t fal_acl_field_map_t[2];
#define FAL_FIELD_FLG_SET(flag, field) \
((flag[(field) / 32]) |= (0x1UL << ((field) % 32)))
#define FAL_FIELD_FLG_CLR(flag, field) \
((flag[(field) / 32]) &= (~(0x1UL << ((field) % 32))))
#define FAL_FIELD_FLG_TST(flag, field) \
(((flag[(field) / 32]) & (0x1UL << ((field) % 32))) ? 1 : 0)
#define FAL_ACL_UDF_MAX_LENGTH 16
/**
* @brief This structure defines the Acl rule.
* @details Fields description:
*
*
* vid_val - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field value.
* If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field low value. If
* vid_op equals other value it's the compared value.
*
* vid_mask - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field mask.
* If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field high value. If vid_op
* equals other value it's meaningless.
*
*
* ip_dscp_val - It's eight bits field we can set any value between 0 - 255.
* ip_dscp_mask - It's eight bits field we can set any value between 0 - 255.
*
*
* src_l4port_val - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
* source port field value. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
* layer four source port field low value. If src_l4port_op equals other value
* it's the compared value.
*
*
* src_l4port_mask - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
* source port field mask. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
* layer four source port field high value. If src_l4port_op equals other value
* it's meaningless.
*
*
* dest_l4port_val - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
* destination port field value. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
* layer four source port field low value. If dest_l4port_op equals other value
* it's the compared value.
*
*
* dest_l4port_mask - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
* source port field mask. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
* layer four source port field high value. If dest_l4port_op equals other value
* it's meaningless.
*
*
* ports - If FAL_ACL_ACTION_REDPT bit is setted in action_flg it's redirect
* destination ports.
*
*
* dot1p - If FAL_ACL_ACTION_REMARK_DOT1P bit is setted in action_flg it's
* the expected dot1p value.
*
*
* queue - If FAL_ACL_ACTION_REMARK_QUEUE bit is setted in action_flg it's
* the expected queue value.
*
*
* vid - If FAL_ACL_ACTION_MODIFY_VLAN or FAL_ACL_ACTION_NEST_VLAN bit is
* setted in action_flg it's the expected vlan id value.
*/
typedef struct
{
fal_acl_rule_type_t rule_type;/*mac, IP4, IP6 and UDF*/
fal_acl_field_map_t field_flg;/*Indicate which fields are selected*/
/* fields of mac rule */
fal_mac_addr_t src_mac_val;/*source mac*/
fal_mac_addr_t src_mac_mask;/*source mac mask*/
fal_mac_addr_t dest_mac_val;/*destination mac*/
fal_mac_addr_t dest_mac_mask;/*destionation mac mask*/
a_uint16_t ethtype_val;/*ethernet type*/
a_uint16_t ethtype_mask;/*ethernet type mask*/
a_uint16_t vid_val;/*vlan id, IPQ807x not support*/
a_uint16_t vid_mask;/*vlan id mask*/
fal_acl_field_op_t vid_op;/*vlan id operation, larger than or smaller than or range or mask*/
a_uint8_t tagged_val;/*tagged or not, IPQ807x not support*/
a_uint8_t tagged_mask;/*tagged or not mask*/
a_uint8_t up_val;/*cos priority, IPQ807x not support*/
a_uint8_t up_mask;/*cos priority mask*/
a_uint8_t cfi_val;/*CFI value, IPQ807x not support*/
a_uint8_t cfi_mask;/*CFI value mask*/
a_uint16_t resv0;/*reserved*/
/* fields of enhanced mac rule*/
a_uint8_t stagged_val; /*for s17c : 0-untag, 1-tag, for hawkeye: 2-pritag, 3-utag+pritag, 4- untag+tag, 5-tag+pritag, 6-all*/
a_uint8_t stagged_mask;
a_uint8_t ctagged_val;/*same as stagged define*/
a_uint8_t ctagged_mask;
a_uint16_t stag_vid_val;/*stag vlan id*/
a_uint16_t stag_vid_mask;/*stag vlan id mask*/
fal_acl_field_op_t stag_vid_op;/*vlan id operation, larger than or smaller than or range or mask*/
a_uint16_t ctag_vid_val;
a_uint16_t ctag_vid_mask;
fal_acl_field_op_t ctag_vid_op;
a_uint8_t stag_pri_val;/*stag priority*/
a_uint8_t stag_pri_mask;/*stag priority mask*/
a_uint8_t ctag_pri_val;
a_uint8_t ctag_pri_mask;
a_uint8_t stag_dei_val;/*stag dei*/
a_uint8_t stag_dei_mask;/*stag dei mask*/
a_uint8_t ctag_cfi_val;/*ctag cfi*/
a_uint8_t ctag_cfi_mask;/*ctag cfi mask*/
/* fields of ip4 rule */
fal_ip4_addr_t src_ip4_val;/*source ipv4 address*/
fal_ip4_addr_t src_ip4_mask;/*source ipv4 address mask*/
fal_ip4_addr_t dest_ip4_val;/*destination ipv4 address*/
fal_ip4_addr_t dest_ip4_mask;/*destination ipv4 address mask*/
/* fields of ip6 rule */
a_uint32_t ip6_lable_val;/*ipv6 flow lable, IPQ807x not support*/
a_uint32_t ip6_lable_mask;/*ipv6 flow lable mask*/
fal_ip6_addr_t src_ip6_val;/*source ipv6 address*/
fal_ip6_addr_t src_ip6_mask;/*source ipv6 address mask*/
fal_ip6_addr_t dest_ip6_val;/*destination ipv6 address*/
fal_ip6_addr_t dest_ip6_mask;/*destination ipv6 address mask*/
/* fields of ip rule */
a_uint8_t ip_proto_val;/*IP protocal*/
a_uint8_t ip_proto_mask;/*IP protocal mask*/
a_uint8_t ip_dscp_val;/*IP DSCP*/
a_uint8_t ip_dscp_mask;/*IP DSCP mask*/
/* fields of layer four */
a_uint16_t src_l4port_val;/*source L4 port*/
a_uint16_t src_l4port_mask;/*source L4 port mask*/
fal_acl_field_op_t src_l4port_op;/*source L4 port operation*/
a_uint16_t dest_l4port_val;/*destination L4 port*/
a_uint16_t dest_l4port_mask;/*destination L4 mask*/
fal_acl_field_op_t dest_l4port_op;/*destination L4 operation*/
a_uint8_t icmp_type_val;/*ICMP type*/
a_uint8_t icmp_type_mask;/*ICMP type mask*/
a_uint8_t icmp_code_val;/*ICMP code*/
a_uint8_t icmp_code_mask;/*ICMP code mask*/
a_uint8_t tcp_flag_val;/*tcp flags value*/
a_uint8_t tcp_flag_mask;/*tcp flags mask*/
a_uint8_t ripv1_val;/*Is RIPv1 or not, IPQ807x not support*/
a_uint8_t ripv1_mask;/*RIPv1 mask*/
a_uint8_t dhcpv4_val;/*Is DHCPv4 or not, IPQ807x not support*/
a_uint8_t dhcpv4_mask;
a_uint8_t dhcpv6_val;/*Is DHCPv6 or not, IPQ807x not support*/
a_uint8_t dhcpv6_mask;
/* user defined fields */
fal_acl_udf_type_t udf_type;/*UDF type, IPQ807x not support*/
a_uint8_t udf_offset;/*UDF offset, IPQ807x not support*/
a_uint8_t udf_len;/*UDF length, IPQ807x not support*/
a_uint8_t udf_val[FAL_ACL_UDF_MAX_LENGTH];/*UDF field value*/
a_uint8_t udf_mask[FAL_ACL_UDF_MAX_LENGTH];/*UDF field mask*/
/* fields of action */
fal_acl_action_map_t action_flg;/*Indicate which action apply*/
fal_pbmp_t ports; /*high 8bits, 00-port bitmap, 01-nexthop, 10-vp*/
a_uint32_t match_cnt;/*rule match frame counter*/
a_uint16_t vid;/*modify vlan id, IPQ807x not support*/
a_uint8_t up;/*modify COS priority, IPQ807x not support*/
a_uint8_t queue;/*modify queue*/
a_uint16_t stag_vid;/*modify stag vlan id*/
a_uint8_t stag_pri;/*modify stag priority*/
a_uint8_t stag_dei;/*modify stag dei*/
a_uint16_t ctag_vid;/*modify ctag vlan id*/
a_uint8_t ctag_pri;/*modify ctag priority*/
a_uint8_t ctag_cfi;/*modify ctag dei*/
a_uint16_t policer_ptr;/*specify policer index*/
a_uint16_t arp_ptr;/*specify arp table index, IPQ807x not support*/
a_uint16_t wcmp_ptr;/*specify wcmp table index, IPQ807x not support*/
a_uint8_t dscp;/*modify dscp*/
a_uint8_t rsv;
fal_policy_forward_t policy_fwd;/*SNAT or DNAT or ROUTE, IPQ807x not support*/
fal_combined_t combined;
/*Only IPQ807x support start*/
a_uint8_t pri; /*rule priority 0-7*/
a_bool_t post_routing;/*post routing or not*/
a_uint8_t acl_pool;/*acl pool*/
a_bool_t is_ip_val;/*is ip or not*/
a_uint8_t is_ip_mask;
a_bool_t is_ipv6_val;/*is ipv6 or ipv4*/
a_uint8_t is_ipv6_mask;
a_bool_t is_fake_mac_header_val;/*is fake mac header or not*/
a_uint8_t is_fake_mac_header_mask;
a_bool_t is_snap_val;/*is snap or not*/
a_uint8_t is_snap_mask;
a_bool_t is_ethernet_val;/*is ethernet or not*/
a_uint8_t is_ethernet_mask;
a_bool_t is_fragement_val;/*is fragment or not*/
a_uint8_t is_fragement_mask;
a_bool_t is_ah_header_val;/*is ah header or not*/
a_uint8_t is_ah_header_mask;
a_bool_t is_esp_header_val;/*is esp header or not*/
a_uint8_t is_esp_header_mask;
a_bool_t is_mobility_header_val;/*is mobility header or not*/
a_uint8_t is_mobility_header_mask;
a_bool_t is_fragment_header_val;/*is fragment header or not*/
a_uint8_t is_fragment_header_mask;
a_bool_t is_other_header_val;/*is other header or not*/
a_uint8_t is_other_header_mask;
a_bool_t is_ipv4_option_val;/*is ipv4 option or not*/
a_uint8_t is_ipv4_option_mask;
a_bool_t is_first_frag_val;/*is first fragment or not*/
a_uint8_t is_first_frag_mask;
/*fields of VLAN rule*/
a_bool_t vsi_valid;/*vsi valid or not*/
a_uint8_t vsi_valid_mask;
a_uint8_t vsi; /*vsi value 0-31*/
a_uint8_t vsi_mask; /*vsi mask 0-31*/
/*fields of L2 MISC rule*/
a_uint16_t pppoe_sessionid;/*pppoe session id*/
a_uint16_t pppoe_sessionid_mask;/*pppoe session mask*/
fal_acl_field_op_t icmp_type_code_op;/*icmp type operation*/
/*fields of IP MISC rule*/
a_uint8_t l3_ttl;/*L3 TTL,0-ttl 0, 1-ttl 1, 2-ttl 255, 3- ttl other*/
a_uint8_t l3_ttl_mask;/*L3 TTL mask*/
fal_acl_field_op_t l3_length_op;/*L3 TTL operation*/
a_uint16_t l3_length;/*L3 length*/
a_uint16_t l3_length_mask;/*L3 length mask*/
a_uint16_t l3_pkt_type;/*l3 packet type, 0-tcp, 1-udp, 3-udp_lite, 5-arp, 7-icmp*/
a_uint16_t l3_pkt_type_mask;
/*field of udf*/
fal_acl_field_op_t udf0_op;/*udf operation*/
a_uint16_t udf0_val;/*udf value, 2bytes*/
a_uint16_t udf0_mask;/*udf mask, 2bytes*/
fal_acl_field_op_t udf1_op;
a_uint16_t udf1_val;
a_uint16_t udf1_mask;
a_uint16_t udf2_val;
a_uint16_t udf2_mask;
a_uint16_t udf3_val;
a_uint16_t udf3_mask;
/*new add acl action for hawkeye*/
a_uint32_t bypass_bitmap;/*bypass bitmap*/
a_uint8_t enqueue_pri;/*enqueue priority*/
a_uint8_t stag_fmt;/*stag format*/
a_uint8_t ctag_fmt;/*ctag format*/
a_uint8_t int_dp;/*internal dp*/
a_uint8_t service_code;/*service code*/
a_uint8_t cpu_code;/*cpu code*/
a_uint64_t match_bytes;/*rule match bytes counter*/
/*Only IPQ807x support End*/
/*new add acl action for IPQ60xx*/
a_uint8_t dscp_mask;/*modify dscp mask,IPQ60xx support*/
a_uint8_t qos_res_prec;/*qos res prec,IPQ60xx support*/
} fal_acl_rule_t;
/**
@brief This enum defines the ACL will work on which derection traffic.
*/
typedef enum
{
FAL_ACL_DIREC_IN = 0, /**< Acl will work on ingressive traffic */
FAL_ACL_DIREC_EG, /**< Acl will work on egressive traffic */
FAL_ACL_DIREC_BOTH, /**< Acl will work on both ingressive and egressive traffic*/
} fal_acl_direc_t;
/**
@brief This enum defines the ACL will work on which partiualr object.
*/
typedef enum
{
FAL_ACL_BIND_PORT = 0, /**< Acl wil work on particular port and virtual port */
FAL_ACL_BIND_PORTBITMAP = 1, /**< Acl wil work on port bitmap */
FAL_ACL_BIND_SERVICE_CODE = 2, /**< Acl wil work on service code */
FAL_ACL_BIND_L3_IF = 3, /**< Acl wil work on l3 interface */
} fal_acl_bind_obj_t;
enum
{
/*acl*/
FUNC_ACL_LIST_CREAT = 0,
FUNC_ACL_LIST_DESTROY,
FUNC_ACL_RULE_ADD,
FUNC_ACL_RULE_DELETE,
FUNC_ACL_RULE_QUERY,
FUNC_ACL_RULE_DUMP,
FUNC_ACL_LIST_BIND,
FUNC_ACL_LIST_UNBIND,
FUNC_ACL_LIST_DUMP,
FUNC_ACL_UDF_PROFILE_SET,
FUNC_ACL_UDF_PROFILE_GET,
};
sw_error_t
fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri);
sw_error_t
fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
sw_error_t
fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule);
sw_error_t
fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
sw_error_t
fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, fal_acl_rule_t * rule);
sw_error_t
fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
sw_error_t
fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id, fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t, a_uint32_t obj_idx);
sw_error_t
fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_acl_list_dump(a_uint32_t dev_id);
sw_error_t
fal_acl_rule_dump(a_uint32_t dev_id);
sw_error_t
fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t offset, a_uint32_t length);
sw_error_t
fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t * offset, a_uint32_t * length);
sw_error_t
fal_acl_udf_profile_set(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t udf_type, a_uint32_t offset);
sw_error_t
fal_acl_udf_profile_get(a_uint32_t dev_id, fal_acl_udf_pkt_type_t pkt_type,a_uint32_t udf_idx, fal_acl_udf_type_t *udf_type, a_uint32_t *offset);
sw_error_t
fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
sw_error_t
fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id, a_uint32_t rule_nr);
sw_error_t
fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t enable);
sw_error_t
fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id, a_uint32_t rule_id, a_bool_t* enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_ACL_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_bm.h
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/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_qos FAL_QM
* @{
*/
#ifndef _FAL_BM_H_
#define _FAL_BM_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef struct
{
a_uint16_t max_thresh; /* Static Maximum threshold */
a_uint16_t resume_off; /*resume offset */
} fal_bm_static_cfg_t;
typedef struct
{
a_uint8_t weight; /* port weight in the shared group */
a_uint16_t shared_ceiling; /* Maximum shared buffers */
a_uint16_t resume_off; /*resume offset */
a_uint16_t resume_min_thresh; /* Minumum thresh for resume */
} fal_bm_dynamic_cfg_t;
typedef struct
{
a_bool_t enable;
a_uint32_t offset;
a_uint32_t depth;
} fal_port_tdm_ctrl_t;
typedef struct
{
a_uint64_t drop_byte_counter; /*drop byte due to overload*/
a_uint32_t drop_packet_counter; /*drop packet due to overload*/
a_uint64_t fc_drop_byte_counter; /*drop byte due to fc*/
a_uint32_t fc_drop_packet_counter; /*drop packet due to fc*/
a_uint32_t used_counter; /*total used buffer counter for the port*/
a_uint32_t react_counter; /*react used buffer counter for the port*/
} fal_bm_port_counter_t;
#define FAL_PORT_TDB_DIR_INGRESS 0
#define FAL_PORT_TDB_DIR_EGRESS 1
typedef struct
{
a_uint8_t valid; /* 0 for invalid and 1 for valid*/
a_uint8_t direction; /* 0 for ingreee and 1 for egress */
fal_port_t port;
} fal_port_tdm_tick_cfg_t;
enum {
FUNC_PORT_BUFGROUP_MAP_GET = 0,
FUNC_BM_PORT_RESERVED_BUFFER_GET,
FUNC_BM_BUFGROUP_BUFFER_GET,
FUNC_BM_PORT_DYNAMIC_THRESH_GET,
FUNC_PORT_BM_CTRL_GET,
FUNC_BM_BUFGROUP_BUFFER_SET,
FUNC_PORT_BUFGROUP_MAP_SET,
FUNC_BM_PORT_STATIC_THRESH_GET,
FUNC_BM_PORT_RESERVED_BUFFER_SET,
FUNC_BM_PORT_STATIC_THRESH_SET,
FUNC_BM_PORT_DYNAMIC_THRESH_SET,
FUNC_PORT_BM_CTRL_SET,
FUNC_PORT_TDM_CTRL_SET,
FUNC_PORT_TDM_TICK_CFG_SET,
FUNC_BM_PORT_COUNTER_GET,
};
sw_error_t
fal_port_bm_ctrl_set(a_uint32_t dev_id, fal_port_t port, a_bool_t enable);
sw_error_t
fal_port_bufgroup_map_set(a_uint32_t dev_id, fal_port_t port,
a_uint8_t group);
sw_error_t
fal_bm_port_dynamic_thresh_set(a_uint32_t dev_id, fal_port_t port,
fal_bm_dynamic_cfg_t *cfg);
sw_error_t
fal_bm_bufgroup_buffer_set(a_uint32_t dev_id, a_uint8_t group,
a_uint16_t buff_num);
sw_error_t
fal_bm_port_reserved_buffer_set(a_uint32_t dev_id, fal_port_t port,
a_uint16_t prealloc_buff, a_uint16_t react_buff);
#ifndef IN_BM_MINI
sw_error_t
fal_port_bm_ctrl_get(a_uint32_t dev_id, fal_port_t port, a_bool_t *enable);
sw_error_t
fal_port_bufgroup_map_get(a_uint32_t dev_id, fal_port_t port,
a_uint8_t *group);
sw_error_t
fal_bm_bufgroup_buffer_get(a_uint32_t dev_id, a_uint8_t group,
a_uint16_t *buff_num);
sw_error_t
fal_bm_port_reserved_buffer_get(a_uint32_t dev_id, fal_port_t port,
a_uint16_t *prealloc_buff, a_uint16_t *react_buff);
sw_error_t
fal_bm_port_static_thresh_set(a_uint32_t dev_id, fal_port_t port,
fal_bm_static_cfg_t *cfg);
sw_error_t
fal_bm_port_static_thresh_get(a_uint32_t dev_id, fal_port_t port,
fal_bm_static_cfg_t *cfg);
sw_error_t
fal_bm_port_dynamic_thresh_get(a_uint32_t dev_id, fal_port_t port,
fal_bm_dynamic_cfg_t *cfg);
sw_error_t
fal_bm_port_counter_get(a_uint32_t dev_id, fal_port_t port,
fal_bm_port_counter_t *counter);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _PORT_BM_H_ */
/**
* @}
*/

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/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_cosmap FAL_COSMAP
* @{
*/
#ifndef _FAL_COSMAP_H_
#define _FAL_COSMAP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef struct
{
a_bool_t remark_dscp;
a_bool_t remark_up;
a_bool_t remark_dei;
a_uint8_t g_dscp;
a_uint8_t y_dscp;
a_uint8_t g_up;
a_uint8_t y_up;
a_uint8_t g_dei;
a_uint8_t y_dei;
} fal_egress_remark_table_t;
#ifndef IN_COSMAP_MINI
sw_error_t
fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t pri);
sw_error_t
fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t * pri);
sw_error_t
fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t dp);
sw_error_t
fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t * dp);
sw_error_t
fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t pri);
sw_error_t
fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t * pri);
sw_error_t
fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t dp);
sw_error_t
fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t * dp);
sw_error_t
fal_cosmap_dscp_to_ehpri_set(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t pri);
sw_error_t
fal_cosmap_dscp_to_ehpri_get(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t * pri);
sw_error_t
fal_cosmap_dscp_to_ehdp_set(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t dp);
sw_error_t
fal_cosmap_dscp_to_ehdp_get(a_uint32_t dev_id, a_uint32_t dscp,
a_uint32_t * dp);
sw_error_t
fal_cosmap_up_to_ehpri_set(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t pri);
sw_error_t
fal_cosmap_up_to_ehpri_get(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t * pri);
sw_error_t
fal_cosmap_up_to_ehdp_set(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t dp);
sw_error_t
fal_cosmap_up_to_ehdp_get(a_uint32_t dev_id, a_uint32_t up,
a_uint32_t * dp);
#endif
sw_error_t
fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
a_uint32_t queue);
sw_error_t
fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
a_uint32_t queue);
#ifndef IN_COSMAP_MINI
sw_error_t
fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
a_uint32_t * queue);
sw_error_t
fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
a_uint32_t * queue);
sw_error_t
fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
fal_egress_remark_table_t * tbl);
sw_error_t
fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
fal_egress_remark_table_t * tbl);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_COSMAP_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_ctrlpkt.h
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/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_gen FAL_CTRLPKT
* @{
*/
#ifndef _FAL_CTRLPKT_H_
#define _FAL_CTRLPKT_H_
#ifdef __cplusplus
extern "C" {
#endif
/* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
#define FAL_CTRLPKT_API_LOCK
#define FAL_CTRLPKT_API_UNLOCK
#else
#define FAL_CTRLPKT_API_LOCK
#define FAL_CTRLPKT_API_UNLOCK
#endif
typedef struct {
fal_fwd_cmd_t action; /* the action when condition matched */
a_bool_t sg_bypass; /* check if sg_bypass when condition matched */
a_bool_t l2_filter_bypass; /* check if l2_filter_bypass when condition matched */
a_bool_t in_stp_bypass; /* check if in_stp_bypass when condition matched */
a_bool_t in_vlan_fltr_bypass; /* check if in_vlan_fltr_bypass when condition matched */
} fal_ctrlpkt_action_t;
typedef struct
{
a_bool_t mgt_eapol; /* eapol protocol management type */
a_bool_t mgt_pppoe; /* pppoe protocol management type */
a_bool_t mgt_igmp; /* igmp protocol management type */
a_bool_t mgt_arp_req; /* arp request protocol management type */
a_bool_t mgt_arp_rep; /* arp response protocol management type */
a_bool_t mgt_dhcp4; /* dhcp4 protocol management type */
a_bool_t mgt_mld; /* mld protocol management type */
a_bool_t mgt_ns; /* ns protocol management type */
a_bool_t mgt_na; /* na protocol management type */
a_bool_t mgt_dhcp6; /* dhcp6 protocol management type */
} fal_ctrlpkt_protocol_type_t;
typedef struct {
fal_ctrlpkt_action_t action; /* the all action when condition matched */
fal_pbmp_t port_map; /* the condition port bitmap */
a_uint32_t ethtype_profile_bitmap; /* the condition ethtype_profile bitmap */
a_uint32_t rfdb_profile_bitmap; /* the condition rfdb_profile bitmap */
fal_ctrlpkt_protocol_type_t protocol_types; /* the condition protocol types */
} fal_ctrlpkt_profile_t;
enum {
FUNC_MGMTCTRL_ETHTYPE_PROFILE_SET = 0,
FUNC_MGMTCTRL_ETHTYPE_PROFILE_GET,
FUNC_MGMTCTRL_RFDB_PROFILE_SET,
FUNC_MGMTCTRL_RFDB_PROFILE_GET,
FUNC_MGMTCTRL_CTRLPKT_PROFILE_ADD,
FUNC_MGMTCTRL_CTRLPKT_PROFILE_DEL,
FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETFIRST,
FUNC_MGMTCTRL_CTRLPKT_PROFILE_GETNEXT,
};
sw_error_t fal_mgmtctrl_ethtype_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t ethtype);
sw_error_t fal_mgmtctrl_ethtype_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, a_uint32_t * ethtype);
sw_error_t fal_mgmtctrl_rfdb_profile_set(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
sw_error_t fal_mgmtctrl_rfdb_profile_get(a_uint32_t dev_id, a_uint32_t profile_id, fal_mac_addr_t *addr);
sw_error_t fal_mgmtctrl_ctrlpkt_profile_add(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
sw_error_t fal_mgmtctrl_ctrlpkt_profile_del(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
sw_error_t fal_mgmtctrl_ctrlpkt_profile_getfirst(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
sw_error_t fal_mgmtctrl_ctrlpkt_profile_getnext(a_uint32_t dev_id, fal_ctrlpkt_profile_t *ctrlpkt);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_CTRLPKT_H_ */
/**
* @}
*/

338
feeds/ipq807x/qca-ssdk/src/include/fal/fal_fdb.h
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/*
* Copyright (c) 2012, 2015-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_fdb FAL_FDB
* @{
*/
#ifndef _FAL_FDB_H_
#define _FAL_FDB_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@details Fields description:
portmap_en - If value of portmap_en is A_TRUE then port.map is valid
otherwise port.id is valid.
leaky_en - If value of leaky_en is A_TRUE then packets which
destination address equals addr in this entry would be leaky.
mirror_en - If value of mirror_en is A_TRUE then packets which
destination address equals addr in this entry would be mirrored.
clone_en - If value of clone_en is A_TRUE which means this address is
a mac clone address.
@brief This structure defines the Fdb entry.
*/
typedef struct
{
fal_mac_addr_t addr; /* mac address of fdb entry */
a_uint16_t fid; /* vlan_id/vsi value of fdb entry */
fal_fwd_cmd_t dacmd; /* source address command */
fal_fwd_cmd_t sacmd; /* dest address command */
union
{
fal_port_t id; /* union value is port id value */
fal_pbmp_t map; /* union value is bitmap value */
} port;
a_bool_t portmap_en; /* use port bitmap or not */
a_bool_t is_multicast; /* if it is a multicast mac fdb entry */
a_bool_t static_en; /* enable static or not */
a_bool_t leaky_en; /* enable leaky or not */
a_bool_t mirror_en; /* enable mirror or not */
a_bool_t clone_en; /* enable clone or not */
a_bool_t cross_pt_state; /* cross port state */
a_bool_t da_pri_en; /* enable da pri or not */
a_uint8_t da_queue; /* da queue value */
a_bool_t white_list_en; /* enable white list or not */
a_bool_t load_balance_en; /* enable load balance value or not */
a_uint8_t load_balance; /* load balance value */
a_bool_t entry_valid; /* check if entry is value */
a_bool_t lookup_valid; /* check if entry is lookup */
} fal_fdb_entry_t;
typedef struct
{
fal_mac_addr_t addr;
a_uint16_t fid;
a_uint8_t load_balance;
} fal_fdb_rfs_t;
typedef struct
{
a_bool_t enable; /* enable port learn limit or not */
a_uint32_t limit_num; /* port learn limit number */
fal_fwd_cmd_t action; /* the action when port learn number exceed limit*/
} fal_maclimit_ctrl_t;
#define FAL_FDB_DEL_STATIC 0x1
typedef struct
{
a_bool_t port_en; /* enable port value matching or not */
a_bool_t fid_en; /* enable fid value matching or not */
a_bool_t multicast_en; /* enable multicast value matching or not */
} fal_fdb_op_t;
typedef enum
{
INVALID_VLAN_SVL=0,
INVALID_VLAN_IVL
} fal_fdb_smode;
enum {
FUNC_FDB_ENTRY_ADD = 0,
FUNC_FDB_ENTRY_FLUSH,
FUNC_FDB_ENTRY_DEL_BYPORT,
FUNC_FDB_ENTRY_DEL_BYMAC,
FUNC_FDB_ENTRY_GETFIRST,
FUNC_FDB_ENTRY_GETNEXT,
FUNC_FDB_ENTRY_SEARCH,
FUNC_FDB_PORT_LEARN_SET,
FUNC_FDB_PORT_LEARN_GET,
FUNC_FDB_PORT_LEARNING_CTRL_SET,
FUNC_FDB_PORT_LEARNING_CTRL_GET,
FUNC_FDB_PORT_STAMOVE_CTRL_SET,
FUNC_FDB_PORT_STAMOVE_CTRL_GET,
FUNC_FDB_AGING_CTRL_SET,
FUNC_FDB_AGING_CTRL_GET,
FUNC_FDB_LEARNING_CTRL_SET,
FUNC_FDB_LEARNING_CTRL_GET,
FUNC_FDB_AGING_TIME_SET,
FUNC_FDB_AGING_TIME_GET,
FUNC_FDB_ENTRY_GETNEXT_BYINDEX,
FUNC_FDB_ENTRY_EXTEND_GETNEXT,
FUNC_FDB_ENTRY_EXTEND_GETFIRST,
FUNC_FDB_ENTRY_UPDATE_BYPORT,
FUNC_PORT_FDB_LEARN_LIMIT_SET,
FUNC_PORT_FDB_LEARN_LIMIT_GET,
FUNC_PORT_FDB_LEARN_EXCEED_CMD_SET,
FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET,
FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET,
FUNC_FDB_PORT_ADD,
FUNC_FDB_PORT_DEL,
FUNC_FDB_PORT_MACLIMIT_CTRL_SET,
FUNC_FDB_PORT_MACLIMIT_CTRL_GET,
FUNC_FDB_DEL_BY_FID,
};
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_entry_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_rfs_set(a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
sw_error_t
fal_fdb_rfs_del(a_uint32_t dev_id, const fal_fdb_rfs_t * entry);
#endif
sw_error_t
fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag);
sw_error_t
fal_fdb_entry_del_byport(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
sw_error_t
fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t *entry);
sw_error_t
fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry);
#endif
sw_error_t
fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
#endif
sw_error_t
fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, fal_fwd_cmd_t cmd);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable, fal_fwd_cmd_t *cmd);
#endif
sw_error_t
fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, fal_fwd_cmd_t cmd);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable, fal_fwd_cmd_t *cmd);
#endif
sw_error_t
fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
#endif
sw_error_t
fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
sw_error_t
fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
sw_error_t
fal_fdb_aging_time_set(a_uint32_t dev_id, a_uint32_t * time);
sw_error_t
fal_fdb_aging_time_get(a_uint32_t dev_id, a_uint32_t * time);
#endif
sw_error_t
fal_fdb_entry_getnext_byindex(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_entry_extend_getnext(a_uint32_t dev_id, fal_fdb_op_t * option,
fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_entry_extend_getfirst(a_uint32_t dev_id, fal_fdb_op_t * option,
fal_fdb_entry_t * entry);
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_entry_update_byport(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
a_uint32_t fid, fal_fdb_op_t * option);
sw_error_t
fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, a_uint32_t cnt);
sw_error_t
fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable, a_uint32_t * cnt);
sw_error_t
fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd);
sw_error_t
fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t * cmd);
sw_error_t
fal_fdb_port_learned_mac_counter_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * cnt);
sw_error_t
fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt);
sw_error_t
fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt);
sw_error_t
fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
sw_error_t
fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
sw_error_t
fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
sw_error_t
fal_fdb_port_maclimit_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
sw_error_t
fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
#endif
sw_error_t
fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag);
#define fal_fdb_add fal_fdb_entry_add
#define fal_fdb_del_all fal_fdb_entry_flush
#define fal_fdb_del_by_port fal_fdb_entry_del_byport
#define fal_fdb_del_by_mac fal_fdb_entry_del_bymac
#define fal_fdb_first fal_fdb_entry_getfirst
#define fal_fdb_next fal_fdb_entry_getnext
#define fal_fdb_find fal_fdb_entry_search
#define fal_fdb_age_ctrl_set fal_fdb_aging_ctrl_set
#define fal_fdb_age_ctrl_get fal_fdb_aging_ctrl_get
#define fal_fdb_age_time_set fal_fdb_aging_time_set
#define fal_fdb_age_time_get fal_fdb_aging_time_get
#define fal_fdb_iterate fal_fdb_entry_getnext_byindex
#define fal_fdb_extend_next fal_fdb_entry_extend_getnext
#define fal_fdb_extend_first fal_fdb_entry_extend_getfirst
#define fal_fdb_transfer fal_fdb_entry_update_byport
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_FDB_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_flow.h
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/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_flow
* @{
*/
#ifndef _FAL_FLOW_H_
#define _FAL_FLOW_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#include "fal/fal_ip.h"
typedef enum {
FAL_FLOW_L3_UNICAST = 0,
FAL_FLOW_L2_UNICAST,
FAL_FLOW_MCAST,
} fal_flow_pkt_type_t;
typedef enum {
FAL_FLOW_LAN_TO_LAN_DIR = 0,
FAL_FLOW_LAN_TO_WAN_DIR,
FAL_FLOW_WAN_TO_LAN_DIR,
FAL_FLOW_WAN_TO_WAN_DIR,
FAL_FLOW_UNKOWN_DIR_DIR,
} fal_flow_direction_t;
typedef enum {
FAL_FLOW_FORWARD = 0,
FAL_FLOW_SNAT,
FAL_FLOW_DNAT,
FAL_FLOW_ROUTE,
FAL_FLOW_BRIDGE,
} fal_flow_fwd_type_t;
/* FLOW entry type field */
#define FAL_FLOW_IP4_5TUPLE_ADDR 0x1
#define FAL_FLOW_IP6_5TUPLE_ADDR 0x2
#define FAL_FLOW_IP4_3TUPLE_ADDR 0x4
#define FAL_FLOW_IP6_3TUPLE_ADDR 0x8
#define FAL_FLOW_OP_MODE_KEY 0x0
#define FAL_FLOW_OP_MODE_INDEX 0x1
#define FAL_FLOW_OP_MODE_FLUSH 0x2
#define FAL_FLOW_PROTOCOL_OTHER 0
#define FAL_FLOW_PROTOCOL_TCP 1
#define FAL_FLOW_PROTOCOL_UDP 2
#define FAL_FLOW_PROTOCOL_UDPLITE 3
typedef struct {
fal_fwd_cmd_t miss_action; /* flow mismatch action*/
a_bool_t frag_bypass_en; /*0 for disable and 1 for enable*/
a_bool_t tcp_spec_bypass_en; /*0 for disable and 1 for enable*/
a_bool_t all_bypass_en; /*0 for disable and 1 for enable*/
a_uint8_t key_sel; /*0 for source ip address and 1 for destination ip address*/
} fal_flow_mgmt_t;
typedef struct {
a_uint32_t entry_id; /*entry index*/
a_uint8_t entry_type; /*1:ipv4 5 tuple, 2:ipv6 5 tuple, 4:ipv4 3 tuple, 8:ipv6 3 tuple*/
a_uint8_t host_addr_type; /*0:souce ip index, 1:destination ip index*/
a_uint16_t host_addr_index; /*host table entry index*/
a_uint8_t protocol; /*1:tcp, 2:udp, 3:udp-lite, 0:other*/
a_uint8_t age; /*aging value*/
a_bool_t src_intf_valid; /*source interface check valid*/
a_uint8_t src_intf_index; /*souce l3 interface*/
a_uint8_t fwd_type; /*forward type*/
a_uint16_t snat_nexthop; /*nexthop index for snat*/
a_uint16_t snat_srcport; /*new source l4 port*/
a_uint16_t dnat_nexthop; /*nexthop index for dnat*/
a_uint16_t dnat_dstport; /*new destination l4 port*/
a_uint16_t route_nexthop; /*nexthop index for route*/
a_bool_t port_valid; /*route port valid*/
fal_port_t route_port; /*port for route*/
fal_port_t bridge_port; /*port for l2 bridge*/
a_bool_t deacclr_en; /*0 for disable and 1 for enable*/
a_bool_t copy_tocpu_en; /*0 for disable and 1 for enable*/
a_uint8_t syn_toggle; /*update by host*/
a_uint8_t pri_profile; /*flow qos index*/
a_uint8_t sevice_code; /*service code for bypass*/
a_uint8_t ip_type; /*0 for ipv4 and 1 for ipv6*/
union {
fal_ip4_addr_t ipv4;
fal_ip6_addr_t ipv6;
} flow_ip;
a_uint16_t src_port; /*l4 source port*/
a_uint16_t dst_port; /*l4 destination port*/
a_uint32_t tree_id; /*for qos*/
a_uint32_t pkt_counter; /*flow packet counter*/
a_uint64_t byte_counter; /*flow byte counter*/
} fal_flow_entry_t;
typedef struct {
fal_fwd_cmd_t src_if_check_action; /*source inferface check fail action*/
a_bool_t src_if_check_deacclr_en; /*0 for disable and 1 for enable*/
a_bool_t service_loop_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t service_loop_action; /*0 for disable and 1 for enable*/
a_bool_t service_loop_deacclr_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t flow_deacclr_action; /*flow de acceleration action*/
fal_fwd_cmd_t sync_mismatch_action; /*sync toggle mismatch action*/
a_bool_t sync_mismatch_deacclr_en; /*0 for disable and 1 for enable*/
a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/
a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/
a_bool_t flow_mismatch_copy_escape_en; /*0 for disable and 1 for enable*/
} fal_flow_global_cfg_t;
typedef struct {
fal_flow_entry_t flow_entry;
fal_host_entry_t host_entry;
} fal_flow_host_entry_t;
typedef struct {
a_uint16_t age_time; /* age value*/
a_uint16_t unit; /*0:second 1:cycle 2:million cycle*/
} fal_flow_age_timer_t;
enum {
FUNC_FLOW_HOST_ADD = 0,
FUNC_FLOW_ENTRY_GET,
FUNC_FLOW_ENTRY_DEL,
FUNC_FLOW_STATUS_GET,
FUNC_FLOW_CTRL_SET,
FUNC_FLOW_AGE_TIMER_GET,
FUNC_FLOW_STATUS_SET,
FUNC_FLOW_HOST_GET,
FUNC_FLOW_HOST_DEL,
FUNC_FLOW_CTRL_GET,
FUNC_FLOW_AGE_TIMER_SET,
FUNC_FLOW_ENTRY_ADD,
FUNC_FLOW_GLOBAL_CFG_GET,
FUNC_FLOW_GLOBAL_CFG_SET,
FUNC_FLOW_ENTRY_NEXT
};
#ifndef IN_FLOW_MINI
sw_error_t
fal_flow_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_flow_status_get(a_uint32_t dev_id, a_bool_t *enable);
sw_error_t
fal_flow_age_timer_set(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
sw_error_t
fal_flow_age_timer_get(a_uint32_t dev_id, fal_flow_age_timer_t *age_timer);
#endif
sw_error_t
fal_flow_mgmt_set(
a_uint32_t dev_id,
fal_flow_pkt_type_t type,
fal_flow_direction_t dir,
fal_flow_mgmt_t *mgmt);
sw_error_t
fal_flow_mgmt_get(
a_uint32_t dev_id,
fal_flow_pkt_type_t type,
fal_flow_direction_t dir,
fal_flow_mgmt_t *mgmt);
#ifndef IN_FLOW_MINI
sw_error_t
fal_flow_entry_add(
a_uint32_t dev_id,
a_uint32_t add_mode, /*index or hash*/
fal_flow_entry_t *flow_entry);
sw_error_t
fal_flow_entry_del(
a_uint32_t dev_id,
a_uint32_t del_mode,
fal_flow_entry_t *flow_entry);
sw_error_t
fal_flow_entry_get(
a_uint32_t dev_id,
a_uint32_t get_mode,
fal_flow_entry_t *flow_entry);
sw_error_t
fal_flow_entry_next(
a_uint32_t dev_id,
a_uint32_t next_mode,
fal_flow_entry_t *flow_entry);
sw_error_t
fal_flow_host_add(
a_uint32_t dev_id,
a_uint32_t add_mode,
fal_flow_host_entry_t *flow_host_entry);
sw_error_t
fal_flow_host_del(
a_uint32_t dev_id,
a_uint32_t del_mode,
fal_flow_host_entry_t *flow_host_entry);
sw_error_t
fal_flow_host_get(
a_uint32_t dev_id,
a_uint32_t get_mode,
fal_flow_host_entry_t *flow_host_entry);
sw_error_t
fal_flow_global_cfg_get(
a_uint32_t dev_id,
fal_flow_global_cfg_t *cfg);
sw_error_t
fal_flow_global_cfg_set(
a_uint32_t dev_id,
fal_flow_global_cfg_t *cfg);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_FLOW_H_ */
/**
* @}
*/

43
feeds/ipq807x/qca-ssdk/src/include/fal/fal_flowcookie.h
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/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _FAL_FLOWCOOKIE_H_
#define _FAL_FLOWCOOKIE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
int ssdk_flow_cookie_set(
u32 protocol, __be32 src_ip,
__be16 src_port, __be32 dst_ip,
__be16 dst_port, u16 flowcookie);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_FLOWCOOKIE_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_igmp.h
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/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_igmp FAL_IGMP
* @{
*/
#ifndef _FAL_IGMP_H_
#define _FAL_IGMP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#include "fal/fal_multi.h"
sw_error_t
fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
sw_error_t
fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
sw_error_t
fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
sw_error_t
fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t static_en);
sw_error_t
fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * static_en);
sw_error_t
fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
sw_error_t
fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
sw_error_t
fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, a_uint32_t cnt);
sw_error_t
fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable, a_uint32_t * cnt);
sw_error_t
fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd);
sw_error_t
fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t * cmd);
sw_error_t
fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
sw_error_t
fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
sw_error_t
fal_igmp_sg_entry_show(a_uint32_t dev_id);
sw_error_t
fal_igmp_sg_entry_query(a_uint32_t dev_id, fal_igmp_sg_info_t * info);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_IGMP_H_ */
/**
* @}
*/

84
feeds/ipq807x/qca-ssdk/src/include/fal/fal_init.h
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@@ -1,84 +0,0 @@
/*
* Copyright (c) 2012, 2016-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*qca808x_start*/
/**
* @defgroup fal_init FAL_INIT
* @{
*/
#ifndef _FAL_INIT_H_
#define _FAL_INIT_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "ssdk_init.h"
/*qca808x_end*/
enum{
FAL_MODULE_ACL,
FAL_MODULE_VSI,
FAL_MODULE_IP,
FAL_MODULE_FLOW,
FAL_MODULE_QM,
FAL_MODULE_QOS,
FAL_MODULE_BM,
FAL_MODULE_SERVCODE,
FAL_MODULE_RSS_HASH,
FAL_MODULE_PPPOE,
FAL_MODULE_SHAPER,
FAL_MODULE_PORTCTRL,
FAL_MODULE_MIB,
FAL_MODULE_MIRROR,
FAL_MODULE_FDB,
FAL_MODULE_STP,
FAL_MODULE_TRUNK,
FAL_MODULE_PORTVLAN,
FAL_MODULE_CTRLPKT,
FAL_MODULE_SEC,
FAL_MODULE_POLICER,
FAL_MODULE_MISC,
FAL_MODULE_PTP,
FAL_MODULE_SFP,
FAL_MODULE_MAX,
};
typedef struct
{
a_uint32_t bitmap[3];
}fal_func_ctrl_t;
/*qca808x_start*/
sw_error_t fal_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
/*qca808x_end*/
sw_error_t fal_reset(a_uint32_t dev_id);
sw_error_t fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg);
/*qca808x_start*/
sw_error_t fal_cleanup(void);
/*qca808x_end*/
sw_error_t fal_module_func_ctrl_set(a_uint32_t dev_id,
a_uint32_t module, fal_func_ctrl_t *func_ctrl);
sw_error_t fal_module_func_ctrl_get(a_uint32_t dev_id,
a_uint32_t module, fal_func_ctrl_t *func_ctrl);
sw_error_t fal_module_func_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
sw_error_t fal_switch_devid_get(ssdk_chip_type chip_type, a_uint32_t *pdev_id);
/*qca808x_start*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_INIT_H_ */
/**
* @}
*/
/*qca808x_end*/

181
feeds/ipq807x/qca-ssdk/src/include/fal/fal_interface_ctrl.h
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@@ -1,181 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL
* @{
*/
#ifndef _FAL_INTERFACECTRL_H_
#define _FAL_INTERFACECTRL_H_
#ifdef __cplusplus
extern "c" {
#endif
#include "sw.h"
#include "fal/fal_type.h"
typedef enum {
FAL_MAC_MODE_RGMII = 0,
FAL_MAC_MODE_GMII,
FAL_MAC_MODE_MII,
FAL_MAC_MODE_SGMII,
FAL_MAC_MODE_FIBER,
FAL_MAC_MODE_RMII,
FAL_MAC_MODE_DEFAULT
}
fal_interface_mac_mode_t;
typedef enum
{
FAL_INTERFACE_CLOCK_MAC_MODE = 0,
FAL_INTERFACE_CLOCK_PHY_MODE = 1,
} fal_interface_clock_mode_t;
typedef struct
{
a_bool_t txclk_delay_cmd;
a_bool_t rxclk_delay_cmd;
a_uint32_t txclk_delay_sel;
a_uint32_t rxclk_delay_sel;
} fal_mac_rgmii_config_t;
typedef struct
{
a_bool_t master_mode;
a_bool_t slave_mode;
a_bool_t clock_inverse;
a_bool_t pipe_rxclk_sel;
} fal_mac_rmii_config_t;
typedef struct
{
fal_interface_clock_mode_t clock_mode;
a_uint32_t txclk_select;
a_uint32_t rxclk_select;
} fal_mac_gmii_config_t;
typedef struct
{
fal_interface_clock_mode_t clock_mode;
a_uint32_t txclk_select;
a_uint32_t rxclk_select;
} fal_mac_mii_config_t;
typedef struct
{
fal_interface_clock_mode_t clock_mode;
a_bool_t auto_neg;
a_bool_t force_speed;
a_bool_t prbs_enable;
a_bool_t rem_phy_lpbk;
} fal_mac_sgmii_config_t;
typedef struct
{
a_bool_t auto_neg;
a_bool_t fx100_enable;
} fal_mac_fiber_config_t;
typedef struct
{
fal_interface_mac_mode_t mac_mode;
union
{
fal_mac_rgmii_config_t rgmii;
fal_mac_gmii_config_t gmii;
fal_mac_mii_config_t mii;
fal_mac_sgmii_config_t sgmii;
fal_mac_rmii_config_t rmii;
fal_mac_fiber_config_t fiber;
} config;
} fal_mac_config_t;
typedef struct
{
fal_interface_mac_mode_t mac_mode;
a_bool_t txclk_delay_cmd;
a_bool_t rxclk_delay_cmd;
a_uint32_t txclk_delay_sel;
a_uint32_t rxclk_delay_sel;
} fal_phy_config_t;
typedef enum
{
Fx100BASE_MODE = 2,
} fx100_ctrl_link_mode_t;
typedef enum
{
FX100_SERDS_MODE = 1,
} sgmii_fiber_mode_t;
#define FX100_HALF_DUPLEX 0
#define FX100_FULL_DUPLEX 1
typedef struct
{
fx100_ctrl_link_mode_t link_mode;
a_bool_t overshoot;
a_bool_t loopback;
a_bool_t fd_mode;
a_bool_t col_test;
sgmii_fiber_mode_t sgmii_fiber_mode;
a_bool_t crs_ctrl;
a_bool_t loopback_ctrl;
a_bool_t crs_col_100_ctrl;
a_bool_t loop_en;
} fal_fx100_ctrl_config_t;
sw_error_t
fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
sw_error_t
fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
sw_error_t
fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
sw_error_t
fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
sw_error_t
fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
sw_error_t
fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
sw_error_t
fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status);
sw_error_t
fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_INTERFACECTRL_H_ */
/**
* @}
*/

646
feeds/ipq807x/qca-ssdk/src/include/fal/fal_ip.h
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@@ -1,646 +0,0 @@
/*
* Copyright (c) 2012, 2015, 2017-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_ip FAL_IP
* @{
*/
#ifndef _FAL_IP_H_
#define _FAL_IP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#include "fal_multi.h"
#define FAL_MIN_VRF_ID 0
#define FAL_MAX_VRF_ID 7
/* IP WCMP hash key flags */
#define FAL_WCMP_HASH_KEY_SIP 0x1
#define FAL_WCMP_HASH_KEY_DIP 0x2
#define FAL_WCMP_HASH_KEY_SPORT 0x4
#define FAL_WCMP_HASH_KEY_DPORT 0x8
/* IP entry operation flags */
#define FAL_IP_ENTRY_ID_EN 0x1
#define FAL_IP_ENTRY_INTF_EN 0x2
#define FAL_IP_ENTRY_PORT_EN 0x4
#define FAL_IP_ENTRY_STATUS_EN 0x8
#define FAL_IP_ENTRY_IPADDR_EN 0x10
#define FAL_IP_ENTRY_ALL_EN 0x20
/* IP host entry structure flags field */
#define FAL_IP_IP4_ADDR 0x1
#define FAL_IP_IP6_ADDR 0x2
#define FAL_IP_CPU_ADDR 0x4
#define FAL_IP_IP4_ADDR_MCAST 0x8
#define FAL_IP_IP6_ADDR_MCAST 0x10
typedef struct {
a_uint8_t vsi; /*vsi value for l2 multicast*/
fal_ip4_addr_t sip4_addr; /*source ipv4 address*/
fal_ip6_addr_t sip6_addr; /*source ipv4 address*/
} fal_host_mcast_t;
typedef struct
{
a_uint32_t rx_pkt_counter; /*rx packet counter*/
a_uint64_t rx_byte_counter; /*rx byte counter*/
a_uint32_t rx_drop_pkt_counter; /*rx drop packet counter*/
a_uint64_t rx_drop_byte_counter; /*rx drop byte counter*/
a_uint32_t tx_pkt_counter; /*tx packet counter*/
a_uint64_t tx_byte_counter; /*tx byte counter*/
a_uint32_t tx_drop_pkt_counter; /*tx drop packet counter*/
a_uint64_t tx_drop_byte_counter; /*tx drop byte counter*/
} fal_ip_counter_t;
typedef struct
{
a_uint32_t entry_id; /*index for host table*/
a_uint32_t flags; /*1:ipv4 uni 2:ipv6 uni 8:ipv4 multi 0x10:ipv6 multi*/
a_uint32_t status; /* valid status: 0 or 1*/
fal_ip4_addr_t ip4_addr; /* ipv4 address */
fal_ip6_addr_t ip6_addr; /* ipv6 address */
fal_mac_addr_t mac_addr; /* unused for ppe */
a_uint32_t intf_id; /* unused for ppe */
a_uint32_t lb_num; /* unused for ppe */
a_uint32_t vrf_id; /* unused for ppe */
a_uint32_t expect_vid; /* unused for ppe */
fal_port_t port_id; /* unused for ppe */
a_bool_t mirror_en; /* unused for ppe */
a_bool_t counter_en; /* unused for ppe */
a_uint32_t counter_id; /* unused for ppe */
a_uint32_t packet; /* unused for ppe */
a_uint32_t byte; /* unused for ppe */
a_bool_t pppoe_en; /* unused for ppe */
a_uint32_t pppoe_id; /* unused for ppe */
fal_fwd_cmd_t action; /*forward action*/
a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/
a_uint8_t syn_toggle; /* sync toggle */
a_uint8_t lan_wan; /*0: ip over lan side ; 1: ip over wan side*/
fal_host_mcast_t mcast_info; /* multicast information */
} fal_host_entry_t;
typedef enum
{
FAL_MAC_IP_GUARD = 0,
FAL_MAC_IP_PORT_GUARD,
FAL_MAC_IP_VLAN_GUARD,
FAL_MAC_IP_PORT_VLAN_GUARD,
FAL_NO_SOURCE_GUARD,
} fal_source_guard_mode_t;
typedef enum
{
FAL_DEFAULT_FLOW_FORWARD = 0,
FAL_DEFAULT_FLOW_DROP,
FAL_DEFAULT_FLOW_RDT_TO_CPU,
FAL_DEFAULT_FLOW_ADMIT_ALL,
} fal_default_flow_cmd_t;
typedef enum
{
FAL_FLOW_LAN_TO_LAN = 0,
FAL_FLOW_WAN_TO_LAN,
FAL_FLOW_LAN_TO_WAN,
FAL_FLOW_WAN_TO_WAN,
} fal_flow_type_t;
typedef enum
{
FAL_GLB_LOCK_TIME_DISABLE = 0,
FAL_GLB_LOCK_TIME_100US,
FAL_GLB_LOCK_TIME_1MS,
FAL_GLB_LOCK_TIME_10MS,
} fal_glb_lock_time_t;
typedef enum
{
FAL_ARP_LEARN_LOCAL = 0,
FAL_ARP_LEARN_ALL,
} fal_arp_learn_mode_t;
/* IP host entry auto learn arp packets type */
#define FAL_ARP_LEARN_REQ 0x1
#define FAL_ARP_LEARN_ACK 0x2
typedef struct
{
a_uint32_t entry_id;
a_uint32_t vrf_id;
a_uint16_t vid_low;
a_uint16_t vid_high;
fal_mac_addr_t mac_addr;
a_bool_t ip4_route;
a_bool_t ip6_route;
} fal_intf_mac_entry_t;
typedef struct
{
a_uint32_t nh_nr;
a_uint32_t nh_id[16];
} fal_ip_wcmp_t;
typedef struct
{
fal_mac_addr_t mac_addr;
fal_ip4_addr_t ip4_addr;
a_uint32_t vid;
a_uint8_t load_balance;
} fal_ip4_rfs_t;
typedef struct
{
fal_mac_addr_t mac_addr;
fal_ip6_addr_t ip6_addr;
a_uint32_t vid;
a_uint8_t load_balance;
} fal_ip6_rfs_t;
typedef struct
{
a_bool_t valid;
a_uint32_t vrf_id;
fal_addr_type_t ip_version; /*0 for IPv4 and 1 for IPv6*/
a_uint32_t droute_type; /*0 for ARP and 1 for WCMP*/
a_uint32_t index;/*when droute_type equals 0, means ARP entry index or means WCMP indexs*/
} fal_default_route_t;
typedef struct
{
a_bool_t valid;
a_uint32_t vrf_id;
a_uint32_t ip_version; /*0 for IPv4 and 1 for IPv6*/
union {
fal_ip4_addr_t ip4_addr;
fal_ip6_addr_t ip6_addr;
}route_addr;
a_uint32_t prefix_length;/*For IPv4, up to 32 and for IPv6, up to 128*/
} fal_host_route_t;
typedef struct
{
a_bool_t ipv4_arp_sg_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t ipv4_arp_sg_vio_action; /* check fail action for arp source guard */
a_bool_t ipv4_arp_sg_port_en; /* source port based arp source guard enable */
a_bool_t ipv4_arp_sg_svlan_en; /* source svlan based arp source guard enable */
a_bool_t ipv4_arp_sg_cvlan_en; /* source cvlan based arp source guard enable */
fal_fwd_cmd_t ipv4_arp_src_unk_action; /* unknown action for arp source guard */
a_bool_t ip_nd_sg_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t ip_nd_sg_vio_action; /* check fail action for nd source guard */
a_bool_t ip_nd_sg_port_en; /* source port based nd source guard enable */
a_bool_t ip_nd_sg_svlan_en; /* source svlan based nd source guard enable */
a_bool_t ip_nd_sg_cvlan_en; /* source cvlan based nd source guard enable */
fal_fwd_cmd_t ip_nd_src_unk_action; /* unknown action for nd source guard */
} fal_arp_sg_cfg_t;
typedef enum
{
FAL_MC_MODE_GV = 0, /*not support igmpv3 source filter*/
FAL_MC_MODE_SGV /*support igmpv3 source filter*/
} fal_mc_mode_t;
typedef struct
{
a_bool_t l2_ipv4_mc_en; /*0 for disable and 1 for enable*/
fal_mc_mode_t l2_ipv4_mc_mode; /*two modes*/
a_bool_t l2_ipv6_mc_en; /*0 for disable and 1 for enable*/
fal_mc_mode_t l2_ipv6_mc_mode; /*same with IPv4*/
} fal_mc_mode_cfg_t;
typedef struct
{
a_uint8_t type; /*0 for IPv4 and 1 for IPv6*/
fal_fwd_cmd_t action; /* forward action */
a_uint32_t dst_info; /*bit 12:13: 1.nexthop, 2.port id, 3.port bitmap*/
a_uint8_t lan_wan; /* 0:ip over lan side; 1:ip over wan side */
union {
fal_ip4_addr_t ip4_addr; /* ipv4 address */
fal_ip6_addr_t ip6_addr; /* ipv6 address */
} route_addr;
union {
fal_ip4_addr_t ip4_addr_mask; /* ipv4 address mask */
fal_ip6_addr_t ip6_addr_mask; /* ipv6 address mask */
} route_addr_mask;
} fal_network_route_entry_t;
typedef struct {
a_uint16_t mru; /* Maximum Receive Unit*/
a_uint16_t mtu; /* Maximum Transmission Unit*/
a_bool_t ttl_dec_bypass_en; /* Bypass TTL Decrement enable*/
a_bool_t ipv4_uc_route_en; /*0 for disble and 1 for enable*/
a_bool_t ipv6_uc_route_en; /*0 for disble and 1 for enable*/
a_bool_t icmp_trigger_en; /* ICMP trigger flag enable*/
fal_fwd_cmd_t ttl_exceed_action; /*action for ttl 0*/
a_bool_t ttl_exceed_deacclr_en; /*0 for disble and 1 for enable*/
a_uint8_t mac_addr_bitmap; /* bitmap for mac address*/
fal_mac_addr_t mac_addr; /* mac address */
fal_ip_counter_t counter; /* interface related counter */
} fal_intf_entry_t;
typedef struct
{
a_bool_t l3_if_valid; /*0 for disable and 1 for enable*/
a_uint32_t l3_if_index; /*index for interface table*/
} fal_intf_id_t;
typedef enum
{
FAL_NEXTHOP_L3 = 0,
FAL_NEXTHOP_VP,
} fal_nexthop_type_t;
typedef struct
{
fal_nexthop_type_t type; /* 0: L3 1:port*/
a_uint8_t vsi; /* output vsi value if type is 0 */
fal_port_t port; /* destination port */
a_uint32_t if_index; /* egress interface index */
a_bool_t ip_to_me_en; /* 0 for disable and 1 for enable*/
a_uint8_t pub_ip_index; /*index to public ip address*/
a_uint8_t stag_fmt; /* 0: untag 1:tagged*/
a_uint16_t svid; /*svlan id*/
a_int8_t ctag_fmt; /* 0: untag 1:tagged*/
a_uint16_t cvid; /* cvlan id */
fal_mac_addr_t mac_addr; /* mac address */
fal_ip4_addr_t dnat_ip; /*dnat ip address*/
} fal_ip_nexthop_t;
typedef struct
{
a_bool_t ipv4_sg_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t ipv4_sg_vio_action; /* check fail action for ipv4 source guard */
a_bool_t ipv4_sg_port_en; /* source port based ipv4 source guard enable */
a_bool_t ipv4_sg_svlan_en; /* source svlan based ipv4 source guard enable */
a_bool_t ipv4_sg_cvlan_en; /* source cvlan based ipv4 source guard enable */
fal_fwd_cmd_t ipv4_src_unk_action; /* unknown action for ipv4 source guard */
a_bool_t ipv6_sg_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t ipv6_sg_vio_action; /* check fail action for ipv6 source guard */
a_bool_t ipv6_sg_port_en; /* source port based ipv6 source guard enable */
a_bool_t ipv6_sg_svlan_en; /* source svlan based ipv6 source guard enable */
a_bool_t ipv6_sg_cvlan_en; /* source cvlan based ipv6 source guard enable */
fal_fwd_cmd_t ipv6_src_unk_action; /* unknown action for ipv6 source guard */
} fal_sg_cfg_t;
typedef struct
{
fal_ip4_addr_t pub_ip_addr; /*public ip address*/
} fal_ip_pub_addr_t;
typedef struct {
a_bool_t valid; /* valid flag */
fal_mac_addr_t mac_addr; /* mac address */
} fal_macaddr_entry_t;
typedef struct
{
fal_fwd_cmd_t mru_fail_action; /*mru check fail action*/
a_bool_t mru_deacclr_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t mtu_fail_action; /*mtu check fail action*/
a_bool_t mtu_deacclr_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t mtu_nonfrag_fail_action; /*mtu check fail action for non-fragment */
a_bool_t mtu_df_deacclr_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t prefix_bc_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/
a_bool_t prefix_deacclr_en; /*0 for disable and 1 for enable*/
fal_fwd_cmd_t icmp_rdt_action; /*0 forward, 1 drop, 2 copy, 3 rdt_cpu*/
a_bool_t icmp_rdt_deacclr_en; /*0 for disable and 1 for enable*/
a_uint8_t hash_mode_0; /*0 crc10, 1 xor, 2 crc16*/
a_uint8_t hash_mode_1; /*0 crc10, 1 xor, 2 crc16*/
} fal_ip_global_cfg_t;
enum {
FUNC_IP_NETWORK_ROUTE_GET = 0,
FUNC_IP_HOST_ADD,
FUNC_IP_VSI_SG_CFG_GET,
FUNC_IP_PUB_ADDR_SET,
FUNC_IP_PORT_SG_CFG_SET,
FUNC_IP_PORT_INTF_GET,
FUNC_IP_VSI_ARP_SG_CFG_SET,
FUNC_IP_PUB_ADDR_GET,
FUNC_IP_PORT_INTF_SET,
FUNC_IP_VSI_SG_CFG_SET,
FUNC_IP_HOST_NEXT,
FUNC_IP_PORT_MACADDR_SET,
FUNC_IP_VSI_INTF_GET,
FUNC_IP_NETWORK_ROUTE_ADD,
FUNC_IP_PORT_SG_CFG_GET,
FUNC_IP_INTF_GET,
FUNC_IP_NETWORK_ROUTE_DEL,
FUNC_IP_HOST_DEL,
FUNC_IP_ROUTE_MISMATCH_GET,
FUNC_IP_VSI_ARP_SG_CFG_GET,
FUNC_IP_PORT_ARP_SG_CFG_SET,
FUNC_IP_VSI_MC_MODE_SET,
FUNC_IP_VSI_INTF_SET,
FUNC_IP_NEXTHOP_GET,
FUNC_IP_ROUTE_MISMATCH_SET,
FUNC_IP_HOST_GET,
FUNC_IP_INTF_SET,
FUNC_IP_VSI_MC_MODE_GET,
FUNC_IP_PORT_MACADDR_GET,
FUNC_IP_PORT_ARP_SG_CFG_GET,
FUNC_IP_NEXTHOP_SET,
FUNC_IP_GLOBAL_CTRL_GET,
FUNC_IP_GLOBAL_CTRL_SET,
};
#ifndef IN_IP_MINI
sw_error_t
fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
sw_error_t
fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
fal_host_entry_t * host_entry);
sw_error_t
fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
fal_host_entry_t * host_entry);
sw_error_t
fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
fal_host_entry_t * host_entry);
sw_error_t
fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
a_uint32_t cnt_id, a_bool_t enable);
sw_error_t
fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
a_uint32_t pppoe_id, a_bool_t enable);
sw_error_t
fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t flags);
sw_error_t
fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * flags);
sw_error_t
fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
sw_error_t
fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
sw_error_t
fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
fal_source_guard_mode_t mode);
sw_error_t
fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
fal_source_guard_mode_t * mode);
sw_error_t
fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
fal_source_guard_mode_t mode);
sw_error_t
fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
fal_source_guard_mode_t * mode);
sw_error_t
fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
sw_error_t
fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
fal_intf_mac_entry_t * entry);
sw_error_t
fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
fal_intf_mac_entry_t * entry);
sw_error_t
fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
sw_error_t
fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
sw_error_t
fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
sw_error_t
fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
sw_error_t
fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
sw_error_t
fal_ip_rfs_ip4_rule_set(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
sw_error_t
fal_ip_rfs_ip6_rule_set(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
sw_error_t
fal_ip_rfs_ip4_rule_del(a_uint32_t dev_id, fal_ip4_rfs_t * rfs);
sw_error_t
fal_ip_rfs_ip6_rule_del(a_uint32_t dev_id, fal_ip6_rfs_t * rfs);
sw_error_t
fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
sw_error_t
fal_ip_vrf_base_addr_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
sw_error_t
fal_ip_vrf_base_addr_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
sw_error_t
fal_ip_vrf_base_mask_set(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t addr);
sw_error_t
fal_ip_vrf_base_mask_get(a_uint32_t dev_id, a_uint32_t vrf_id, fal_ip4_addr_t * addr);
sw_error_t
fal_ip_default_route_set(a_uint32_t dev_id, a_uint32_t droute_id,
fal_default_route_t * entry);
sw_error_t
fal_ip_default_route_get(a_uint32_t dev_id, a_uint32_t droute_id,
fal_default_route_t * entry);
sw_error_t
fal_ip_host_route_set(a_uint32_t dev_id, a_uint32_t hroute_id,
fal_host_route_t * entry);
sw_error_t
fal_ip_host_route_get(a_uint32_t dev_id, a_uint32_t hroute_id,
fal_host_route_t * entry);
sw_error_t
fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id,
fal_ip_wcmp_t * wcmp);
sw_error_t
fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id,
fal_ip_wcmp_t * wcmp);
sw_error_t
fal_default_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
fal_flow_type_t type, fal_default_flow_cmd_t cmd);
sw_error_t
fal_default_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
sw_error_t
fal_default_rt_flow_cmd_set(a_uint32_t dev_id, a_uint32_t vrf_id,
fal_flow_type_t type, fal_default_flow_cmd_t cmd);
sw_error_t
fal_default_rt_flow_cmd_get(a_uint32_t dev_id, a_uint32_t vrf_id,
fal_flow_type_t type, fal_default_flow_cmd_t * cmd);
sw_error_t
fal_ip_vsi_arp_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
fal_arp_sg_cfg_t *arp_sg_cfg);
sw_error_t
fal_ip_vsi_arp_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
fal_arp_sg_cfg_t *arp_sg_cfg);
sw_error_t
fal_ip_network_route_add(a_uint32_t dev_id, a_uint32_t index,
fal_network_route_entry_t *entry);
sw_error_t
fal_ip_network_route_get(a_uint32_t dev_id,
a_uint32_t index, a_uint8_t type,
fal_network_route_entry_t *entry);
sw_error_t
fal_ip_network_route_del(a_uint32_t dev_id,
a_uint32_t index, a_uint8_t type);
sw_error_t
fal_ip_intf_set(a_uint32_t dev_id,
a_uint32_t index,
fal_intf_entry_t *entry);
sw_error_t
fal_ip_intf_get(a_uint32_t dev_id,
a_uint32_t index,
fal_intf_entry_t *entry);
sw_error_t
fal_ip_vsi_intf_set(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
sw_error_t
fal_ip_vsi_intf_get(a_uint32_t dev_id, a_uint32_t vsi, fal_intf_id_t *id);
sw_error_t
fal_ip_port_intf_set(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
sw_error_t
fal_ip_port_intf_get(a_uint32_t dev_id, fal_port_t port_id, fal_intf_id_t *id);
sw_error_t
fal_ip_nexthop_set(a_uint32_t dev_id, a_uint32_t index,
fal_ip_nexthop_t *entry);
sw_error_t
fal_ip_nexthop_get(a_uint32_t dev_id, a_uint32_t index,
fal_ip_nexthop_t *entry);
sw_error_t
fal_ip_vsi_sg_cfg_get(a_uint32_t dev_id, a_uint32_t vsi,
fal_sg_cfg_t *sg_cfg);
sw_error_t
fal_ip_vsi_sg_cfg_set(a_uint32_t dev_id, a_uint32_t vsi,
fal_sg_cfg_t *sg_cfg);
sw_error_t
fal_ip_port_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
fal_sg_cfg_t *sg_cfg);
sw_error_t
fal_ip_port_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
fal_sg_cfg_t *sg_cfg);
sw_error_t
fal_ip_pub_addr_set(a_uint32_t dev_id, a_uint32_t index,
fal_ip_pub_addr_t *entry);
sw_error_t
fal_ip_pub_addr_get(a_uint32_t dev_id, a_uint32_t index,
fal_ip_pub_addr_t *entry);
sw_error_t
fal_ip_port_macaddr_set(a_uint32_t dev_id, fal_port_t port_id,
fal_macaddr_entry_t *macaddr);
sw_error_t
fal_ip_port_macaddr_get(a_uint32_t dev_id, fal_port_t port_id,
fal_macaddr_entry_t *macaddr);
sw_error_t
fal_ip_route_mismatch_action_set(a_uint32_t dev_id, fal_fwd_cmd_t action);
sw_error_t
fal_ip_route_mismatch_action_get(a_uint32_t dev_id, fal_fwd_cmd_t *action);
sw_error_t
fal_ip_port_arp_sg_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
fal_arp_sg_cfg_t *arp_sg_cfg);
sw_error_t
fal_ip_port_arp_sg_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
fal_arp_sg_cfg_t *arp_sg_cfg);
sw_error_t
fal_ip_vsi_mc_mode_set(a_uint32_t dev_id, a_uint32_t vsi,
fal_mc_mode_cfg_t *cfg);
sw_error_t
fal_ip_vsi_mc_mode_get(a_uint32_t dev_id, a_uint32_t vsi,
fal_mc_mode_cfg_t *cfg);
sw_error_t
fal_ip_global_ctrl_get(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg);
sw_error_t
fal_ip_global_ctrl_set(a_uint32_t dev_id, fal_ip_global_cfg_t *cfg);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_IP_H_ */
/**
* @}
*/

107
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/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_leaky FAL_LEAKY
* @{
*/
#ifndef _FAL_LEAKY_H_
#define _FAL_LEAKY_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This enum defines the leaky control mode.
*/
typedef enum {
FAL_LEAKY_PORT_CTRL = 0, /**< control leaky through port which packets received*/
FAL_LEAKY_FDB_CTRL, /**< control leaky through fdb entry*/
FAL_LEAKY_CTRL_MODE_BUTT
}
fal_leaky_ctrl_mode_t;
sw_error_t
fal_uc_leaky_mode_set(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t ctrl_mode);
sw_error_t
fal_uc_leaky_mode_get(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t * ctrl_mode);
sw_error_t
fal_mc_leaky_mode_set(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t ctrl_mode);
sw_error_t
fal_mc_leaky_mode_get(a_uint32_t dev_id,
fal_leaky_ctrl_mode_t * ctrl_mode);
sw_error_t
fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_LEAKY_H_ */
/**
* @}
*/

142
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/*
* Copyright (c) 2012,2018,2020, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_led FAL_LED
* @{
*/
#ifndef _FAL_LED_H_
#define _FAL_LED_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This enum defines the led group.
*/
typedef enum {
LED_LAN_PORT_GROUP = 0, /**< control lan ports*/
LED_WAN_PORT_GROUP, /**< control wan ports*/
LED_MAC_PORT_GROUP, /**< control mac ports*/
LED_GROUP_BUTT
}
led_pattern_group_t;
/**
@brief This enum defines the led pattern id, each ports has three led
and pattern0 relates to led0, pattern1 relates to led1, pattern2 relates to led2.
*/
typedef a_uint32_t led_pattern_id_t;
/**
@brief This enum defines the led control pattern mode.
*/
typedef enum
{
LED_ALWAYS_OFF = 0,
LED_ALWAYS_BLINK,
LED_ALWAYS_ON,
LED_PATTERN_MAP_EN,
LED_PATTERN_MODE_BUTT
} led_pattern_mode_t;
#define FULL_DUPLEX_LIGHT_EN 0
#define HALF_DUPLEX_LIGHT_EN 1
#define POWER_ON_LIGHT_EN 2
#define LINK_1000M_LIGHT_EN 3
#define LINK_100M_LIGHT_EN 4
#define LINK_10M_LIGHT_EN 5
#define COLLISION_BLINK_EN 6
#define RX_TRAFFIC_BLINK_EN 7
#define TX_TRAFFIC_BLINK_EN 8
#define LINKUP_OVERRIDE_EN 9
#define LED_ACTIVE_HIGH 10
#define LINK_2500M_LIGHT_EN 11
#define LED_MAP_10M_SPEED \
(BIT(POWER_ON_LIGHT_EN) | BIT(LINK_10M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
#define LED_MAP_100M_SPEED \
(BIT(POWER_ON_LIGHT_EN) | BIT(LINK_100M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
#define LED_MAP_1000M_SPEED \
(BIT(POWER_ON_LIGHT_EN) | BIT(LINK_1000M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
#define LED_MAP_2500M_SPEED \
(BIT(POWER_ON_LIGHT_EN) | BIT(LINK_2500M_LIGHT_EN) | BIT(COLLISION_BLINK_EN) |\
BIT(RX_TRAFFIC_BLINK_EN) | BIT(TX_TRAFFIC_BLINK_EN) | BIT(LINKUP_OVERRIDE_EN))
#define LED_MAP_ALL_SPEED \
(LED_MAP_10M_SPEED | LED_MAP_100M_SPEED | LED_MAP_1000M_SPEED |\
LED_MAP_2500M_SPEED)
#define PORT_LED_SOURCE_MAX 0x3
/**
@brief This enum defines the led control pattern map.
*/
typedef a_uint32_t led_pattern_map_t;
/**
@brief This enum defines the led control pattern mode.
*/
typedef enum
{
LED_BLINK_2HZ = 0,
LED_BLINK_4HZ,
LED_BLINK_8HZ,
LED_BLINK_TXRX, /**< Frequency relates to speed, 1000M-8HZ,100M->4HZ,10M->2HZ,Others->4HZ */
LED_BLINK_FREQ_BUTT
} led_blink_freq_t;
typedef struct
{
led_pattern_mode_t mode;
led_pattern_map_t map;
led_blink_freq_t freq;
} led_ctrl_pattern_t;
sw_error_t
fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
led_pattern_id_t id, led_ctrl_pattern_t * pattern);
sw_error_t
fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
led_pattern_id_t id, led_ctrl_pattern_t * pattern);
sw_error_t
fal_led_source_pattern_set(a_uint32_t dev_id, a_uint32_t source_id,
led_ctrl_pattern_t * pattern);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_LED_H_ */
/**
* @}
*/

260
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@@ -1,260 +0,0 @@
/*
* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_mib FAL_MIB
* @{
*/
#ifndef _FAL_MIB_H
#define _FAL_MIB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**@brief This structure defines the mib infomation.
*/
typedef struct
{
a_uint32_t RxBroad;
a_uint32_t RxPause;
a_uint32_t RxMulti;
a_uint32_t RxFcsErr;
a_uint32_t RxAllignErr;
a_uint32_t RxRunt;
a_uint32_t RxFragment;
a_uint32_t Rx64Byte;
a_uint32_t Rx128Byte;
a_uint32_t Rx256Byte;
a_uint32_t Rx512Byte;
a_uint32_t Rx1024Byte;
a_uint32_t Rx1518Byte;
a_uint32_t RxMaxByte;
a_uint32_t RxTooLong;
a_uint32_t RxGoodByte_lo; /**< low 32 bits of RxGoodByte statistc item */
a_uint32_t RxGoodByte_hi; /**< high 32 bits of RxGoodByte statistc item*/
a_uint32_t RxBadByte_lo; /**< low 32 bits of RxBadByte statistc item */
a_uint32_t RxBadByte_hi; /**< high 32 bits of RxBadByte statistc item */
a_uint32_t RxOverFlow; /* no this counter for Hawkeye*/
a_uint32_t Filtered; /*no this counter for Hawkeye*/
a_uint32_t TxBroad;
a_uint32_t TxPause;
a_uint32_t TxMulti;
a_uint32_t TxUnderRun;
a_uint32_t Tx64Byte;
a_uint32_t Tx128Byte;
a_uint32_t Tx256Byte;
a_uint32_t Tx512Byte;
a_uint32_t Tx1024Byte;
a_uint32_t Tx1518Byte;
a_uint32_t TxMaxByte;
a_uint32_t TxOverSize; /*no this counter for Hawkeye*/
a_uint32_t TxByte_lo; /**< low 32 bits of TxByte statistc item */
a_uint32_t TxByte_hi; /**< high 32 bits of TxByte statistc item */
a_uint32_t TxCollision;
a_uint32_t TxAbortCol;
a_uint32_t TxMultiCol;
a_uint32_t TxSingalCol;
a_uint32_t TxExcDefer;
a_uint32_t TxDefer;
a_uint32_t TxLateCol;
a_uint32_t RxUniCast;
a_uint32_t TxUniCast;
a_uint32_t RxJumboFcsErr; /* add for Hawkeye*/
a_uint32_t RxJumboAligenErr; /* add for Hawkeye*/
a_uint32_t Rx14To63; /*add for ipq60xx lpbk port*/
a_uint32_t RxTooLongByte_lo; /*add for ipq60xx lpbk port*/
a_uint32_t RxTooLongByte_hi; /*add for ipq60xx lpbk port*/
a_uint32_t RxRuntByte_lo; /*add for ipq60xx lpbk port*/
a_uint32_t RxRuntByte_hi; /*add for ipq60xx lpbk port*/
} fal_mib_info_t;
/*define structure for software with 64bit*/
typedef struct
{
a_uint64_t RxBroad;
a_uint64_t RxPause;
a_uint64_t RxMulti;
a_uint64_t RxFcsErr;
a_uint64_t RxAllignErr;
a_uint64_t RxRunt;
a_uint64_t RxFragment;
a_uint64_t Rx64Byte;
a_uint64_t Rx128Byte;
a_uint64_t Rx256Byte;
a_uint64_t Rx512Byte;
a_uint64_t Rx1024Byte;
a_uint64_t Rx1518Byte;
a_uint64_t RxMaxByte;
a_uint64_t RxTooLong;
a_uint64_t RxGoodByte;
a_uint64_t RxBadByte;
a_uint64_t RxOverFlow; /* no this counter for Hawkeye*/
a_uint64_t Filtered; /*no this counter for Hawkeye*/
a_uint64_t TxBroad;
a_uint64_t TxPause;
a_uint64_t TxMulti;
a_uint64_t TxUnderRun;
a_uint64_t Tx64Byte;
a_uint64_t Tx128Byte;
a_uint64_t Tx256Byte;
a_uint64_t Tx512Byte;
a_uint64_t Tx1024Byte;
a_uint64_t Tx1518Byte;
a_uint64_t TxMaxByte;
a_uint64_t TxOverSize; /*no this counter for Hawkeye*/
a_uint64_t TxByte;
a_uint64_t TxCollision;
a_uint64_t TxAbortCol;
a_uint64_t TxMultiCol;
a_uint64_t TxSingalCol;
a_uint64_t TxExcDefer;
a_uint64_t TxDefer;
a_uint64_t TxLateCol;
a_uint64_t RxUniCast;
a_uint64_t TxUniCast;
a_uint64_t RxJumboFcsErr; /* add for Hawkeye*/
a_uint64_t RxJumboAligenErr; /* add for Hawkeye*/
a_uint64_t Rx14To63; /*add for ipq60xx lpbk port*/
a_uint64_t RxTooLongByte; /*add for ipq60xx lpbk port*/
a_uint64_t RxRuntByte; /*add for ipq60xx lpbk port*/
} fal_mib_counter_t;
enum
{
/*mib*/
FUNC_GET_MIB_INFO = 0,
FUNC_GET_RX_MIB_INFO,
FUNC_GET_TX_MIB_INFO,
FUNC_GET_XGMIB_INFO,
FUNC_GET_TX_XGMIB_INFO,
FUNC_GET_RX_XGMIB_INFO,
FUNC_MIB_STATUS_SET,
FUNC_MIB_STATUS_GET,
FUNC_MIB_PORT_FLUSH_COUNTERS,
FUNC_MIB_CPUKEEP_SET,
FUNC_MIB_CPUKEEP_GET
};
typedef struct
{
a_uint64_t RxFrame;
a_uint64_t RxByte;
a_uint64_t RxByteGood;
a_uint64_t RxBroadGood;
a_uint64_t RxMultiGood;
a_uint64_t RxFcsErr;
a_uint64_t RxRuntErr ;
a_uint64_t RxJabberError;
a_uint64_t RxUndersizeGood;
a_uint64_t RxOversizeGood;
a_uint64_t Rx64Byte;
a_uint64_t Rx128Byte;
a_uint64_t Rx256Byte;
a_uint64_t Rx512Byte;
a_uint64_t Rx1024Byte;
a_uint64_t RxMaxByte;
a_uint64_t RxUnicastGood;
a_uint64_t RxLengthError;
a_uint64_t RxOutOfRangeError;
a_uint64_t RxPause;
a_uint64_t RxOverFlow;
a_uint64_t RxVLANFrameGoodBad;
a_uint64_t RxWatchDogError;
a_uint64_t RxLPIUsec;
a_uint64_t RxLPITran;
a_uint64_t RxDropFrameGoodBad;
a_uint64_t RxDropByteGoodBad;
a_uint64_t TxByte;
a_uint64_t TxFrame;
a_uint64_t TxBroadGood;
a_uint64_t TxMultiGood;
a_uint64_t Tx64Byte;
a_uint64_t Tx128Byte;
a_uint64_t Tx256Byte;
a_uint64_t Tx512Byte;
a_uint64_t Tx1024Byte;
a_uint64_t TxMaxByte;
a_uint64_t TxUnicast;
a_uint64_t TxMulti;
a_uint64_t TxBroad;
a_uint64_t TxUnderFlowError;
a_uint64_t TxByteGood;
a_uint64_t TxFrameGood;
a_uint64_t TxPause;
a_uint64_t TxVLANFrameGood;
a_uint64_t TxLPIUsec;
a_uint64_t TxLPITran;
} fal_xgmib_info_t;
sw_error_t
fal_get_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_xgmib_info_t * mib_info );
sw_error_t
fal_get_rx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_xgmib_info_t * mib_info );
sw_error_t
fal_get_tx_xgmib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_xgmib_info_t * mib_info );
sw_error_t
fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info );
sw_error_t
fal_get_rx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info );
sw_error_t
fal_get_tx_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info );
sw_error_t
fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
sw_error_t
fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_mib_counter_alloc(a_uint32_t dev_id, a_uint64_t **p_mibcounter);
sw_error_t
fal_mib_counter_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_counter_t *mib_counter);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_MIB_H */
/**
* @}
*/

86
feeds/ipq807x/qca-ssdk/src/include/fal/fal_mirror.h
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@@ -1,86 +0,0 @@
/*
* Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_mirror FAL_MIRROR
* @{
*/
#ifndef _FAL_MIRROR_H_
#define _FAL_MIRROR_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef struct
{
fal_port_t port_id;
a_uint32_t priority;
} fal_mirr_analysis_config_t;
typedef enum
{
FAL_MIRR_INGRESS= 0,
FAL_MIRR_EGRESS,
FAL_MIRR_BOTH,
} fal_mirr_direction_t;
enum
{
FUNC_MIRR_ANALYSIS_PORT_SET = 0,
FUNC_MIRR_ANALYSIS_PORT_GET,
FUNC_MIRR_PORT_IN_SET,
FUNC_MIRR_PORT_IN_GET,
FUNC_MIRR_PORT_EG_SET,
FUNC_MIRR_PORT_EG_GET,
FUNC_MIRR_ANALYSIS_CONFIG_SET,
FUNC_MIRR_ANALYSIS_CONFIG_GET,
};
sw_error_t
fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
sw_error_t
fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
sw_error_t
fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_mirr_analysis_config_set(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config);
sw_error_t
fal_mirr_analysis_config_get(a_uint32_t dev_id, fal_mirr_direction_t direction, fal_mirr_analysis_config_t * config);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _PORT_MIRROR_H_ */
/**
* @}
*/

256
feeds/ipq807x/qca-ssdk/src/include/fal/fal_misc.h
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@@ -1,256 +0,0 @@
/*
* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_gen FAL_MISC
* @{
*/
#ifndef _FAL_MISC_H_
#define _FAL_MISC_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef enum
{
FAL_LOOP_CHECK_1MS = 0,
FAL_LOOP_CHECK_10MS,
FAL_LOOP_CHECK_100MS,
FAL_LOOP_CHECK_500MS,
} fal_loop_check_time_t;
typedef struct
{
a_bool_t rx_counter_en; /* Enable/disable virtual port rx counter */
a_bool_t vp_uni_tx_counter_en; /* Enable/disable virtual port unicast tx counter */
a_bool_t port_mc_tx_counter_en; /* Enable/disable physical port multicast tx counter */
a_bool_t port_tx_counter_en; /* Enable/disable physical port tx counter */
} fal_counter_en_t;
sw_error_t
fal_debug_port_counter_enable(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en);
sw_error_t
fal_debug_port_counter_status_get(a_uint32_t dev_id, fal_port_t port_id, fal_counter_en_t * cnt_en);
/* define switch interrupt type bitmap */
#define FAL_SWITCH_INTR_LINK_STATUS 0x1 /* up/down/speed/duplex status */
#ifndef IN_MISC_MINI
sw_error_t fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
#endif
sw_error_t fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
sw_error_t fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
sw_error_t
fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd);
sw_error_t
fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t * cmd);
sw_error_t
fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
#ifndef IN_MISC_MINI
sw_error_t
fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
#endif
sw_error_t
fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
#ifndef IN_MISC_MINI
sw_error_t
fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
#endif
sw_error_t
fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
#ifndef IN_MISC_MINI
sw_error_t
fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
sw_error_t
fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
sw_error_t
fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
sw_error_t
fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
sw_error_t
fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
sw_error_t
fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
sw_error_t
fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
sw_error_t
fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask);
sw_error_t
fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
sw_error_t
fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
sw_error_t
fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
sw_error_t
fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
sw_error_t
fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
sw_error_t
fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
sw_error_t
fal_global_macaddr_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
sw_error_t
fal_global_macaddr_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
sw_error_t
fal_lldp_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_lldp_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_frame_crc_reserve_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_frame_crc_reserve_get(a_uint32_t dev_id, a_bool_t * enable);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_MISC_H_ */
/**
* @}
*/

73
feeds/ipq807x/qca-ssdk/src/include/fal/fal_multi.h
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@@ -1,73 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _FAL_MULTI_H_
#define _FAL_MULTI_H_
/*supports 32 entries*/
#define FAL_IGMP_SG_ENTRY_MAX 32
typedef enum
{
FAL_ADDR_IPV4 = 0,
FAL_ADDR_IPV6
} fal_addr_type_t;
typedef struct
{
fal_addr_type_t type;
union
{
fal_ip4_addr_t ip4_addr;
fal_ip6_addr_t ip6_addr;
} u;
} fal_igmp_sg_addr_t;
typedef struct
{
fal_igmp_sg_addr_t source;
fal_igmp_sg_addr_t group;
fal_pbmp_t port_map;
a_uint32_t vlan_id;
} fal_igmp_sg_entry_t;
//#define MULTI_DEBUG_
#ifdef MULTI_DEBUG_
#define MULTI_DEBUG(x...) aos_printk(x)
#else
#define MULTI_DEBUG(x...)
#endif
#define FAL_ACL_LIST_MULTICAST 55
#define FAL_MULTICAST_PRI 5
#define MULT_ACTION_SET 0
#define MULT_ACTION_CLEAR 1
// static a_uint32_t rule_nr=1;
typedef struct
{
a_uint8_t index; //MAX is 32
fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
} multi_acl_info_t;
typedef struct
{
a_uint8_t cnt; //MAX is 32
multi_acl_info_t acl_info[FAL_IGMP_SG_ENTRY_MAX]; //Stores the all ACL rule info
} fal_igmp_sg_info_t;
#endif

294
feeds/ipq807x/qca-ssdk/src/include/fal/fal_nat.h
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@@ -1,294 +0,0 @@
/*
* Copyright (c) 2012, 2015,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_nat FAL_NAT
* @{
*/
#ifndef _FAL_NAT_H_
#define _FAL_NAT_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1
#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2
#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4
#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8
#define FAL_NAT_ENTRY_TRANS_IPADDR_INDEX 0x10
#define FAL_NAT_ENTRY_PORT_CHECK 0x20
#define FAL_NAT_HASH_KEY_PORT 0x40
#define FAL_NAT_HASH_KEY_IPADDR 0x80
/* NAT entry operation flags */
#define FAL_NAT_ENTRY_ID_EN 0x1
#define FAL_NAT_ENTRY_SRC_IPADDR_EN 0x2
#define FAL_NAT_ENTRY_TRANS_IPADDR_EN 0x4
#define FAL_NAT_ENTRY_KEY_EN 0x8
#define FAL_NAT_ENTRY_PUBLIC_IP_EN 0x10
#define FAL_NAT_ENTRY_SOURCE_IP_EN 0x20
#define FAL_NAT_ENTRY_AGE_EN 0x40
#define FAL_NAT_ENTRY_SYNC_EN 0x80
typedef struct
{
a_uint32_t entry_id;
a_uint32_t flags;
a_uint32_t status;
fal_ip4_addr_t src_addr;
fal_ip4_addr_t dst_addr;
a_uint16_t src_port;
a_uint16_t dst_port;
fal_ip4_addr_t trans_addr;
a_uint16_t trans_port;
a_uint16_t rsv;
a_bool_t mirror_en;
a_bool_t counter_en;
a_uint32_t counter_id;
a_uint32_t ingress_packet;
a_uint32_t ingress_byte;
a_uint32_t egress_packet;
a_uint32_t egress_byte;
fal_fwd_cmd_t action;
a_uint32_t load_balance;
a_uint32_t flow_cookie;
a_uint32_t vrf_id;
a_uint32_t aging_sync;
a_bool_t priority_en;
a_uint32_t priority_val;
} fal_napt_entry_t;
typedef struct
{
a_uint32_t proto; /*1 tcp; 2 udp*/
fal_ip4_addr_t src_addr;
fal_ip4_addr_t dst_addr;
a_uint16_t src_port;
a_uint16_t dst_port;
a_uint32_t flow_cookie;
} fal_flow_cookie_t;
typedef struct
{
a_uint32_t proto; /*1 tcp; 2 udp*/
fal_ip4_addr_t src_addr;
fal_ip4_addr_t dst_addr;
a_uint16_t src_port;
a_uint16_t dst_port;
a_uint8_t load_balance;
} fal_flow_rfs_t;
typedef struct
{
a_uint32_t entry_id;
a_uint32_t flags;
a_uint32_t status;
fal_ip4_addr_t src_addr;
fal_ip4_addr_t trans_addr;
a_uint16_t port_num;
a_uint16_t port_range;
a_uint32_t slct_idx;
a_bool_t mirror_en;
a_bool_t counter_en;
a_uint32_t counter_id;
a_uint32_t ingress_packet;
a_uint32_t ingress_byte;
a_uint32_t egress_packet;
a_uint32_t egress_byte;
fal_fwd_cmd_t action;
a_uint32_t vrf_id;
} fal_nat_entry_t;
typedef enum
{
FAL_NAPT_FULL_CONE = 0,
FAL_NAPT_STRICT_CONE,
FAL_NAPT_PORT_STRICT,
FAL_NAPT_SYNMETRIC,
} fal_napt_mode_t;
typedef struct
{
a_uint32_t entry_id;
fal_ip4_addr_t pub_addr;
} fal_nat_pub_addr_t;
sw_error_t
fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
sw_error_t
fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * nat_entry);
sw_error_t
fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
sw_error_t
fal_nat_next(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
sw_error_t
fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
sw_error_t
fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
sw_error_t
fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
sw_error_t
fal_flow_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
sw_error_t
fal_flow_cookie_set(a_uint32_t dev_id, fal_flow_cookie_t * flow_cookie);
sw_error_t
fal_flow_rfs_set(a_uint32_t dev_id, a_uint8_t action, fal_flow_rfs_t * rfs);
sw_error_t
fal_flow_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_flow_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_flow_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry);
sw_error_t
fal_flow_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
sw_error_t
fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
sw_error_t
fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
sw_error_t
fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
sw_error_t
fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
sw_error_t
fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
sw_error_t
fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
sw_error_t
fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
sw_error_t
fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
sw_error_t
fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
sw_error_t
fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en);
sw_error_t
fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en);
sw_error_t
fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
sw_error_t
fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_pub_addr_t * entry);
sw_error_t
fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_pub_addr_t * entry);
sw_error_t
fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_nat_global_set(a_uint32_t dev_id, a_bool_t enable,
a_bool_t sync_cnt_enable, a_uint32_t portbmp);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_NAT_H_ */
/**
* @}
*/

164
feeds/ipq807x/qca-ssdk/src/include/fal/fal_policer.h
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@@ -1,164 +0,0 @@
/*
* Copyright (c) 2016-2018, 2021, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_policer FAL_POLICER
* @{
*/
#ifndef _FAL_POLICER_H_
#define _FAL_POLICER_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef struct
{
a_bool_t meter_en; /* meter enable or disable */
a_bool_t couple_en; /* two buckets coupling enable or disable*/
a_uint32_t color_mode; /* color aware or color blind */
a_uint32_t frame_type; /* frame type, bit0:unicast;bit1: unkown unicast;bit2:multicast;bit3: unknown multicast; bit4:broadcast */
a_uint32_t meter_mode;
a_uint32_t meter_unit; /* 0:byte based; 1:packet based*/
a_uint32_t cir; /* committed information rate */
a_uint32_t cbs; /* committed burst size */
a_uint32_t eir; /* excess information rate */
a_uint32_t ebs; /* excess burst size */
} fal_policer_config_t;
typedef struct
{
a_bool_t yellow_priority_en; /* yellow traffic internal priority change enable*/
a_bool_t yellow_drop_priority_en; /* yellow traffic internal drop priority change enable*/
a_bool_t yellow_pcp_en; /* yellow traffic pcp change enable*/
a_bool_t yellow_dei_en; /* yellow traffic dei change enable*/
a_uint32_t yellow_priority; /* yellow traffic internal priority value*/
a_uint32_t yellow_drop_priority; /* yellow traffic internal drop priority value*/
a_uint32_t yellow_pcp; /* yellow traffic pcp value*/
a_uint32_t yellow_dei; /* yellow traffic dei value*/
fal_fwd_cmd_t red_action; /* red traffic drop or forward*/
a_bool_t red_priority_en; /* red traffic internal priority change enable*/
a_bool_t red_drop_priority_en; /* red traffic internal drop priority change enable*/
a_bool_t red_pcp_en; /* red traffic pcp change enable*/
a_bool_t red_dei_en; /* red traffic dei change enable*/
a_uint32_t red_priority; /* red traffic internal priority value*/
a_uint32_t red_drop_priority; /* red traffic internal drop priority value*/
a_uint32_t red_pcp; /* red traffic pcp value*/
a_uint32_t red_dei; /* red traffic dei value*/
}fal_policer_action_t;
typedef struct
{
a_uint32_t green_packet_counter; /*green packet counter */
a_uint64_t green_byte_counter; /*green byte counter */
a_uint32_t yellow_packet_counter; /*yellow packet counter */
a_uint64_t yellow_byte_counter; /*yellow byte counter */
a_uint32_t red_packet_counter; /*red packet counter */
a_uint64_t red_byte_counter; /*red byte counter */
} fal_policer_counter_t;
typedef struct
{
a_uint32_t policer_drop_packet_counter; /*drop packet counter by policer*/
a_uint64_t policer_drop_byte_counter; /*drop byte counter by policer */
a_uint32_t policer_forward_packet_counter; /*forward packet counter by policer*/
a_uint64_t policer_forward_byte_counter; /*forward byte counter by policer*/
a_uint32_t policer_bypass_packet_counter; /*bypass packet counter by policer*/
a_uint64_t policer_bypass_byte_counter; /*bypass byte counter by policer */
} fal_policer_global_counter_t;
enum
{
FUNC_ADPT_ACL_POLICER_COUNTER_GET = 0,
FUNC_ADPT_PORT_POLICER_COUNTER_GET,
FUNC_ADPT_PORT_COMPENSATION_BYTE_GET,
FUNC_ADPT_PORT_POLICER_ENTRY_GET,
FUNC_ADPT_PORT_POLICER_ENTRY_SET,
FUNC_ADPT_ACL_POLICER_ENTRY_GET,
FUNC_ADPT_ACL_POLICER_ENTRY_SET,
FUNC_ADPT_POLICER_TIME_SLOT_GET,
FUNC_ADPT_PORT_COMPENSATION_BYTE_SET,
FUNC_ADPT_POLICER_TIME_SLOT_SET,
FUNC_ADPT_POLICER_GLOBAL_COUNTER_GET,
FUNC_ADPT_POLICER_BYPASS_EN_SET,
FUNC_ADPT_POLICER_BYPASS_EN_GET,
};
typedef enum {
FAL_FRAME_DROPPED = 0,
} fal_policer_frame_type_t;
#ifndef IN_POLICER_MINI
sw_error_t
fal_port_policer_entry_set(a_uint32_t dev_id, fal_port_t port_id,
fal_policer_config_t *policer, fal_policer_action_t *action);
sw_error_t
fal_port_policer_entry_get(a_uint32_t dev_id, fal_port_t port_id,
fal_policer_config_t *policer, fal_policer_action_t *atcion);
sw_error_t
fal_acl_policer_entry_set(a_uint32_t dev_id, a_uint32_t index,
fal_policer_config_t *policer, fal_policer_action_t *action);
sw_error_t
fal_acl_policer_entry_get(a_uint32_t dev_id, a_uint32_t index,
fal_policer_config_t *policer, fal_policer_action_t *action);
sw_error_t
fal_port_policer_counter_get(a_uint32_t dev_id, fal_port_t port_id,
fal_policer_counter_t *counter);
sw_error_t
fal_acl_policer_counter_get(a_uint32_t dev_id, a_uint32_t index,
fal_policer_counter_t *counter);
sw_error_t
fal_port_policer_compensation_byte_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t *length);
sw_error_t
fal_policer_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
sw_error_t
fal_policer_global_counter_get(a_uint32_t dev_id,
fal_policer_global_counter_t *counter);
sw_error_t
fal_policer_bypass_en_get(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
a_bool_t *enable);
#endif
sw_error_t
fal_port_policer_compensation_byte_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t length);
sw_error_t
fal_policer_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
sw_error_t
fal_policer_bypass_en_set(a_uint32_t dev_id, fal_policer_frame_type_t frame_type,
a_bool_t enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_POLICER_H_ */
/**
* @}
*/

801
feeds/ipq807x/qca-ssdk/src/include/fal/fal_port_ctrl.h
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@@ -1,801 +0,0 @@
/*
* Copyright (c) 2012, 2015-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*qca808x_start*/
/**
* @defgroup fal_port_ctrl FAL_PORT_CONTROL
* @{
*/
#ifndef _FAL_PORTCTRL_H_
#define _FAL_PORTCTRL_H_
#ifdef __cplusplus
extern "c" {
#endif
#include "sw.h"
#include "fal/fal_type.h"
typedef enum {
FAL_HALF_DUPLEX = 0,
FAL_FULL_DUPLEX,
FAL_DUPLEX_BUTT = 0xffff
} fal_port_duplex_t;
typedef enum {
FAL_SPEED_10 = 10,
FAL_SPEED_100 = 100,
FAL_SPEED_1000 = 1000,
FAL_SPEED_2500 = 2500,
FAL_SPEED_5000 = 5000,
FAL_SPEED_10000 = 10000,
FAL_SPEED_BUTT = 0xffff,
} fal_port_speed_t;
typedef enum {
FAL_CABLE_STATUS_NORMAL = 0,
FAL_CABLE_STATUS_SHORT = 1,
FAL_CABLE_STATUS_OPENED = 2,
FAL_CABLE_STATUS_INVALID = 3,
FAL_CABLE_STATUS_CROSSOVERA = 4,
FAL_CABLE_STATUS_CROSSOVERB = 5,
FAL_CABLE_STATUS_CROSSOVERC = 6,
FAL_CABLE_STATUS_CROSSOVERD = 7,
FAL_CABLE_STATUS_LOW_MISMATCH =8,
FAL_CABLE_STATUS_HIGH_MISMATCH =9,
FAL_CABLE_STATUS_BUTT = 0xffff,
} fal_cable_status_t;
struct port_phy_status
{
a_uint32_t link_status;
fal_port_speed_t speed;
fal_port_duplex_t duplex;
a_bool_t tx_flowctrl;
a_bool_t rx_flowctrl;
};
#define FAL_ENABLE 1
#define FAL_DISABLE 0
#define FAL_MAX_PORT_NUMBER 8
#define FAL_DEFAULT_LOOPBACK_RATE 14
//phy autoneg adv
#define FAL_PHY_ADV_10T_HD 0x01
#define FAL_PHY_ADV_10T_FD 0x02
#define FAL_PHY_ADV_100TX_HD 0x04
#define FAL_PHY_ADV_100TX_FD 0x08
//#define FAL_PHY_ADV_1000T_HD 0x100
#define FAL_PHY_ADV_1000T_FD 0x200
#define FAL_PHY_ADV_1000BX_HD 0x400
#define FAL_PHY_ADV_1000BX_FD 0x800
#define FAL_PHY_ADV_2500T_FD 0x1000
#define FAL_PHY_ADV_5000T_FD 0x2000
#define FAL_PHY_ADV_10000T_FD 0x4000
#define FAL_PHY_ADV_10G_R_FD 0x8000
#define FAL_DEFAULT_MAX_FRAME_SIZE 0x5ee
#define FAL_PHY_ADV_FE_SPEED_ALL \
(FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
FAL_PHY_ADV_100TX_FD)
#define FAL_PHY_ADV_GE_SPEED_ALL \
(FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_1000T_FD)
#define FAL_PHY_ADV_BX_SPEED_ALL \
(FAL_PHY_ADV_1000BX_HD | FAL_PHY_ADV_1000BX_FD |FAL_PHY_ADV_10G_R_FD)
#define FAL_PHY_ADV_XGE_SPEED_ALL \
(FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD)
#define FAL_PHY_ADV_PAUSE 0x10
#define FAL_PHY_ADV_ASY_PAUSE 0x20
#define FAL_PHY_FE_ADV_ALL \
(FAL_PHY_ADV_FE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
#define FAL_PHY_GE_ADV_ALL \
(FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
#define FAL_PHY_COMBO_ADV_ALL \
(FAL_PHY_ADV_BX_SPEED_ALL | FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_XGE_SPEED_ALL|\
FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
//phy capablity
#define FAL_PHY_AUTONEG_CAPS 0x01
#define FAL_PHY_100T2_HD_CAPS 0x02
#define FAL_PHY_100T2_FD_CAPS 0x04
#define FAL_PHY_10T_HD_CAPS 0x08
#define FAL_PHY_10T_FD_CAPS 0x10
#define FAL_PHY_100X_HD_CAPS 0x20
#define FAL_PHY_100X_FD_CAPS 0x40
#define FAL_PHY_100T4_CAPS 0x80
//#define FAL_PHY_1000T_HD_CAPS 0x100
#define FAL_PHY_1000T_FD_CAPS 0x200
//#define FAL_PHY_1000X_HD_CAPS 0x400
#define FAL_PHY_1000X_FD_CAPS 0x800
//phy partner capablity
#define FAL_PHY_PART_10T_HD 0x1
#define FAL_PHY_PART_10T_FD 0x2
#define FAL_PHY_PART_100TX_HD 0x4
#define FAL_PHY_PART_100TX_FD 0x8
//#define FAL_PHY_PART_1000T_HD 0x10
#define FAL_PHY_PART_1000T_FD 0x20
#define FAL_PHY_PART_2500T_FD 0x40
#define FAL_PHY_PART_5000T_FD 0x80
#define FAL_PHY_PART_10000T_FD 0x100
//phy interrupt flag
#define FAL_PHY_INTR_SPEED_CHANGE 0x1
#define FAL_PHY_INTR_DUPLEX_CHANGE 0x2
#define FAL_PHY_INTR_STATUS_UP_CHANGE 0x4
#define FAL_PHY_INTR_STATUS_DOWN_CHANGE 0x8
#define FAL_PHY_INTR_BX_FX_STATUS_UP_CHANGE 0x10
#define FAL_PHY_INTR_BX_FX_STATUS_DOWN_CHANGE 0x20
#define FAL_PHY_INTR_MEDIA_STATUS_CHANGE 0x40
#define FAL_PHY_INTR_WOL_STATUS 0x80
#define FAL_PHY_INTR_POE_STATUS 0x100
/* phy eee */
#define FAL_PHY_EEE_10BASE_T 0x1
#define FAL_PHY_EEE_100BASE_T 0x2
#define FAL_PHY_EEE_1000BASE_T 0x4
#define FAL_PHY_EEE_2500BASE_T 0x8
#define FAL_PHY_EEE_5000BASE_T 0x10
#define FAL_PHY_EEE_10000BASE_T 0x20
typedef enum {
FAL_NO_HEADER_EN = 0,
FAL_ONLY_MANAGE_FRAME_EN,
FAL_ALL_TYPE_FRAME_EN
} fal_port_header_mode_t;
typedef struct {
a_uint16_t pair_a_status;
a_uint16_t pair_b_status;
a_uint16_t pair_c_status;
a_uint16_t pair_d_status;
a_uint32_t pair_a_len;
a_uint32_t pair_b_len;
a_uint32_t pair_c_len;
a_uint32_t pair_d_len;
} fal_port_cdt_t;
/*below is new add for malibu phy*/
/** Phy mdix mode */
typedef enum {
PHY_MDIX_AUTO = 0,
/**< Auto MDI/MDIX */
PHY_MDIX_MDI = 1,
/**< Fixed MDI */
PHY_MDIX_MDIX = 2
/**< Fixed MDIX */
} fal_port_mdix_mode_t;
/** Phy mdix status */
typedef enum {
PHY_MDIX_STATUS_MDI = 0,
/**< Fixed MDI */
PHY_MDIX_STATUS_MDIX = 1
/**< Fixed MDIX */
} fal_port_mdix_status_t;
/** Phy master mode */
typedef enum {
PHY_MASTER_MASTER = 0,
/**< Phy manual MASTER configuration */
PHY_MASTER_SLAVE = 1,
/**< Phy manual SLAVE configuration */
PHY_MASTER_AUTO = 2
/**< Phy automatic MASTER/SLAVE configuration */
} fal_port_master_t;
/** Phy preferred medium type */
typedef enum {
PHY_MEDIUM_COPPER = 0,
/**< Copper */
PHY_MEDIUM_FIBER = 1,
/**< Fiber */
} fal_port_medium_t;
/** Phy pages */
typedef enum {
PHY_SGBX_PAGES = 0,
/**< sgbx pages */
PHY_COPPER_PAGES = 1
/**< copper pages */
} fal_port_reg_pages_t;
/** Phy preferred Fiber mode */
typedef enum {
PHY_FIBER_100FX = 0,
/**< 100FX fiber mode */
PHY_FIBER_1000BX = 1,
/**< 1000BX fiber mode */
PHY_FIBER_10G_R = 2,
} fal_port_fiber_mode_t;
/** Phy reset status */
typedef enum {
PHY_RESET_DONE = 0,
/**< Phy reset done */
PHY_RESET_BUSY = 1
/**< Phy still in reset process */
} fal_port_reset_status_t;
/** Phy auto-negotiation status */
typedef enum {
PHY_AUTO_NEG_STATUS_BUSY = 0,
/**< Phy still in auto-negotiation process */
PHY_AUTO_NEG_STATUS_DONE = 1
/**< Phy auto-negotiation done */
} fal_port_auto_neg_status_t;
/** Phy interface mode */
typedef enum {
PHY_PSGMII_BASET = 0,
/**< PSGMII mode */
PHY_PSGMII_BX1000 = 1,
/**< PSGMII BX1000 mode */
PHY_PSGMII_FX100 = 2,
/**< PSGMII FX100 mode */
PHY_PSGMII_AMDET = 3,
/**< PSGMII Auto mode */
PHY_SGMII_BASET = 4,
/**< SGMII mode */
PORT_QSGMII,
/**<QSGMII mode*/
PORT_SGMII_PLUS,
/**<PORT_SGMII_PLUS mode*/
PORT_USXGMII,
/**<PORT_USXGMII mode*/
PORT_10GBASE_R,
/**<PORT_10GBASE_R mode*/
PORT_RGMII_BASET,
/**< RGMII mode */
PORT_RGMII_BX1000,
/**< RGMII BX1000 mode */
PORT_RGMII_FX100,
/**< RGMII FX100 mode */
PORT_RGMII_AMDET,
/**< RGMII Auto mode */
PHY_PSGMII_FIBER,
/** <PHY_PSGMII_FIBER mode */
PORT_SGMII_FIBER,
/** <PORT SGMII_FIBER mode*/
PORT_INTERFACE_MODE_MAX = 0xFF
} fal_port_interface_mode_t;
/** Phy counter information */
typedef struct {
a_uint32_t RxGoodFrame;
a_uint32_t RxBadCRC;
a_uint32_t TxGoodFrame;
a_uint32_t TxBadCRC;
a_uint32_t SysRxGoodFrame;
a_uint32_t SysRxBadCRC;
a_uint32_t SysTxGoodFrame;
a_uint32_t SysTxBadCRC;
} fal_port_counter_info_t;
/*above is new add for malibu phy*/
/*qca808x_end*/
typedef struct {
a_bool_t enable;
a_uint32_t capability;
a_uint32_t lpi_sleep_timer; /* unit is us*/
a_uint32_t advertisement;
a_uint32_t lpi_tx_enable;
a_uint32_t eee_status;
a_uint32_t lpi_wakeup_timer; /* unit is us*/
a_uint32_t link_partner_advertisement;
} fal_port_eee_cfg_t;
enum
{
/*port contorl*/
FUNC_ADPT_PORT_LOCAL_LOOPBACK_GET = 0,
FUNC_ADPT_PORT_AUTONEG_RESTART,
FUNC_ADPT_PORT_DUPLEX_SET,
FUNC_ADPT_PORT_RXMAC_STATUS_GET,
FUNC_ADPT_PORT_CDT,
FUNC_ADPT_PORT_TXMAC_STATUS_SET,
FUNC_ADPT_PORT_COMBO_FIBER_MODE_SET,
FUNC_ADPT_PORT_COMBO_MEDIUM_STATUS_GET,
FUNC_ADPT_PORT_MAGIC_FRAME_MAC_SET,
FUNC_ADPT_PORT_POWERSAVE_SET,
FUNC_ADPT_PORT_HIBERNATE_SET,
FUNC_ADPT_PORT_8023AZ_GET,
FUNC_ADPT_PORT_RXFC_STATUS_GET,
FUNC_ADPT_PORT_TXFC_STATUS_GET,
FUNC_ADPT_PORT_REMOTE_LOOPBACK_SET,
FUNC_ADPT_PORT_FLOWCTRL_SET,
FUNC_ADPT_PORT_MRU_SET,
FUNC_ADPT_PORT_AUTONEG_STATUS_GET,
FUNC_ADPT_PORT_TXMAC_STATUS_GET,
FUNC_ADPT_PORT_MDIX_GET,
FUNC_ADPT_PORTS_LINK_STATUS_GET,
FUNC_ADPT_PORT_MAC_LOOPBACK_SET,
FUNC_ADPT_PORT_PHY_ID_GET,
FUNC_ADPT_PORT_MRU_GET,
FUNC_ADPT_PORT_POWER_ON,
FUNC_ADPT_PORT_SPEED_SET,
FUNC_ADPT_PORT_INTERFACE_MODE_GET,
FUNC_ADPT_PORT_DUPLEX_GET,
FUNC_ADPT_PORT_AUTONEG_ADV_GET,
FUNC_ADPT_PORT_MDIX_STATUS_GET,
FUNC_ADPT_PORT_MTU_SET,
FUNC_ADPT_PORT_LINK_STATUS_GET,
FUNC_ADPT_PORT_8023AZ_SET,
FUNC_ADPT_PORT_POWERSAVE_GET,
FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_GET,
FUNC_ADPT_PORT_COMBO_PREFER_MEDIUM_SET,
FUNC_ADPT_PORT_POWER_OFF,
FUNC_ADPT_PORT_TXFC_STATUS_SET,
FUNC_ADPT_PORT_COUNTER_SET,
FUNC_ADPT_PORT_COMBO_FIBER_MODE_GET,
FUNC_ADPT_PORT_LOCAL_LOOPBACK_SET,
FUNC_ADPT_PORT_WOL_STATUS_SET,
FUNC_ADPT_PORT_MAGIC_FRAME_MAC_GET,
FUNC_ADPT_PORT_FLOWCTRL_GET,
FUNC_ADPT_PORT_RXMAC_STATUS_SET,
FUNC_ADPT_PORT_COUNTER_GET,
FUNC_ADPT_PORT_INTERFACE_MODE_SET,
FUNC_ADPT_PORT_MAC_LOOPBACK_GET,
FUNC_ADPT_PORT_HIBERNATE_GET,
FUNC_ADPT_PORT_AUTONEG_ADV_SET,
FUNC_ADPT_PORT_REMOTE_LOOPBACK_GET,
FUNC_ADPT_PORT_COUNTER_SHOW,
FUNC_ADPT_PORT_AUTONEG_ENABLE,
FUNC_ADPT_PORT_MTU_GET,
FUNC_ADPT_PORT_INTERFACE_MODE_STATUS_GET,
FUNC_ADPT_PORT_RESET,
FUNC_ADPT_PORT_RXFC_STATUS_SET,
FUNC_ADPT_PORT_SPEED_GET,
FUNC_ADPT_PORT_MDIX_SET,
FUNC_ADPT_PORT_WOL_STATUS_GET,
FUNC_ADPT_PORT_MAX_FRAME_SIZE_SET,
FUNC_ADPT_PORT_MAX_FRAME_SIZE_GET,
FUNC_ADPT_PORT_SOURCE_FILTER_GET,
FUNC_ADPT_PORT_SOURCE_FILTER_SET,
FUNC_ADPT_PORT_INTERFACE_MODE_APPLY,
FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_SET,
FUNC_ADPT_PORT_INTERFACE_3AZ_STATUS_GET,
FUNC_ADPT_PORT_PROMISC_MODE_SET,
FUNC_ADPT_PORT_PROMISC_MODE_GET,
FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_SET,
FUNC_ADPT_PORT_FLOWCTRL_FORCEMODE_GET,
};
typedef struct {
a_uint32_t mtu_size;
fal_fwd_cmd_t action;
} fal_mtu_ctrl_t;
typedef struct {
a_uint32_t mru_size;
fal_fwd_cmd_t action;
} fal_mru_ctrl_t;
typedef enum {
FAL_SRC_FILTER_MODE_VP = 0,
FAL_SRC_FILTER_MODE_PHYSICAL = 1,
} fal_src_filter_mode_t;
typedef struct {
a_bool_t src_filter_enable;
fal_src_filter_mode_t src_filter_mode;
} fal_src_filter_config_t;
typedef struct {
a_bool_t enable;
a_bool_t crc_stripped;
a_uint32_t loopback_rate; /*Mpps*/
}fal_loopback_config_t;
sw_error_t
fal_port_max_frame_size_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t max_frame);
sw_error_t
fal_port_max_frame_size_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t *max_frame);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
fal_mtu_ctrl_t *ctrl);
sw_error_t
fal_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mtu_ctrl_t *ctrl);
sw_error_t
fal_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
fal_mru_ctrl_t *ctrl);
sw_error_t
fal_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mru_ctrl_t *ctrl);
#endif
/*qca808x_start*/
sw_error_t
fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t duplex);
sw_error_t
fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t * pduplex);
sw_error_t
fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_speed_t speed);
sw_error_t
fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_speed_t * pspeed);
sw_error_t
fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * status);
sw_error_t
fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
sw_error_t
fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
sw_error_t
fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t autoadv);
sw_error_t
fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * autoadv);
/*qca808x_end*/
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_flowctrl_forcemode_set(a_uint32_t dev_id,
fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_flowctrl_forcemode_get(a_uint32_t dev_id,
fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_header_mode_t mode);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_header_mode_t * mode);
#endif
sw_error_t
fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_header_mode_t mode);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_header_mode_t * mode);
#endif
sw_error_t
fal_header_type_set(a_uint32_t dev_id, a_bool_t enable,
a_uint32_t type);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable,
a_uint32_t * type);
#endif
sw_error_t
fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
/*qca808x_start*/
sw_error_t
fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * status);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_ports_link_status_get(a_uint32_t dev_id, a_uint32_t * status);
/*qca808x_end*/
sw_error_t
fal_port_congestion_drop_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t queue_id, a_bool_t enable);
sw_error_t
fal_port_congestion_drop_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t queue_id,
a_bool_t * enable);
sw_error_t
fal_ring_flow_ctrl_thres_set(a_uint32_t dev_id, a_uint32_t ring_id,
a_uint8_t on_thres,
a_uint8_t off_thres);
sw_error_t
fal_ring_flow_ctrl_thres_get(a_uint32_t dev_id, a_uint32_t ring_id,
a_uint8_t * on_thres,
a_uint8_t * off_thres);
/*qca808x_start*/
sw_error_t
fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mdi_pair, fal_cable_status_t * cable_status,
a_uint32_t * cable_len);
sw_error_t
fal_port_8023az_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_8023az_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_mdix_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_mdix_mode_t mode);
sw_error_t
fal_port_mdix_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_mdix_mode_t * mode);
sw_error_t
fal_port_mdix_status_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_mdix_status_t * mode);
/*qca808x_end*/
sw_error_t
fal_port_combo_prefer_medium_set(a_uint32_t dev_id,
a_uint32_t port_id,
fal_port_medium_t medium);
sw_error_t
fal_port_combo_prefer_medium_get(a_uint32_t dev_id,
a_uint32_t port_id,
fal_port_medium_t *
medium);
sw_error_t
fal_port_combo_medium_status_get(a_uint32_t dev_id,
a_uint32_t port_id,
fal_port_medium_t *
medium);
sw_error_t
fal_port_combo_fiber_mode_set(a_uint32_t dev_id,
a_uint32_t port_id,
fal_port_fiber_mode_t mode);
sw_error_t
fal_port_combo_fiber_mode_get(a_uint32_t dev_id,
a_uint32_t port_id,
fal_port_fiber_mode_t * mode);
/*qca808x_start*/
sw_error_t
fal_port_local_loopback_set(a_uint32_t dev_id,
fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_remote_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_remote_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_reset(a_uint32_t dev_id, fal_port_t port_id);
#endif
sw_error_t
fal_port_power_off(a_uint32_t dev_id, fal_port_t port_id);
sw_error_t
fal_port_power_on(a_uint32_t dev_id, fal_port_t port_id);
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_magic_frame_mac_set(a_uint32_t dev_id, fal_port_t port_id,
fal_mac_addr_t * mac);
sw_error_t
fal_port_magic_frame_mac_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mac_addr_t * mac);
sw_error_t
fal_port_phy_id_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint16_t * org_id, a_uint16_t * rev_id);
sw_error_t
fal_port_wol_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
/*all indirect */
sw_error_t
fal_port_wol_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
/*qca808x_end*/
sw_error_t
fal_port_interface_mode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_interface_mode_t mode);
sw_error_t
fal_port_interface_mode_apply(a_uint32_t dev_id);
sw_error_t
fal_port_interface_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_interface_mode_t * mode);
/*qca808x_start*/
sw_error_t
fal_port_interface_mode_status_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_interface_mode_t * mode);
sw_error_t
fal_debug_phycounter_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_debug_phycounter_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_debug_phycounter_show(a_uint32_t dev_id, fal_port_t port_id,
fal_port_counter_info_t * port_counter_info);
#endif
/*qca808x_end*/
#ifndef IN_PORTCONTROL_MINI
sw_error_t
fal_port_source_filter_status_get(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_port_source_filter_enable(a_uint32_t dev_id,
fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_source_filter_config_get(a_uint32_t dev_id,
fal_port_t port_id, fal_src_filter_config_t * src_filter_config);
sw_error_t
fal_port_source_filter_config_set(a_uint32_t dev_id,
fal_port_t port_id, fal_src_filter_config_t *src_filter_config);
sw_error_t
fal_port_interface_3az_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_interface_3az_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_promisc_mode_get(a_uint32_t dev_id,fal_port_t port_id,a_bool_t *enable);
#endif
sw_error_t
fal_port_promisc_mode_set(a_uint32_t dev_id,fal_port_t port_id,a_bool_t enable);
sw_error_t
fal_port_interface_eee_cfg_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_eee_cfg_t *port_eee_cfg);
sw_error_t
fal_port_interface_eee_cfg_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_eee_cfg_t *port_eee_cfg);
sw_error_t
fal_switch_port_loopback_set(a_uint32_t dev_id, fal_port_t port_id,
fal_loopback_config_t *loopback_cfg);
sw_error_t
fal_switch_port_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
fal_loopback_config_t *loopback_cfg);
/*qca808x_start*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_PORTCTRL_H_ */
/**
* @}
*/
/*qca808x_end*/

738
feeds/ipq807x/qca-ssdk/src/include/fal/fal_portvlan.h
View File

@@ -1,738 +0,0 @@
/*
* Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_port_vlan FAL_PORT_VLAN
* @{
*/
#ifndef _FAL_PORT_VLAN_H_
#define _FAL_PORT_VLAN_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
#define FAL_PORTVLAN_API_LOCK
#define FAL_PORTVLAN_API_UNLOCK
#else
#define FAL_PORTVLAN_API_LOCK
#define FAL_PORTVLAN_API_UNLOCK
#endif
#define FAL_DEF_VLAN_STPID 0x88a8
#define FAL_DEF_VLAN_CTPID 0x8100
/**
@brief This enum defines 802.1q mode type.
*/
typedef enum {
FAL_1Q_DISABLE = 0, /**< 802.1q mode disbale, port based vlan */
FAL_1Q_SECURE, /**< secure mode, packets which vid isn't in vlan table or source port isn't in vlan port member will be discarded.*/
FAL_1Q_CHECK, /**< check mode, packets which vid isn't in vlan table will be discarded, packets which source port isn't in vlan port member will forward base on vlan port member*/
FAL_1Q_FALLBACK, /**< fallback mode, packets which vid isn't in vlan table will forwarded base on port vlan, packet's which source port isn't in vlan port member will forward base on vlan port member.*/
FAL_1Q_MODE_BUTT
}
fal_pt_1qmode_t;
/**
@brief This enum defines receive packets tagged mode.
*/
typedef enum
{
FAL_INVLAN_ADMIT_ALL = 0, /**< receive all packets include tagged and untagged */
FAL_INVLAN_ADMIT_TAGGED, /**< only receive tagged packets*/
FAL_INVLAN_ADMIT_UNTAGGED, /**< only receive untagged packets include priority tagged */
FAL_INVLAN_MODE_BUTT
} fal_pt_invlan_mode_t;
/**
@brief This enum defines vlan propagation mode.
*/
typedef enum
{
FAL_VLAN_PROPAGATION_DISABLE = 0, /**< vlan propagation disable */
FAL_VLAN_PROPAGATION_CLONE, /**< vlan paopagation mode is clone */
FAL_VLAN_PROPAGATION_REPLACE, /**< vlan paopagation mode is repalce */
FAL_VLAN_PROPAGATION_MODE_BUTT
} fal_vlan_propagation_mode_t;
typedef enum
{
FAL_FRAMETYPE_ETHERNET = 0,
FAL_FRAMETYPE_RFC_1024 = 1,
FAL_FRAMETYPE_LLC_OTHER = 2,
FAL_FRAMETYPE_ETHORRFC1024 = 3,
} fal_frametype_t;
typedef enum
{
FAL_VID_XLT_CMD_UNCHANGED = 0,
FAL_VID_XLT_CMD_ADDORREPLACE = 1,
FAL_VID_XLT_CMD_DELETE = 2,
} fal_vid_xlt_cmd_t;
typedef enum
{
FAL_PORT_VLAN_ALL = 0,
FAL_PORT_VLAN_INGRESS = 1,
FAL_PORT_VLAN_EGRESS = 2,
} fal_port_vlan_direction_t;
/**
@details Fields description:
o_vid - original vlan id
s_vid - service vid id
c_vid - custom vid id
bi_dir - entry search direction
forward_dir - entry search direction only be forward
reverse_dir - entry search direction only be reverse
o_vid_is_cvid - o_vid in entry means c_vid not s_vid
s_vid_enable - s_vid in entry is valid
c_vid_enable - c_vid in entry is valid
one_2_one_vlan- the entry used for 1:1 vlan
@brief This structure defines the vlan translation entry.
*/
typedef struct
{
a_uint32_t o_vid; /* original vid */
a_uint32_t s_vid; /* service vid */
a_uint32_t c_vid; /* customer vid */
a_bool_t bi_dir; /* lookup can be forward and reverse */
a_bool_t forward_dir; /* lookup direction only can be from o_vid to s_vid and/or c_vid*/
a_bool_t reverse_dir; /* lookup direction only can be from s_vid and/or c_vid to o_vid*/
a_bool_t o_vid_is_cvid;
a_bool_t s_vid_enable; /* enable svid value or not */
a_bool_t c_vid_enable; /* enable cvid value or not */
a_bool_t one_2_one_vlan;
/*direction check*/
a_uint32_t trans_direction; /* 0 is for ingress, 1 is for egress */
/*vsi check*/
a_bool_t vsi_valid; /* check if rule will include vsi value valid */
a_bool_t vsi_enable; /* check if rule will include vsi value */
a_uint32_t vsi; /* vsi value */
/*protocol and ethernet type*/
a_bool_t protocol_enable; /* enable protocol value or not */
a_uint16_t protocol; /* protocol value */
a_bool_t frmtype_enable; /* enable frame type value or not */
fal_frametype_t frmtype; /* frame type value */
/*tagged mode, bit 0 for untagged, bit 1 for priority tagged and bit 2 for tagged*/
a_uint8_t s_tagged; /* stag type is untagged/pri tagged/tagged */
a_uint8_t c_tagged; /* ctag type is untagged/pri tagged/tagged */
/*cpcp and cdei*/
a_bool_t c_pcp_enable; /* check if rule will include customer pcp value */
a_uint8_t c_pcp; /* customer pcp value */
a_bool_t c_dei_enable; /* check if rule will include customer dei value */
a_uint8_t c_dei; /* customer dei value */
/*spcp and sdei*/
a_bool_t s_pcp_enable; /* check if rule will include service pcp value */
a_uint8_t s_pcp; /* service pcp value */
a_bool_t s_dei_enable; /* check if rule will include service dei value */
a_uint8_t s_dei; /* service dei value */
/*translation action*/
/*counter action*/
a_bool_t counter_enable; /* check if action will enable counter_id */
a_uint8_t counter_id; /* counter id */
/*vsi action*/
a_bool_t vsi_action_enable; /* check if action will enable vsi action */
a_uint8_t vsi_action; /* vsi action */
/*svid action*/
fal_vid_xlt_cmd_t svid_xlt_cmd; /* check if action will do svid xlt */
a_uint16_t svid_xlt; /* svid xlt operation */
/*cvid action*/
fal_vid_xlt_cmd_t cvid_xlt_cmd; /* check if action will do cvid xlt */
a_uint16_t cvid_xlt; /* cvid xlt operation */
/*swap svid and cvid action*/
a_bool_t swap_svid_cvid; /* check if action will do svid and cvid swap operation */
/*spcp action*/
a_bool_t spcp_xlt_enable; /* check if action will enable spcp xlt */
a_uint8_t spcp_xlt; /* spcp xlt operation */
/*cpcp action*/
a_bool_t cpcp_xlt_enable; /* check if action will enable cpcp xlt */
a_uint8_t cpcp_xlt; /* cpcp xlt operation */
/*swap spcp and cpcp action*/
a_bool_t swap_spcp_cpcp; /* check if action will do spcp and cpcp swap operation */
/*sdei action*/
a_bool_t sdei_xlt_enable; /* check if action will enable sdei xlt */
a_uint8_t sdei_xlt; /* sdei xlt operation */
/*cdei action*/
a_bool_t cdei_xlt_enable; /* check if action will enable cdei xlt */
a_uint8_t cdei_xlt; /* cdei xlt operation */
/*swap sdei and cdei action*/
a_bool_t swap_sdei_cdei; /* check if action will do sdei and cdei swap operation */
/*port bitmap for this entry*/
a_uint32_t port_bitmap; /* rule must be include port_bitmap */
} fal_vlan_trans_entry_t;
/**
@brief This enum defines qinq working mode.
*/
typedef enum
{
FAL_QINQ_CTAG_MODE = 0,
FAL_QINQ_STAG_MODE,
FAL_QINQ_MODE_BUTT
} fal_qinq_mode_t;
/**
@brief This enum defines port role in qinq mode.
*/
typedef enum
{
FAL_QINQ_EDGE_PORT = 0,
FAL_QINQ_CORE_PORT,
FAL_QINQ_PORT_ROLE_BUTT
} fal_qinq_port_role_t;
enum {
FUNC_PORT_INVLAN_MODE_SET = 0,
FUNC_PORT_INVLAN_MODE_GET,
FUNC_PORT_VLAN_TRANS_ADD,
FUNC_PORT_VLAN_TRANS_DEL,
FUNC_PORT_VLAN_TRANS_GET,
FUNC_QINQ_MODE_SET,
FUNC_QINQ_MODE_GET,
FUNC_PORT_QINQ_ROLE_SET,
FUNC_PORT_QINQ_ROLE_GET,
FUNC_PORT_VLAN_TRANS_ITERATE,
FUNC_GLOBAL_QINQ_MODE_SET,
FUNC_GLOBAL_QINQ_MODE_GET,
FUNC_PORT_QINQ_MODE_SET,
FUNC_PORT_QINQ_MODE_GET,
FUNC_INGRESS_TPID_SET,
FUNC_INGRESS_TPID_GET,
FUNC_EGRESS_TPID_SET,
FUNC_EGRESS_TPID_GET,
FUNC_PORT_INGRESS_VLAN_FILTER_SET,
FUNC_PORT_INGRESS_VLAN_FILTER_GET,
FUNC_PORT_DEFAULT_VLANTAG_SET,
FUNC_PORT_DEFAULT_VLANTAG_GET,
FUNC_PORT_TAG_PROPAGATION_SET,
FUNC_PORT_TAG_PROPAGATION_GET,
FUNC_PORT_VLANTAG_EGMODE_SET,
FUNC_PORT_VLANTAG_EGMODE_GET,
FUNC_PORT_VLAN_XLT_MISS_CMD_SET,
FUNC_PORT_VLAN_XLT_MISS_CMD_GET,
FUNC_PORT_VSI_EGMODE_SET,
FUNC_PORT_VSI_EGMODE_GET,
FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_SET,
FUNC_PORT_VLANTAG_VSI_EGMODE_ENABLE_GET,
FUNC_PORT_VLAN_TRANS_ADV_ADD,
FUNC_PORT_VLAN_TRANS_ADV_DEL,
FUNC_PORT_VLAN_TRANS_ADV_GETFIRST,
FUNC_PORT_VLAN_TRANS_ADV_GETNEXT,
FUNC_PORT_VLAN_COUNTER_GET,
FUNC_PORT_VLAN_COUNTER_CLEANUP,
FUNC_PORT_VLAN_MEMBER_ADD,
FUNC_PORT_VLAN_MEMBER_DEL,
FUNC_PORT_VLAN_MEMBER_UPDATE,
FUNC_PORT_VLAN_MEMBER_GET,
};
sw_error_t
fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t port_1qmode);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t * pport_1qmode);
#endif
sw_error_t
fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t port_egvlanmode);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t * pport_egvlanmode);
#endif
sw_error_t
fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
fal_port_t mem_port_id);
sw_error_t
fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
fal_port_t mem_port_id);
sw_error_t
fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t mem_port_map);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t * mem_port_map);
#endif
sw_error_t
fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t vid);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * vid);
#endif
sw_error_t
fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
#endif
sw_error_t
fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_invlan_mode_t mode);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_invlan_mode_t * mode);
#endif
sw_error_t
fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
#endif
sw_error_t
fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t vid);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * vid);
#endif
sw_error_t
fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t vid);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * vid);
#endif
sw_error_t
fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
fal_vlan_propagation_mode_t mode);
sw_error_t
fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
sw_error_t
fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
sw_error_t
fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
#ifndef IN_PORTVLAN_MINI
sw_error_t
fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
fal_vlan_propagation_mode_t * mode);
sw_error_t
fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
sw_error_t
fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
sw_error_t
fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
sw_error_t
fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
sw_error_t
fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
sw_error_t
fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable);
sw_error_t
fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable);
sw_error_t
fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable);
sw_error_t
fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable);
sw_error_t
fal_port_vrf_id_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t vrf_id);
sw_error_t
fal_port_vrf_id_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * vrf_id);
#endif
#define FAL_FLG_TST(flag, field) \
(((flag) & (field)) ? 1 : 0)
#define FAL_GLOBAL_QINQ_MODE_INGRESS_EN (0x1UL << 0)
#define FAL_GLOBAL_QINQ_MODE_EGRESS_EN (0x1UL << 1)
#define FAL_GLOBAL_QINQ_MODE_EGRESS_UNTOUCHED_FOR_CPU_CODE (0x1UL << 2)
typedef struct {
a_uint32_t mask;/*bit 0 for ingress and bit 1 for egress*/
fal_qinq_mode_t ingress_mode; /* ingress direction mode */
fal_qinq_mode_t egress_mode; /* egress direction mode */
a_bool_t untouched_for_cpucode; /*egress untouched with cpu_code!=0 to cpu port 0 */
} fal_global_qinq_mode_t;
#define FAL_PORT_QINQ_ROLE_INGRESS_EN (0x1UL << 0)
#define FAL_PORT_QINQ_ROLE_EGRESS_EN (0x1UL << 1)
typedef struct {
a_uint32_t mask;/*bit 0 for ingress and bit 1 for egress*/
fal_qinq_port_role_t ingress_port_role; /* port inress direction role */
fal_qinq_port_role_t egress_port_role; /* port egress direction role */
} fal_port_qinq_role_t;
#define FAL_TPID_CTAG_EN (0x1UL << 0)
#define FAL_TPID_STAG_EN (0x1UL << 1)
typedef struct
{
a_uint32_t mask; /*bit 0 for ctpid and bit 1 for stpid*/
a_uint16_t ctpid; /* customer tpid value */
a_uint16_t stpid; /* service tpid value */
} fal_tpid_t;
typedef struct {
a_bool_t membership_filter; /* check if ingress will filter port in vlan filter */
a_bool_t tagged_filter; /* check if ingress will filter tagged packet */
a_bool_t untagged_filter; /* check if ingress will filter untagged packet */
a_bool_t priority_filter; /* check if ingress will filter priority packet */
} fal_ingress_vlan_filter_t;
#define FAL_PORT_VLAN_TAG_CVID_EN (0x1UL << 0)
#define FAL_PORT_VLAN_TAG_SVID_EN (0x1UL << 1)
#define FAL_PORT_VLAN_TAG_CPCP_EN (0x1UL << 2)
#define FAL_PORT_VLAN_TAG_SPCP_EN (0x1UL << 3)
#define FAL_PORT_VLAN_TAG_CDEI_EN (0x1UL << 4)
#define FAL_PORT_VLAN_TAG_SDEI_EN (0x1UL << 5)
typedef struct
{
a_uint32_t mask; /*bit 0 for ctag vid;
*bit 1 for stag vid;
*bit 2 for ctag priority;
*bit 3 for stag priority;
*bit 4 for ctag dei;
*bit 5 for stag dei*/
a_uint16_t cvid; /* customer vid value */
a_uint16_t svid; /* service vid value */
a_uint16_t cpri; /* customer pri value */
a_uint16_t spri; /* service pri value */
a_uint16_t cdei; /* customer dei value */
a_uint16_t sdei; /* service dei value */
} fal_port_vlan_tag_t;
typedef struct {
a_bool_t default_cvid_en; /* enable default cvid or not */
a_bool_t default_svid_en; /* enable default svid or not */
} fal_port_default_vid_enable_t;
#define FAL_PORT_PROPAGATION_VID_EN (0x1UL << 0)
#define FAL_PORT_PROPAGATION_PCP_EN (0x1UL << 1)
#define FAL_PORT_PROPAGATION_DEI_EN (0x1UL << 2)
typedef struct
{
a_uint32_t mask; /*bit 0 for vid;
*bit 1 for priority;
*bit 2 for dei*/
fal_vlan_propagation_mode_t vid_propagation; /* enable vid propagation or not */
fal_vlan_propagation_mode_t pri_propagation; /* enable pri propagation or not */
fal_vlan_propagation_mode_t dei_propagation; /* enable dei propagation or not */
} fal_vlantag_propagation_t;
#define FAL_EGRESSMODE_CTAG_EN (0x1UL << 0)
#define FAL_EGRESSMODE_STAG_EN (0x1UL << 1)
typedef struct
{
a_uint32_t mask; /*bit 0 for ctag and bit 1 for stag*/
fal_pt_1q_egmode_t stag_mode; /* stag mode */
fal_pt_1q_egmode_t ctag_mode; /* ctag mode */
} fal_vlantag_egress_mode_t;
typedef struct
{
a_uint32_t port_bitmap; /* rule need know which ports matched this rule */
a_uint8_t s_tagged; /* rule need know stag type(untagged/pri_tagged/tagged) */
a_bool_t s_vid_enable; /* check if rule will include service vid value */
a_uint32_t s_vid; /* service vid */
a_bool_t s_pcp_enable; /* check if rule will include service pcp value */
a_uint8_t s_pcp; /* service pcp value */
a_bool_t s_dei_enable; /* check if rule will include service dei value */
a_uint8_t s_dei; /* service dei value */
a_uint8_t c_tagged; /* rule need know ctag type(untagged/pri_tagged/tagged) */
a_bool_t c_vid_enable; /* check if rule will include customer vid value */
a_uint32_t c_vid; /* customer vid */
a_bool_t c_pcp_enable; /* check if rule will include customer pcp value */
a_uint8_t c_pcp; /* customer pcp value */
a_bool_t c_dei_enable; /* check if rule will include customer dei value */
a_uint8_t c_dei; /* customert dei value */
/* these four fields just for vlan ingress rule */
a_bool_t frmtype_enable; /* check if rule will include frame type value */
fal_frametype_t frmtype; /* frame type value */
a_bool_t protocol_enable; /* check if rule will include protocol value */
a_uint16_t protocol; /* protocol value */
/* these three fields just for vlan egress rule */
a_bool_t vsi_valid; /* check if rule will include vsi value valid */
a_bool_t vsi_enable; /* check if rule will include vsi value */
a_uint32_t vsi; /* vsi value */
} fal_vlan_trans_adv_rule_t;
typedef struct
{
a_bool_t swap_svid_cvid; /* check if action will do svid and cvid swap operation */
fal_vid_xlt_cmd_t svid_xlt_cmd; /* check if action will do svid xlt operation */
a_uint16_t svid_xlt; /* service vid xlt value */
fal_vid_xlt_cmd_t cvid_xlt_cmd; /* check if action will do cvid xlt operation */
a_uint16_t cvid_xlt; /* customer vid xlt value */
a_bool_t swap_spcp_cpcp; /* check if action will do spcp and cpcp swap operation */
a_bool_t spcp_xlt_enable; /* check if action will enable spcp xlt */
a_uint8_t spcp_xlt; /* service pcp xlt value */
a_bool_t cpcp_xlt_enable; /* check if action will enable cpcp xlt */
a_uint8_t cpcp_xlt; /* customer pcp xlt value */
a_bool_t swap_sdei_cdei; /* check if action will do sdei and cdei swap operation */
a_bool_t sdei_xlt_enable; /* check if action will enable sdei xlt */
a_uint8_t sdei_xlt; /* service dei xlt value */
a_bool_t cdei_xlt_enable; /* check if action will enable cdei xlt */
a_uint8_t cdei_xlt; /* customer dei xlt value */
a_bool_t counter_enable; /* check if action will enable counter_id */
a_uint8_t counter_id; /* counter id */
/* these two fields just for vlan ingress action */
a_bool_t vsi_xlt_enable; /* check if action will enable vsi xlt */
a_uint8_t vsi_xlt; /* vsi xlt value */
} fal_vlan_trans_adv_action_t;
typedef struct
{
a_uint32_t rx_packet_counter; /* ingress vlan translation pkt counter */
a_uint64_t rx_byte_counter; /* ingress vlan translation byte counter */
a_uint32_t tx_packet_counter; /* egress vlan translation pkt counter */
a_uint64_t tx_byte_counter; /* egress vlan translation byte counter */
} fal_port_vlan_counter_t;
sw_error_t
fal_port_vlan_counter_get(a_uint32_t dev_id, a_uint32_t cnt_index, fal_port_vlan_counter_t * counter);
sw_error_t
fal_port_vlan_counter_cleanup(a_uint32_t dev_id, a_uint32_t cnt_index);
sw_error_t
fal_global_qinq_mode_set(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
sw_error_t
fal_global_qinq_mode_get(a_uint32_t dev_id, fal_global_qinq_mode_t *mode);
sw_error_t
fal_port_qinq_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
sw_error_t
fal_port_qinq_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_qinq_role_t *mode);
sw_error_t
fal_ingress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid);
sw_error_t
fal_ingress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid);
sw_error_t
fal_egress_tpid_set(a_uint32_t dev_id, fal_tpid_t *tpid);
sw_error_t
fal_egress_tpid_get(a_uint32_t dev_id, fal_tpid_t *tpid);
sw_error_t
fal_port_ingress_vlan_filter_set(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
sw_error_t
fal_port_ingress_vlan_filter_get(a_uint32_t dev_id, fal_port_t port_id, fal_ingress_vlan_filter_t *filter);
sw_error_t
fal_port_default_vlantag_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_vlan_direction_t direction, fal_port_default_vid_enable_t *default_vid_en,
fal_port_vlan_tag_t *default_tag);
sw_error_t
fal_port_default_vlantag_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_vlan_direction_t direction, fal_port_default_vid_enable_t *default_vid_en,
fal_port_vlan_tag_t *default_tag);
sw_error_t
fal_port_tag_propagation_set(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlantag_propagation_t *prop);
sw_error_t
fal_port_tag_propagation_get(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlantag_propagation_t *prop);
sw_error_t
fal_port_vlan_xlt_miss_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t cmd);
sw_error_t
fal_port_vlan_xlt_miss_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
fal_fwd_cmd_t *cmd);
sw_error_t
fal_port_vlantag_egmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_vlantag_egress_mode_t *port_egvlanmode);
sw_error_t
fal_port_vlantag_egmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_vlantag_egress_mode_t *port_egvlanmode);
sw_error_t
fal_port_vsi_egmode_set(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t egmode);
sw_error_t
fal_port_vsi_egmode_get(a_uint32_t dev_id, a_uint32_t vsi, a_uint32_t port_id, fal_pt_1q_egmode_t * egmode);
sw_error_t
fal_port_vlantag_vsi_egmode_enable(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
sw_error_t
fal_port_vlantag_vsi_egmode_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
sw_error_t
fal_port_vlan_trans_adv_add(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
sw_error_t
fal_port_vlan_trans_adv_del(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
sw_error_t
fal_port_vlan_trans_adv_getfirst(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
sw_error_t
fal_port_vlan_trans_adv_getnext(a_uint32_t dev_id, fal_port_t port_id, fal_port_vlan_direction_t direction,
fal_vlan_trans_adv_rule_t * rule, fal_vlan_trans_adv_action_t * action);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _PORT_VLAN_H_ */
/**
* @}
*/

109
feeds/ipq807x/qca-ssdk/src/include/fal/fal_pppoe.h
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@@ -1,109 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_pppoe FAL_PPPOE
* @{
*/
#ifndef _FAL_PPPOE_H_
#define _FAL_PPPOE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
enum {
FUNC_PPPOE_SESSION_TABLE_ADD = 0,
FUNC_PPPOE_SESSION_TABLE_DEL,
FUNC_PPPOE_SESSION_TABLE_GET,
FUNC_PPPOE_EN_SET,
FUNC_PPPOE_EN_GET,
};
typedef struct
{
a_uint32_t entry_id; /* the entry id saved to pppoe table */
a_uint32_t session_id; /* pppoe session id */
a_bool_t multi_session; /* matched multicast session */
a_bool_t uni_session; /* matched unicast session */
a_uint32_t vrf_id; /* vrf id, HPPE not supported */
a_uint32_t port_bitmap; /* matched ports */
a_uint32_t l3_if_index; /* if matched, this l3 interface index will remove pppoe header */
a_bool_t l3_if_valid; /* this l3 interface index valid or not */
a_bool_t smac_valid; /* if matched source mac address */
fal_mac_addr_t smac_addr; /* matched source mac address */
} fal_pppoe_session_t;
sw_error_t
fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
sw_error_t
fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
sw_error_t
fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
sw_error_t
fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id);
sw_error_t
fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
sw_error_t
fal_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
sw_error_t
fal_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
sw_error_t
fal_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
sw_error_t
fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
a_uint32_t id);
sw_error_t
fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
a_uint32_t * id);
sw_error_t
fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
sw_error_t
fal_pppoe_l3intf_enable(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t enable);
sw_error_t
fal_pppoe_l3intf_status_get(a_uint32_t dev_id, a_uint32_t l3_if, a_uint32_t *enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_PPPOE_H_ */
/**
* @}
*/

496
feeds/ipq807x/qca-ssdk/src/include/fal/fal_ptp.h
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@@ -1,496 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_ptp FAL_PTP
* @{
*/
#ifndef _FAL_PTP_H_
#define _FAL_PTP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "common/sw.h"
#include "fal/fal_type.h"
typedef enum {
FAL_OC_CLOCK_MODE = 0, /* OC clock mode */
FAL_BC_CLOCK_MODE, /* BC clock mode */
FAL_E2ETC_CLOCK_MODE, /* E2E TC clock mode */
FAL_P2PTC_CLOCK_MODE /* P2P TC clock mode */
} fal_ptp_clock_mode_t;
typedef enum {
FAL_ONE_STEP_MODE = 0, /* one step mode */
FAL_TWO_STEP_MODE, /* two step mode */
FAL_AUTO_MODE /* step mode is selected through packet field */
} fal_ptp_step_mode_t;
typedef struct {
a_bool_t ptp_en; /* enable/disable ptp feature */
fal_ptp_clock_mode_t clock_mode; /* clock mode */
fal_ptp_step_mode_t step_mode; /* step mode */
} fal_ptp_config_t;
typedef enum {
FAL_REF_CLOCK_LOCAL = 0,/* use local clock as reference clock */
FAL_REF_CLOCK_SYNCE, /* use synce clock as reference clock */
FAL_REF_CLOCK_EXTERNAL, /* use external clock as reference clock */
} fal_ptp_reference_clock_t;
typedef enum {
FAL_RX_TS_MDIO = 0, /* timestamp will be saved to MDIO register */
FAL_RX_TS_EMBED, /* timestamp will be saved to packet PTP header */
} fal_ptp_rx_timestamp_mode_t;
typedef struct{
a_int64_t seconds; /* second field */
a_int32_t nanoseconds; /* nano second field */
a_int32_t fracnanoseconds; /* fraction nano second field */
} fal_ptp_time_t;
typedef enum {
FAL_RX_DIRECTION = 0, /* ptp rx direction */
FAL_TX_DIRECTION /* ptp tx direction */
} fal_ptp_direction_t;
typedef struct{
a_uint32_t sequence_id; /* packet field: sequenceId */
a_uint64_t clock_identify; /* packet field: ClockIdentify */
a_uint32_t port_number; /* packet field: SourcePortID */
a_uint32_t msg_type; /* packet field: message type */
} fal_ptp_pkt_info_t;
typedef enum {
FAL_GM_PPSIN_MODE = 0, /* use PSSIN mode to sync nanoseconds */
FAL_GM_HWPLL_MODE, /* use HWPLL mode to sync nanoseconds */
FAL_GM_SWPLL_MODE, /* use SWPLL mode to sync nanoseconds */
} fal_ptp_grandmaster_ns_sync_mode_t;
typedef enum { /* maximun frequency offset of rtc_clk from PPS source */
FAL_GM_MAXFREQ_1PPM = 0,
FAL_GM_MAXFREQ_10PPM,
FAL_GM_MAXFREQ_50PPM,
FAL_GM_MAXFREQ_100PPM,
FAL_GM_MAXFREQ_150PPM,
FAL_GM_MAXFREQ_200PPM, /* 802.3 standard select this value */
FAL_GM_MAXFREQ_250PPM,
FAL_GM_MAXFREQ_300PPM,
FAL_GM_MAXFREQ_0PPM
} fal_ptp_grandmaster_maxfreq_offset_t;
typedef struct {
a_bool_t grandmaster_mode_en; /* enable/disable grandmaster mode */
a_bool_t grandmaster_second_sync_en; /* GPS receiver second sync feature */
fal_ptp_grandmaster_maxfreq_offset_t freq_offset; /* for HWPLL */
a_bool_t right_shift_in_kp; /* for HWPLL, left or right shift */
a_uint32_t kp_value; /* for HWPLL, proportional part coefficient */
a_bool_t right_shift_in_ki; /* for HWPLL, left or right shift */
a_uint32_t ki_value; /* for HWPLL, integral part coefficient */
fal_ptp_grandmaster_ns_sync_mode_t ns_sync_mode; /* nano second sync mode */
} fal_ptp_grandmaster_mode_t;
typedef struct {
a_bool_t address_check_en; /* address should matched when regard it as PTP packet */
a_bool_t ipv6_udp_checksum_recal_en; /* recalculate ipv6 udp checksum on TX direction */
a_bool_t version_check_en; /* PTP version should matched when regard it as PTP packet */
a_uint32_t ptp_version; /* ptp version number to match */
a_bool_t ipv4_udp_checksum_force_zero_en; /* force ipv4 checksum to 0 on TX direction */
a_bool_t ipv6_embed_udp_checksum_force_zero_en; /* force RX ipv6 checksum to 0 */
} fal_ptp_security_t;
typedef struct {
a_bool_t negative_in_latency; /* ingress latency value is positive or negative */
a_uint32_t in_latency; /* ingress latency value */
a_uint32_t out_phase; /* adjust the phase of PPS outout signal */
a_uint32_t out_pulse_width; /* adjust the pulse width of PPS outout signal */
} fal_ptp_pps_signal_control_t;
typedef struct {
a_bool_t eg_asym_en; /* enable egress asymmetry correction */
a_bool_t in_asym_en; /* enable ingress asymmetry correction */
a_uint32_t eg_asym_value; /* egress asymmetry correction value */
a_uint32_t in_asym_value; /* ingress asymmetry correction value */
} fal_ptp_asym_correction_t;
typedef enum {
FAL_WAVE_FREQ = 0, /* select wave period as SYNC_CLKO_PTP output */
FAL_PULSE_10MS, /* select pulse 10ms as SYNC_CLKO_PTP output */
FAL_TRIGGER0_GPIO, /* select trigger0 status as SYNC_CLKO_PTP output */
FAL_RX_PTP_STATE, /* select RX PTP state as SYNC_CLKO_PTP output */
} fal_ptp_waveform_type_t;
typedef struct {
fal_ptp_waveform_type_t waveform_type; /* select the wave output type */
a_bool_t wave_align_pps_out_en; /* for FAL_WAVE_FREQ, enable wave align pps output */
a_uint64_t wave_period; /* for FAL_WAVE_FREQ, wave period */
} fal_ptp_output_waveform_t;
enum {
FAL_UART_START_POLARITY_HIGH_EN = 0, /* polarity of start bit is low/high */
FAL_UART_MSB_FIRST_EN, /* output LSB/MSB first */
FAL_UART_PARITY_CHECK_EN, /* parity check is enable/disable */
FAL_UART_AUTO_TOD_OUT_EN, /* enable output TOD via UART automatically */
FAL_UART_AUTO_TOD_IN_EN /* enable input TOD via UART automatically */
};
enum {
FAL_UART_RX_BUFFER_DATA_PRESENT = 0, /* RX BUFFER has data */
FAL_UART_RX_BUFFER_FULL, /* RX BUFFER is full */
FAL_UART_RX_BUFFER_ALMOST_FULL, /* RX BUFFER is full-1 */
FAL_UART_RX_BUFFER_HALF_FULL, /* RX BUFFER is half full */
FAL_UART_RX_BUFFER_ALMOST_EMPTY, /* RX BUFFER is 1 */
FAL_UART_TX_BUFFER_FULL, /* TX BUFFER is full */
FAL_UART_TX_BUFFER_ALMOST_FULL, /* TX BUFFER is full-1 */
FAL_UART_TX_BUFFER_HALF_FULL, /* TX BUFFER is half full */
FAL_UART_TX_BUFFER_ALMOST_EMPTY, /* TX BUFFER is 1 */
};
typedef struct {
a_uint16_t baud_config; /* baud_config = (125 * 10^6)/(16)/baud_rate for speed <= 1G */
/* baud_config = (200 * 10^6)/(16)/baud_rate for speed >= 2.5 G */
a_uint32_t uart_config_bmp; /* refer to FAL_UART_START_POLARITY_HIGH_EN */
a_bool_t reset_buf_en; /* reset TOD UART RX/TX buffer, self clearing */
a_uint32_t buf_status_bmp; /* refer to FAL_UART_RX_BUFFER_DATA_PRESENT */
a_uint16_t tx_buf_value; /* the uart data to transport */
a_uint16_t rx_buf_value; /* the uart data received */
} fal_ptp_tod_uart_t;
enum {
FAL_ENHANCED_TS_ETH_TYPE_EN = 0, /* timestamp the matched ethernet type */
FAL_ENHANCED_TS_DMAC_EN, /* timestamp the matched dst mac */
FAL_ENHANCED_TS_RESV_DMAC_EN, /* timestamp the matched ptp dst mac */
FAL_ENHANCED_TS_IPV4_L4_PROTO_EN, /* timestamp the matched layer 4 protocol id */
FAL_ENHANCED_TS_IPV4_DIP_EN, /* timestamp the matched ipv4 dst addr */
FAL_ENHANCED_TS_RESV_IPV4_DIP_EN, /* timestamp the matched ptp ipv4 dst addr */
FAL_ENHANCED_TS_IPV6_NEXT_HEADER_EN, /* timestamp the matched ipv6 next header field */
FAL_ENHANCED_TS_IPV6_DIP_EN, /* timestamp the matched ipv6 dst addr */
FAL_ENHANCED_TS_RESV_IPV6_DIP_EN, /* timestamp the matched ptp ipv6 dst addr */
FAL_ENHANCED_TS_UDP_DPORT_EN, /* timestamp the matched udp dport number */
FAL_ENHANCED_TS_RESV_UDP_DPORT_EN, /* timestamp the matched udp dport number */
FAL_ENHANCED_TS_Y1731_EN, /* timestamp the received Y1731 frame */
FAL_ENHANCED_TS_Y1731_TIMESTAMP_INSERT_EN, /* enable inserting RX Y1731 timestamp */
FAL_ENHANCED_TS_Y1731_MAC_EN /* TX direction check smac, RX direction check dmac */
};
enum {
FAL_ENHANCED_TS_ETH_TYPE_STATUS = 0, /* the MAC type of received packet matches
the filter setting */
FAL_ENHANCED_TS_DMAC_STATUS, /* the dest MAC of received packet matches
the filter setting */
FAL_ENHANCED_TS_RESV_PRIM_DMAC_STATUS, /* the dest MAC of received packet matches
PTP primary multicast MAC address */
FAL_ENHANCED_TS_RESV_PDELAY_DMAC_STATUS, /* the dest MAC of received packet matches
PTP peer delay multicast MAC address */
FAL_ENHANCED_TS_IPV4_L4_PROTO_STATUS, /* the L4 layer protocol of received packet
matched the filter setting */
FAL_ENHANCED_TS_IPV4_DIP_STATUS, /* the IPv4 dest address of received packet
matched the filter setting */
FAL_ENHANCED_TS_RESV_IPV4_PRIM_DIP_STATUS, /* the IPv4 dest address of received packet
matches PTP primary multicast ipv4 addr */
FAL_ENHANCED_TS_RESV_IPV4_PDELAY_DIP_STATUS,/* the IPv4 dest address of received packet
matches PTP peer delay multicast addr */
FAL_ENHANCED_TS_IPV6_NEXT_HEADER_STATUS, /* the next header fielf of receviced packet
matches the filter setting */
FAL_ENHANCED_TS_IPV6_DIP_STATUS, /* the ipv6 dest addr of received packet
matches the filter setting */
FAL_ENHANCED_TS_RESV_IPV6_PRIM_DIP_STATUS, /* the ipv6 dest address of received packet
matches PTP primary multicast ipv6 addr */
FAL_ENHANCED_TS_RESV_IPV6_PDELAY_DIP_STATUS,/* the ipv6 dest address of received packet
matches PTP peer delay multicast addr */
FAL_ENHANCED_TS_UDP_DPORT_STATUS, /* the UDP dest port of received packet
matches the filter setting */
FAL_ENHANCED_TS_RESV_UDP_DPORT_STATUS, /* the UDP dest port of received packet
matches udp dport of ptp event packet */
FAL_ENHANCED_TS_Y1731_MATCH_STATUS /* the received frame is Y.1731 OAM frame */
};
typedef struct {
a_bool_t filt_en; /* enable/disable filter feature */
a_uint32_t enhance_ts_conf_bmp; /* refer to FAL_ENHANCED_TS_ETH_TYPE_EN */
a_uint32_t eth_type; /* ethernet type value */
fal_mac_addr_t dmac_addr; /* dest mac address */
a_uint32_t ipv4_l4_proto; /* ipv4 layer 4 protocol field */
fal_ip4_addr_t ipv4_dip; /* ipv4 dest ip addr */
fal_ip6_addr_t ipv6_dip; /* ipv6 dest ip addr */
a_uint32_t udp_dport; /* udp dest port */
fal_mac_addr_t y1731_mac_addr; /* TX check smac, RX check dmac */
a_uint32_t enhance_ts_status_bmp; /* refer to FAL_ENHANCED_TS_ETH_TYPE_STATUS */
a_uint32_t enhance_ts_status_pre_bmp; /* TX NOT SUPPORT */
a_uint32_t y1731_identity; /* save Y1731 identify value */
a_uint32_t y1731_identity_pre; /* TX NOT SUPPORT */
fal_ptp_time_t timestamp; /* save packet timestamp when matched */
fal_ptp_time_t timestamp_pre; /* TX NOT SUPPORT */
} fal_ptp_enhanced_ts_engine_t;
typedef struct {
a_bool_t trigger_en; /* enable trigger or not */
a_bool_t output_force_en; /* force trigger output a force value */
int output_force_value; /* the forced value */
int patten_select; /* trigger pattern:
0 single rising edge;
1 single falling edge;
2 trigger pulse;
3 trigger periodic waveform;
4 toggle mode;
*/
int late_operation; /* if later, trigger immediately */
int notify; /* report the completion of trigger */
int trigger_effect; /* write 1 to generate a high pulse when trigger happen */
fal_ptp_time_t tim; /* the trigger timestamp */
} fal_ptp_trigger_conf_t;
typedef struct {
int trigger_finished; /* trigger finished or not */
int trigger_active; /* trigger is active or not */
int trigger_error; /* trigger error status
0 no error
1 trigger time prior to current time
2 initial value error for edge trigger
*/
} fal_ptp_trigger_status_t;
typedef struct {
fal_ptp_trigger_conf_t trigger_conf;
fal_ptp_trigger_status_t trigger_status;
} fal_ptp_trigger_t;
typedef struct {
int status_clear; /* clear event status register */
int notify_event; /* notify event through interrupt */
int single_multi_select; /* 1 for single or 0 for multi event capture */
a_bool_t fall_edge_en; /* enable falling edge detection */
a_bool_t rise_edge_en; /* enable rising edge detection */
} fal_ptp_capture_conf_t;
typedef struct {
int event_detected; /* event detected or not */
int fall_rise_edge_detected; /* 0 for rising edge, 1 for falling edge detected */
int single_multi_detected; /* 0 for single event, 1 for multi event detected */
int event_missed_cnt; /* the number of events missed */
fal_ptp_time_t tim; /* event timestamp */
} fal_ptp_capture_status_t;
typedef struct {
fal_ptp_capture_conf_t capture_conf;
fal_ptp_capture_status_t capture_status;
} fal_ptp_capture_t;
enum {
FAL_PTP_INTR_EXPAND = 0,/* expand interrupt, FAL_PTP_INTR_TX_GTSE ~ FAL_PTP_INTR_CAP1 */
FAL_PTP_INTR_RX, /* ptp pkt rx interrupt */
FAL_PTP_INTR_TX, /* ptp pkt tx interrupt */
FAL_PTP_INTR_TX_GTSE, /* gtse pkt tx interrupt */
FAL_PTP_INTR_RX_GTSE, /* gtse pkt rx interrupt */
FAL_PTP_INTR_TX_BUF, /* uart tod tx buffer half full interrupt */
FAL_PTP_INTR_RX_BUF, /* uart tod rx buffer half full interrupt */
FAL_PTP_INTR_PPS_OUT, /* PPS output interrupt */
FAL_PTP_INTR_PPS_IN, /* PPS input interrupt */
FAL_PTP_INTR_10MS, /* each 10ms interrupt */
FAL_PTP_INTR_TRIG0, /* trigger0 interrupt */
FAL_PTP_INTR_TRIG1, /* trigger1 interrupt */
FAL_PTP_INTR_CAP0, /* capture0 interrupt */
FAL_PTP_INTR_CAP1 /* capture1 interrupt */
};
typedef struct {
a_uint32_t intr_mask;
a_uint32_t intr_status;
} fal_ptp_interrupt_t;
sw_error_t
fal_ptp_config_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_config_t *config);
sw_error_t
fal_ptp_config_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_config_t *config);
sw_error_t
fal_ptp_reference_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_reference_clock_t ref_clock);
sw_error_t
fal_ptp_reference_clock_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_reference_clock_t *ref_clock);
sw_error_t
fal_ptp_rx_timestamp_mode_set(a_uint32_t dev_id,
a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t ts_mode);
sw_error_t
fal_ptp_rx_timestamp_mode_get(a_uint32_t dev_id,
a_uint32_t port_id, fal_ptp_rx_timestamp_mode_t *ts_mode);
sw_error_t
fal_ptp_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_direction_t direction,
fal_ptp_pkt_info_t *pkt_info,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_pkt_timestamp_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_pkt_timestamp_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_grandmaster_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_grandmaster_mode_t *gm_mode);
sw_error_t
fal_ptp_grandmaster_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_grandmaster_mode_t *gm_mode);
sw_error_t
fal_ptp_rtc_time_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_rtc_time_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_rtc_time_clear(a_uint32_t dev_id, a_uint32_t port_id);
sw_error_t
fal_ptp_rtc_adjtime_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_rtc_adjfreq_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_rtc_adjfreq_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_link_delay_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_link_delay_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_time_t *time);
sw_error_t
fal_ptp_security_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_security_t *sec);
sw_error_t
fal_ptp_security_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_security_t *sec);
sw_error_t
fal_ptp_pps_signal_control_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_pps_signal_control_t *sig_control);
sw_error_t
fal_ptp_pps_signal_control_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_pps_signal_control_t *sig_control);
sw_error_t
fal_ptp_rx_crc_recalc_enable(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t status);
sw_error_t
fal_ptp_rx_crc_recalc_status_get(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t *status);
sw_error_t
fal_ptp_asym_correction_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_asym_correction_t *asym_cf);
sw_error_t
fal_ptp_asym_correction_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_asym_correction_t* asym_cf);
sw_error_t
fal_ptp_output_waveform_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_output_waveform_t *waveform);
sw_error_t
fal_ptp_output_waveform_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_output_waveform_t *waveform);
sw_error_t
fal_ptp_rtc_time_snapshot_enable(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t status);
sw_error_t
fal_ptp_rtc_time_snapshot_status_get(a_uint32_t dev_id, a_uint32_t port_id,
a_bool_t *status);
sw_error_t
fal_ptp_increment_sync_from_clock_enable(a_uint32_t dev_id,
a_uint32_t port_id, a_bool_t status);
sw_error_t
fal_ptp_increment_sync_from_clock_status_get(a_uint32_t dev_id,
a_uint32_t port_id, a_bool_t *status);
sw_error_t
fal_ptp_tod_uart_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_tod_uart_t *tod_uart);
sw_error_t
fal_ptp_tod_uart_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_tod_uart_t *tod_uart);
sw_error_t
fal_ptp_enhanced_timestamp_engine_set(a_uint32_t dev_id,
a_uint32_t port_id, fal_ptp_direction_t direction,
fal_ptp_enhanced_ts_engine_t *ts_engine);
sw_error_t
fal_ptp_enhanced_timestamp_engine_get(a_uint32_t dev_id,
a_uint32_t port_id, fal_ptp_direction_t direction,
fal_ptp_enhanced_ts_engine_t *ts_engine);
sw_error_t
fal_ptp_trigger_set(a_uint32_t dev_id, a_uint32_t port_id,
a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
sw_error_t
fal_ptp_trigger_get(a_uint32_t dev_id, a_uint32_t port_id,
a_uint32_t trigger_id, fal_ptp_trigger_t *triger);
sw_error_t
fal_ptp_capture_set(a_uint32_t dev_id, a_uint32_t port_id,
a_uint32_t capture_id, fal_ptp_capture_t *capture);
sw_error_t
fal_ptp_capture_get(a_uint32_t dev_id, a_uint32_t port_id,
a_uint32_t capture_id, fal_ptp_capture_t *capture);
sw_error_t
fal_ptp_interrupt_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_interrupt_t *interrupt);
sw_error_t
fal_ptp_interrupt_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_ptp_interrupt_t *interrupt);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_PTP_H_ */
/**
* @}
*/

344
feeds/ipq807x/qca-ssdk/src/include/fal/fal_qm.h
View File

@@ -1,344 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_qos FAL_QM
* @{
*/
#ifndef _FAL_QM_H_
#define _FAL_QM_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef enum {
FAL_AC_QUEUE = 0,
FAL_AC_GROUP
} fal_ac_type_t;
typedef struct {
fal_ac_type_t type;
a_uint32_t obj_id;
} fal_ac_obj_t;
typedef struct {
a_bool_t ac_en; /* 0 for disable and 1 for enable*/
a_bool_t ac_fc_en; /* ac for flow control packets */
} fal_ac_ctrl_t;
typedef struct {
a_uint16_t prealloc_buffer; /* guareented buffer number */
a_uint16_t total_buffer; /* total buffer number */
} fal_ac_group_buffer_t;
typedef struct {
a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */
a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */
a_uint16_t green_max;
a_uint16_t green_min_off; /*gap between green max and green min*/
a_uint16_t yel_max_off; /*gap between green max and yel max*/
a_uint16_t yel_min_off; /*gap between green max and yel min*/
a_uint16_t red_max_off; /*gap between green max and red max*/
a_uint16_t red_min_off; /*gap between green max and red min*/
a_uint16_t green_resume_off; /* green resume offset */
a_uint16_t yel_resume_off; /* yellow resume offset */
a_uint16_t red_resume_off; /* red resume offset */
} fal_ac_static_threshold_t;
typedef struct {
a_bool_t color_enable; /* 1 for color aware and 0 for color-blind */
a_bool_t wred_enable; /* 1 for wred and 0 for tail drop */
a_uint8_t shared_weight; /* weight in the shared group */
a_uint16_t green_min_off; /*gap between green max and green min*/
a_uint16_t yel_max_off; /*gap between green max and yel max*/
a_uint16_t yel_min_off; /*gap between green max and yel min*/
a_uint16_t red_max_off; /*gap between green max and red max*/
a_uint16_t red_min_off; /*gap between green max and red min*/
a_uint16_t green_resume_off; /* green resume offset */
a_uint16_t yel_resume_off; /* yellow resume offset */
a_uint16_t red_resume_off; /* red resume offset */
a_uint16_t ceiling; /*shared ceiling*/
} fal_ac_dynamic_threshold_t;
typedef struct {
a_uint8_t src_profile; /* queue source profile */
a_bool_t service_code_en;
a_uint16_t service_code;
a_bool_t cpu_code_en;
a_uint16_t cpu_code;
fal_port_t dst_port; /* destination physical or VP port */
} fal_ucast_queue_dest_t;
#define FAL_QM_DROP_ITEMS 6
typedef struct {
a_uint32_t tx_packets;
a_uint64_t tx_bytes;
a_uint32_t pending_buff_num;
a_uint32_t drop_packets[FAL_QM_DROP_ITEMS];
a_uint64_t drop_bytes[FAL_QM_DROP_ITEMS];
} fal_queue_stats_t;
enum {
FUNC_UCAST_HASH_MAP_SET = 0,
FUNC_AC_DYNAMIC_THRESHOLD_GET,
FUNC_UCAST_QUEUE_BASE_PROFILE_GET,
FUNC_PORT_MCAST_PRIORITY_CLASS_GET,
FUNC_AC_DYNAMIC_THRESHOLD_SET,
FUNC_AC_PREALLOC_BUFFER_SET,
FUNC_UCAST_DEFAULT_HASH_GET,
FUNC_UCAST_DEFAULT_HASH_SET,
FUNC_AC_QUEUE_GROUP_GET,
FUNC_AC_CTRL_GET,
FUNC_AC_PREALLOC_BUFFER_GET,
FUNC_PORT_MCAST_PRIORITY_CLASS_SET,
FUNC_UCAST_HASH_MAP_GET,
FUNC_AC_STATIC_THRESHOLD_SET,
FUNC_AC_QUEUE_GROUP_SET,
FUNC_AC_GROUP_BUFFER_GET,
FUNC_MCAST_CPU_CODE_CLASS_GET,
FUNC_AC_CTRL_SET,
FUNC_UCAST_PRIORITY_CLASS_GET,
FUNC_QUEUE_FLUSH,
FUNC_MCAST_CPU_CODE_CLASS_SET,
FUNC_UCAST_PRIORITY_CLASS_SET,
FUNC_AC_STATIC_THRESHOLD_GET,
FUNC_UCAST_QUEUE_BASE_PROFILE_SET,
FUNC_AC_GROUP_BUFFER_SET,
FUNC_QUEUE_COUNTER_CLEANUP,
FUNC_QUEUE_COUNTER_GET,
FUNC_QUEUE_COUNTER_CTRL_GET,
FUNC_QUEUE_COUNTER_CTRL_SET,
FUNC_QM_ENQUEUE_CTRL_GET,
FUNC_QM_ENQUEUE_CTRL_SET,
FUNC_QM_PORT_SRCPROFILE_GET,
FUNC_QM_PORT_SRCPROFILE_SET,
};
sw_error_t
fal_ac_ctrl_set(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
fal_ac_ctrl_t *cfg);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_ctrl_get(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
fal_ac_ctrl_t *cfg);
#endif
sw_error_t
fal_ac_prealloc_buffer_set(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
a_uint16_t num);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_prealloc_buffer_get(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
a_uint16_t *num);
#endif
sw_error_t
fal_ac_queue_group_set(
a_uint32_t dev_id,
a_uint32_t queue_id,
a_uint8_t group_id);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_queue_group_get(
a_uint32_t dev_id,
a_uint32_t queue_id,
a_uint8_t *group_id);
#endif
sw_error_t
fal_ac_static_threshold_set(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
fal_ac_static_threshold_t *cfg);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_static_threshold_get(
a_uint32_t dev_id,
fal_ac_obj_t *obj,
fal_ac_static_threshold_t *cfg);
#endif
sw_error_t
fal_ac_dynamic_threshold_set(
a_uint32_t dev_id,
a_uint32_t queue_id,
fal_ac_dynamic_threshold_t *cfg);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_dynamic_threshold_get(
a_uint32_t dev_id,
a_uint32_t queue_id,
fal_ac_dynamic_threshold_t *cfg);
#endif
sw_error_t
fal_ac_group_buffer_set(
a_uint32_t dev_id,
a_uint8_t group_id,
fal_ac_group_buffer_t *cfg);
#ifndef IN_QM_MINI
sw_error_t
fal_ac_group_buffer_get(
a_uint32_t dev_id,
a_uint8_t group_id,
fal_ac_group_buffer_t *cfg);
#endif
sw_error_t
fal_ucast_queue_base_profile_set(
a_uint32_t dev_id,
fal_ucast_queue_dest_t *queue_dest,
a_uint32_t queue_base, a_uint8_t profile);
#ifndef IN_QM_MINI
sw_error_t
fal_ucast_queue_base_profile_get(
a_uint32_t dev_id,
fal_ucast_queue_dest_t *queue_dest,
a_uint32_t *queue_base, a_uint8_t *profile);
sw_error_t
fal_ucast_priority_class_set(
a_uint32_t dev_id,
a_uint8_t profile,
a_uint8_t priority,
a_uint8_t class);
sw_error_t
fal_ucast_priority_class_get(
a_uint32_t dev_id,
a_uint8_t profile,
a_uint8_t priority,
a_uint8_t *class);
sw_error_t
fal_ucast_hash_map_set(
a_uint32_t dev_id,
a_uint8_t profile,
a_uint8_t rss_hash,
a_int8_t queue_hash);
sw_error_t
fal_ucast_hash_map_get(
a_uint32_t dev_id,
a_uint8_t profile,
a_uint8_t rss_hash,
a_int8_t *queue_hash);
sw_error_t
fal_mcast_cpu_code_class_set(
a_uint32_t dev_id,
a_uint8_t cpu_code,
a_uint8_t queue_class);
sw_error_t
fal_mcast_cpu_code_class_get(
a_uint32_t dev_id,
a_uint8_t cpu_code,
a_uint8_t *queue_class);
sw_error_t
fal_port_mcast_priority_class_set(
a_uint32_t dev_id,
fal_port_t port,
a_uint8_t priority,
a_uint8_t queue_class);
sw_error_t
fal_port_mcast_priority_class_get(
a_uint32_t dev_id,
fal_port_t port,
a_uint8_t priority,
a_uint8_t *queue_class);
#endif
sw_error_t
fal_queue_flush(
a_uint32_t dev_id,
fal_port_t port,
a_uint16_t queue_id);
#ifndef IN_QM_MINI
sw_error_t
fal_ucast_default_hash_set(
a_uint32_t dev_id,
a_uint8_t hash_value);
sw_error_t
fal_ucast_default_hash_get(
a_uint32_t dev_id,
a_uint8_t *hash_value);
sw_error_t
fal_queue_counter_ctrl_set(a_uint32_t dev_id, a_bool_t cnt_en);
sw_error_t
fal_queue_counter_ctrl_get(a_uint32_t dev_id, a_bool_t *cnt_en);
sw_error_t
fal_queue_counter_get(a_uint32_t dev_id, a_uint32_t queue_id, fal_queue_stats_t *info);
sw_error_t
fal_queue_counter_cleanup(a_uint32_t dev_id, a_uint32_t queue_id);
#endif
sw_error_t
fal_qm_enqueue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable);
#ifndef IN_QM_MINI
sw_error_t
fal_qm_enqueue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable);
sw_error_t
fal_qm_port_source_profile_set(
a_uint32_t dev_id,
fal_port_t port,
a_uint32_t src_profile);
sw_error_t
fal_qm_port_source_profile_get(
a_uint32_t dev_id,
fal_port_t port,
a_uint32_t *src_profile);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _PORT_QM_H_ */
/**
* @}
*/

442
feeds/ipq807x/qca-ssdk/src/include/fal/fal_qos.h
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@@ -1,442 +0,0 @@
/*
* Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_qos FAL_QOS
* @{
*/
#ifndef _FAL_QOS_H_
#define _FAL_QOS_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This enum defines traffic scheduling mode.
*/
typedef enum {
FAL_SCH_SP_MODE = 0, /**< strict priority scheduling mode */
FAL_SCH_WRR_MODE, /**< weight round robin scheduling mode*/
FAL_SCH_MIX_MODE, /**< sp and wrr mixed scheduling mode */
FAL_SCH_MIX_PLUS_MODE, /**< sp and wrr mixed plus scheduling mode */
FAL_SCH_MODE_BUTT
}
fal_sch_mode_t;
/**
@brief This enum defines qos assignment mode.
*/
typedef enum
{
FAL_QOS_DA_MODE = 0, /**< qos assignment based on destination mac address*/
FAL_QOS_UP_MODE, /**< qos assignment based on 802.1p field in vlan tag*/
FAL_QOS_DSCP_MODE, /**< qos assignment based on dscp field in ip header */
FAL_QOS_PORT_MODE, /**< qos assignment based on port */
FAL_QOS_FLOW_MODE, /**< qos assignment based on flow */
FAL_QOS_MODE_BUTT
} fal_qos_mode_t;
typedef struct {
a_uint8_t pcp_group; /* 0: group 0 1: group 1 */
a_uint8_t dscp_group;
a_uint8_t flow_group;
} fal_qos_group_t;
typedef struct {
a_uint8_t pcp_pri;
a_uint8_t dscp_pri;
a_int8_t preheader_pri;
a_uint8_t flow_pri;
a_uint8_t acl_pri;
a_uint8_t post_acl_pri;
a_bool_t pcp_pri_force;
a_bool_t dscp_pri_force;
} fal_qos_pri_precedence_t;
typedef struct {
a_bool_t pcp_change_en;
a_bool_t dei_chage_en;
a_bool_t dscp_change_en;
} fal_qos_remark_enable_t;
typedef struct {
a_uint8_t internal_pcp;
a_uint8_t internal_dei;
a_uint8_t internal_pri;
a_uint8_t internal_dscp;
a_uint8_t internal_dp;
a_uint8_t dscp_mask;
a_bool_t dscp_en;
a_bool_t pcp_en;
a_bool_t dei_en;
a_bool_t pri_en;
a_bool_t dp_en;
a_uint8_t qos_prec; /* resolution precedence */
} fal_qos_cosmap_t;
typedef enum {
FAL_DRR_IPG_PREAMBLE_FRAME_CRC = 0, /* IPG + Preamble + Frame + CRC */
FAL_DRR_FRAME_CRC, /* Frame + CRC */
FAL_DRR_L3_EXCLUDE_CRC /* after Ethernet type excude CRC*/
} fal_qos_drr_frame_mode_t;
typedef struct {
a_uint8_t sp_id; /* SP id L0:0~63 L1:0~7 */
a_uint8_t e_pri; /*SP priority for E path:0~7 low to high */
a_uint8_t c_pri; /* SP priority for C path: 0~7 low to high */
a_uint8_t c_drr_id; /*C DRR ID L0:0~159 L1:0~35*/
a_uint8_t e_drr_id; /*E DRR ID L0:0~159 L1:0~35*/
a_uint16_t e_drr_wt; /* DRR weight in E DRR: 0~1023 */
a_uint16_t c_drr_wt; /* DRR weight in C DRR: 0~1023 */
a_uint8_t c_drr_unit; /* 0:byte based; 1:packet based */
a_uint8_t e_drr_unit; /* 0:byte based; 1:packet based */
fal_qos_drr_frame_mode_t drr_frame_mode;
} fal_qos_scheduler_cfg_t;
typedef struct {
a_uint32_t en_scheduler_port_bmp; /* port bitmap of en-scheduler */
a_uint32_t en_scheduler_port; /* port of en-scheduler */
a_uint32_t de_scheduler_port; /* port of de-shceduler */
} fal_port_scheduler_cfg_t;
typedef enum {
FAL_QUEUE_SCHEDULER_LEVEL0 = 0,
FAL_QUEUE_SCHEDULER_LEVEL1,
} fal_queue_scheduler_level_t;
typedef struct {
a_uint32_t bmp[10];
} fal_queue_bmp_t;
enum {
FUNC_QOS_PORT_PRI_SET = 0,
FUNC_QOS_PORT_PRI_GET,
FUNC_QOS_COSMAP_PCP_GET,
FUNC_QUEUE_SCHEDULER_SET,
FUNC_QUEUE_SCHEDULER_GET,
FUNC_PORT_QUEUES_GET,
FUNC_QOS_COSMAP_PCP_SET,
FUNC_QOS_PORT_REMARK_GET,
FUNC_QOS_COSMAP_DSCP_GET,
FUNC_QOS_COSMAP_FLOW_SET,
FUNC_QOS_PORT_GROUP_SET,
FUNC_RING_QUEUE_MAP_SET,
FUNC_QOS_COSMAP_DSCP_SET,
FUNC_QOS_PORT_REMARK_SET,
FUNC_QOS_COSMAP_FLOW_GET,
FUNC_QOS_PORT_GROUP_GET,
FUNC_RING_QUEUE_MAP_GET,
FUNC_TDM_TICK_NUM_SET,
FUNC_TDM_TICK_NUM_GET,
FUNC_PORT_SCHEDULER_CFG_SET,
FUNC_PORT_SCHEDULER_CFG_GET,
FUNC_SCHEDULER_DEQUEUE_CTRL_GET,
FUNC_SCHEDULER_DEQUEUE_CTRL_SET,
FUNC_QOS_PORT_MODE_PRI_GET,
FUNC_QOS_PORT_MODE_PRI_SET,
FUNC_QOS_PORT_SCHEDULER_CFG_RESET,
FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET,
};
typedef struct {
a_uint16_t ucastq_start;
a_uint16_t ucastq_num;
a_uint16_t mcastq_start;
a_uint16_t mcastq_num;
a_uint16_t l0sp_start;
a_uint16_t l0sp_num;
a_uint16_t l0cdrr_start;
a_uint16_t l0cdrr_num;
a_uint16_t l0edrr_start;
a_uint16_t l0edrr_num;
a_uint16_t l1sp_start;
a_uint16_t l1sp_num;
a_uint16_t l1cdrr_start;
a_uint16_t l1cdrr_num;
a_uint16_t l1edrr_start;
a_uint16_t l1edrr_num;
} fal_portscheduler_resource_t;
#define FAL_DOT1P_MIN 0
#define FAL_DOT1P_MAX 7
#define FAL_DSCP_MIN 0
#define FAL_DSCP_MAX 63
#ifndef IN_QOS_MINI
sw_error_t
fal_qos_sch_mode_set(a_uint32_t dev_id,
fal_sch_mode_t mode, const a_uint32_t weight[]);
sw_error_t
fal_qos_sch_mode_get(a_uint32_t dev_id,
fal_sch_mode_t * mode, a_uint32_t weight[]);
sw_error_t
fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * number);
sw_error_t
fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
sw_error_t
fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * number);
sw_error_t
fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * number);
sw_error_t
fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
fal_queue_t queue);
sw_error_t
fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
fal_queue_t * queue);
sw_error_t
fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
fal_queue_t queue);
sw_error_t
fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
fal_queue_t * queue);
#endif
sw_error_t
fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * number);
sw_error_t
fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_bool_t enable);
sw_error_t
fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * number);
sw_error_t
fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * number);
#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_bool_t * enable);
sw_error_t
fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_uint32_t pri);
sw_error_t
fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_uint32_t * pri);
sw_error_t
fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t up);
sw_error_t
fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * up);
sw_error_t
fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_sch_mode_t mode, const a_uint32_t weight[]);
sw_error_t
fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sch_mode_t * mode, a_uint32_t weight[]);
sw_error_t
fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t spri);
sw_error_t
fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * spri);
sw_error_t
fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t cpri);
sw_error_t
fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * cpri);
sw_error_t
fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t* enable);
sw_error_t
fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t* enable);
sw_error_t
fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
sw_error_t
fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
#endif
sw_error_t
fal_qos_port_group_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_group_t *group);
sw_error_t
fal_qos_port_group_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_group_t *group);
sw_error_t
fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_pri_precedence_t *pri);
sw_error_t
fal_qos_port_pri_precedence_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_pri_precedence_t *pri);
sw_error_t
fal_qos_port_remark_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_remark_enable_t *remark);
sw_error_t
fal_qos_port_remark_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_remark_enable_t *remark);
sw_error_t
fal_qos_cosmap_pcp_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_qos_cosmap_pcp_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t pcp, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_qos_cosmap_flow_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint16_t flow, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_qos_cosmap_flow_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint16_t flow, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_qos_cosmap_dscp_set(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_qos_cosmap_dscp_get(a_uint32_t dev_id, a_uint8_t group_id,
a_uint8_t dscp, fal_qos_cosmap_t *cosmap);
sw_error_t
fal_queue_scheduler_set(a_uint32_t dev_id,
a_uint32_t node_id, fal_queue_scheduler_level_t level,
fal_port_t port_id,
fal_qos_scheduler_cfg_t *scheduler_cfg);
sw_error_t
fal_queue_scheduler_get(a_uint32_t dev_id,
a_uint32_t node_id, fal_queue_scheduler_level_t level,
fal_port_t *port_id,
fal_qos_scheduler_cfg_t *scheduler_cfg);
sw_error_t
fal_edma_ring_queue_map_get(a_uint32_t dev_id,
a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
sw_error_t
fal_edma_ring_queue_map_set(a_uint32_t dev_id,
a_uint32_t ring_id, fal_queue_bmp_t *queue_bmp);
sw_error_t
fal_port_queues_get(a_uint32_t dev_id,
fal_port_t port_id, fal_queue_bmp_t *queue_bmp);
sw_error_t
fal_scheduler_dequeue_ctrl_set(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t enable);
sw_error_t
fal_scheduler_dequeue_ctrl_get(a_uint32_t dev_id, a_uint32_t queue_id, a_bool_t *enable);
sw_error_t
fal_port_scheduler_cfg_reset(
a_uint32_t dev_id,
fal_port_t port_id);
sw_error_t
fal_port_scheduler_resource_get(
a_uint32_t dev_id,
fal_port_t port_id,
fal_portscheduler_resource_t *cfg);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _PORT_QOS_H_ */
/**
* @}
*/

234
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@@ -1,234 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_rate FAL_RATE
* @{
*/
#ifndef _FAL_RATE_H_
#define _FAL_RATE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This enum defines storm type
*/
typedef enum {
FAL_UNICAST_STORM = 0, /**< storm caused by unknown unicast packets */
FAL_MULTICAST_STORM, /**< storm caused by unknown multicast packets */
FAL_BROADCAST_STORM, /**< storm caused by broadcast packets */
FAL_STORM_TYPE_BUTT
}
fal_storm_type_t;
sw_error_t
fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * speed,
a_bool_t enable);
sw_error_t
fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * speed,
a_bool_t * enable);
sw_error_t
fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * speed, a_bool_t enable);
sw_error_t
fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * speed, a_bool_t * enable);
sw_error_t
fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * speed, a_bool_t enable);
sw_error_t
fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * speed, a_bool_t * enable);
sw_error_t
fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
fal_storm_type_t frame_type, a_bool_t enable);
sw_error_t
fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
fal_storm_type_t frame_type,
a_bool_t * enable);
sw_error_t
fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * rate);
sw_error_t
fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * rate);
typedef enum
{
FAL_RATE_MI_100US = 0,
FAL_RATE_MI_1MS,
FAL_RATE_MI_10MS,
FAL_RATE_MI_100MS,
} fal_rate_mt_t;
typedef struct
{
fal_traffic_unit_t meter_unit;
a_uint32_t cir;
a_uint32_t eir;
a_uint32_t cbs;
a_uint32_t ebs;
} fal_egress_shaper_t;
#define FAL_INGRESS_POLICING_TCP_CTRL 0x2
#define FAL_INGRESS_POLICING_MANAGEMENT 0x4
#define FAL_INGRESS_POLICING_BROAD 0x8
#define FAL_INGRESS_POLICING_UNK_UNI 0x10
#define FAL_INGRESS_POLICING_UNK_MUL 0x20
#define FAL_INGRESS_POLICING_UNI 0x40
#define FAL_INGRESS_POLICING_MUL 0x80
typedef struct
{
a_bool_t c_enable;
a_bool_t e_enable;
a_bool_t combine_mode;
fal_traffic_unit_t meter_unit;
a_bool_t color_mode;
a_bool_t couple_flag;
a_bool_t deficit_en;
a_uint32_t cir;
a_uint32_t eir;
a_uint32_t cbs;
a_uint32_t ebs;
a_uint32_t c_rate_flag;
a_uint32_t e_rate_flag;
fal_rate_mt_t c_meter_interval;
fal_rate_mt_t e_meter_interval;
} fal_port_policer_t;
typedef struct
{
a_bool_t counter_mode;
fal_traffic_unit_t meter_unit;
fal_rate_mt_t meter_interval;
a_bool_t color_mode;
a_bool_t couple_flag;
a_bool_t deficit_en;
a_uint32_t cir;
a_uint32_t eir;
a_uint32_t cbs;
a_uint32_t ebs;
a_uint32_t counter_high;
a_uint32_t counter_low;
} fal_acl_policer_t;
sw_error_t
fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_policer_t * policer);
sw_error_t
fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_policer_t * policer);
sw_error_t
fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, fal_egress_shaper_t * shaper);
sw_error_t
fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable, fal_egress_shaper_t * shaper);
sw_error_t
fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_bool_t enable,
fal_egress_shaper_t * shaper);
sw_error_t
fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_bool_t * enable,
fal_egress_shaper_t * shaper);
sw_error_t
fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
fal_acl_policer_t * policer);
sw_error_t
fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
fal_acl_policer_t * policer);
sw_error_t
fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t number);
sw_error_t
fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t *number);
sw_error_t
fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
sw_error_t
fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t* enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_RATE_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_reg_access.h
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@@ -1,97 +0,0 @@
/*
* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*qca808x_start*/
/**
* @defgroup fal_reg_access FAL_REG_ACCESS
* @{
*/
#ifndef _FAL_REG_ACCESS_H_
#define _FAL_REG_ACCESS_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
sw_error_t
fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t reg, a_uint16_t * value);
sw_error_t
fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t reg, a_uint16_t value);
/*qca808x_end*/
sw_error_t
fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
fal_psgmii_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
fal_psgmii_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
a_uint32_t bit_offset, a_uint32_t field_len,
a_uint8_t value[], a_uint32_t value_len);
sw_error_t
fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
a_uint32_t bit_offset, a_uint32_t field_len,
const a_uint8_t value[], a_uint32_t value_len);
sw_error_t
fal_debug_reg_dump(a_uint32_t dev_id, fal_debug_reg_dump_t *reg_dump);
sw_error_t
fal_reg_dump(a_uint32_t dev_id, a_uint32_t reg_idx,fal_reg_dump_t *reg_dump);
sw_error_t
fal_debug_psgmii_self_test(a_uint32_t dev_id, a_bool_t enable,
a_uint32_t times, a_uint32_t *result);
sw_error_t
fal_phy_dump(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t idx, fal_phy_dump_t * phy_dump);
sw_error_t
fal_uniphy_reg_get(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
a_uint8_t value[], a_uint32_t value_len);
sw_error_t
fal_uniphy_reg_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t reg_addr,
a_uint8_t value[], a_uint32_t value_len);
/*qca808x_start*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_REG_ACCESS_H_ */
/**
* @}
*/
/*qca808x_end*/

90
feeds/ipq807x/qca-ssdk/src/include/fal/fal_rfs.h
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@@ -1,90 +0,0 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_rfs FAL_RFS
* @{
*/
#ifndef _FAL_RFS_H_
#define _FAL_RFS_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#if 0
typedef struct
{
u8 addr[6];
u16 fid;
u8 load_balance;
} ssdk_fdb_rfs_t;
typedef struct
{
u8 mac_addr[6];
u32 ip4_addr;
u32 vid;
u8 load_balance;
} ssdk_ip4_rfs_t;
typedef struct
{
u8 mac_addr[6];
u32 ip6_addr[4];
u32 vid;
u8 load_balance;
} ssdk_ip6_rfs_t;
int ssdk_rfs_ipct_rule_set(
__be32 ip_src, __be32 ip_dst,
__be16 sport, __be16 dport, uint8_t proto,
u16 loadbalance, bool action);
int ssdk_rfs_mac_rule_set(ssdk_fdb_rfs_t *rfs);
int ssdk_rfs_mac_rule_del(ssdk_fdb_rfs_t *rfs);
int
ssdk_ip_rfs_ip4_rule_set(ssdk_ip4_rfs_t * rfs);
int
ssdk_ip_rfs_ip6_rule_set(ssdk_ip6_rfs_t * rfs);
int
ssdk_ip_rfs_ip4_rule_del(ssdk_ip4_rfs_t * rfs);
int
ssdk_ip_rfs_ip6_rule_del(ssdk_ip6_rfs_t * rfs);
#endif
int ssdk_rfs_mac_rule_set(u16 vid, u8* mac, u8 ldb, int is_set);
int ssdk_rfs_ip4_rule_set(u16 vid, u32 ip, u8* mac, u8 ldb, int is_set);
int ssdk_rfs_ip6_rule_set(u16 vid, u8* ip, u8* mac, u8 ldb, int is_set);
int ssdk_rfs_ipct_rule_set(
__be32 ip_src, __be32 ip_dst,
__be16 sport, __be16 dport, uint8_t proto,
u16 loadbalance, bool action);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_RFS_H_ */
/**
* @}
*/

77
feeds/ipq807x/qca-ssdk/src/include/fal/fal_rss_hash.h
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@@ -1,77 +0,0 @@
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_gen FAL_RSS_HASH
* @{
*/
#ifndef _FAL_RSS_HASH_H_
#define _FAL_RSS_HASH_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
#define FAL_RSS_HASH_API_LOCK
#define FAL_RSS_HASH_API_UNLOCK
#else
#define FAL_RSS_HASH_API_LOCK
#define FAL_RSS_HASH_API_UNLOCK
#endif
typedef enum
{
FAL_RSS_HASH_IPV4V6 = 0,
FAL_RSS_HASH_IPV4ONLY = 1,
FAL_RSS_HASH_IPV6ONLY = 2,
} fal_rss_hash_mode_t;
typedef struct
{
a_uint32_t hash_mask; /* final hash value bits */
a_bool_t hash_fragment_mode; /* enable fragment mode or not */
a_uint32_t hash_seed; /* rss hash seed value */
a_uint32_t hash_sip_mix; /* source ip hash mix */
a_uint32_t hash_dip_mix; /* dest ip hash mix */
a_uint8_t hash_protocol_mix; /* L4 protocol hash mix */
a_uint8_t hash_sport_mix; /* L4 source port hash mix */
a_uint8_t hash_dport_mix; /* L4 dest port hash mix */
a_uint32_t hash_fin_inner; /* hash fin inner mix */
a_uint32_t hash_fin_outer; /* hash fin outer mix */
} fal_rss_hash_config_t;
enum {
FUNC_RSS_HASH_CONFIG_SET = 0,
FUNC_RSS_HASH_CONFIG_GET,
};
sw_error_t
fal_rss_hash_config_set(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
sw_error_t
fal_rss_hash_config_get(a_uint32_t dev_id, fal_rss_hash_mode_t mode, fal_rss_hash_config_t * config);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_RSS_HASH_H_ */
/**
* @}
*/

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/*
* Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_sec FAL_SEC
* @{
*/
#ifndef _FAL_SEC_H_
#define _FAL_SEC_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/* Exception: L2 */
#define FAL_SEC_EXP_UNKNOWN_L2_PROT 1
#define FAL_SEC_EXP_PPPOE_WRONG_VER_TYPE 2
#define FAL_SEC_EXP_PPPOE_WRONG_CODE 3
#define FAL_SEC_EXP_PPPOE_UNSUPPORTED_PPP_PROT 4
/* Exception: IPv4 */
#define FAL_SEC_EXP_IPV4_WRONG_VER 5
#define FAL_SEC_EXP_IPV4_SMALL_IHL 6
#define FAL_SEC_EXP_IPV4_WITH_OPTION 7
#define FAL_SEC_EXP_IPV4_HDR_INCOMPLETE 8
#define FAL_SEC_EXP_IPV4_BAD_TOTAL_LEN 9
#define FAL_SEC_EXP_IPV4_DATA_INCOMPLETE 10
#define FAL_SEC_EXP_IPV4_FRAG 11
#define FAL_SEC_EXP_IPV4_PING_OF_DEATH 12
#define FAL_SEC_EXP_IPV4_SNALL_TTL 13
#define FAL_SEC_EXP_IPV4_UNK_IP_PROT 14
#define FAL_SEC_EXP_IPV4_CHECKSUM_ERR 15
#define FAL_SEC_EXP_IPV4_INV_SIP 16
#define FAL_SEC_EXP_IPV4_INV_DIP 17
#define FAL_SEC_EXP_IPV4_LAND_ATTACK 18
#define FAL_SEC_EXP_IPV4_AH_HDR_INCOMPLETE 19
#define FAL_SEC_EXP_IPV4_AH_HDR_CROSS_BORDER 20
#define FAL_SEC_EXP_IPV4_ESP_HDR_INCOMPLETE 21
/* Exception: IPv6 */
#define FAL_SEC_EXP_IPV6_WRONG_VER 22
#define FAL_SEC_EXP_IPV6_HDR_INCOMPLETE 23
#define FAL_SEC_EXP_IPV6_BAD_PAYLOAD_LEN 24
#define FAL_SEC_EXP_IPV6_DATA_INCOMPLETE 25
#define FAL_SEC_EXP_IPV6_WITH_EXT_HDR 26
#define FAL_SEC_EXP_IPV6_SMALL_HOP_LIMIT 27
#define FAL_SEC_EXP_IPV6_INV_SIP 28
#define FAL_SEC_EXP_IPV6_INV_DIP 29
#define FAL_SEC_EXP_IPV6_LAND_ATTACK 30
#define FAL_SEC_EXP_IPV6_FRAG 31
#define FAL_SEC_EXP_IPV6_PING_OF_DEATH 32
#define FAL_SEC_EXP_IPV6_WITH_MORE_EXT_HDR 33
#define FAL_SEC_EXP_IPV6_UNK_LAST_NEXT_HDR 34
#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_INCOMPLETE 35
#define FAL_SEC_EXP_IPV6_MOBILITY_HDR_CROSS_BORDER 36
#define FAL_SEC_EXP_IPV6_AH_HDR_INCOMPLETE 37
#define FAL_SEC_EXP_IPV6_AH_HDR_CROSS_BORDER 38
#define FAL_SEC_EXP_IPV6_ESP_HDR_INCOMPLETE 39
#define FAL_SEC_EXP_IPV6_ESP_HDR_CROSS_BORDER 40
#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_INCOMPLETE 41
#define FAL_SEC_EXP_IPV6_OTHER_EXT_HDR_CROSS_BORDER 42
/* Exception: L4 */
#define FAL_SEC_EXP_TCP_HDR_INCOMPLETE 43
#define FAL_SEC_EXP_TCP_HDR_CROSS_BORDER 44
#define FAL_SEC_EXP_TCP_SMAE_SP_DP 45
#define FAL_SEC_EXP_TCP_SMALL_DATA_OFFSET 46
#define FAL_SEC_EXP_TCP_FLAGS_0 47
#define FAL_SEC_EXP_TCP_FLAGS_1 48
#define FAL_SEC_EXP_TCP_FLAGS_2 49
#define FAL_SEC_EXP_TCP_FLAGS_3 50
#define FAL_SEC_EXP_TCP_FLAGS_4 51
#define FAL_SEC_EXP_TCP_FLAGS_5 52
#define FAL_SEC_EXP_TCP_FLAGS_6 53
#define FAL_SEC_EXP_TCP_FLAGS_7 54
#define FAL_SEC_EXP_TCP_CHECKSUM_ERR 55
#define FAL_SEC_EXP_UDP_HDR_INCOMPLETE 56
#define FAL_SEC_EXP_UDP_HDR_CROSS_BORDER 57
#define FAL_SEC_EXP_UDP_SMAE_SP_DP 58
#define FAL_SEC_EXP_UDP_BAD_LEN 59
#define FAL_SEC_EXP_UDP_DATA_INCOMPLETE 60
#define FAL_SEC_EXP_UDP_CHECKSUM_ERR 61
#define FAL_SEC_EXP_UDP_LITE_HDR_INCOMPLETE 62
#define FAL_SEC_EXP_UDP_LITE_HDR_CROSS_BORDER 63
#define FAL_SEC_EXP_UDP_LITE_SMAE_SP_DP 64
/* Other exception */
#define FAL_SEC_EXP_UDP_LITE_CSM_COV_1_TO_7 65
#define FAL_SEC_EXP_UDP_LITE_CSM_COV_TOO_LONG 66
#define FAL_SEC_EXP_UDP_LITE_CSM_COV_CROSS_BORDER 67
#define FAL_SEC_EXP_UDP_LITE_CHECKSUM_ERR 68
/**/
#define FAL_SEC_EXP_FAKE_L2_PROT_ERR 69
#define FAL_SEC_EXP_FAKE_MAC_HEADER_ERR 70
typedef enum {
/* define MAC layer related normalization items */
FAL_NORM_MAC_RESV_VID_CMD = 0,
FAL_NORM_MAC_INVALID_SRC_ADDR_CMD,
/* define IP layer related normalization items */
FAL_NORM_IP_INVALID_VER_CMD,
FAL_NROM_IP_SAME_ADDR_CMD,
FAL_NROM_IP_TTL_CHANGE_STATUS,
FAL_NROM_IP_TTL_VALUE,
/* define IP4 related normalization items */
FAL_NROM_IP4_INVALID_HL_CMD,
FAL_NROM_IP4_HDR_OPTIONS_CMD,
FAL_NROM_IP4_INVALID_DF_CMD,
FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD,
FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD,
FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD,
FAL_NROM_IP4_INVALID_SIP_CMD,
FAL_NROM_IP4_INVALID_DIP_CMD,
FAL_NROM_IP4_INVALID_CHKSUM_CMD,
FAL_NROM_IP4_INVALID_PL_CMD,
FAL_NROM_IP4_DF_CLEAR_STATUS,
FAL_NROM_IP4_IPID_RANDOM_STATUS,
FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE,
/* define IP4 related normalization items */
FAL_NROM_IP6_INVALID_PL_CMD,
FAL_NROM_IP6_INVALID_SIP_CMD,
FAL_NROM_IP6_INVALID_DIP_CMD,
/* define TCP related normalization items */
FAL_NROM_TCP_BLAT_CMD,
FAL_NROM_TCP_INVALID_HL_CMD,
FAL_NROM_TCP_INVALID_SYN_CMD,
FAL_NROM_TCP_SU_BLOCK_CMD,
FAL_NROM_TCP_SP_BLOCK_CMD,
FAL_NROM_TCP_SAP_BLOCK_CMD,
FAL_NROM_TCP_XMAS_SCAN_CMD,
FAL_NROM_TCP_NULL_SCAN_CMD,
FAL_NROM_TCP_SR_BLOCK_CMD,
FAL_NROM_TCP_SF_BLOCK_CMD,
FAL_NROM_TCP_SAR_BLOCK_CMD,
FAL_NROM_TCP_RST_SCAN_CMD,
FAL_NROM_TCP_SYN_WITH_DATA_CMD,
FAL_NROM_TCP_RST_WITH_DATA_CMD,
FAL_NROM_TCP_FA_BLOCK_CMD,
FAL_NROM_TCP_PA_BLOCK_CMD,
FAL_NROM_TCP_UA_BLOCK_CMD,
FAL_NROM_TCP_INVALID_CHKSUM_CMD,
FAL_NROM_TCP_INVALID_URGPTR_CMD,
FAL_NROM_TCP_INVALID_OPTIONS_CMD,
FAL_NROM_TCP_MIN_HDR_SIZE,
/* define UDP related normalization items */
FAL_NROM_UDP_BLAT_CMD,
FAL_NROM_UDP_INVALID_LEN_CMD,
FAL_NROM_UDP_INVALID_CHKSUM_CMD,
/* define ICMP related normalization items */
FAL_NROM_ICMP4_PING_PL_EXCEED_CMD,
FAL_NROM_ICMP6_PING_PL_EXCEED_CMD,
FAL_NROM_ICMP4_PING_FRAG_CMD,
FAL_NROM_ICMP6_PING_FRAG_CMD,
FAL_NROM_ICMP4_PING_MAX_PL_VALUE,
FAL_NROM_ICMP6_PING_MAX_PL_VALUE,
}
fal_norm_item_t;
typedef struct {
fal_fwd_cmd_t cmd; /* action for the exception */
a_bool_t deacclr_en; /* 0 for disable and 1 for disable */
a_bool_t l3route_only_en; /*host/network route 0: disable and 1: enable*/
a_bool_t l2fwd_only_en; /*l2 forward 0: disable and 1: enable*/
a_bool_t l3flow_en; /* 0 for disable and 1 for disable */
a_bool_t l2flow_en; /* 0 for disable and 1 for disable */
a_bool_t multicast_en; /* 0 for disable and 1 for disable */
} fal_l3_excep_ctrl_t;
typedef struct {
a_uint8_t small_ip4ttl; /* small ttl value checking */
a_uint8_t small_ip6hoplimit; /*small hoplimit value for check*/
} fal_l3_excep_parser_ctrl;
#define TCP_FLAGS_MAX 8
typedef struct {
a_uint8_t tcp_flags[TCP_FLAGS_MAX]; /*flag for exception*/
a_uint8_t tcp_flags_mask[TCP_FLAGS_MAX]; /*flag mask*/
} fal_l4_excep_parser_ctrl;
enum {
FUNC_SEC_L3_EXCEP_CTRL_SET = 0,
FUNC_SEC_L3_EXCEP_CTRL_GET,
FUNC_SEC_L3_EXCEP_PARSER_CTRL_SET,
FUNC_SEC_L3_EXCEP_PARSER_CTRL_GET,
FUNC_SEC_L4_EXCEP_PARSER_CTRL_SET,
FUNC_SEC_L4_EXCEP_PARSER_CTRL_GET,
};
sw_error_t
fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value);
sw_error_t
fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value);
sw_error_t
fal_sec_l3_excep_ctrl_set(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
sw_error_t
fal_sec_l3_excep_ctrl_get(a_uint32_t dev_id, a_uint32_t excep_type, fal_l3_excep_ctrl_t *ctrl);
sw_error_t
fal_sec_l3_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl);
sw_error_t
fal_sec_l3_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l3_excep_parser_ctrl *ctrl);
sw_error_t
fal_sec_l4_excep_parser_ctrl_set(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
sw_error_t
fal_sec_l4_excep_parser_ctrl_get(a_uint32_t dev_id, fal_l4_excep_parser_ctrl *ctrl);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_SEC_H_ */
/**
* @}
*/

137
feeds/ipq807x/qca-ssdk/src/include/fal/fal_servcode.h
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@@ -1,137 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_gen FAL_SERVCODE
* @{
*/
#ifndef _FAL_SERVCODE_H_
#define _FAL_SERVCODE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
#define FAL_SERVCODE_API_LOCK
#define FAL_SERVCODE_API_UNLOCK
#else
#define FAL_SERVCODE_API_LOCK
#define FAL_SERVCODE_API_UNLOCK
#endif
enum {
FLD_UPDATE_CAPWAP_EN = 0, /*only for IP197*/
FLD_UPDATE_DIRECTION, /*only for IP197*/
FLD_UPDATE_DEST_INFO,
FLD_UPDATE_SRC_INFO,
FLD_UPDATE_INT_PRI,
FLD_UPDATE_SERVICE_CODE,
FLD_UPDATE_HASH_FLOW_INDEX,
FLD_UPDATE_FAKE_L2_PROT_EN, /*only for IP197*/
};
enum {
IN_VLAN_TAG_FMT_CHECK_BYP = 0,
IN_VLAN_MEMBER_CHECK_BYP,
IN_VLAN_XLT_BYP,
MY_MAC_CHECK_BYP,
DIP_LOOKUP_BYP,
FLOW_LOOKUP_BYP = 5,
FLOW_ACTION_BYP,
ACL_BYP,
FAKE_MAC_HEADER_BYP,
SERVICE_CODE_BYP,
WRONG_PKT_FMT_L2_BYP = 10,
WRONG_PKT_FMT_L3_IPV4_BYP,
WRONG_PKT_FMT_L3_IPV6_BYP,
WRONG_PKT_FMT_L4_BYP,
FLOW_SERVICE_CODE_BYP,
ACL_SERVICE_CODE_BYP = 15,
FAKE_L2_PROTO_BYP,
PPPOE_TERMINATION_BYP,
DEFAULT_VLAN_BYP,
IN_VLAN_ASSIGN_FAIL_BYP = 24,
SOURCE_GUARD_BYP,
MRU_MTU_CHECK_BYP,
FLOW_SRC_CHECK_BYP,
FLOW_QOS_BYP,
EG_VLAN_MEMBER_CHECK_BYP = 32,
EG_VLAN_XLT_BYP,
EG_VLAN_TAG_FMT_CTRL_BYP,
FDB_LEARN_BYP = 35,
FDB_REFRESH_BYP,
L2_SOURCE_SEC_BYP,
MANAGEMENT_FWD_BYP,
BRIDGING_FWD_BYP,
IN_STP_FLTR_BYP = 40,
EG_STP_FLTR_BYP,
SOURCE_FLTR_BYP,
POLICER_BYP,
L2_PKT_EDIT_BYP,
L3_PKT_EDIT_BYP = 45,
ACL_POST_ROUTING_CHECK_BYP,
PORT_ISOLATION_BYP,
/* for cypress Qos bypass */
PRE_ACL_QOS_BYP,
POST_ACL_QOS_BYP,
DSCP_QOS_BYP,
PCP_QOS_BYP,
PREHEADER_QOS_BYP,
RX_VLAN_COUNTER_BYP = 64,
RX_COUNTER_BYP,
TX_VLAN_COUNTER_BYP,
TX_COUNTER_BYP,
};
typedef struct {
a_bool_t dest_port_valid; /* dest_port_id valid or not */
fal_port_t dest_port_id; /* destination physical port id:0-7 */
a_uint32_t bypass_bitmap[3]; /* refer to enum IN_VLAN_TAG_FMT_CHECK_BYP... */
a_uint32_t direction; /* if dest is vp, fill it in dest_info or src_info, 0:dest, 1:src */
a_uint32_t field_update_bitmap; /* refer to enum FLD_UPDATE_CAPWAP_EN... */
a_uint32_t next_service_code; /* next service code */
a_uint32_t hw_services; /* HW_SERVICES to IP-197 */
a_uint32_t offset_sel; /* Select the offset value to IP-197:0: l3_offset, 1:l4_offset */
} fal_servcode_config_t;
enum
{
/*servcode*/
FUNC_SERVCODE_CONFIG_SET = 0,
FUNC_SERVCODE_CONFIG_GET,
FUNC_SERVCODE_LOOPCHECK_EN,
FUNC_SERVCODE_LOOPCHECK_STATUS_GET,
};
sw_error_t fal_servcode_config_set(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry);
sw_error_t fal_servcode_config_get(a_uint32_t dev_id, a_uint32_t servcode_index, fal_servcode_config_t *entry);
sw_error_t fal_servcode_loopcheck_en(a_uint32_t dev_id, a_bool_t enable);
sw_error_t fal_servcode_loopcheck_status_get(a_uint32_t dev_id, a_bool_t *enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_SERVCODE_H_ */
/**
* @}
*/

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feeds/ipq807x/qca-ssdk/src/include/fal/fal_sfp.h
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@@ -1,578 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_sfp FAL_SFP
* @{
*/
#ifndef _FAL_SFP_H_
#define _FAL_SFP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef enum {
FAL_SFP_CC_BASE = 0, /* Check code for Base ID Fields (addresses 0 to 62) */
FAL_SFP_CC_EXT, /* Check code for the Extended ID Fields (addresses 64 to 94) */
FAL_SFP_CC_DMI, /* Check code for Base Diagnostic Fields (addresses 0 to 94) */
} fal_sfp_cc_type_t;
typedef struct {
a_uint32_t addr; /* Addr A0h or A2h */
a_uint32_t offset; /* offset in eeprom */
a_uint32_t count; /* data bytes */
a_uint8_t data[256]; /* data value */
} fal_sfp_data_t;
/* A0h offset: 0-2 bytes */
typedef struct {
a_uint8_t identifier; /* type of transceiver */
/*
* 00h: Unknown or unspecified
* 01h: GBIC
* 02h: Module soldered to motherboard (ex: SFF)
* 03h: SFP or SFP “Plus”
* 04h: Reserved for “300 pin XBI” devices*
* 05h: Reserved for “Xenpak” devices*
* 06h: Reserved for “XFP” devices*
* 07h: Reserved for “XFF” devices*
* 08h: Reserved for “XFP-E” devices*
* 09h: Reserved for “XPak” devices*
* 0Ah: Reserved for “X2” devices*
* 0Bh: Reserved for “DWDM-SFP” devices*
* 0Ch: Reserved for “QSFP” devices*
* 0D-7Fh: Reserved, unallocated
* 80-FFh: Vendor specific
*/
a_uint8_t ext_indentifier; /* Extended identifier of type of transceiver */
/*
* 00h: GBIC definition is not specified or not compliant with a defined MOD_DEF.
* 01h: GBIC is compliant with MOD_DEF 1
* 02h: GBIC is compliant with MOD_DEF 2
* 03h: GBIC is compliant with MOD_DEF 3
* 04h: GBIC/SFP function is defined by two-wire interface ID only
* 05h: GBIC is compliant with MOD_DEF 5
* 06h: GBIC is compliant with MOD_DEF 6
* 07h: GBIC is compliant with MOD_DEF 7
* 08-FFh: Unallocated
*/
a_uint8_t connector_type; /* Code for connector type */
/*
* 00h: Unknown or unspecified
* 01h: SC
* 02h: Fibre Channel Style 1 copper connector
* 03h: Fibre Channel Style 2 copper connector
* 04h: BNC/TNC
* 05h: Fibre Channel coaxial headers
* 06h: FiberJack
* 07h: LC
* 08h: MT-RJ
* 09h: MU
* 0AH: SG
* 0Bh: Optical pigtail
* 0Ch: MPO Parallel Optic
* 0D-1Fh: Unallocated
* 20h: HSSDC II
* 21h: Copper pigtail
* 22h: RJ45
* 23h-7Fh: Unallocated
* 80h-FFh: Vendor specific
*/
} fal_sfp_dev_type_t;
/* A0h offset: 3-10 bytes */
typedef struct {
a_uint8_t eth_10g_ccode; /* 10G Ethernet Compliance Codes */
/*
* offset 3 bit7: 10G Base-ER
* offset 3 bit6: 10G Base-LRM
* offset 3 bit5: 10G Base-LR
* offset 3 bit4: 10G Base-SR
*/
a_uint8_t infiniband_ccode; /* Infiniband Compliance Codes */
/*
* offset 3 bit3: 1X SX
* offset 3 bit2: 1X LX
* offset 3 bit1: 1X Copper Active
* offset 3 bit0: 1X Copper Passive
*/
a_uint8_t escon_ccode; /* ESCON Compliance Codes */
/*
* offset 4 bit7: ESCON MMF, 1310nm LED
* offset 4 bit6: ESCON SMF, 1310nm Laser
*/
a_uint16_t sonet_ccode; /* SONET Compliance Codes */
/*
* offset 4 bit5: OC-192, short reach
* offset 4 bit4: SONET reach specifier bit 1
* offset 4 bit3: SONET reach specifier bit 2
* offset 4 bit2: OC-48, long reach
* offset 4 bit1: OC-48, intermediate reach
* offset 4 bit0: OC-48, short reach
* offset 5 bit7: Unallocated
* offset 5 bit6: OC-12, single mode, long reach
* offset 5 bit5: OC-12, single mode, inter. reach
* offset 5 bit4: OC-12, short reach
* offset 5 bit3: Unallocated
* offset 5 bit2: OC-3, single mode, long reach
* offset 5 bit1: OC-3, single mode, inter. reach
* offset 5 bit0: OC-3, short reach
*/
a_uint8_t eth_ccode; /* Ethernet Compliance Codes */
/*
* offset 6 bit7: BASE-PX
* offset 6 bit6: BASE-BX10
* offset 6 bit5: 100BASE-FX
* offset 6 bit4: 100BASE-LX/LX10
* offset 6 bit3: 1000BASE-T
* offset 6 bit2: 1000BASE-CX
* offset 6 bit1: 1000BASE-LX
* offset 6 bit0: 1000BASE-SX
*/
a_uint8_t fibre_chan_link_length; /* Fibre Channel Link Length */
/*
* offset 7 bit7: very long distance (V)
* offset 7 bit6: short distance (S)
* offset 7 bit5: intermediate distance (I)
* offset 7 bit4: long distance (L)
* offset 7 bit3: medium distance (M)
*/
a_uint8_t fibre_chan_tech; /* Fibre Channel Technology */
/*
* offset 7 bit2: Shortwave laser, linear Rx (SA)
* offset 7 bit1: Longwave laser (LC)
* offset 7 bit0: Electrical inter-enclosure (EL)
* offset 8 bit7: Electrical intra-enclosure (EL)
* offset 8 bit6: Shortwave laser w/o OFC (SN)
* offset 8 bit5: Shortwave laser with OFC4 (SL)
* offset 8 bit4: Longwave laser (LL)
*/
a_uint8_t sfp_cable_tech; /* SFP+ Cable Technology */
/*
* offset 8 bit3: Active Cable
* offset 8 bit2: passive Cable
* offset 8 bit1: unallocated
* offset 8 bit0: unallocated
*/
a_uint8_t fibre_chan_trans_md; /* Fibre Channel Transmission Media */
/*
* offset 9 bit7: twin axial pair(TW)
* offset 9 bit6: twisted pair(TP)
* offset 9 bit5: miniature coax(MI)
* offset 9 bit4: video coax(TV)
* offset 9 bit3: multimode, 62.5um(M6)
* offset 9 bit2: multimode, 50um(M5,M5E)
* offset 9 bit1: unallocated
* offset 9 bit0: sigle mode(SM)
*/
a_uint8_t fibre_chan_speed; /* Fibre Channel Speed */
/*
* offset 10 bit7: 1200 MBytes/sec
* offset 10 bit6: 800 MBytes/sec
* offset 10 bit5: 1600 MBytes/sec
* offset 10 bit4: 400 MBytes/sec
* offset 10 bit3: unallocated
* offset 10 bit2: 200 MBytes/sec
* offset 10 bit1: unallocated
* offset 10 bit0: 100 MBytes/sec
*/
} fal_sfp_transc_code_t;
/* A0h offset: 11-13 bytes */
typedef struct {
a_uint8_t encode; /* the serial encoding mechanism */
/*
* 0h: Unspecified
* 1h: 8B/10B
* 2h: 4B/5B
* 3h: NRZ
* 4h: Manchester
* 5h: SONET Scrambled
* 6h： 64B/66B
* 7h-FFh: Unallocated
*/
a_uint8_t nominal_bit_rate; /* the nomial bit rate */
/*
* these bits necessary to encode and delimit the signal
* as well as those bits carrying data information,
* the actual transfer rate will depend on the encoding
* of the data definded by the encode value above.
*/
a_uint8_t rate_id; /* the selected rate */
/*
* 0h: Unspecified
* 1h: Defined for SFF-8079 (4/2/1G Rate_Select & AS0/AS1)
* 2h: Defined for SFF-8431 (8/4/2G Rx Rate_Select only)
* 3h: Unspecified *
* 4h: Defined for SFF-8431 (8/4/2G Tx Rate_Select only)
* 5h: Unspecified *
* 6h: Defined for SFF-8431 (8/4/2G Independent Rx & Tx Rate_select)
* 7h-FFh: Unallocated
*/
} fal_sfp_rate_encode_t;
/* A0h offset: 14-19 bytes */
typedef struct {
a_uint8_t single_mode_length_km; /* the link length of km in single mode */
a_uint8_t single_mode_length_100m; /* the link length of 100m in single mode */
a_uint8_t om2_mode_length_10m; /* the link length of 10m micron multimode OM2 */
a_uint8_t om1_mode_length_10m; /* the link length of 10m micron multimode OM1 */
a_uint8_t copper_mode_length_1m; /* the link length of 1m copper mode */
a_uint8_t om3_mode_length_1m; /* the link length of 10m micron multimode OM3 */
} fal_sfp_link_length_t;
/* A0h offset: 20-35 bytes vendor name*/
/* A0h offset: 36th byte transceiver code */
/* A0h offset: 37-39 bytes vendor oui */
/* A0h offset: 40-55 bytes vendor pn */
/* A0h offset: 56-59 bytes vendor rev */
/* A0h offset: 68-83 bytes for the vendor serial number */
/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */
typedef struct {
a_uint8_t vendor_name[16]; /* vendor name */
a_uint8_t vendor_oui[3]; /* vendor OUI */
a_uint8_t vendor_pn[16]; /* vendor PN */
a_uint8_t vendor_rev[4]; /* vendor Rev */
a_uint8_t vendor_sn[16]; /* the vendor serial number */
a_uint8_t vendor_date_code[8]; /* the vendor's date code in ascii charaters */
} fal_sfp_vendor_info_t;
/* A0h offset: 60-61 bytes */
typedef struct {
a_uint16_t laser_wavelength; /* the output laser wave length in nm */
} fal_sfp_laser_wavelength_t;
/* A0h offset: 62 byte unallocated */
/* A0h offset: 63 byte for checksum base */
/* A0h offset: 64-65 bytes */
typedef struct {
/* the implemented options */
a_uint8_t linear_recv_output:1;
a_uint8_t pwr_level_declar:1;
a_uint8_t cool_transc_declar:1;
a_uint8_t reversed_1:5;
a_uint8_t reversed_2:1;
a_uint8_t loss_signal:1;
a_uint8_t loss_invert_signal:1;
a_uint8_t tx_fault_signal:1;
a_uint8_t tx_disable:1;
a_uint8_t rate_sel:1;
a_uint8_t reversed_3:2;
/*
* offset 64 bit7-3: Unallocated
* offset 64 bit2: Cooled Transceiver Declaration (see SFF-8431)
* offset 64 bit1: Power Level Declaration (see SFF-8431)
* offset 64 bit0: Linear Receiver Output Implemented (see SFF-8431)
* offset 65 bit7-6: Unallocated
* offset 65 bit5: RATE_SELECT functionality is implemented
* offset 65 bit4: TX_DISABLE is implemented and disables the high speed serial output
* offset 65 bit3: TX_FAULT signal implemented. (See SFP MSA)
* offset 65 bit2: Loss of Signal implemented, signal inverted from standard definition
* offset 65 bit1: Loss of Signal implemented, signal as defined in SFP MSA
* offset 65 bit0: Unallocated
*/
} fal_sfp_option_t;
/* A0h offset: 66-67 bytes */
typedef struct {
a_uint8_t upper_rate_limit; /* the upper rate limit */
a_uint8_t lower_rate_limit; /* the lower rate limit */
} fal_sfp_rate_t;
/* A0h offset: 68-83 bytes for the vendor serial number */
/* A0h offset: 84-91 bytes for the vendor's date code in ascii charaters */
/* A0h offset: 92-94 bytes */
typedef struct {
/* digital diagnostic monitoring type */
a_uint8_t reserved_type:2;
a_uint8_t addr_mode:1;
a_uint8_t rec_pwr_type:1;
a_uint8_t external_cal:1;
a_uint8_t internal_cal:1;
a_uint8_t diag_mon_flag:1;
a_uint8_t legacy_type:1;
/*
* bit 7: Reserved for legacy diagnostic
* bit 6: Digital diagnostic monitoring implemented
* bit 5: Internally calibrated
* bit 4: Externally calibrated
* bit 3: Received power measurement type
* 0 = OMA, 1 = average power
* bit 2: Address change required “addressing modes”
* bit1~0: unallocated
*/
/* optional digital diagnostic features implemented */
a_uint8_t reserved_op:1;
a_uint8_t soft_rate_sel_op:1;
a_uint8_t app_sel_op:1;
a_uint8_t soft_rate_ctrl_op:1;
a_uint8_t rx_los_op:1;
a_uint8_t tx_fault_op:1;
a_uint8_t tx_disable_ctrl_op:1;
a_uint8_t alarm_warning_flag_op:1;
/*
* bit 7: Optional Alarm/warning flags implemented for all monitored quantities
* bit 6: Optional soft TX_DISABLE control and monitoring implemented
* bit 5: Optional soft TX_FAULT monitoring implemented
* bit 4: Optional soft RX_LOS monitoring implemented
* bit 3: Optional soft RATE_SELECT control and monitoring implemented
* bit 2: Optional Application Select control implemented per SFF-8079
* bit 1: Optional soft Rate Select control implemented per SFF-8431
* bit 0: Unallocated
*/
a_uint8_t compliance_feature; /* the implemented features */
/*
* 00h: Digital diagnostic functionality not included or undefined
* 01h: Includes functionality described in Rev 9.3 of SFF-8472.
* 02h: Includes functionality described in Rev 9.5 of SFF-8472.
* 03h: Includes functionality described in Rev 10.2 of SFF-8472.
* 04h: Includes functionality described in Rev 10.4 of SFF-8472.
* 05h~FFh: Unallocated
*/
} fal_sfp_enhanced_cfg_t;
/* A0h offset: 95th byte for checksum extended id field */
/* A0h offset: 96-127 bytes Vendor Specific */
/* A0h offset: 128-255 bytes Reserved */
/* A2h offset: 0-39 bytes */
typedef struct {
a_uint16_t temp_high_alarm; /* the temperature alarm high value */
a_uint16_t temp_low_alarm; /* the temperature alarm low value */
a_uint16_t temp_high_warning; /* the temperature warning high value */
a_uint16_t temp_low_warning; /* the temperature warning low value */
a_uint16_t vol_high_alarm; /* the voltage alarm high value */
a_uint16_t vol_low_alarm; /* the voltage alarm low value */
a_uint16_t vol_high_warning; /* the voltage warning high value */
a_uint16_t vol_low_warning; /* the voltage warning low value */
a_uint16_t bias_high_alarm; /* the bias alarm high value */
a_uint16_t bias_low_alarm; /* the bias alarm low value */
a_uint16_t bias_high_warning; /* the bias warning high value */
a_uint16_t bias_low_warning; /* the bias warning low value */
a_uint16_t tx_power_high_alarm; /* the tx power alarm high value */
a_uint16_t tx_power_low_alarm; /* the tx power alarm low value */
a_uint16_t tx_power_high_warning;/* the tx power warning high value */
a_uint16_t tx_power_low_warning; /* the tx power warning low value */
a_uint16_t rx_power_high_alarm; /* the rx power alarm high value */
a_uint16_t rx_power_low_alarm; /* the rx power alarm low value */
a_uint16_t rx_power_high_warning;/* the rx power warning high value */
a_uint16_t rx_power_low_warning; /* the rx power warning low value */
} fal_sfp_internal_threshold_t;
/* A2h offset: 40-55 bytes Reserved for future monitored quantities */
/* A2h offset: 56-91 bytes */
typedef struct {
a_uint32_t rx_power4; /* Single precision floating point Rx optical power4 */
a_uint32_t rx_power3; /* Single precision floating point Rx optical power3 */
a_uint32_t rx_power2; /* Single precision floating point Rx optical power2 */
a_uint32_t rx_power1; /* Single precision floating point Rx optical power1 */
a_uint32_t rx_power0; /* Single precision floating point Rx optical power0 */
a_uint16_t tx_bias_slope; /* Fixed decimal for laser bias current */
a_uint16_t tx_bias_offset; /* Fixed decimal for laser bias current */
a_uint16_t tx_power_slope; /* Fixed decimal for transmitter coupled output power */
a_uint16_t tx_power_offset;/* Fixed decimal for transmitter coupled output power */
a_uint16_t temp_slope; /* Fixed decimal for internal module temperature */
a_uint16_t temp_offset; /* Fixed decimal for internal module temperature */
a_uint16_t vol_slope; /* Fixed decimal for internal module supply voltage */
a_uint16_t vol_offset; /* Fixed decimal for internal module supply voltage */
} fal_sfp_cal_const_t;
/* A2h offset: 92-94 bytes Unallocated */
/* A2h offset: 95th byte checsum for Base Diagnostic Fields*/
/* A2h offset: 96-105 bytes */
typedef struct {
a_uint16_t cur_temp; /* Internally measured module temperature */
a_uint16_t cur_vol; /* Internally measured supply voltage in transceiver */
a_uint16_t tx_cur_bias; /* Internally measured TX Bias Current */
a_uint16_t tx_cur_power; /* Measured TX output power */
a_uint16_t rx_cur_power; /* Measured RX input power */
} fal_sfp_realtime_diag_t;
/* A2h offset: 106-109 bytes Unallocated */
/* A2h offset: 110th byte for base control/status */
/* A2h offset: 111th byte Reserved */
/* A2h offset: 118th byte for extend control/status */
typedef struct {
/* Optional Status/Control Bits */
a_uint8_t data_ready:1;
a_uint8_t rx_los:1;
a_uint8_t tx_fault:1;
a_uint8_t soft_rate_sel:1;
a_uint8_t rate_sel:1;
a_uint8_t rs_state:1;
a_uint8_t soft_tx_disable:1;
a_uint8_t tx_disable:1;
/*
* bit7: tx disable state
* bit6: soft tx disable select
* bit5: rs state
* bit4: rate_select state
* bit3: soft rate_select select
* bit2: tx fault state
* bit1: rx_los state
* bit0: data_ready_bar state
*/
/* Extended Control/Status Bits */
a_uint8_t pwr_level_sel:1;
a_uint8_t pwr_level_op_state:1;
a_uint8_t reserved_1:1;
a_uint8_t soft_rs_sel:1;
a_uint8_t reserved_2:4;
/*
* bit7-4: Reserved
* bit3: soft RS select
* bit2: Reserved
* bit1: Power level operation state
* bit0: Power level select
*/
} fal_sfp_ctrl_status_t;
/* A2h offset: 112-113 byte Alarm flag bits */
/* A2h offset: 114-115 byte Alarm Reserved */
/* A2h offset: 116-117 byte Warning flag bits */
typedef struct {
/* internal diagnose exceeds high alarm level */
a_uint8_t tx_pwr_low_alarm:1;
a_uint8_t tx_pwr_high_alarm:1;
a_uint8_t tx_bias_low_alarm:1;
a_uint8_t tx_bias_high_alarm:1;
a_uint8_t vcc_low_alarm:1;
a_uint8_t vcc_high_alarm:1;
a_uint8_t tmp_low_alarm:1;
a_uint8_t tmp_high_alarm:1;
a_uint8_t reserved_alarm:6;
a_uint8_t rx_pwr_low_alarm:1;
a_uint8_t rx_pwr_high_alarm:1;
/* internal diagnose exceeds high warn level */
a_uint8_t tx_pwr_low_warning:1;
a_uint8_t tx_pwr_high_warning:1;
a_uint8_t tx_bias_low_warning:1;
a_uint8_t tx_bias_high_warning:1;
a_uint8_t vcc_low_warning:1;
a_uint8_t vcc_high_warning:1;
a_uint8_t tmp_low_warning:1;
a_uint8_t tmp_high_warning:1;
a_uint8_t reserved_warning:6;
a_uint8_t rx_pwr_low_warning:1;
a_uint8_t rx_pwr_high_warning:1;
/*
* bit 15: internal temperature exceeds high alarm/warning level
* bit 14: internal temperature is below low alarm/warning level
* bit 13: internal supply voltage exceeds high alarm/warning level
* bit 12: internal supply voltage is below low alarm/warning level
* bit 11: TX Bias current exceeds high alarm/warning level
* bit 10: TX Bias current is below low alarm/warning level
* bit 09: TX output power exceeds high alarm/warning level
* bit 08: TX output power is below low alarm/warning level
* bit 07: Received Power exceeds high alarm/warning level
* bit 06: Received Power is below low alarm/warning level
* bit 05~00: reserved alarm/warning
*/
} fal_sfp_alarm_warn_flag_t;
/* A2h offset: 119th byte Reserved */
/* A2h offset: 120-127 byte Vendor Specific locations */
/* A2h offset: 128-247 byte User EEPROM */
/* A2h offset: 248-255 byte Vendor Specific locations */
sw_error_t
fal_sfp_eeprom_data_get(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry);
sw_error_t
fal_sfp_eeprom_data_set(a_uint32_t dev_id, a_uint32_t port_id, fal_sfp_data_t *entry);
sw_error_t
fal_sfp_device_type_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_dev_type_t *sfp_id);
sw_error_t
fal_sfp_transceiver_code_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_transc_code_t *transc_code);
sw_error_t
fal_sfp_rate_encode_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_rate_encode_t *encode);
sw_error_t
fal_sfp_link_length_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_link_length_t *link_len);
sw_error_t
fal_sfp_vendor_info_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_vendor_info_t *vender_info);
sw_error_t
fal_sfp_laser_wavelength_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_laser_wavelength_t *laser_wavelen);
sw_error_t
fal_sfp_option_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_option_t *option);
sw_error_t
fal_sfp_ctrl_rate_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_rate_t *rate_limit);
sw_error_t
fal_sfp_enhanced_cfg_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_enhanced_cfg_t *enhanced_feature);
sw_error_t
fal_sfp_diag_internal_threshold_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_internal_threshold_t *threshold);
sw_error_t
fal_sfp_diag_extenal_calibration_const_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_cal_const_t *cal_const);
sw_error_t
fal_sfp_diag_realtime_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_realtime_diag_t *real_diag);
sw_error_t
fal_sfp_diag_ctrl_status_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_ctrl_status_t *ctrl_status);
sw_error_t
fal_sfp_diag_alarm_warning_flag_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_alarm_warn_flag_t *alarm_warn_flag);
sw_error_t
fal_sfp_checkcode_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sfp_cc_type_t cc_type, a_uint8_t *ccode);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_SFP_H_ */
/**
* @}
*/

163
feeds/ipq807x/qca-ssdk/src/include/fal/fal_shaper.h
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@@ -1,163 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_shaper FAL_SHAPER
* @{
*/
#ifndef _FAL_SHAPER_H_
#define _FAL_SHAPER_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
typedef enum
{
FAL_IPG_PREAMBLE_FRAME_CRC = 0, /* IPG + Preamble + Frame + CRC */
FAL_FRAME_CRC, /* Frame + CRC */
FAL_L3_EXCLUDE_CRC /* after Ethernet type excude CRC*/
} fal_shaper_frame_mode_t;
typedef struct
{
a_bool_t couple_en; /* two buckets coupled enable or disable*/
a_uint32_t meter_unit; /* 0 byte based, 1 frame based */
a_bool_t c_shaper_en; /* egress shaer C bucket enable or disable */
a_uint32_t cbs; /* committed burst size */
a_uint32_t cir; /* committed information rate */
a_bool_t e_shaper_en; /* egress shaper E bucket enable or disable */
a_uint32_t ebs; /* excess burst size */
a_uint32_t eir; /* excess information rate */
fal_shaper_frame_mode_t shaper_frame_mode; /* shaper frame mode */
} fal_shaper_config_t;
typedef struct
{
a_bool_t c_token_number_negative_en; /* C token is negative or not */
a_uint32_t c_token_number; /* C token value */
a_bool_t e_token_number_negative_en; /* E token is negative or not */
a_uint32_t e_token_number; /* E token value */
} fal_shaper_token_number_t;
enum
{
FUNC_ADPT_FLOW_SHAPER_SET = 0,
FUNC_ADPT_QUEUE_SHAPER_GET,
FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_SET,
FUNC_ADPT_PORT_SHAPER_GET,
FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_GET,
FUNC_ADPT_PORT_SHAPER_TIME_SLOT_GET,
FUNC_ADPT_FLOW_SHAPER_TIME_SLOT_SET,
FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_SET,
FUNC_ADPT_QUEUE_SHAPER_TOKEN_NUMBER_GET,
FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_GET,
FUNC_ADPT_PORT_SHAPER_TOKEN_NUMBER_GET,
FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_SET,
FUNC_ADPT_FLOW_SHAPER_TOKEN_NUMBER_GET,
FUNC_ADPT_PORT_SHAPER_SET,
FUNC_ADPT_PORT_SHAPER_TIME_SLOT_SET,
FUNC_ADPT_FLOW_SHAPER_GET,
FUNC_ADPT_QUEUE_SHAPER_SET,
FUNC_ADPT_QUEUE_SHAPER_TIME_SLOT_SET,
FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_SET,
FUNC_ADPT_SHAPER_IPG_PREAMBLE_LENGTH_GET,
};
sw_error_t
fal_queue_shaper_token_number_set(a_uint32_t dev_id,a_uint32_t queue_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_flow_shaper_token_number_set(a_uint32_t dev_id, a_uint32_t flow_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_port_shaper_token_number_set(a_uint32_t dev_id, fal_port_t port_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_port_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
sw_error_t
fal_queue_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
sw_error_t
fal_flow_shaper_timeslot_set(a_uint32_t dev_id, a_uint32_t timeslot);
sw_error_t
fal_shaper_ipg_preamble_length_set(a_uint32_t dev_id, a_uint32_t ipg_pre_length);
sw_error_t
fal_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
fal_shaper_config_t * shaper);
sw_error_t
fal_queue_shaper_set(a_uint32_t dev_id,a_uint32_t queue_id,
fal_shaper_config_t * shaper);
sw_error_t
fal_queue_shaper_get(a_uint32_t dev_id, a_uint32_t queue_id,
fal_shaper_config_t * shaper);
sw_error_t
fal_flow_shaper_set(a_uint32_t dev_id, a_uint32_t flow_id,
fal_shaper_config_t * shaper);
#ifndef IN_SHAPER_MINI
sw_error_t
fal_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
fal_shaper_config_t * shaper);
sw_error_t
fal_flow_shaper_get(a_uint32_t dev_id, a_uint32_t flow_id,
fal_shaper_config_t * shaper);
sw_error_t
fal_queue_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t queue_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_flow_shaper_token_number_get(a_uint32_t dev_id, a_uint32_t flow_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_port_shaper_token_number_get(a_uint32_t dev_id, fal_port_t port_id,
fal_shaper_token_number_t *token_number);
sw_error_t
fal_port_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
sw_error_t
fal_queue_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
sw_error_t
fal_flow_shaper_timeslot_get(a_uint32_t dev_id, a_uint32_t *timeslot);
sw_error_t
fal_shaper_ipg_preamble_length_get(a_uint32_t dev_id, a_uint32_t *ipg_pre_length);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_SHAPER_H_ */
/**
* @}
*/

75
feeds/ipq807x/qca-ssdk/src/include/fal/fal_stp.h
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/*
* Copyright (c) 2012, 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_stp FAL_STP
* @{
*/
#ifndef _FAL_STP_H_
#define _FAL_STP_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#define FAL_SINGLE_STP_ID 0
/**
@brief This enum defines port state for spanning tree.
*/
typedef enum {
FAL_STP_DISABLED = 0, /**< disable state*/
FAL_STP_BLOCKING, /**< blocking state*/
FAL_STP_LISTENING, /**< listening state*/
FAL_STP_LEARNING, /**< learning state*/
FAL_STP_FORWARDING, /**< forwarding state*/
FAL_STP_STATE_BUTT
}
fal_stp_state_t;
/*
* These two #define lines are used to keep them for the
* compatibility of previous project.
*/
#define FAL_STP_BLOKING FAL_STP_BLOCKING
#define FAL_STP_FARWARDING FAL_STP_FORWARDING
enum {
FUNC_STP_PORT_STATE_SET = 0,
FUNC_STP_PORT_STATE_GET,
};
sw_error_t
fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
fal_port_t port_id, fal_stp_state_t state);
sw_error_t
fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
fal_port_t port_id, fal_stp_state_t * state);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_STP_H_ */
/**
* @}
*/

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@@ -1,84 +0,0 @@
/*
* Copyright (c) 2012, 2016-2018, 2020, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_trunk FAL_TRUNK
* @{
*/
#ifndef _FAL_TRUNK_H_
#define _FAL_TRUNK_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#define FAL_TRUNK_HASH_KEY_DA 0x1
#define FAL_TRUNK_HASH_KEY_SA 0x2
#define FAL_TRUNK_HASH_KEY_DIP 0x4
#define FAL_TRUNK_HASH_KEY_SIP 0x8
#define FAL_TRUNK_HASH_KEY_SRC_PORT 0x10
#define FAL_TRUNK_HASH_KEY_L4_SRC_PORT 0x20
#define FAL_TRUNK_HASH_KEY_L4_DST_PORT 0x40
#define FAL_TRUNK_HASH_KEY_UDF0 0x80
#define FAL_TRUNK_HASH_KEY_UDF1 0x100
#define FAL_TRUNK_HASH_KEY_UDF2 0x200
#define FAL_TRUNK_HASH_KEY_UDF3 0x400
#define FAL_TRUNK_GROUP_MAX_MEMEBER 8
enum {
FUNC_TRUNK_GROUP_SET = 0,
FUNC_TRUNK_GROUP_GET,
FUNC_TRUNK_HASH_MODE_SET,
FUNC_TRUNK_HASH_MODE_GET,
FUNC_TRUNK_FAILOVER_ENABLE,
FUNC_TRUNK_FAILOVER_STATUS_GET,
};
sw_error_t
fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
a_bool_t enable, fal_pbmp_t member);
sw_error_t
fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
a_bool_t * enable, fal_pbmp_t * member);
sw_error_t
fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
sw_error_t
fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
sw_error_t
fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
sw_error_t
fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
sw_error_t
fal_trunk_failover_enable(a_uint32_t dev_id, a_bool_t failover);
sw_error_t
fal_trunk_failover_status_get(a_uint32_t dev_id, a_bool_t * failover);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_TRUNK_H_ */
/**
* @}
*/

137
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@@ -1,137 +0,0 @@
/*
* Copyright (c) 2012, 2016-2017, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_type FAL_TYPE
* @{
*/
#ifndef _FAL_TYPE_H_
#define _FAL_TYPE_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
typedef a_uint32_t fal_port_t;
/*fal_port_t definition,
bit31-bit24: port_type, 0-physical port, 1-trunk port, 2-virtual port
bit23-bit0: physical port id or trunk id or virtual port id*/
#define FAL_PORT_TYPE_PPORT 0
#define FAL_PORT_TYPE_TRUNK 1
#define FAL_PORT_TYPE_VPORT 2
#define FAL_PORT_ID_TYPE(port_id) (((port_id)>>24)&0xff)
#define FAL_PORT_ID_VALUE(port_id) ((port_id)&0xffffff)
#define FAL_PORT_ID(type, value) (((type)<<24)|(value))
#define FAL_IS_PPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_PPORT)?1:0)
#define FAL_IS_TRUNK(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_TRUNK)?1:0)
#define FAL_IS_VPORT(port_id) (((FAL_PORT_ID_TYPE(port_id))==FAL_PORT_TYPE_VPORT)?1:0)
#if (SW_MAX_NR_PORT <= 32)
typedef a_uint32_t fal_pbmp_t;
#else
typedef a_uint64_t fal_pbmp_t;
#endif
typedef struct
{
a_uint8_t uc[6];
} fal_mac_addr_t;
typedef a_uint32_t fal_ip4_addr_t;
typedef struct
{
a_uint32_t ul[4];
} fal_ip6_addr_t;
/**
@brief This enum defines several forwarding command type.
* Field description:
FAL_MAC_FRWRD - packets are normally forwarded
FAL_MAC_DROP - packets are dropped
FAL_MAC_CPY_TO_CPU - packets are copyed to cpu
FAL_MAC_RDT_TO_CPU - packets are redirected to cpu
*/
typedef enum
{
FAL_MAC_FRWRD = 0, /**< packets are normally forwarded */
FAL_MAC_DROP, /**< packets are dropped */
FAL_MAC_CPY_TO_CPU, /**< packets are copyed to cpu */
FAL_MAC_RDT_TO_CPU /**< packets are redirected to cpu */
} fal_fwd_cmd_t;
typedef enum
{
FAL_BYTE_BASED = 0,
FAL_FRAME_BASED,
FAL_RATE_MODE_BUTT
} fal_traffic_unit_t;
typedef a_uint32_t fal_queue_t;
#define FAL_SVL_FID 0xffff
/**
@brief This enum defines packets transmitted out vlan tagged mode.
*/
typedef enum
{
FAL_EG_UNMODIFIED = 0, /**< egress transmit packets unmodified */
FAL_EG_UNTAGGED, /**< egress transmit packets without vlan tag*/
FAL_EG_TAGGED, /**< egress transmit packets with vlan tag */
FAL_EG_HYBRID, /**< egress transmit packets in hybrid tag mode */
FAL_EG_UNTOUCHED,
FAL_EG_MODE_BUTT
} fal_pt_1q_egmode_t;
#define FAL_NEXT_ENTRY_FIRST_ID 0xffffffff
typedef struct{
a_uint32_t reg_count;
a_uint32_t reg_base;
a_uint32_t reg_end;
a_uint32_t reg_value[256];
a_int8_t reg_name[32];
}fal_reg_dump_t;
typedef struct{
a_uint32_t reg_count;
a_uint32_t reg_addr[32];
a_uint32_t reg_value[32];
a_int8_t reg_name[32];
}fal_debug_reg_dump_t;
typedef struct{
a_uint32_t phy_count;
a_uint32_t phy_base;
a_uint32_t phy_end;
a_uint16_t phy_value[256];
a_int8_t phy_name[32];
}fal_phy_dump_t;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_TYPE_H_ */
/**
* @}
*/

42
feeds/ipq807x/qca-ssdk/src/include/fal/fal_uk_if.h
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@@ -1,42 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _FAL_UK_IF_H_
#define _FAL_UK_IF_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#include "ssdk_init.h"
sw_error_t
sw_uk_exec(a_uint32_t api_id, ...);
sw_error_t
ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
sw_error_t
ssdk_cleanup(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_UK_IF_H_ */

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/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_vlan FAL_VLAN
* @{
*/
#ifndef _FAL_VLAN_H
#define _FAL_VLAN_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
/**
@brief This structure defines vlan entry.
*/
typedef struct
{
a_uint16_t vid; /**< vlan entry id */
a_uint16_t fid; /**< filter data base id*/
fal_pbmp_t mem_ports; /**< member port bit map */
fal_pbmp_t tagged_ports; /**< bit map of tagged infomation for member port*/
fal_pbmp_t untagged_ports; /**< bit map of untagged infomation for member port*/
fal_pbmp_t unmodify_ports;/**< bit map of unmodified infomation for member port*/
fal_pbmp_t u_ports;
a_bool_t learn_dis; /**< disable address learning*/
a_bool_t vid_pri_en; /**< enable 802.1p*/
a_uint8_t vid_pri; /**< vlaue of 802.1p when enable vid_pri_en*/
} fal_vlan_t;
sw_error_t
fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry);
sw_error_t
fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
sw_error_t
fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
sw_error_t
fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
sw_error_t
fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
fal_pbmp_t member, fal_pbmp_t u_member);
sw_error_t
fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
sw_error_t
fal_vlan_reset(a_uint32_t dev_id);
sw_error_t
fal_vlan_flush(a_uint32_t dev_id);
sw_error_t
fal_vlan_init(a_uint32_t dev_id);
sw_error_t
fal_vlan_cleanup(void);
sw_error_t
fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
sw_error_t
fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
sw_error_t
fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
fal_port_t port_id, fal_pt_1q_egmode_t port_info);
sw_error_t
fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
sw_error_t
fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
a_bool_t enable);
sw_error_t
fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
a_bool_t * enable);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_VLAN_H */
/**
* @}
*/

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/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup fal_stp FAL_VSI
* @{
*/
#ifndef _FAL_VSI_H_
#define _FAL_VSI_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
#include "fal/fal_type.h"
#define FAL_VSI_INVALID 0xffff
#define FAL_VLAN_INVALID 0xffff
#define FAL_VSI_MAX 31
#define FAL_VLAN_MAX 4095
typedef struct{
a_uint32_t lrn_en; /*0: disable new address learn, 1: enable new address learn*/
fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/
}fal_vsi_newaddr_lrn_t;
typedef struct{
a_uint32_t stamove_en;/*0:disable station move, 1: enable station move*/
fal_fwd_cmd_t action;/*0:forward, 1:drop, 2: copy to CPU, 3: redirect to CPU*/
}fal_vsi_stamove_t;
typedef struct{
a_uint32_t member_ports;/*VSI member ports for all packets*/
a_uint32_t uuc_ports;/*VSI member ports for unknown unicast*/
a_uint32_t umc_ports;/*VSI member ports for unknown multicast*/
a_uint32_t bc_ports;/*VSI member ports for broadcast*/
}fal_vsi_member_t;
typedef struct
{
a_uint32_t rx_packet_counter;
a_uint64_t rx_byte_counter;
a_uint32_t tx_packet_counter;
a_uint64_t tx_byte_counter;
a_uint32_t fwd_packet_counter;
a_uint64_t fwd_byte_counter;
a_uint32_t drop_packet_counter;
a_uint64_t drop_byte_counter;
}fal_vsi_counter_t;
enum{
FUNC_PORT_VLAN_VSI_SET,
FUNC_PORT_VLAN_VSI_GET,
FUNC_PORT_VSI_SET,
FUNC_PORT_VSI_GET,
FUNC_VSI_STAMOVE_SET,
FUNC_VSI_STAMOVE_GET,
FUNC_VSI_NEWADDR_LRN_SET,
FUNC_VSI_NEWADDR_LRN_GET,
FUNC_VSI_MEMBER_SET,
FUNC_VSI_MEMBER_GET,
FUNC_VSI_COUNTER_GET,
FUNC_VSI_COUNTER_CLEANUP,
};
sw_error_t
fal_vsi_alloc(a_uint32_t dev_id, a_uint32_t *vsi);
sw_error_t
fal_vsi_free(a_uint32_t dev_id, a_uint32_t vsi);
sw_error_t
fal_port_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vsi_id);
#ifndef IN_VSI_MINI
sw_error_t
fal_port_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vsi_id);
sw_error_t
fal_vsi_stamove_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
sw_error_t
fal_vsi_newaddr_lrn_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
sw_error_t
fal_vsi_counter_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_counter_t *counter);
sw_error_t
fal_vsi_counter_cleanup(a_uint32_t dev_id, a_uint32_t vsi_id);
#endif
sw_error_t
fal_port_vlan_vsi_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t vsi_id);
sw_error_t
fal_port_vlan_vsi_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t stag_vid, a_uint32_t ctag_vid, a_uint32_t *vsi_id);
sw_error_t
fal_vsi_tbl_dump(a_uint32_t dev_id);
sw_error_t
fal_vsi_newaddr_lrn_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_newaddr_lrn_t *newaddr_lrn);
sw_error_t
fal_vsi_stamove_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_stamove_t *stamove);
sw_error_t
fal_vsi_member_set(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
sw_error_t
fal_vsi_member_get(a_uint32_t dev_id, a_uint32_t vsi_id, fal_vsi_member_t *vsi_member);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _FAL_VSI_H_ */
/**
* @}
*/

198
feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_api.h
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@@ -1,198 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_API_H_
#define _ATHENA_API_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#ifdef IN_PORTCONTROL
#define PORTCONTROL_API \
SW_API_DEF(SW_API_PT_DUPLEX_GET, athena_port_duplex_get), \
SW_API_DEF(SW_API_PT_DUPLEX_SET, athena_port_duplex_set), \
SW_API_DEF(SW_API_PT_SPEED_GET, athena_port_speed_get), \
SW_API_DEF(SW_API_PT_SPEED_SET, athena_port_speed_set), \
SW_API_DEF(SW_API_PT_AN_GET, athena_port_autoneg_status_get), \
SW_API_DEF(SW_API_PT_AN_ENABLE, athena_port_autoneg_enable), \
SW_API_DEF(SW_API_PT_AN_RESTART, athena_port_autoneg_restart), \
SW_API_DEF(SW_API_PT_AN_ADV_GET, athena_port_autoneg_adv_get), \
SW_API_DEF(SW_API_PT_AN_ADV_SET, athena_port_autoneg_adv_set), \
SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, athena_port_igmps_status_set), \
SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, athena_port_igmps_status_get), \
SW_API_DEF(SW_API_PT_POWERSAVE_SET, athena_port_powersave_set), \
SW_API_DEF(SW_API_PT_POWERSAVE_GET, athena_port_powersave_get), \
SW_API_DEF(SW_API_PT_HIBERNATE_SET, athena_port_hibernate_set), \
SW_API_DEF(SW_API_PT_HIBERNATE_GET, athena_port_hibernate_get),
#define PORTCONTROL_API_PARAM \
SW_API_DESC(SW_API_PT_DUPLEX_GET) \
SW_API_DESC(SW_API_PT_DUPLEX_SET) \
SW_API_DESC(SW_API_PT_SPEED_GET) \
SW_API_DESC(SW_API_PT_SPEED_SET) \
SW_API_DESC(SW_API_PT_AN_GET) \
SW_API_DESC(SW_API_PT_AN_ENABLE) \
SW_API_DESC(SW_API_PT_AN_RESTART) \
SW_API_DESC(SW_API_PT_AN_ADV_GET) \
SW_API_DESC(SW_API_PT_AN_ADV_SET) \
SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
SW_API_DESC(SW_API_PT_HIBERNATE_GET)
#else
#define PORTCONTROL_API
#define PORTCONTROL_API_PARAM
#endif
#ifdef IN_VLAN
#define VLAN_API \
SW_API_DEF(SW_API_VLAN_ADD, athena_vlan_create), \
SW_API_DEF(SW_API_VLAN_DEL, athena_vlan_delete), \
SW_API_DEF(SW_API_VLAN_MEM_UPDATE, athena_vlan_member_update), \
SW_API_DEF(SW_API_VLAN_FIND, athena_vlan_find), \
SW_API_DEF(SW_API_VLAN_NEXT, athena_vlan_next), \
SW_API_DEF(SW_API_VLAN_APPEND, athena_vlan_entry_append),
#define VLAN_API_PARAM \
SW_API_DESC(SW_API_VLAN_ADD) \
SW_API_DESC(SW_API_VLAN_DEL) \
SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
SW_API_DESC(SW_API_VLAN_FIND) \
SW_API_DESC(SW_API_VLAN_NEXT) \
SW_API_DESC(SW_API_VLAN_APPEND)
#else
#define VLAN_API
#define VLAN_API_PARAM
#endif
#ifdef IN_PORTVLAN
#define PORTVLAN_API \
SW_API_DEF(SW_API_PT_ING_MODE_GET, athena_port_1qmode_get), \
SW_API_DEF(SW_API_PT_ING_MODE_SET, athena_port_1qmode_set), \
SW_API_DEF(SW_API_PT_EG_MODE_GET, athena_port_egvlanmode_get), \
SW_API_DEF(SW_API_PT_EG_MODE_SET, athena_port_egvlanmode_set), \
SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, athena_portvlan_member_add), \
SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, athena_portvlan_member_del), \
SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, athena_portvlan_member_update), \
SW_API_DEF(SW_API_PT_VLAN_MEM_GET, athena_portvlan_member_get), \
#define PORTVLAN_API_PARAM \
SW_API_DESC(SW_API_PT_ING_MODE_GET) \
SW_API_DESC(SW_API_PT_ING_MODE_SET) \
SW_API_DESC(SW_API_PT_EG_MODE_GET) \
SW_API_DESC(SW_API_PT_EG_MODE_SET) \
SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
SW_API_DESC(SW_API_PT_VLAN_MEM_GET)
#else
#define PORTVLAN_API
#define PORTVLAN_API_PARAM
#endif
#ifdef IN_FDB
#define FDB_API \
SW_API_DEF(SW_API_FDB_ADD, athena_fdb_add), \
SW_API_DEF(SW_API_FDB_DELALL, athena_fdb_del_all), \
SW_API_DEF(SW_API_FDB_DELPORT,athena_fdb_del_by_port), \
SW_API_DEF(SW_API_FDB_DELMAC, athena_fdb_del_by_mac), \
SW_API_DEF(SW_API_FDB_FIRST, athena_fdb_first), \
SW_API_DEF(SW_API_FDB_NEXT, athena_fdb_next),
#define FDB_API_PARAM \
SW_API_DESC(SW_API_FDB_ADD) \
SW_API_DESC(SW_API_FDB_DELALL) \
SW_API_DESC(SW_API_FDB_DELPORT) \
SW_API_DESC(SW_API_FDB_DELMAC) \
SW_API_DESC(SW_API_FDB_FIRST) \
SW_API_DESC(SW_API_FDB_NEXT)
#else
#define FDB_API
#define FDB_API_PARAM
#endif
#ifdef IN_MIB
#define MIB_API \
SW_API_DEF(SW_API_PT_MIB_GET, athena_get_mib_info),
#define MIB_API_PARAM \
SW_API_DESC(SW_API_PT_MIB_GET)
#else
#define MIB_API
#define MIB_API_PARAM
#endif
#define REG_API \
SW_API_DEF(SW_API_PHY_GET, athena_phy_get), \
SW_API_DEF(SW_API_PHY_SET, athena_phy_set), \
SW_API_DEF(SW_API_REG_GET, athena_reg_get), \
SW_API_DEF(SW_API_REG_SET, athena_reg_set), \
SW_API_DEF(SW_API_REG_FIELD_GET, athena_reg_field_get), \
SW_API_DEF(SW_API_REG_FIELD_SET, athena_reg_field_set),
#define REG_API_PARAM \
SW_API_DESC(SW_API_PHY_GET) \
SW_API_DESC(SW_API_PHY_SET) \
SW_API_DESC(SW_API_REG_GET) \
SW_API_DESC(SW_API_REG_SET) \
SW_API_DESC(SW_API_REG_FIELD_GET) \
SW_API_DESC(SW_API_REG_FIELD_SET)
#define SSDK_API \
SW_API_DEF(SW_API_SWITCH_RESET, athena_reset), \
SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
MIB_API \
PORTCONTROL_API \
PORTVLAN_API \
VLAN_API \
FDB_API \
REG_API \
SW_API_DEF(SW_API_MAX, NULL)
#define SSDK_PARAM \
SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
MIB_API_PARAM \
PORTCONTROL_API_PARAM \
PORTVLAN_API_PARAM \
VLAN_API_PARAM \
FDB_API_PARAM \
REG_API_PARAM \
SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
#if (defined(USER_MODE) && defined(KERNEL_MODULE))
#undef SSDK_API
#undef SSDK_PARAM
#define SSDK_API \
REG_API \
SW_API_DEF(SW_API_MAX, NULL),
#define SSDK_PARAM \
REG_API_PARAM \
SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_API_H_ */

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@@ -1,76 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_FDB_H
#define _ATHENA_FDB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_fdb.h"
sw_error_t athena_fdb_init(a_uint32_t dev_id);
#ifdef IN_FDB
#define ATHENA_FDB_INIT(rv, dev_id) \
{ \
rv = athena_fdb_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define ATHENA_FDB_INIT(rv, dev_id)
#endif
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
HSL_LOCAL sw_error_t
athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
HSL_LOCAL sw_error_t
athena_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id,
a_uint32_t flag);
HSL_LOCAL sw_error_t
athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * addr);
HSL_LOCAL sw_error_t
athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
HSL_LOCAL sw_error_t
athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_FDB_H */

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/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_INIT_H_
#define _ATHENA_INIT_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "init/ssdk_init.h"
sw_error_t
athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
sw_error_t
athena_cleanup(a_uint32_t dev_id);
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_reset(a_uint32_t dev_id);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_INIT_H_ */

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feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_mib.h
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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_MIB_H
#define _ATHENA_MIB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_mib.h"
sw_error_t
athena_mib_init(a_uint32_t dev_id);
#ifdef IN_MIB
#define ATHENA_MIB_INIT(rv, dev_id) \
{ \
rv = athena_mib_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define ATHENA_MIB_INIT(rv, dev_id)
#endif
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
fal_mib_info_t * mib_info );
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_MIB_H */

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@@ -1,127 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_PORT_CTRL_H
#define _ATHENA_PORT_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_port_ctrl.h"
sw_error_t athena_port_ctrl_init(a_uint32_t dev_id);
#ifdef IN_PORTCONTROL
#define ATHENA_PORT_CTRL_INIT(rv, dev_id) \
{ \
rv = athena_port_ctrl_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define ATHENA_PORT_CTRL_INIT(rv, dev_id)
#endif
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t duplex);
HSL_LOCAL sw_error_t
athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_duplex_t * pduplex);
HSL_LOCAL sw_error_t
athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
fal_port_speed_t speed);
HSL_LOCAL sw_error_t
athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
fal_port_speed_t * pspeed);
HSL_LOCAL sw_error_t
athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * status);
HSL_LOCAL sw_error_t
athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
HSL_LOCAL sw_error_t
athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
HSL_LOCAL sw_error_t
athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t autoadv);
HSL_LOCAL sw_error_t
athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * autoadv);
HSL_LOCAL sw_error_t
athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
HSL_LOCAL sw_error_t
athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t * enable);
HSL_LOCAL sw_error_t
athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
HSL_LOCAL sw_error_t
athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
HSL_LOCAL sw_error_t
athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
HSL_LOCAL sw_error_t
athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_PORT_CTRL_H */

94
feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_portvlan.h
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@@ -1,94 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_PORTVLAN_H
#define _ATHENA_PORTVLAN_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_portvlan.h"
sw_error_t
athena_portvlan_init(a_uint32_t dev_id);
#ifdef IN_PORTVLAN
#define ATHENA_PORTVLAN_INIT(rv, dev_id) \
{ \
rv = athena_portvlan_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define ATHENA_PORTVLAN_INIT(rv, dev_id)
#endif
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t port_1qmode);
HSL_LOCAL sw_error_t
athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1qmode_t * pport_1qmode);
HSL_LOCAL sw_error_t
athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t port_egvlanmode);
HSL_LOCAL sw_error_t
athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pt_1q_egmode_t * pport_egvlanmode);
HSL_LOCAL sw_error_t
athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mem_port_id);
HSL_LOCAL sw_error_t
athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t mem_port_id);
HSL_LOCAL sw_error_t
athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t mem_port_map);
HSL_LOCAL sw_error_t
athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
fal_pbmp_t *mem_port_map);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_PORTVLAN_H */

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63
feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_reg_access.h
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@@ -1,63 +0,0 @@
/*
* Copyright (c) 2012,2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_REG_ACCESS_H_
#define _ATHENA_REG_ACCESS_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "sw.h"
sw_error_t
athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t reg, a_uint16_t * value);
sw_error_t
athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t reg, a_uint16_t value);
sw_error_t
athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
a_uint32_t value_len);
sw_error_t
athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
a_uint32_t bit_offset, a_uint32_t field_len,
a_uint8_t value[], a_uint32_t value_len);
sw_error_t
athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
a_uint32_t bit_offset, a_uint32_t field_len,
const a_uint8_t value[], a_uint32_t value_len);
sw_error_t
athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
sw_error_t
athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_REG_ACCESS_H_ */

94
feeds/ipq807x/qca-ssdk/src/include/hsl/athena/athena_vlan.h
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@@ -1,94 +0,0 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ATHENA_VLAN_H
#define _ATHENA_VLAN_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_vlan.h"
sw_error_t
athena_vlan_reset(a_uint32_t dev_id);
sw_error_t
athena_vlan_init(a_uint32_t dev_id);
sw_error_t
athena_vlan_cleanup(a_uint32_t dev_id);
#ifdef IN_VLAN
#define ATHENA_VLAN_RESET(rv, dev_id) \
{ \
rv = athena_vlan_reset(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#define ATHENA_VLAN_INIT(rv, dev_id) \
{ \
rv = athena_vlan_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#define ATHENA_VLAN_CLEANUP(rv, dev_id) \
{ \
rv = athena_vlan_cleanup(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define ATHENA_VLAN_RESET(rv, dev_id)
#define ATHENA_VLAN_INIT(rv, dev_id)
#define ATHENA_VLAN_CLEANUP(rv, dev_id)
#endif
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
HSL_LOCAL sw_error_t
athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
HSL_LOCAL sw_error_t
athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
HSL_LOCAL sw_error_t
athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
HSL_LOCAL sw_error_t
athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
fal_pbmp_t member, fal_pbmp_t u_member);
HSL_LOCAL sw_error_t
athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _ATHENA_VLAN_H */

213
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback.h
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@@ -1,213 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _CPPE_LOOPBACK_H_
#define _CPPE_LOOPBACK_H_
sw_error_t
cppe_lpbk_enable_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_enable_u *value);
sw_error_t
cppe_lpbk_enable_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_enable_u *value);
sw_error_t
cppe_lpbk_fifo_1_ctrl_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_fifo_1_ctrl_u *value);
sw_error_t
cppe_lpbk_fifo_1_ctrl_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_fifo_1_ctrl_u *value);
sw_error_t
cppe_lpbk_fifo_2_ctrl_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_fifo_2_ctrl_u *value);
sw_error_t
cppe_lpbk_fifo_2_ctrl_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_fifo_2_ctrl_u *value);
sw_error_t
cppe_lpbk_pps_ctrl_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_pps_ctrl_u *value);
sw_error_t
cppe_lpbk_pps_ctrl_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_pps_ctrl_u *value);
sw_error_t
cppe_lpbk_mac_junmo_size_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_mac_junmo_size_u *value);
sw_error_t
cppe_lpbk_mac_junmo_size_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_mac_junmo_size_u *value);
sw_error_t
cppe_lpbk_mib_ctrl_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_mib_ctrl_u *value);
sw_error_t
cppe_lpbk_mib_ctrl_set(
a_uint32_t dev_id,
a_uint32_t index,
union lpbk_mib_ctrl_u *value);
sw_error_t
cppe_lpbk_mib_uni_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkuni_u *value);
sw_error_t
cppe_lpbk_mib_multi_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkmulti_u *value);
sw_error_t
cppe_lpbk_mib_broad_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkbroad_u *value);
sw_error_t
cppe_lpbk_mib_pkt64_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt64_u *value);
sw_error_t
cppe_lpbk_mib_pkt65to127_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt65to127_u *value);
sw_error_t
cppe_lpbk_mib_pkt128to255_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt128to255_u *value);
sw_error_t
cppe_lpbk_mib_pkt256to511_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt256to511_u *value);
sw_error_t
cppe_lpbk_mib_pkt512to1023_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt512to1023_u *value);
sw_error_t
cppe_lpbk_mib_pkt1024to1518_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt1024to1518_u *value);
sw_error_t
cppe_lpbk_mib_pkt1519tox_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt1519tox_u *value);
sw_error_t
cppe_lpbk_mib_toolong_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkttoolong_u *value);
sw_error_t
cppe_lpbk_mib_byte_l_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkbyte_l_u *value);
sw_error_t
cppe_lpbk_mib_byte_h_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkbyte_h_u *value);
sw_error_t
cppe_lpbk_mib_drop_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkdropcounter_u *value);
sw_error_t
cppe_lpbk_mib_tooshort_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkttooshort_u *value);
sw_error_t
cppe_lpbk_mib_pkt14to63_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbkpkt14to63_u *value);
sw_error_t
cppe_lpbk_mib_toolongbyte_l_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbktoolongbyte_l_u *value);
sw_error_t
cppe_lpbk_mib_toolongbyte_h_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbktoolongbyte_h_u *value);
sw_error_t
cppe_lpbk_mib_tooshortbyte_l_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbktooshortbyte_l_u *value);
sw_error_t
cppe_lpbk_mib_tooshortbyte_h_get(
a_uint32_t dev_id,
a_uint32_t index,
union lpbktooshortbyte_h_u *value);
#endif

578
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_loopback_reg.h
View File

@@ -1,578 +0,0 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef CPPE_LOOPBACK_REG_H
#define CPPE_LOOPBACK_REG_H
/*[register] LPBK_ENABLE*/
#define LPBK_ENABLE
#define LPBK_ENABLE_ADDRESS 0x00
#define LPBK_ENABLE_NUM 6
#define LPBK_ENABLEL_INC 0x200
#define LPBK_ENABLE_TYPE REG_TYPE_RW
#define LPBK_ENABLE_DEFAULT 0x0
/*[field] LPBK_EN*/
#define LPBK_EN_LPBK_EN
#define LPBK_EN_LPBK_EN_OFFSET 0
#define LPBK_EN_LPBK_EN_LEN 1
#define LLPBK_EN_LPBK_EN_DEFAULT 0x0
/*[field] FLOWCTRL_EN*/
#define LPBK_ENABLE_FLOWCTRL_EN
#define LPBK_ENABLE_FLOWCTRL_EN_OFFSET 1
#define LPBK_ENABLE_FLOWCTRL_EN_LEN 1
#define LPBK_ENABLE_FLOWCTRL_EN_DEFAULT 0x1
/*[field] FLOWCTRL_MODE*/
#define LPBK_EN_FLOWCTRL_MODE
#define LPBK_EN_FLOWCTRL_MODE_OFFSET 2
#define LPBK_EN_FLOWCTRL_MODE_LEN 1
#define LPBK_EN_FLOWCTRL_MODE_DEFAULT 0x0
/*[field] CRC_STRIP_EN*/
#define LPBK_EN_CRC_STRIP_EN
#define LPBK_EN_CRC_STRIP_EN_OFFSET 2
#define LPBK_EN_CRC_STRIP_EN_LEN 1
#define LPBK_EN_CRC_STRIP_EN_DEFAULT 0x1
struct lpbk_enable {
a_uint32_t lpbk_en:1;
a_uint32_t flowctrl_en :1;
a_uint32_t flowctrl_mode:1;
a_uint32_t crc_strip_en:1;
a_uint32_t _reserved0:28;
};
union lpbk_enable_u {
a_uint32_t val;
struct lpbk_enable bf;
};
/*[register] LPBK_FIFO_1_CTRL*/
#define LPBK_FIFO_1_CTRL
#define LPBK_FIFO_1_CTRL_ADDRESS 0x04
#define LPBK_FIFO_1_CTRL_NUM 6
#define LPBK_FIFO_1_CTRL_INC 0x200
#define LPBK_FIFO_1_CTRL_TYPE REG_TYPE_RW
#define LPBK_FIFO_1_CTRL_DEFAULT 0x3
/*[field] LPBK_FIFO_1_THRESHOLD*/
#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD
#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_OFFSET 0
#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_LEN 3
#define LPBK_FIFO_1_CTRL_LPBK_FIFO_1_THRESHOLD_DEFAULT 0x0
struct lpbk_fifo_1_ctrl {
a_uint32_t lpbk_fifo_1_threshold:3;
a_uint32_t _reserved0:29;
};
union lpbk_fifo_1_ctrl_u {
a_uint32_t val;
struct lpbk_fifo_1_ctrl bf;
};
/*[register] LPBK_FIFO_2_CTRL*/
#define LPBK_FIFO_2_CTRL
#define LPBK_FIFO_2_CTRL_ADDRESS 0x08
#define LPBK_FIFO_2_CTRL_NUM 6
#define LPBK_FIFO_2_CTRL_INC 0x200
#define LPBK_FIFO_2_CTRL_TYPE REG_TYPE_RW
#define LPBK_FIFO_2_CTRL_DEFAULT 0x1
/*[field] LPBK_FIFO_2_THRESHOLD*/
#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD
#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_OFFSET 0
#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_LEN 3
#define LPBK_FIFO_2_CTRL_LPBK_FIFO_2_THRESHOLD_DEFAULT 0x0
struct lpbk_fifo_2_ctrl {
a_uint32_t lpbk_fifo_2_threshold:3;
a_uint32_t _reserved0:29;
};
union lpbk_fifo_2_ctrl_u {
a_uint32_t val;
struct lpbk_fifo_2_ctrl bf;
};
/*[register] LPBK_PPS_CTRL*/
#define LPBK_PPS_CTRL
#define LPBK_PPS_CTRL_ADDRESS 0x0c
#define LPBK_PPS_CTRL_NUM 6
#define LPBK_PPS_CTRL_INC 0x200
#define LPBK_PPS_CTRL_TYPE REG_TYPE_RW
#define LPBK_PPS_CTRL_DEFAULT 0x0
/*[field] LPBK_PPS_THRESHOLD*/
#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD
#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_OFFSET 0
#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_LEN 9
#define LPBK_PPS_CTRL_LPBK_PPS_THRESHOLD_DEFAULT 0x16
struct lpbk_pps_ctrl {
a_uint32_t lpbk_pps_threshold:9;
a_uint32_t _reserved0:13;
};
union lpbk_pps_ctrl_u {
a_uint32_t val;
struct lpbk_pps_ctrl bf;
};
/*[register] LPBK_MAC_JUNMO_SIZE*/
#define LPBK_MAC_JUNMO_SIZE
#define LPBK_MAC_JUNMO_SIZE_ADDRESS 0x10
#define LPBK_MAC_JUNMO_SIZE_NUM 6
#define LPBK_MAC_JUNMO_SIZE_INC 0x200
#define LPBK_MAC_JUNMO_SIZE_TYPE REG_TYPE_RW
#define LPBK_MAC_JUNMO_SIZE_DEFAULT 0x0
/*[field] LPBK_MAC_JUMBO_SIZE*/
#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE
#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_OFFSET 0
#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_LEN 14
#define LPBK_MAC_JUNMO_SIZE_LPBK_MAC_JUMBO_SIZE_DEFAULT 0x5EA
struct lpbk_mac_junmo_size {
a_uint32_t lpbk_mac_jumbo_size:14;
a_uint32_t _reserved0:18;
};
union lpbk_mac_junmo_size_u {
a_uint32_t val;
struct lpbk_mac_junmo_size bf;
};
/*[register] LPBK_MIB_CTRL*/
#define LPBK_MIB_CTRL
#define LPBK_MIB_CTRL_ADDRESS 0x14
#define LPBK_MIB_CTRL_NUM 6
#define LPBK_MIB_CTRL_INC 0x200
#define LPBK_MIB_CTRL_TYPE REG_TYPE_RW
#define LPBK_MIB_CTRL_DEFAULT 0x0
/*[field] MIB_EN*/
#define LPBK_MIB_CTRL_MIB_EN
#define LPBK_MIB_CTRL_MIB_EN_OFFSET 0
#define LPBK_MIB_CTRL_MIB_EN_LEN 1
#define LPBK_MIB_CTRL_MIB_EN_DEFAULT 0x1
/*[field] MIB_RESET*/
#define LPBK_MIB_CTRL_MIB_RESET
#define LPBK_MIB_CTRL_MIB_RESET_OFFSET 1
#define LPBK_MIB_CTRL_MIB_RESET_LEN 1
#define LPBK_MIB_CTRL_MIB_RESET_DEFAULT 0x0
/*[field] MIB_RD_CLR*/
#define LPBK_MIB_CTRL_MIB_RD_CLR
#define LPBK_MIB_CTRL_MIB_RD_CLR_OFFSET 2
#define LPBK_MIB_CTRL_MIB_RD_CLR_LEN 1
#define LPBK_MIB_CTRL_MIB_RD_CLR_DEFAULT 0x0
struct lpbk_mib_ctrl {
a_uint32_t mib_en:1;
a_uint32_t mib_reset:1;
a_uint32_t mib_rd_clr:1;
a_uint32_t _reserved0:29;
};
union lpbk_mib_ctrl_u {
a_uint32_t val;
struct lpbk_mib_ctrl bf;
};
/*[register] LPBKUNI*/
#define LPBKUNI
#define LPBKUNI_ADDRESS 0x20
#define LPBKUNI_NUM 6
#define LPBKUNI_INC 0x200
#define LPBKUNI_TYPE REG_TYPE_RO
#define LPBKUNI_DEFAULT 0x0
/*[field] LPBKUNI*/
#define LPBKUNI_LPBKUNI
#define LPBKUNI_LPBKUNI_OFFSET 0
#define LPBKUNI_LPBKUNI_LEN 32
#define LPBKUNI_LPBKUNI_DEFAULT 0x0
struct lpbkuni {
a_uint32_t lpbkuni:32;
};
union lpbkuni_u {
a_uint32_t val;
struct lpbkuni bf;
};
/*[register] LPBKMULTI*/
#define LPBKMULTI
#define LPBKMULTI_ADDRESS 0x24
#define LPBKMULTI_NUM 6
#define LPBKMULTI_INC 0x200
#define LPBKMULTI_TYPE REG_TYPE_RO
#define LPBKMULTI_DEFAULT 0x0
/*[field] LPBKMULTI*/
#define LPBKMULTI_LPBKMULTI
#define LPBKMULTI_LPBKMULTI_OFFSET 0
#define LPBKMULTI_LPBKMULTI_LEN 32
#define LPBKMULTI_LPBKMULTI_DEFAULT 0x0
struct lpbkmulti {
a_uint32_t lpbkmulti:32;
};
union lpbkmulti_u {
a_uint32_t val;
struct lpbkmulti bf;
};
/*[register] LPBKBROAD*/
#define LPBKBROAD
#define LPBKBROAD_ADDRESS 0x28
#define LPBKBROAD_NUM 6
#define LPBKBROAD_INC 0x200
#define LPBKBROAD_TYPE REG_TYPE_RO
#define LPBKBROAD_DEFAULT 0x0
/*[field] LPBK_BROAD*/
#define LPBKBROAD_LPBKBROAD
#define LPBKBROAD_LPBKBROAD_OFFSET 0
#define LPBKBROAD_LPBKBROAD_LEN 32
#define LPBKBROAD_LPBKBROAD_DEFAULT 0x0
struct lpbkbroad {
a_uint32_t lpbkbroad:32;
};
union lpbkbroad_u {
a_uint32_t val;
struct lpbkbroad bf;
};
/*[register] LPBKPKT64*/
#define LPBKPKT64
#define LPBKPKT64_ADDRESS 0x2c
#define LPBKPKT64_NUM 6
#define LPBKPKT64_INC 0x200
#define LPBKPKT64_TYPE REG_TYPE_RO
#define LPBKPKT64_DEFAULT 0x0
/*[field] LPBKPKT64*/
#define LPBKPKT64_LPBKPKT64
#define LPBKPKT64_LPBKPKT64_OFFSET 0
#define LPBKPKT64_LPBKPKT64_LEN 32
#define LPBKPKT64_LPBKPKT64_DEFAULT 0x0
struct lpbkpkt64 {
a_uint32_t lpbkpkt64:32;
};
union lpbkpkt64_u {
a_uint32_t val;
struct lpbkpkt64 bf;
};
/*[register] LPBKPKT65TO127*/
#define LPBKPKT65TO127
#define LPBKPKT65TO127_ADDRESS 0x30
#define LPBKPKT65TO127_NUM 6
#define LPBKPKT65TO127_INC 0x200
#define LPBKPKT65TO127_TYPE REG_TYPE_RO
#define LPBKPKT65TO1277_DEFAULT 0x0
/*[field] LPBKPKT65TO127*/
#define LPBKPKT65TO127_LPBKPKT65TO127
#define LPBKPKT65TO127_LPBKPKT65TO127_OFFSET 0
#define LPBKPKT65TO127_LPBKPKT65TO127_LEN 32
#define LPBKPKT65TO127_LPBKPKT65TO127_DEFAULT 0x0
struct lpbkpkt65to127 {
a_uint32_t lpbkpkt65to127:32;
};
union lpbkpkt65to127_u {
a_uint32_t val;
struct lpbkpkt65to127 bf;
};
/*[register] LPBKPKT128TO255*/
#define LPBKPKT128TO255
#define LPBKPKT128TO255_ADDRESS 0x34
#define LPBKPKT128TO255_NUM 6
#define LPBKPKT128TO255_INC 0x200
#define LPBKPKT128TO255_TYPE REG_TYPE_RO
#define LPBKPKT128TO255_DEFAULT 0x0
/*[field] LPBKPKT128TO255*/
#define LPBKPKT128TO255_LPBKPKT128TO255
#define LPBKPKT128TO255_LPBKPKT128TO255_OFFSET 0
#define LPBKPKT128TO255_LPBKPKT128TO255_LEN 32
#define LPBKPKT128TO255_LPBKPKT128TO255_DEFAULT 0x0
struct lpbkpkt128to255 {
a_uint32_t lpbkpkt128to255:32;
};
union lpbkpkt128to255_u {
a_uint32_t val;
struct lpbkpkt128to255 bf;
};
/*[register] LPBKPKT256TO511*/
#define LPBKPKT256TO511
#define LPBKPKT256TO511_ADDRESS 0x38
#define LPBKPKT256TO511_NUM 6
#define LPBKPKT256TO511_INC 0x200
#define LPBKPKT256TO511_TYPE REG_TYPE_RO
#define LPBKPKT256TO511_DEFAULT 0x0
/*[field] LPBKPKT256TO511*/
#define LPBKPKT256TO511_LPBKPKT256TO511
#define LPBKPKT256TO511_LPBKPKT256TO511_OFFSET 0
#define LPBKPKT256TO511_LPBKPKT256TO511_LEN 32
#define LPBKPKT256TO511_LPBKPKT256TO511_DEFAULT 0x0
struct lpbkpkt256to511 {
a_uint32_t lpbkpkt256to511:32;
};
union lpbkpkt256to511_u {
a_uint32_t val;
struct lpbkpkt256to511 bf;
};
/*[register] LPBKPKT512TO1023*/
#define LPBKPKT512TO1023
#define LPBKPKT512TO1023_ADDRESS 0x3c
#define LPBKPKT512TO1023_NUM 6
#define LPBKPKT512TO1023_INC 0x200
#define LPBKPKT512TO1023_TYPE REG_TYPE_RO
#define LPBKPKT512TO1023_DEFAULT 0x0
/*[field] LPBKPKT512TO1023*/
#define LPBKPKT512TO1023_LPBKPKT512TO1023
#define LPBKPKT512TO1023_LPBKPKT512TO1023_OFFSET 0
#define LPBKPKT512TO1023_LPBKPKT512TO1023_LEN 32
#define LPBKPKT512TO1023_LPBKPKT512TO1023_DEFAULT 0x0
struct lpbkpkt512to1023 {
a_uint32_t lpbkpkt512to1023:32;
};
union lpbkpkt512to1023_u {
a_uint32_t val;
struct lpbkpkt512to1023 bf;
};
/*[register] LPBKPKT1024TO1518*/
#define LPBKPKT1024TO1518
#define LPBKPKT1024TO1518_ADDRESS 0x40
#define LPBKPKT1024TO1518_NUM 6
#define LPBKPKT1024TO1518_INC 0x200
#define LPBKPKT1024TO1518_TYPE REG_TYPE_RO
#define LPBKPKT1024TO1518_DEFAULT 0x0
/*[field] RXPKT1024TO1518*/
#define LPBKPKT1024TO1518_LPBKPKT1024TO1518
#define LPBKPKT1024TO1518_OFFSET 0
#define LPBKPKT1024TO1518_LEN 32
#define LPBKPKT1024TO1518_DEFAULT 0x0
struct lpbkpkt1024to1518 {
a_uint32_t lpbkpkt1024to1518:32;
};
union lpbkpkt1024to1518_u {
a_uint32_t val;
struct lpbkpkt1024to1518 bf;
};
/*[register] LPBKPKT1519TOX*/
#define LPBKPKT1519TOX
#define LPBKPKT1519TOX_ADDRESS 0x44
#define LPBKPKT1519TOX_NUM 6
#define LPBKPKT1519TOX_INC 0x200
#define LPBKPKT1519TOX_TYPE REG_TYPE_RO
#define LPBKPKT1519TOX_DEFAULT 0x0
/*[field] RXPKT1519TOX*/
#define LPBKPKT1519TOX_LPBKPKT1519TOX
#define LPBKPKT1519TOX_LPBKPKT1519TOX_OFFSET 0
#define LPBKPKT1519TOX_LPBKPKT1519TOX_LEN 32
#define LPBKPKT1519TOX_LPBKPKT1519TOX_DEFAULT 0x0
struct lpbkpkt1519tox {
a_uint32_t lpbkpkt1519tox:32;
};
union lpbkpkt1519tox_u {
a_uint32_t val;
struct lpbkpkt1519tox bf;
};
/*[register] LPBKPKTTOOLONG*/
#define LPBKPKTTOOLONG
#define LPBKPKTTOOLONG_ADDRESS 0x48
#define LPBKPKTTOOLONG_NUM 6
#define LPBKPKTTOOLONG_INC 0x200
#define LPBKPKTTOOLONG_TYPE REG_TYPE_RO
#define LPBKPKTTOOLONG_DEFAULT 0x0
/*[field] RXTOOLONG*/
#define LPBKPKTTOOLONG_LPBKPKTTOOLONG
#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_OFFSET 0
#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_LEN 32
#define LPBKPKTTOOLONG_LPBKPKTTOOLONG_DEFAULT 0x0
struct lpbkpkttoolong {
a_uint32_t lpbkpkttoolong:32;
};
union lpbkpkttoolong_u {
a_uint32_t val;
struct lpbkpkttoolong bf;
};
/*[register] LPBKBYTE_L*/
#define LPBKBYTE_L
#define LPBKBYTE_L_ADDRESS 0x4c
#define LPBKBYTE_L_NUM 6
#define LPBKBYTE_L_INC 0x200
#define LPBKBYTE_L_TYPE REG_TYPE_RO
#define LPBKBYTE_L_DEFAULT 0x0
/*[field] LPBKBYTE_L*/
#define LPBKBYTE_L_LPBKBYTE_L
#define LPBKBYTE_L_LPBKBYTE_L_OFFSET 0
#define LPBKBYTE_L_LPBKBYTE_L_LEN 32
#define LPBKBYTE_L_LPBKBYTE_L_DEFAULT 0x0
struct lpbkbyte_l {
a_uint32_t lpbkbyte_l:32;
};
union lpbkbyte_l_u {
a_uint32_t val;
struct lpbkbyte_l bf;
};
/*[register] LPBKBYTE_H*/
#define LPBKBYTE_H
#define LPBKBYTE_H_ADDRESS 0x50
#define LPBKBYTE_H_NUM 6
#define LPBKBYTE_H_INC 0x200
#define LPBKBYTE_H_TYPE REG_TYPE_RO
#define LPBKBYTE_H_DEFAULT 0x0
/*[field] LPBKBYTE_H*/
#define LPBKBYTE_H_LPBKBYTE_H
#define LPBKBYTE_H_LPBKBYTE_H_OFFSET 0
#define LPBKBYTE_H_LPBKBYTE_H_LEN 32
#define LPBKBYTE_H_LPBKBYTE_H_DEFAULT 0x0
struct lpbkbyte_h {
a_uint32_t lpbkbyte_h:32;
};
union lpbkbyte_h_u {
a_uint32_t val;
struct lpbkbyte_h bf;
};
/*[register] LPBKDROPCOUNTER*/
#define LPBKDROPCOUNTER
#define LPBKDROPCOUNTER_ADDRESS 0x54
#define LPBKDROPCOUNTER_NUM 6
#define LPBKDROPCOUNTER_INC 0x200
#define LPBKDROPCOUNTER_TYPE REG_TYPE_RO
#define LPBKDROPCOUNTER_DEFAULT 0x0
/*[field] LPBKDROPCOUNTER*/
#define LPBKDROPCOUNTER_LPBKDROPCOUNTER
#define LPBKDROPCOUNTER_OFFSET 0
#define LPBKDROPCOUNTER_LEN 32
#define LPBKDROPCOUNTER_DEFAULT 0x0
struct lpbkdropcounter {
a_uint32_t lpbkdropcounter:32;
};
union lpbkdropcounter_u {
a_uint32_t val;
struct lpbkdropcounter bf;
};
/*[register] LPBKTOOSHORT*/
#define LPBKPKTTOOSHORT
#define LPBKPKTTOOSHORT_ADDRESS 0x68
#define LPBKPKTTOOSHORT_NUM 6
#define LPBKPKTTOOSHORT_INC 0x200
#define LPBKPKTTOOSHORT_TYPE REG_TYPE_RO
#define LPBKPKTTOOSHORT_DEFAULT 0x0
/*[field] LPBKPKTTOOSHORT*/
#define LPBKPKTTOOSHORT_LPBKPKTTOOSHORT
#define LPBKPKTTOOSHORT_OFFSET 0
#define LPBKPKTTOOSHORT_LEN 32
#define LPBKPKTTOOSHORT_DEFAULT 0x0
struct lpbkpkttooshort {
a_uint32_t lpbkpkttooshort:32;
};
union lpbkpkttooshort_u {
a_uint32_t val;
struct lpbkpkttooshort bf;
};
/*[register] LPBKPKT14TO63*/
#define LPBKPKT14TO63
#define LPBKPKT14TO63_ADDRESS 0x6c
#define LPBKPKT14TO63_NUM 6
#define LPBKPKT14TO63_INC 0x200
#define LPBKPKT14TO63_TYPE REG_TYPE_RO
#define LPBKPKT14TO63_DEFAULT 0x0
/*[field] LPBKPKT14TO63*/
#define LPBKPKT14TO63_LPBKPKT14TO63
#define LPBKPKT14TO63_OFFSET 0
#define LPBKPKT14TO63_LEN 32
#define LPBKPKT14TO63_DEFAULT 0x0
struct lpbkpkt14to63 {
a_uint32_t lpbkpkt14to63:32;
};
union lpbkpkt14to63_u {
a_uint32_t val;
struct lpbkpkt14to63 bf;
};
/*[register] LPBKTOOLONGBYTE_L*/
#define LPBKTOOLONGBYTE_L
#define LPBKTOOLONGBYTE_L_ADDRESS 0x70
#define LPBKTOOLONGBYTE_L_NUM 6
#define LPBKTOOLONGBYTE_L_INC 0x200
#define LPBKTOOLONGBYTE_L_TYPE REG_TYPE_RO
#define LPBKTOOLONGBYTE_L_DEFAULT 0x0
/*[field] LPBKTOOLONGBYTE_L*/
#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L
#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_OFFSET 0
#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_LEN 32
#define LPBKTOOLONGBYTE_L_LPBKTOOLONGBYTE_L_DEFAULT 0x0
struct lpbktoolongbyte_l {
a_uint32_t lpbktoolongbyte_l:32;
};
union lpbktoolongbyte_l_u {
a_uint32_t val;
struct lpbktoolongbyte_l bf;
};
/*[register] LPBKTOOLONGBYTE_H*/
#define LPBKTOOLONGBYTE_H
#define LPBKTOOLONGBYTE_H_ADDRESS 0x74
#define LPBKTOOLONGBYTE_H_NUM 6
#define LPBKTOOLONGBYTE_H_INC 0x200
#define LPBKTOOLONGBYTE_H_TYPE REG_TYPE_RO
#define LPBKTOOLONGBYTE_H_DEFAULT 0x0
/*[field] LPBKTOOLONGBYTE_L*/
#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H
#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_OFFSET 0
#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_LEN 32
#define LPBKTOOLONGBYTE_H_LPBKTOOLONGBYTE_H_DEFAULT 0x0
struct lpbktoolongbyte_h {
a_uint32_t lpbktoolongbyte_h:32;
};
union lpbktoolongbyte_h_u {
a_uint32_t val;
struct lpbktoolongbyte_h bf;
};
/*[register] LPBKTOOSHORTBYTE_L*/
#define LPBKTOOSHORTBYTE_L
#define LPBKTOOSHORTBYTE_L_ADDRESS 0x78
#define LPBKTOOSHORTBYTE_L_NUM 6
#define LPBKTOOSHORTBYTE_L_INC 0x200
#define LPBKTOOLONGBYTE_L_TYPE REG_TYPE_RO
#define LPBKTOOLONGBYTE_L_DEFAULT 0x0
/*[field] LPBKTOOLONGBYTE_L*/
#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L
#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_OFFSET 0
#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_LEN 32
#define LPBKTOOSHORTBYTE_L_LPBKTOOSHORTBYTE_L_DEFAULT 0x0
struct lpbktooshortbyte_l {
a_uint32_t lpbktooshortbyte_l:32;
};
union lpbktooshortbyte_l_u {
a_uint32_t val;
struct lpbktooshortbyte_l bf;
};
/*[register] LPBKTOOSHORTBYTE_H*/
#define LPBKTOOSHORTBYTE_H
#define LPBKTOOSHORTBYTE_H_ADDRESS 0x7c
#define LPBKTOOSHORTBYTE_H_NUM 6
#define LPBKTOOSHORTBYTE_H_INC 0x200
#define LPBKTOOSHORTBYTE_H_TYPE REG_TYPE_RO
#define LPBKTOOSHORTBYTE_H_DEFAULT 0x0
/*[field] LPBKTOOLONGBYTE_L*/
#define LPBKTOOSHORTBYTE_H_LPBKTOOSHORTBYTE_H
#define LPBKTOOSHORTBYTE_H_OFFSET 0
#define LPBKTOOSHORTBYTE_H_LEN 32
#define LPBKTOOSHORTBYTE_H_DEFAULT 0x0
struct lpbktooshortbyte_h {
a_uint32_t lpbktooshortbyte_h:32;
};
union lpbktooshortbyte_h_u {
a_uint32_t val;
struct lpbktooshortbyte_h bf;
};
#endif

204
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl.h
View File

@@ -1,204 +0,0 @@
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _CPPE_PORTCTRL_H_
#define _CPPE_PORTCTRL_H_
#include "cppe_portctrl_reg.h"
#define CPPE_MRU_MTU_CTRL_TBL_MAX_ENTRY 256
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_res_prec_force_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_qos_group_id_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pcp_res_prec_force_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_post_acl_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_preheader_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_preheader_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_pre_acl_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_flow_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_flow_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_dscp_qos_group_id_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_src_profile_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_src_profile_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_source_filter_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_source_filter_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_source_filter_mode_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_source_filter_mode_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_get(
a_uint32_t dev_id,
a_uint32_t index,
union cppe_mru_mtu_ctrl_tbl_u *value);
sw_error_t
cppe_mru_mtu_ctrl_tbl_set(
a_uint32_t dev_id,
a_uint32_t index,
union cppe_mru_mtu_ctrl_tbl_u *value);
sw_error_t
cppe_port_phy_status_1_get(
a_uint32_t dev_id,
union cppe_port_phy_status_1_u *value);
sw_error_t
cppe_port5_pcs1_phy_status_get(
a_uint32_t dev_id,
unsigned int *value);
#endif

166
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_portctrl_reg.h
View File

@@ -1,166 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _CPPE_PORTCTRL_REG_H_
#define _CPPE_PORTCTRL_REG_H_
/*[table] CPPE_MRU_MTU_CTRL_TBL*/
#define CPPE_MRU_MTU_CTRL_TBL
#define CPPE_MRU_MTU_CTRL_TBL_ADDRESS 0x3000
#define CPPE_MRU_MTU_CTRL_TBL_NUM 256
#define CPPE_MRU_MTU_CTRL_TBL_INC 0x10
#define CPPE_MRU_MTU_CTRL_TBL_TYPE REG_TYPE_RW
#define CPPE_MRU_MTU_CTRL_TBL_DEFAULT 0x0
/*[field] MRU*/
#define CPPE_MRU_MTU_CTRL_TBL_MRU
#define CPPE_MRU_MTU_CTRL_TBL_MRU_OFFSET 0
#define CPPE_MRU_MTU_CTRL_TBL_MRU_LEN 14
#define CPPE_MRU_MTU_CTRL_TBL_MRU_DEFAULT 0x0
/*[field] MRU_CMD*/
#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD
#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_OFFSET 14
#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_LEN 2
#define CPPE_MRU_MTU_CTRL_TBL_MRU_CMD_DEFAULT 0x0
/*[field] MTU*/
#define CPPE_MRU_MTU_CTRL_TBL_MTU
#define CPPE_MRU_MTU_CTRL_TBL_MTU_OFFSET 16
#define CPPE_MRU_MTU_CTRL_TBL_MTU_LEN 14
#define CPPE_MRU_MTU_CTRL_TBL_MTU_DEFAULT 0x0
/*[field] MTU_CMD*/
#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD
#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_OFFSET 30
#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_LEN 2
#define CPPE_MRU_MTU_CTRL_TBL_MTU_CMD_DEFAULT 0x0
/*[field] RX_CNT_EN*/
#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN
#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_OFFSET 32
#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_RX_CNT_EN_DEFAULT 0x0
/*[field] TX_CNT_EN*/
#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN
#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_OFFSET 33
#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_TX_CNT_EN_DEFAULT 0x0
/*[field] SRC_PROFILE*/
#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE
#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_OFFSET 34
#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_LEN 2
#define CPPE_MRU_MTU_CTRL_TBL_SRC_PROFILE_DEFAULT 0x0
/*[field] PCP_QOS_GROUP_ID*/
#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID
#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_OFFSET 36
#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_PCP_QOS_GROUP_ID_DEFAULT 0x0
/*[field] DSCP_QOS_GROUP_ID*/
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_OFFSET 37
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_QOS_GROUP_ID_DEFAULT 0x0
/*[field] PCP_RES_PREC_FORCE*/
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_OFFSET 38
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_FORCE_DEFAULT 0x0
/*[field] DSCP_RES_PREC_FORCE*/
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_OFFSET 39
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_FORCE_DEFAULT 0x0
/*[field] PREHEADER_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_OFFSET 40
#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_PREHEADER_RES_PREC_DEFAULT 0x0
/*[field] PCP_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_OFFSET 43
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_PCP_RES_PREC_DEFAULT 0x0
/*[field] DSCP_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_OFFSET 46
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_DSCP_RES_PREC_DEFAULT 0x0
/*[field] FLOW_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_OFFSET 49
#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_FLOW_RES_PREC_DEFAULT 0x0
/*[field] PRE_ACL_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_OFFSET 52
#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_PRE_ACL_RES_PREC_DEFAULT 0x0
/*[field] POST_ACL_RES_PREC*/
#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC
#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_OFFSET 55
#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_LEN 3
#define CPPE_MRU_MTU_CTRL_TBL_POST_ACL_RES_PREC_DEFAULT 0x0
/*[field] SOURCE_FILTERING_BYPASS*/
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_OFFSET 58
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_BYPASS_DEFAULT 0x0
/*[field] SOURCE_FILTERING_MODE*/
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_OFFSET 59
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_LEN 1
#define CPPE_MRU_MTU_CTRL_TBL_SOURCE_FILTERING_MODE_DEFAULT 0x0
struct cppe_mru_mtu_ctrl_tbl {
a_uint32_t mru:14;
a_uint32_t mru_cmd:2;
a_uint32_t mtu:14;
a_uint32_t mtu_cmd:2;
a_uint32_t rx_cnt_en:1;
a_uint32_t tx_cnt_en:1;
a_uint32_t src_profile:2;
a_uint32_t pcp_qos_group_id:1;
a_uint32_t dscp_qos_group_id:1;
a_uint32_t pcp_res_prec_force:1;
a_uint32_t dscp_res_prec_force:1;
a_uint32_t preheader_res_prec:3;
a_uint32_t pcp_res_prec:3;
a_uint32_t dscp_res_prec:3;
a_uint32_t flow_res_prec:3;
a_uint32_t pre_acl_res_prec:3;
a_uint32_t post_acl_res_prec:3;
a_uint32_t source_filtering_bypass:1;
a_uint32_t source_filtering_mode:1;
a_uint32_t _reserved0:4;
};
union cppe_mru_mtu_ctrl_tbl_u {
a_uint32_t val[2];
struct cppe_mru_mtu_ctrl_tbl bf;
};
struct cppe_port_phy_status_1 {
a_uint32_t port5_pcs0_phy_status:8;
a_uint32_t port4_pcs0_phy_status:8;
a_uint32_t port5_pcs1_phy_status:8;
a_uint32_t _reserved0:8;
};
union cppe_port_phy_status_1_u {
a_uint32_t val;
struct cppe_port_phy_status_1 bf;
};
#endif

186
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos.h
View File

@@ -1,186 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _CPPE_QOS_H_
#define _CPPE_QOS_H_
#define QOS_MAPPING_TBL_MAX_ENTRY 2592
#define QOS_MAPPING_FLOW_TBL_MAX_ENTRY 2048
#define QOS_MAPPING_DSCP_TBL_MAX_ENTRY 256
#define QOS_MAPPING_PCP_TBL_MAX_ENTRY 16
#define QOS_MAPPING_TBL_MAX_GROUP 2
sw_error_t
cppe_qos_mapping_tbl_get(
a_uint32_t dev_id,
a_uint32_t index,
union qos_mapping_tbl_u *value);
sw_error_t
cppe_qos_mapping_tbl_set(
a_uint32_t dev_id,
a_uint32_t index,
union qos_mapping_tbl_u *value);
sw_error_t
cppe_qos_mapping_tbl_int_pcp_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_pcp_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dei_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dei_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dei_en_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dei_en_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_dscp_tc_mask_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_dscp_tc_mask_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dscp_tc_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dscp_tc_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dp_en_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dp_en_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dp_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dp_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_pri_en_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_pri_en_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_qos_res_prec_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_qos_res_prec_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_pcp_en_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_pcp_en_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_pri_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_pri_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
sw_error_t
cppe_qos_mapping_tbl_int_dscp_en_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
cppe_qos_mapping_tbl_int_dscp_en_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
#endif

113
feeds/ipq807x/qca-ssdk/src/include/hsl/cppe/cppe_qos_reg.h
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@@ -1,113 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup
* @{
*/
#ifndef _CPPE_QOS_REG_H_
#define _CPPE_QOS_REG_H_
/*[table] QOS_MAPPING_TBL*/
#define QOS_MAPPING_TBL
#define QOS_MAPPING_TBL_ADDRESS 0x20000
#define QOS_MAPPING_TBL_NUM 2592
#define QOS_MAPPING_TBL_INC 0x10
#define QOS_MAPPING_TBL_TYPE REG_TYPE_RW
#define QOS_MAPPING_TBL_DEFAULT 0x0
/*[field] INT_DSCP_TC*/
#define QOS_MAPPING_TBL_INT_DSCP_TC
#define QOS_MAPPING_TBL_INT_DSCP_TC_OFFSET 0
#define QOS_MAPPING_TBL_INT_DSCP_TC_LEN 8
#define QOS_MAPPING_TBL_INT_DSCP_TC_DEFAULT 0x0
/*[field] DSCP_TC_MASK*/
#define QOS_MAPPING_TBL_DSCP_TC_MASK
#define QOS_MAPPING_TBL_DSCP_TC_MASK_OFFSET 8
#define QOS_MAPPING_TBL_DSCP_TC_MASK_LEN 8
#define QOS_MAPPING_TBL_DSCP_TC_MASK_DEFAULT 0x0
/*[field] INT_DSCP_EN*/
#define QOS_MAPPING_TBL_INT_DSCP_EN
#define QOS_MAPPING_TBL_INT_DSCP_EN_OFFSET 16
#define QOS_MAPPING_TBL_INT_DSCP_EN_LEN 1
#define QOS_MAPPING_TBL_INT_DSCP_EN_DEFAULT 0x0
/*[field] INT_PCP_EN*/
#define QOS_MAPPING_TBL_INT_PCP_EN
#define QOS_MAPPING_TBL_INT_PCP_EN_OFFSET 17
#define QOS_MAPPING_TBL_INT_PCP_EN_LEN 1
#define QOS_MAPPING_TBL_INT_PCP_EN_DEFAULT 0x0
/*[field] INT_PCP*/
#define QOS_MAPPING_TBL_INT_PCP
#define QOS_MAPPING_TBL_INT_PCP_OFFSET 18
#define QOS_MAPPING_TBL_INT_PCP_LEN 3
#define QOS_MAPPING_TBL_INT_PCP_DEFAULT 0x0
/*[field] INT_DEI_EN*/
#define QOS_MAPPING_TBL_INT_DEI_EN
#define QOS_MAPPING_TBL_INT_DEI_EN_OFFSET 21
#define QOS_MAPPING_TBL_INT_DEI_EN_LEN 1
#define QOS_MAPPING_TBL_INT_DEI_EN_DEFAULT 0x0
/*[field] INT_DEI*/
#define QOS_MAPPING_TBL_INT_DEI
#define QOS_MAPPING_TBL_INT_DEI_OFFSET 22
#define QOS_MAPPING_TBL_INT_DEI_LEN 1
#define QOS_MAPPING_TBL_INT_DEI_DEFAULT 0x0
/*[field] INT_PRI_EN*/
#define QOS_MAPPING_TBL_INT_PRI_EN
#define QOS_MAPPING_TBL_INT_PRI_EN_OFFSET 23
#define QOS_MAPPING_TBL_INT_PRI_EN_LEN 1
#define QOS_MAPPING_TBL_INT_PRI_EN_DEFAULT 0x0
/*[field] INT_PRI*/
#define QOS_MAPPING_TBL_INT_PRI
#define QOS_MAPPING_TBL_INT_PRI_OFFSET 24
#define QOS_MAPPING_TBL_INT_PRI_LEN 4
#define QOS_MAPPING_TBL_INT_PRI_DEFAULT 0x0
/*[field] INT_DP_EN*/
#define QOS_MAPPING_TBL_INT_DP_EN
#define QOS_MAPPING_TBL_INT_DP_EN_OFFSET 28
#define QOS_MAPPING_TBL_INT_DP_EN_LEN 1
#define QOS_MAPPING_TBL_INT_DP_EN_DEFAULT 0x0
/*[field] INT_DP*/
#define QOS_MAPPING_TBL_INT_DP
#define QOS_MAPPING_TBL_INT_DP_OFFSET 29
#define QOS_MAPPING_TBL_INT_DP_LEN 2
#define QOS_MAPPING_TBL_INT_DP_DEFAULT 0x0
/*[field] QOS_RES_PREC*/
#define QOS_MAPPING_TBL_QOS_RES_PREC
#define QOS_MAPPING_TBL_QOS_RES_PREC_OFFSET 31
#define QOS_MAPPING_TBL_QOS_RES_PREC_LEN 3
#define QOS_MAPPING_TBL_QOS_RES_PREC_DEFAULT 0x0
struct qos_mapping_tbl {
a_uint32_t int_dscp_tc:8;
a_uint32_t dscp_tc_mask:8;
a_uint32_t int_dscp_en:1;
a_uint32_t int_pcp_en:1;
a_uint32_t int_pcp:3;
a_uint32_t int_dei_en:1;
a_uint32_t int_dei:1;
a_uint32_t int_pri_en:1;
a_uint32_t int_pri:4;
a_uint32_t int_dp_en:1;
a_uint32_t int_dp:2;
a_uint32_t qos_res_prec_0:1;
a_uint32_t qos_res_prec_1:2;
a_uint32_t _reserved0:30;
};
union qos_mapping_tbl_u {
a_uint32_t val[2];
struct qos_mapping_tbl bf;
};
#endif

144
feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_acl.h
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@@ -1,144 +0,0 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* @defgroup dess_acl DESS_ACL
* @{
*/
#ifndef _DESS_ACL_H_
#define _DESS_ACL_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "fal/fal_acl.h"
sw_error_t dess_acl_init(a_uint32_t dev_id);
sw_error_t dess_acl_reset(a_uint32_t dev_id);
sw_error_t dess_acl_cleanup(a_uint32_t dev_id);
#ifdef IN_ACL
#define DESS_ACL_INIT(rv, dev_id) \
{ \
rv = dess_acl_init(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#define DESS_ACL_RESET(rv, dev_id) \
{ \
rv = dess_acl_reset(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#define DESS_ACL_CLEANUP(rv, dev_id) \
{ \
rv = dess_acl_cleanup(dev_id); \
SW_RTN_ON_ERROR(rv); \
}
#else
#define DESS_ACL_INIT(rv, dev_id)
#define DESS_ACL_RESET(rv, dev_id)
#define DESS_ACL_CLEANUP(rv, dev_id)
#endif
sw_error_t
dess_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t list_pri);
sw_error_t
dess_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t rule_id, a_uint32_t rule_nr,
fal_acl_rule_t * rule);
sw_error_t
dess_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t rule_id, a_uint32_t rule_nr);
a_uint32_t
dess_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
sw_error_t
dess_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
a_uint32_t obj_idx);
sw_error_t
dess_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
a_uint32_t obj_idx);
sw_error_t
dess_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
sw_error_t
dess_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t rule_id, fal_acl_rule_t * rule);
sw_error_t
dess_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
#ifdef HSL_STANDALONG
HSL_LOCAL sw_error_t
dess_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
HSL_LOCAL sw_error_t
dess_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
HSL_LOCAL sw_error_t
dess_acl_list_dump(a_uint32_t dev_id);
HSL_LOCAL sw_error_t
dess_acl_rule_dump(a_uint32_t dev_id);
HSL_LOCAL sw_error_t
dess_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
fal_acl_udf_type_t udf_type,
a_uint32_t offset, a_uint32_t length);
HSL_LOCAL sw_error_t
dess_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
fal_acl_udf_type_t udf_type,
a_uint32_t * offset, a_uint32_t * length);
HSL_LOCAL sw_error_t
dess_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t rule_id, a_uint32_t rule_nr);
HSL_LOCAL sw_error_t
dess_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
a_uint32_t rule_id, a_uint32_t rule_nr);
HSL_LOCAL sw_error_t
dess_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
a_uint32_t rule_id, a_bool_t enable);
HSL_LOCAL sw_error_t
dess_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
a_uint32_t rule_id, a_bool_t* enable);
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _DESS_ACL_H_ */
/**
* @}
*/

1174
feeds/ipq807x/qca-ssdk/src/include/hsl/dess/dess_api.h
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