Compare commits

...

8 Commits

Author SHA1 Message Date
jaspreetsachdev
dab5ebd31f Merge pull request #832 from Telecominfraproject/release-4
Release 4
2025-05-02 04:47:18 -07:00
Jaspreet Sachdev
f4d2d3d12a Merge branch 'main' into release-4 2025-05-02 07:42:57 -04:00
John Crispin
adac3818a4 ucentral-schema: update to latest HEAD
52afdf8 fix wifi-scan on wifi-7 devices

Fixes: WIFI-14541
Fixes: WIFI-14537
Signed-off-by: John Crispin <john@phrozen.org>
2025-04-30 08:03:26 +02:00
Ken
a516b035ab qca-wifi-7: WF189 10G PHY code optimization
* add "limit_rtlphy_10g_ablity" in DTS , no side effect on other product.
* disable 10G capability if DTS defined limit_rtlphy_10g_ablity , no side effect on other product.
* revert the last 0006-qca-ssdk-Fix-10G-rtl-phy-driver-for-c45-mdio-read-wr.patch and based on 0005 patch.

Fixes: WIFI-14567
Signed-off-by: Ken Shi <xshi@actiontec.com>
2025-04-29 08:25:22 +02:00
Ken
29b088ef21 qca-wifi-7: fix WF189 WAN port link issues
Fixes: WIFI-14546
Signed-off-by: Ken <xshi@actiontec.com>
2025-04-28 17:06:48 +02:00
John Crispin
10b875d42c ucentral-schema: update to latest HEAD
3b88fc1 dhcp_inject: Multiple ssids sometime didn't display dhcp option 82 rules

Fixes: WIFI-14564
Signed-off-by: John Crispin <john@phrozen.org>
2025-04-28 12:35:34 +02:00
alex18_huang
1f0a24a941 udhcpinject: Multiple ssids sometime didn't display dhcp option 82 rules
Added check when parsing ssid info retrieved from iwinfo.
Program will exit if expected interface count and iwinfo entry count mismatch.

Fixes: WIFI-14564
Signed-off-by: alex18_huang <alex18_huang@accton.com>
2025-04-28 12:33:00 +02:00
jaspreetsachdev
4c9b22f999 Merge pull request #815 from Telecominfraproject/release-4
Release 4
2025-04-11 10:58:12 -04:00
7 changed files with 159 additions and 18 deletions

View File

@@ -44,9 +44,11 @@
uniphyaddr_fixup = <0xC90F014>;
mdio_clk_fixup; /* MDIO clock sequence fix up flag */
tip,clk_div = <0xff>; /* MDIO Frequency reduction*/
limit_rtlphy_10g_ablity;
phy0: ethernet-phy@0 {
reg = <8>;
compatible ="ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {

View File

@@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include <linux/of.h>
#include "phy_rtl826xb_patch.h"
#include "phy_rtl8251b_patch.h"
@@ -30,6 +31,7 @@ static int rtl8251_match_phy_device(struct phy_device *phydev)
static int rtl826xb_get_features(struct phy_device *phydev)
{
int ret;
struct device_node *np;
ret = genphy_c45_pma_read_abilities(phydev);
if (ret)
return ret;
@@ -48,6 +50,14 @@ static int rtl826xb_get_features(struct phy_device *phydev)
linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
phydev->supported);
np = of_find_node_by_name(NULL, "mdio");
if (np)
if (of_property_read_bool(np, "limit_rtlphy_10g_ablity"))
{
linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, phydev->supported);
}
return 0;
}
@@ -80,7 +90,6 @@ static int rtkphy_config_init(struct phy_device *phydev)
case REALTEK_PHY_ID_RTL8261N:
case REALTEK_PHY_ID_RTL8264B:
phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
phy_modify_mmd_changed(phydev, 7, 0x20, BIT(12), 0);
#if 1 /* toggle reset */
phy_modify_mmd_changed(phydev, 30, 0x145, BIT(0) , 1);
@@ -213,7 +222,6 @@ static int rtkphy_c45_aneg_done(struct phy_device *phydev)
static int rtkphy_c45_read_status(struct phy_device *phydev)
{
int ret = 0, status = 0;
uint16_t local;
phydev->speed = SPEED_UNKNOWN;
phydev->duplex = DUPLEX_UNKNOWN;
phydev->pause = 0;
@@ -232,9 +240,6 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
if (ret)
return ret;
phy_write_mmd(phydev, 7, 0x20, 0x181);
local = phy_read_mmd(phydev, 7, 0x20);
status = phy_read_mmd(phydev, 31, 0xA414);
if (status < 0)
return status;
@@ -242,11 +247,6 @@ static int rtkphy_c45_read_status(struct phy_device *phydev)
phydev->lp_advertising, status & BIT(11));
phy_resolve_aneg_linkmode(phydev);
if((phydev->speed == 10000) && (local == 0x181))
{
phydev->speed = 5000;
phydev->duplex = DUPLEX_FULL;
}
}
else
{

View File

@@ -0,0 +1,116 @@
From 85a7c62d4e3385de1a379959dd45148cfdc95b3b Mon Sep 17 00:00:00 2001
From: huangyunxiang <huangyunxiang@cigtech.com>
Date: Tue, 29 Apr 2025 09:56:28 +0800
Subject: [PATCH] qca-ssdk modify rtl826x phy mdio read/write as c45 mode and
clear 10G ablity
---
src/hsl/phy/rtl826xb_phy.c | 55 ++++++-------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/src/hsl/phy/rtl826xb_phy.c b/src/hsl/phy/rtl826xb_phy.c
index a336348aa9..9a67b45948 100644
--- a/src/hsl/phy/rtl826xb_phy.c
+++ b/src/hsl/phy/rtl826xb_phy.c
@@ -48,46 +48,39 @@ void rtl826xb_phy_lock_init(void)
static a_uint16_t rtl826x_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
-
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, reg_mmd, reg_id);
}
static sw_error_t rtl826x_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_mmd, a_uint16_t reg_id, a_uint16_t reg_val)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(reg_mmd, reg_id);
-
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, reg_val);
+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, reg_mmd, reg_id, reg_val);
}
static a_uint16_t rtl826x_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg)
{
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg);
+ return hsl_phy_mii_reg_read(dev_id, phy_id, reg);
}
static sw_error_t rtl826x_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t reg, a_uint16_t reg_val)
{
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
+
+ return hsl_phy_mii_reg_write(dev_id, phy_id, reg, reg_val);
}
static a_int16_t hal_miim_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
-
- return __hsl_phy_mii_reg_read(dev_id, phy_id, reg_id_c45);
+ return hsl_phy_mmd_reg_read(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg);
}
static a_int32_t hal_miim_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t mmdAddr, a_uint16_t mmdReg, a_uint16_t phy_data)
{
- a_uint32_t reg_id_c45 = RTL826XB_REG_ADDRESS(mmdAddr, mmdReg);
-
- return __hsl_phy_mii_reg_write(dev_id, phy_id, reg_id_c45, phy_data);
+ return hsl_phy_mmd_reg_write(dev_id, phy_id, A_TRUE, mmdAddr, mmdReg, phy_data);
}
@@ -1281,34 +1274,20 @@ phy_826xb_autoNegoAbility_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t a
hsl_phy_phydev_autoneg_update(dev_id, phy_id, A_TRUE, autoneg);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 16);
+ phyData &= (~(0x0020 | 0x0040 | FAL_PHY_ADV_100TX_HD | FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE));
+ phyData |= (autoneg & FAL_PHY_ADV_100TX_HD) ? (FAL_PHY_ADV_100TX_HD) : (0);
+ phyData |= ((autoneg & FAL_PHY_ADV_100TX_FD)) ? (FAL_PHY_ADV_100TX_FD) : (0);
- phyData &= (~(0x0020 | 0x0040 | 0x0080 | 0x0100 | 0x0400 | 0x0800));
- phyData |= ((autoneg & 1 << 1)) ? (0x0040) : (0);
- phyData |= ((autoneg & 1 << 2)) ? (0x0080) : (0);
- phyData |= ((autoneg & 1 << 3)) ? (0x0100) : (0);
- phyData |= ((autoneg & 1 << 4)) ? (0x0400) : (0);
- phyData |= ((autoneg & 1 << 5)) ? (0x0800) : (0);
-// phyData |= ((autoneg & 1 << 9)) ? (0x0400) : (0);
-// phyData |= ((autoneg & 1 << 10)) ? (0x0800) : (0);
-
- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
-
+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 16, phyData);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_AN, 32);
+ phyData &= (~(FAL_PHY_ADV_2500T_FD | FAL_PHY_ADV_5000T_FD | FAL_PHY_ADV_10000T_FD));
+ phyData |= (autoneg & FAL_PHY_ADV_2500T_FD) ? (FAL_PHY_ADV_2500T_FD) : (0);
+ phyData |= (autoneg & FAL_PHY_ADV_5000T_FD) ? (FAL_PHY_ADV_5000T_FD) : (0);
- phyData &= (~(0x4000 | 0x2000 | 0x1000));
- phyData |= (autoneg & 1 << 12) ? (0x0080) : (0);
- phyData |= (autoneg & 1 << 13) ? (0x0100) : (0);
- phyData |= (autoneg & 1 << 14) ? (0x1000) : (0);
-
- phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
-
-
+ phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_AN, 32, phyData);
phyData = phy_common_general_reg_mmd_get(dev_id, phy_id, PHY_MMD_VEND2, 0xA412);
-
-
- phyData &= (~(0x0100 | 0x0200));
- phyData |= (autoneg & 1 << 9) ? (0x0200) : (0);
-// phyData |= (autoneg & 1 << 5) ? (0x0200) : (0);
+ phyData &= (~(0x0100 | FAL_PHY_ADV_1000T_FD));
+ phyData |= (autoneg & FAL_PHY_ADV_1000T_FD) ? (FAL_PHY_ADV_1000T_FD) : (0);
phy_common_general_reg_mmd_set(dev_id, phy_id, PHY_MMD_VEND2, 0xA412, phyData);
--
2.34.1

View File

@@ -4,10 +4,10 @@ PKG_NAME:=ucentral-schema
PKG_RELEASE:=1
PKG_SOURCE_URL=https://github.com/Telecominfraproject/wlan-ucentral-schema.git
PKG_MIRROR_HASH:=cd070141672c85e72001e2e36616aa7159c6dc8ca4bbacca1b61a41c145cde2f
PKG_MIRROR_HASH:=280d87658fa36c1d5d6852dcb8203042eba6bbc9101ac317a2088e2dd68249da
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2025-01-27
PKG_SOURCE_VERSION:=048a53d4a6cf3ef570dab9e2d10989844ae7c355
PKG_SOURCE_VERSION:=52afdf8f1d1cb8445b6b56eba3768d0edffa63e1
PKG_MAINTAINER:=John Crispin <john@phrozen.org>
PKG_LICENSE:=BSD-3-Clause

View File

@@ -5,3 +5,6 @@
# list ssid 'EAP101-ERICHI'
# list ssid 'EAP101-AKIHO'
# list ssid 'EAP101-DAMAYU'
#
# config dhcpinject 'dhcpinject'
# option iface_count '6'

View File

@@ -9,9 +9,9 @@ SERVICE_NAME="dhcpinject"
PROG=/usr/bin/udhcpinject
start_service() {
local ssid_list=""
local ssids=""
local ports=""
local ifaces=""
# Function to process each ssid
append_ssid() {
@@ -40,6 +40,9 @@ start_service() {
# Get the list of ports
config_list_foreach uplink port append_port
# Get the iface_count
config_get ifaces dhcpinject iface_count
# Fallback to eth0 if no ports are specified
if [ -z "$ports" ]; then
@@ -47,11 +50,11 @@ start_service() {
fi
# Optional: Log or echo for debugging
logger -t dhcp_inject "Generated SSIDs=$ssids, Uplink=$ports"
logger -t dhcp_inject "Generated SSIDs=$ssids, Uplink=$ports, IFACEs=$ifaces"
procd_open_instance "$SERVICE_NAME"
procd_set_param command $PROG
procd_set_param env SSIDs="$ssids" PORTs="$ports"
procd_set_param env SSIDs="$ssids" PORTs="$ports" IFACEs="$ifaces"
procd_set_param respawn 3600 10 10
procd_set_param file /etc/config/dhcpinject
procd_set_param reload_signal SIGHUP

View File

@@ -26,6 +26,7 @@ struct iface_info *iface_map = NULL;
static struct port_info *ports = NULL;
int iface_count = 0;
int port_count = 0;
int total_iface = 0;
static pcap_t *handle = NULL;
static char *provided_ssids = NULL;
static char *provided_ports = NULL;
@@ -192,6 +193,11 @@ int parse_ssids(const char *ssids) {
return -1;
}
if (iface_count != total_iface) {
syslog(LOG_ERR, "Expect %d but only %d interfaces were found.\n", total_iface, iface_count);
return -1;
}
syslog(LOG_INFO, "Found %d matching interfaces\n", iface_count);
return 0;
}
@@ -310,7 +316,6 @@ void signal_handler(int sig) {
exit(0);
} else if (sig == SIGHUP) {
syslog(LOG_INFO, "Received reload signal, reconfiguring...\n");
sleep(5);
// Clean up existing resources
cleanup_tc();
@@ -561,7 +566,19 @@ int main(int argc, char *argv[]) {
signal(SIGTERM, signal_handler);
signal(SIGHUP, signal_handler);
sleep(5);
// Read IFACEs from environment variable
char *iface_env = getenv("IFACEs");
if (!iface_env) {
syslog(LOG_ERR, "No IFACEs provided. Exiting...\n");
cleanup();
return 1;
}
total_iface = atoi(iface_env);
if (total_iface <= 0) {
syslog(LOG_ERR, "Invalid IFACEs value: %s. Exiting...\n", iface_env);
cleanup();
return 1;
}
provided_ssids = getenv("SSIDs");
syslog(LOG_INFO, "Provided SSIDs: %s\n", provided_ssids);
@@ -618,4 +635,4 @@ int main(int argc, char *argv[]) {
cleanup();
return 0;
}
}