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@@ -1,914 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ5332 RDP480 board device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "ipq5332.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "EdgeCore oap106";
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compatible = "edgecore,oap106", "qcom,ipq5332-ap-mi01.13", "qcom,ipq5332";
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/* Layout for IPQ5332 + QCN9224 + QCN9224 + QCN9160
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* +==========+==============+========================+
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* | | | |
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* | Region | Start Offset | Size |
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* | | | |
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* +---------+--------------+-------------------------+
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* | Q6 | | |
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* | code/ | 0x4A900000 | 27MB |
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* | data | | |
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* +---------+--------------+-------------------------+
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* | IPQ5332 | | |
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* | data | 0x4C400000 | 21MB |
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* +---------+--------------+-------------------------+
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* | IPQ5332 | | |
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* | M3 Dump | 0x4D900000 | 1MB |
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* +---------+--------------+-------------------------+
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* | IPQ5332 | | |
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* | QDSS | 0x4DA00000 | 1MB |
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* +---------+--------------+-------------------------+
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* | IPQ5332 | | |
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* | CALDB | 0x4DB00000 | 5MB |
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* +---------+--------------+-------------------------+
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* |QCN6432_1| | |
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* | data | 0x4E000000 | 21MB |
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* +---------+--------------+-------------------------+
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* |QCN6432_1| | |
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* | M3 Dump | 0x4F500000 | 1MB |
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* +---------+--------------+-------------------------+
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* |QCN6432_1| | |
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* | QDSS | 0x4F600000 | 1MB |
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* +---------+--------------+-------------------------+
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* |QCN6432_1| | |
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* | CALDB | 0x4F700000 | 5MB |
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* +---------+--------------+-------------------------+
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* | QCN9160 | | |
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* | data | 0x4FC00000 | 14MB |
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* +---------+--------------+-------------------------+
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* | QCN9160 | | |
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* | M3 Dump | 0x50A00000 | 1MB |
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* +---------+--------------+-------------------------+
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* | QCN9160 | | |
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* | QDSS | 0x50B00000 | 1MB |
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* +---------+--------------+-------------------------+
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* | QCN9160 | | |
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* | CALDB | 0x50C00000 | 5MB |
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* +---------+--------------+-------------------------+
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* | | | |
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* | MLO | 0x51100000 | 18MB |
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* +---------+--------------+-------------------------+
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* | | | |
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* | WKK1 | 0x52300000 | 50MB |
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* | | | |
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* +---------+--------------+-------------------------+
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* | | | |
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* | WKK0 | 0x55500000 | 50MB |
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* | | | |
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* +---------+--------------+-------------------------+
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* | | | |
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* | MHI0 | DYNAMIC | 9MB |
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* | | | |
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* +---------+--------------+-------------------------+
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* | | | |
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* | MHI1 | DYNAMIC | 9MB |
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* | | | |
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* +==================================================+
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* | |
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* | |
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* | |
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* | Rest of memory for Linux |
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* | |
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* | |
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* | |
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* +==================================================+
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*/
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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q6_mem_regions: q6_mem_regions@4A900000 {
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no-map;
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reg = <0x0 0x4a900000 0x0 0x6800000>;
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};
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q6_code_data: q6_code_data@4A900000 {
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no-map;
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reg = <0x0 0x4a900000 0x0 0x1B00000>;
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};
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q6_ipq5332_data: q6_ipq5332_data@4C400000 {
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no-map;
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reg = <0x0 0x4C400000 0x0 0x1500000>;
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};
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m3_dump: m3_dump@4D900000 {
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no-map;
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reg = <0x0 0x4D900000 0x0 0x100000>;
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};
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q6_etr_region: q6_etr_dump@4DA00000 {
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no-map;
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reg = <0x0 0x4DA00000 0x0 0x100000>;
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};
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q6_ipq5332_caldb: q6_ipq5332_caldb@4DB00000 {
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no-map;
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reg = <0x0 0x4DB00000 0x0 0x500000>;
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};
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q6_qcn6432_data_1: q6_qcn6432_data_1@4E000000 {
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no-map;
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reg = <0x0 0x4E000000 0x0 0x1500000>;
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};
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m3_dump_qcn6432_1: m3_dump_qcn6432_1@4F500000 {
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no-map;
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reg = <0x0 0x4F500000 0x0 0x100000>;
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};
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q6_qcn6432_etr_1: q6_qcn6432_etr_1@4F600000 {
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no-map;
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reg = <0x0 0x4F600000 0x0 0x100000>;
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};
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q6_qcn6432_caldb_1: q6_qcn6432_caldb_1@4F700000 {
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no-map;
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reg = <0x0 0x4F700000 0x0 0x500000>;
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};
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q6_qcn9160_data_2: q6_qcn9160_data_2@4FC00000 {
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no-map;
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reg = <0x0 0x4FC00000 0x0 0xe00000>;
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};
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m3_dump_qcn9160_2: m3_dump_qcn9160_2@50A00000 {
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no-map;
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reg = <0x0 0x50A00000 0x0 0x100000>;
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};
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q6_qcn9160_etr_2: q6_qcn9160_etr_2@50B00000 {
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no-map;
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reg = <0x0 0x50B00000 0x0 0x100000>;
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};
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q6_qcn9160_caldb_2: q6_qcn9160_caldb_2@50C00000 {
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no-map;
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reg = <0x0 0x50C00000 0x0 0x500000>;
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};
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mlo_global_mem0: mlo_global_mem_0@51100000 {
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no-map;
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reg = <0x0 0x51100000 0x0 0x1200000>;
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};
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qcn9224_pcie1: qcn9224_pcie1@52300000 {
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no-map;
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reg = <0x0 0x52300000 0x0 0x03200000>;
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};
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qcn9224_pcie0: qcn9224_pcie0@55500000 {
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no-map;
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reg = <0x0 0x55500000 0x0 0x03200000>;
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};
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mhi_region0: dma_pool0@0 {
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compatible = "shared-dma-pool";
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no-map;
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size = <0x0 0x00900000>;
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};
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mhi_region1: dma_pool1@1 {
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compatible = "shared-dma-pool";
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no-map;
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size = <0x0 0x00900000>;
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};
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};
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aliases {
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serial0 = &blsp1_uart0;
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serial1 = &blsp1_uart1;
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ethernet0 = "/soc/dp1";
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ethernet1 = "/soc/dp2";
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};
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chosen {
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stdout-path = "serial0";
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};
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soc@0 {
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mdio:mdio@90000 {
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pinctrl-0 = <&mdio1_pins>;
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pinctrl-names = "default";
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/*gpio22 for manhattan reset*/
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phy-reset-gpio = <&tlmm 22 GPIO_ACTIVE_LOW>;
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phyaddr_fixup = <0xC90F018>;
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uniphyaddr_fixup = <0xC90F014>;
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mdio_clk_fixup; /* MDIO clock sequence fix up flag */
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <12>;
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compatible ="ethernet-phy-ieee802.3-c45";
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};
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phy1: ethernet-phy@1 {
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reg = <8>;
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compatible ="ethernet-phy-ieee802.3-c45";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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status = "okay";
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button@1 {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
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linux,input-type = <1>;
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debounce-interval = <60>;
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};
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};
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ess-instance {
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num_devices = <0x1>;
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ess-switch@3a000000 {
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switch_cpu_bmp = <0x1>; /* cpu port bitmap */
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switch_lan_bmp = <0x2>; /* lan port bitmap */
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switch_wan_bmp = <0x4>; /* wan port bitmap */
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switch_mac_mode = <0xd>; /* mac mode for uniphy instance0*/
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switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
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switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
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qcom,port_phyinfo {
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port@0 {
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port_id = <1>;
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phy_address = <12>;
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ethernet-phy-ieee802.3-c45;
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};
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port@1 {
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port_id = <2>;
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phy_address = <8>;
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ethernet-phy-ieee802.3-c45;
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};
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};
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};
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};
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dp1 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <2>;
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reg = <0x3a504000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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mdio-bus = <&mdio>;
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qcom,phy-mdio-addr = <8>;
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qcom,link-poll = <1>;
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phy-mode = "usxgmii";
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};
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dp2 {
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device_type = "network";
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compatible = "qcom,nss-dp";
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qcom,id = <1>;
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reg = <0x3a500000 0x4000>;
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qcom,mactype = <1>;
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local-mac-address = [000000000000];
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mdio-bus = <&mdio>;
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qcom,phy-mdio-addr = <12>;
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qcom,link-poll = <1>;
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phy-mode = "usxgmii";
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};
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/* EDMA host driver configuration for the board */
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edma@3ab00000 {
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qcom,txdesc-ring-start = <4>; /* Tx desc ring start ID */
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qcom,txdesc-rings = <12>; /* Total number of Tx desc rings to be provisioned */
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qcom,mht-txdesc-rings = <8>; /* Extra Tx desc rings to be provisioned for MHT SW ports */
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qcom,txcmpl-ring-start = <4>; /* Tx complete ring start ID */
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qcom,txcmpl-rings = <12>; /* Total number of Tx complete rings to be provisioned */
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qcom,mht-txcmpl-rings = <8>; /* Extra Tx complete rings to be provisioned for mht sw ports. */
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qcom,rxfill-ring-start = <4>; /* Rx fill ring start ID */
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qcom,rxfill-rings = <4>; /* Total number of Rx fill rings to be provisioned */
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qcom,rxdesc-ring-start = <12>; /* Rx desc ring start ID */
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qcom,rxdesc-rings = <4>; /* Total number of Rx desc rings to be provisioned */
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qcom,rx-page-mode = <0>; /* Rx fill ring page mode */
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qcom,tx-map-priority-level = <1>; /* Tx priority level per port */
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qcom,rx-map-priority-level = <1>; /* Rx priority level per core */
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qcom,ppeds-num = <2>; /* Number of PPEDS nodes */
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/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
|
|
|
|
|
qcom,ppeds-map = <1 1 1 1 32 8>, /* PPEDS Node#0 ring and queue map */
|
|
|
|
|
<2 2 2 2 40 8>; /* PPEDS Node#1 ring and queue map */
|
|
|
|
|
qcom,txdesc-map = <8 9 10 11>, /* Port0 per-core Tx ring map */
|
|
|
|
|
<12 13 14 15>, /* MHT-Port1 per-core Tx ring map */
|
|
|
|
|
<4 5 6 7>, /* MHT-Port2 per-core Tx ring map/packets from vp*/
|
|
|
|
|
<16 17 18 19>, /* MHT-Port3 per-core Tx ring map */
|
|
|
|
|
<20 21 22 23>; /* MHT-Port4 per-core Tx ring map */
|
|
|
|
|
qcom,txdesc-fc-grp-map = <1 2 3 4 5>; /* Per GMAC flow control group map */
|
|
|
|
|
qcom,rxfill-map = <4 5 6 7>; /* Per-core Rx fill ring map */
|
|
|
|
|
qcom,rxdesc-map = <12 13 14 15>; /* Per-core Rx desc ring map */
|
|
|
|
|
qcom,rx-queue-start = <0>; /* Rx queue start */
|
|
|
|
|
qcom,rx-ring-queue-map = <0 8 16 24>, /* Priority 0 queues per-core Rx ring map */
|
|
|
|
|
<1 9 17 25>, /* Priority 1 queues per-core Rx ring map */
|
|
|
|
|
<2 10 18 26>, /* Priority 2 queues per-core Rx ring map */
|
|
|
|
|
<3 11 19 27>, /* Priority 3 queues per-core Rx ring map */
|
|
|
|
|
<4 12 20 28>, /* Priority 4 queues per-core Rx ring map */
|
|
|
|
|
<5 13 21 29>, /* Priority 5 queues per-core Rx ring map */
|
|
|
|
|
<6 14 22 30>, /* Priority 6 queues per-core Rx ring map */
|
|
|
|
|
<7 15 23 31>; /* Priority 7 queues per-core Rx ring map */
|
|
|
|
|
interrupts = <0 163 4>, /* Tx complete ring id #4 IRQ info */
|
|
|
|
|
<0 164 4>, /* Tx complete ring id #5 IRQ info */
|
|
|
|
|
<0 165 4>, /* Tx complete ring id #6 IRQ info */
|
|
|
|
|
<0 166 4>, /* Tx complete ring id #7 IRQ info */
|
|
|
|
|
<0 167 4>, /* Tx complete ring id #8 IRQ info */
|
|
|
|
|
<0 168 4>, /* Tx complete ring id #9 IRQ info */
|
|
|
|
|
<0 169 4>, /* Tx complete ring id #10 IRQ info */
|
|
|
|
|
<0 170 4>, /* Tx complete ring id #11 IRQ info */
|
|
|
|
|
<0 171 4>, /* Tx complete ring id #12 IRQ info */
|
|
|
|
|
<0 172 4>, /* Tx complete ring id #13 IRQ info */
|
|
|
|
|
<0 173 4>, /* Tx complete ring id #14 IRQ info */
|
|
|
|
|
<0 174 4>, /* Tx complete ring id #15 IRQ info */
|
|
|
|
|
<0 139 4>, /* Rx desc ring id #12 IRQ info */
|
|
|
|
|
<0 140 4>, /* Rx desc ring id #13 IRQ info */
|
|
|
|
|
<0 141 4>, /* Rx desc ring id #14 IRQ info */
|
|
|
|
|
<0 142 4>, /* Rx desc ring id #15 IRQ info */
|
|
|
|
|
<0 191 4>, /* Misc error IRQ info */
|
|
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|
|
<0 155 4>, /* RxFill ring id #4 IRQ info */
|
|
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|
|
<0 156 4>, /* RxFill ring id #5 IRQ info */
|
|
|
|
|
<0 157 4>, /* RxFill ring id #6 IRQ info */
|
|
|
|
|
<0 158 4>, /* RxFill ring id #7 IRQ info */
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|
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|
|
<0 160 4>, /* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
|
|
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|
|
<0 128 4>, /* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
|
|
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|
|
<0 152 4>, /* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
|
|
|
|
|
<0 161 4>, /* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
|
|
|
|
|
<0 129 4>, /* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
|
|
|
|
|
<0 153 4>, /* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
|
|
|
|
|
<0 175 4>, /* MHT port Tx complete ring id #16 IRQ info */
|
|
|
|
|
<0 176 4>, /* MHT port Tx complete ring id #17 IRQ info */
|
|
|
|
|
<0 177 4>, /* MHT port Tx complete ring id #18 IRQ info */
|
|
|
|
|
<0 178 4>, /* MHT port Tx complete ring id #19 IRQ info */
|
|
|
|
|
<0 179 4>, /* MHT port Tx complete ring id #20 IRQ info */
|
|
|
|
|
<0 180 4>, /* MHT port Tx complete ring id #21 IRQ info */
|
|
|
|
|
<0 181 4>, /* MHT port Tx complete ring id #22 IRQ info */
|
|
|
|
|
<0 182 4>; /* MHT port Tx complete ring id #23 IRQ info */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wsi: wsi {
|
|
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|
|
id = <0>;
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|
|
num_chip = <3>;
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|
|
status = "okay";
|
|
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|
|
chip_info = <0 2 1 2>,
|
|
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|
|
<1 2 0 2>,
|
|
|
|
|
<2 2 0 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
q6v5_wcss: remoteproc@d100000 {
|
|
|
|
|
boot-args = <0x1 0x5 0x3 0x0 0x26 0x2 0x0>,
|
|
|
|
|
<0x1 0x5 0x4 0x2 0x2C 0x0 0x0>;
|
|
|
|
|
memory-region = <&q6_mem_regions>,
|
|
|
|
|
<&mlo_global_mem0>;
|
|
|
|
|
|
|
|
|
|
upd-firmware-names = "IPQ5332/q6_fw1.mdt",
|
|
|
|
|
"IPQ5332/q6_fw3.mdt";
|
|
|
|
|
/delete-node/ remoteproc_pd1;
|
|
|
|
|
/delete-node/ remoteproc_pd3;
|
|
|
|
|
|
|
|
|
|
q6_wcss_pd1: remoteproc_pd1 {
|
|
|
|
|
compatible = "qcom,ipq5332-wcss-ahb-mpd";
|
|
|
|
|
firmware = "IPQ5332/q6_fw1.mdt";
|
|
|
|
|
m3_firmware = "IPQ5332/iu_fw.mdt";
|
|
|
|
|
interrupts-extended = <&wcss_smp2p_in 8 0>,
|
|
|
|
|
<&wcss_smp2p_in 9 0>,
|
|
|
|
|
<&wcss_smp2p_in 12 0>,
|
|
|
|
|
<&wcss_smp2p_in 11 0>;
|
|
|
|
|
interrupt-names = "fatal",
|
|
|
|
|
"ready",
|
|
|
|
|
"spawn-ack",
|
|
|
|
|
"stop-ack";
|
|
|
|
|
|
|
|
|
|
qcom,smem-states = <&wcss_smp2p_out 8>,
|
|
|
|
|
<&wcss_smp2p_out 9>,
|
|
|
|
|
<&wcss_smp2p_out 10>;
|
|
|
|
|
qcom,smem-state-names = "shutdown",
|
|
|
|
|
"stop",
|
|
|
|
|
"spawn";
|
|
|
|
|
memory-region = <&q6_ipq5332_data>,
|
|
|
|
|
<&m3_dump>,
|
|
|
|
|
<&q6_etr_region>,
|
|
|
|
|
<&q6_ipq5332_caldb>,
|
|
|
|
|
<&mlo_global_mem0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
q6_wcss_pd3: remoteproc_pd3 {
|
|
|
|
|
compatible = "qcom,ipq5332-wcss-pcie-mpd";
|
|
|
|
|
firmware = "IPQ5332/q6_fw3.mdt";
|
|
|
|
|
m3_firmware = "qcn9160/m3_fw.mdt";
|
|
|
|
|
interrupts-extended = <&wcss_smp2p_in 24 0>,
|
|
|
|
|
<&wcss_smp2p_in 25 0>,
|
|
|
|
|
<&wcss_smp2p_in 28 0>,
|
|
|
|
|
<&wcss_smp2p_in 27 0>;
|
|
|
|
|
interrupt-names = "fatal",
|
|
|
|
|
"ready",
|
|
|
|
|
"spawn-ack",
|
|
|
|
|
"stop-ack";
|
|
|
|
|
|
|
|
|
|
qcom,smem-states = <&wcss_smp2p_out 24>,
|
|
|
|
|
<&wcss_smp2p_out 25>,
|
|
|
|
|
<&wcss_smp2p_out 26>;
|
|
|
|
|
qcom,smem-state-names = "shutdown",
|
|
|
|
|
"stop",
|
|
|
|
|
"spawn";
|
|
|
|
|
memory-region = <&q6_qcn9160_data_2>,
|
|
|
|
|
<&m3_dump_qcn9160_2>,
|
|
|
|
|
<&q6_qcn9160_etr_2>,
|
|
|
|
|
<&q6_qcn9160_caldb_2>;
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&blsp1_uart0 {
|
|
|
|
|
pinctrl-0 = <&serial_0_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&blsp1_uart1 {
|
|
|
|
|
pinctrl-0 = <&serial_1_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&blsp1_i2c1 {
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
pinctrl-0 = <&i2c_1_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
gpio_expander: gpio@74 {
|
|
|
|
|
compatible = "ti,tca9539";
|
|
|
|
|
reg = <0x74>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
gpio-export {
|
|
|
|
|
compatible = "gpio-export";
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
led_o {
|
|
|
|
|
gpios = <&gpio_expander 0 GPIO_ACTIVE_HIGH>; // P00
|
|
|
|
|
gpio-export,name = "led_o";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
led_g {
|
|
|
|
|
gpios = <&gpio_expander 1 GPIO_ACTIVE_HIGH>; // P01
|
|
|
|
|
gpio-export,name = "led_g";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
led_b {
|
|
|
|
|
gpios = <&gpio_expander 2 GPIO_ACTIVE_HIGH>; // P02
|
|
|
|
|
gpio-export,name = "led_b";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
w_disable1 {
|
|
|
|
|
gpios = <&gpio_expander 3 GPIO_ACTIVE_HIGH>; // P03
|
|
|
|
|
gpio-export,name = "w_disable1_l";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
w_disable2 {
|
|
|
|
|
gpios = <&gpio_expander 4 GPIO_ACTIVE_HIGH>; // P04
|
|
|
|
|
gpio-export,name = "w_disable2_l";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
heater_1 {
|
|
|
|
|
gpios = <&gpio_expander 7 GPIO_ACTIVE_HIGH>; // P07
|
|
|
|
|
gpio-export,name = "heater_1";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
heater_2 {
|
|
|
|
|
gpios = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; // P10
|
|
|
|
|
gpio-export,name = "heater_2";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tpm_int {
|
|
|
|
|
gpios = <&gpio_expander 9 GPIO_ACTIVE_LOW>; // P11
|
|
|
|
|
gpio-export,name = "tpm_int_l";
|
|
|
|
|
gpio-export,direction = "in";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tpm_rst {
|
|
|
|
|
gpios = <&gpio_expander 10 GPIO_ACTIVE_LOW>; // P12
|
|
|
|
|
gpio-export,name = "tpm_rst_l";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gps_rst {
|
|
|
|
|
gpios = <&gpio_expander 11 GPIO_ACTIVE_LOW>; // P13
|
|
|
|
|
gpio-export,name = "gps_rst_l";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ble_rst {
|
|
|
|
|
gpios = <&gpio_expander 12 GPIO_ACTIVE_LOW>; // P14
|
|
|
|
|
gpio-export,name = "ble_rst_l";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ble_backdoor {
|
|
|
|
|
gpios = <&gpio_expander 13 GPIO_ACTIVE_HIGH>; // P15
|
|
|
|
|
gpio-export,name = "ble_backdoor";
|
|
|
|
|
gpio-export,direction = "in";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
m2_coex_txd {
|
|
|
|
|
gpios = <&gpio_expander 14 GPIO_ACTIVE_HIGH>; // P16
|
|
|
|
|
gpio-export,name = "m2_coex_txd";
|
|
|
|
|
gpio-export,direction = "out";
|
|
|
|
|
gpio-export,output = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
m2_coex_rxd {
|
|
|
|
|
gpios = <&gpio_expander 15 GPIO_ACTIVE_HIGH>; // P17
|
|
|
|
|
gpio-export,name = "m2_coex_rxd";
|
|
|
|
|
gpio-export,direction = "in";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
st33htpi: tpm@2e {
|
|
|
|
|
compatible = "infineon,slb9673";
|
|
|
|
|
reg = <0x2e>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&blsp1_spi0 {
|
|
|
|
|
pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
flash@0 {
|
|
|
|
|
compatible = "n25q128a11", "micron,n25q128a11", "jedec,spi-nor";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
spi-max-frequency = <50000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&sdhc {
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
max-frequency = <192000000>;
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
mmc-hs200-1_8v;
|
|
|
|
|
non-removable;
|
|
|
|
|
pinctrl-0 = <&sdc_default_state>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&sleep_clk {
|
|
|
|
|
clock-frequency = <32000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&xo {
|
|
|
|
|
clock-frequency = <24000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qpic_bam {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qpic_nand {
|
|
|
|
|
pinctrl-0 = <&qspi_default_state>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
nandcs@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
|
|
|
|
nand-ecc-strength = <8>;
|
|
|
|
|
nand-ecc-step-size = <512>;
|
|
|
|
|
nand-bus-width = <8>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pcie0_phy {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pcie1_phy {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pcie0 {
|
|
|
|
|
pinctrl-0 = <&pcie0_default_state>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
pcie0_rp {
|
|
|
|
|
reg = <0 0 0 0 0>;
|
|
|
|
|
|
|
|
|
|
qcom,mhi@2 {
|
|
|
|
|
reg = <0 0 0 0 0>;
|
|
|
|
|
boot-args = <0x2 0x4 0x34 0x3 0x0 0x0 /* MX Rail, GPIO52, Drive strength 0x3 */
|
|
|
|
|
0x4 0x4 0x18 0x3 0x0 0x0 /* RFA1p2 Rail, GPIO24, Drive strength 0x3 */
|
|
|
|
|
0x0 0x4 0x0 0x0 0x0 0x0>; /* End of arguments */
|
|
|
|
|
memory-region = <&qcn9224_pcie0>, <&mhi_region0>;
|
|
|
|
|
qcom,board_id = <0x12>;
|
|
|
|
|
qcom,wsi = <&wsi>;
|
|
|
|
|
qcom,wsi_index = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pcie1 {
|
|
|
|
|
pinctrl-0 = <&pcie1_default_state>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
phys = <&pcie1_phy>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
pcie1_rp {
|
|
|
|
|
reg = <0 0 0 0 0>;
|
|
|
|
|
|
|
|
|
|
qcom,mhi@1 {
|
|
|
|
|
reg = <0 0 0 0 0>;
|
|
|
|
|
memory-region = <&qcn9224_pcie1>, <&mhi_region1>;
|
|
|
|
|
qcom,board_id = <0x4>;
|
|
|
|
|
qcom,wsi = <&wsi>;
|
|
|
|
|
qcom,wsi_index = <2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qcn9224_pcie0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qcn9224_pcie1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* PINCTRL */
|
|
|
|
|
|
|
|
|
|
&tlmm {
|
|
|
|
|
qspi_default_state: qspi-default-state {
|
|
|
|
|
qspi_clock {
|
|
|
|
|
pins = "gpio13";
|
|
|
|
|
function = "qspi_clk";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-down;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
qspi_cs {
|
|
|
|
|
pins = "gpio12";
|
|
|
|
|
function = "qspi_cs";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
qspi_data {
|
|
|
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
|
|
|
function = "qspi_data";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-down;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial_1_pins: serial1-pinmux {
|
|
|
|
|
pins = "gpio33", "gpio34", "gpio35", "gpio36";
|
|
|
|
|
function = "blsp1_uart2";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c_1_pins: i2c-1-state {
|
|
|
|
|
pins = "gpio29", "gpio30";
|
|
|
|
|
function = "blsp1_i2c0";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie0_default_state: pcie0-default-state {
|
|
|
|
|
pins = "gpio38";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
output-low;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie1_default_state: pcie1-default-state {
|
|
|
|
|
pins = "gpio47";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
output-low;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
button_pins: button-state {
|
|
|
|
|
pins = "gpio25";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdc_default_state: sdc-default-state {
|
|
|
|
|
clk-pins {
|
|
|
|
|
pins = "gpio13";
|
|
|
|
|
function = "sdc_clk";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-disable;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cmd-pins {
|
|
|
|
|
pins = "gpio12";
|
|
|
|
|
function = "sdc_cmd";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
data-pins {
|
|
|
|
|
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
|
|
|
|
function = "sdc_data";
|
|
|
|
|
drive-strength = <8>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi_0_data_clk_pins: spi-0-data-clk-state {
|
|
|
|
|
pins = "gpio14", "gpio15", "gpio16";
|
|
|
|
|
function = "blsp0_spi";
|
|
|
|
|
drive-strength = <2>;
|
|
|
|
|
bias-pull-down;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi_0_cs_pins: spi-0-cs-state {
|
|
|
|
|
pins = "gpio17";
|
|
|
|
|
function = "blsp0_spi";
|
|
|
|
|
drive-strength = <2>;
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&license_manager {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usb3 {
|
|
|
|
|
qcom,select-utmi-as-pipe-clk;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
dwc3@8a00000 {
|
|
|
|
|
phys = <&hs_m31phy_0>;
|
|
|
|
|
phy-names = "usb2-phy";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&hs_m31phy_0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&wifi0 {
|
|
|
|
|
qcom,multipd_arch;
|
|
|
|
|
qcom,rproc = <&q6_wcss_pd1>;
|
|
|
|
|
qcom,rproc_rpd = <&q6v5_wcss>;
|
|
|
|
|
qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
|
|
|
|
|
qcom,tgt-mem-mode = <0>;
|
|
|
|
|
qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0 0x0>;
|
|
|
|
|
qcom,caldb-addr = <0x4DB00000 0x4DB00000 0x4DB00000 0x0 0x0 0x0>;
|
|
|
|
|
qcom,caldb-size = <0x500000>;
|
|
|
|
|
qcom,board_id = <0x13>;
|
|
|
|
|
mem-region = <&q6_ipq5332_data>;
|
|
|
|
|
memory-region = <&q6_ipq5332_data>;
|
|
|
|
|
qcom,wsi = <&wsi>;
|
|
|
|
|
qcom,wsi_index = <0>;
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qcn9224_pcie0 {
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qcn9224_pcie1 {
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&mhi_region1 {
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&wifi3 {
|
|
|
|
|
hremote_node = <&qcn9224_pcie0>;
|
|
|
|
|
/* QCN9224 radio 5G
|
|
|
|
|
* +=========+==============+=========+
|
|
|
|
|
* | Region | Start Offset | Size |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | HREMOTE | 0x55500000 | 28MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | M3 Dump | 0x57100000 | 1MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | ETR | 0x57200000 | 1MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | Caldb | 0x57300000 | 8MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* |Pageable | 0x57B00000 | 12MB |
|
|
|
|
|
* +==================================+
|
|
|
|
|
*/
|
|
|
|
|
base-addr = <0x55500000>;
|
|
|
|
|
m3-dump-addr = <0x57100000>;
|
|
|
|
|
etr-addr = <0x57200000>;
|
|
|
|
|
caldb-addr = <0x57300000>;
|
|
|
|
|
pageable-addr = <0x57B00000>;
|
|
|
|
|
hremote-size = <0x1C00000>;
|
|
|
|
|
pageable-size = <0xC00000>;
|
|
|
|
|
tgt-mem-mode = <0x0>;
|
|
|
|
|
board_id = <0x2>;
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&wifi4 {
|
|
|
|
|
hremote_node = <&qcn9224_pcie1>;
|
|
|
|
|
/* QCN9224 radio 6G
|
|
|
|
|
* +=========+==============+=========+
|
|
|
|
|
* | Region | Start Offset | Size |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | HREMOTE | 0x52300000 | 28MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | M3 Dump | 0x53F00000 | 1MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | ETR | 0x54000000 | 1MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* | Caldb | 0x54100000 | 8MB |
|
|
|
|
|
* +---------+--------------+---------+
|
|
|
|
|
* |Pageable | 0x54900000 | 12MB |
|
|
|
|
|
* +==================================+
|
|
|
|
|
*/
|
|
|
|
|
base-addr = <0x52300000>;
|
|
|
|
|
m3-dump-addr = <0x53F00000>;
|
|
|
|
|
etr-addr = <0x54000000>;
|
|
|
|
|
caldb-addr = <0x54100000>;
|
|
|
|
|
pageable-addr = <0x54900000>;
|
|
|
|
|
hremote-size = <0x1C00000>;
|
|
|
|
|
pageable-size = <0xC00000>;
|
|
|
|
|
tgt-mem-mode = <0x0>;
|
|
|
|
|
node_id=<0x1>;
|
|
|
|
|
board_id = <0x4>;
|
|
|
|
|
status = "ok";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
//&wifi5 {
|
|
|
|
|
// qcom,multipd_arch;
|
|
|
|
|
// qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
|
|
|
|
|
// qcom,rproc = <&q6_wcss_pd3>;
|
|
|
|
|
// qcom,tgt-mem-mode = <0>;
|
|
|
|
|
// qcom,board_id = <0x101>;
|
|
|
|
|
// qcom,bdf-addr = <0x4FC00000 0x4FC00000 0x4FC00000 0x0 0x0 0x0>;
|
|
|
|
|
// qcom,caldb-addr = <0x50C00000 0x50C00000 0x50C00000 0x0 0x0 0x0>;
|
|
|
|
|
// qcom,caldb-size = <0x500000>;
|
|
|
|
|
// m3-dump-addr = <0x50A00000>;
|
|
|
|
|
// mem-region = <&q6_qcn9160_data_2>;
|
|
|
|
|
// memory-region = <&q6_qcn9160_data_2>;
|
|
|
|
|
// qcom,pci_slot_id = <2>;
|
|
|
|
|
// status = "ok";
|
|
|
|
|
//};
|
