Merge pull request #453 from Telecominfraproject/main

Merge Main to release/v2.6.0

feeds/ipq807x/ipq807x/Makefile

@@ -4,17 +4,17 @@ ARCH:=arm
 BOARD:=ipq807x
 BOARDNAME:=Qualcomm Atheros AX
 SUBTARGETS:=ipq807x ipq60xx ipq50xx
-FEATURES:=squashfs ramdisk nand pcie usb usbgadget
+FEATURES:=squashfs ramdisk nand pcie usb
 KERNELNAME:=Image dtbs
 CPU_TYPE:=cortex-a7
 
-KERNEL_PATCHVER:=5.4
+KERNEL_PATCHVER:=4.4
-KERNEL_NAME_SUFFIX=-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac
+KERNEL_NAME_SUFFIX=-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016
 
 include $(INCLUDE_DIR)/target.mk
 DEFAULT_PACKAGES += kmod-qca-nss-dp kmod-qca-ssdk swconfig \
 	kmod-qca-nss-drv \
-	kmod-usb-phy-ipq807x kmod-usb-dwc3-qcom-internal \
+	kmod-usb-phy-ipq807x kmod-usb-dwc3-of-simple \
 	kmod-ath11k-ahb kmod-qrtr_mproc wpad \
 	kmod-gpio-button-hotplug \
 	qca-thermald-10.4 qca-ssdk-shell kmod-qca-nss-drv-bridge-mgr \

feeds/ipq807x/ipq807x/base-files/etc/board.d/02_network

@@ -33,6 +33,7 @@ qcom_setup_interfaces()
 	edgecore,eap106|\
 	qcom,ipq5018-mp03.3|\
 	yuncore,ax840|\
+	motorola,q14|\
 	sercomm,wallaby)
 		ucidef_set_interface_lan "eth0"
 		ucidef_set_interface_wan "eth1"

feeds/ipq807x/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata

@@ -107,13 +107,22 @@ ath11k/IPQ5018/hw1.0/caldata.bin)
 	case "$board" in
 	cybertan,eww622-a1|\
 	edgecore,eap104|\
+	motorola,q14|\
 	qcom,ipq5018-mp03.1)
                 caldata_extract "0:ART" 0x1000 0x20000  
 		;;
 	esac
 	;;
+ath11k/qcn6122/hw1.0/caldata_1.bin)
+	case "$board" in
+	motorola,q14)
+                caldata_extract "0:ART" 0x26800 0x20000  
+		;;
+	esac
+	;;
 ath11k/qcn6122/hw1.0/caldata_2.bin)
 	case "$board" in
+	motorola,q14|\
 	edgecore,eap104)
                 caldata_extract "0:ART" 0x4c000 0x20000  
 		;;

feeds/ipq807x/ipq807x/base-files/lib/upgrade/platform.sh

@@ -19,6 +19,50 @@ qca_do_upgrade() {
         fi
 }
 
+find_mmc_part() {
+	local DEVNAME PARTNAME
+
+	if grep -q "$1" /proc/mtd; then
+		echo "" && return 0
+	fi
+
+	for DEVNAME in /sys/block/mmcblk*/mmcblk*p*; do
+		PARTNAME=$(grep PARTNAME ${DEVNAME}/uevent | cut -f2 -d'=')
+		[ "$PARTNAME" = "$1" ] && echo "/dev/$(basename $DEVNAME)" && return 0
+	done
+}
+
+do_flash_emmc() {
+	local tar_file=$1
+	local emmcblock=$(find_mmc_part $2)
+	local board_dir=$3
+	local part=$4
+
+	[ -z "$emmcblock" ] && {
+		echo failed to find $2
+		return
+	}
+
+	echo erase $4
+	dd if=/dev/zero of=${emmcblock}
+	echo flash $4
+	tar Oxf $tar_file ${board_dir}/$part | dd of=${emmcblock}
+}
+
+emmc_do_upgrade() {
+	local tar_file="$1"
+
+	local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
+	board_dir=${board_dir%/}
+	do_flash_emmc $tar_file '0:HLOS' $board_dir kernel
+	do_flash_emmc $tar_file 'rootfs' $board_dir root
+
+	local emmcblock="$(find_mmc_part "rootfs_data")"
+        if [ -e "$emmcblock" ]; then
+                mkfs.ext4 "$emmcblock"
+        fi
+}
+
 platform_check_image() {
 	local magic_long="$(get_magic_long "$1")"
 	board=$(board_name)
@@ -42,6 +86,7 @@ platform_check_image() {
 	tplink,ex227|\
 	tplink,ex447|\
 	yuncore,ax840|\
+	motorola,q14|\
 	qcom,ipq6018-cp01|\
 	qcom,ipq807x-hk01|\
 	qcom,ipq807x-hk14|\
@@ -62,6 +107,9 @@ platform_do_upgrade() {
 	cig,wf188)
 		qca_do_upgrade $1
 		;;
+	motorola,q14)
+		emmc_do_upgrade $1
+		;;
 	cig,wf188n|\
 	cig,wf194c|\
 	cig,wf194c4|\

feeds/ipq807x/ipq807x/config-4.4

@@ -0,0 +1,829 @@
+# CONFIG_AHCI_IPQ is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_AMBA_PL08X is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+# CONFIG_AR8216_PHY is not set
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+# CONFIG_ARCH_IPQ40XX is not set
+# CONFIG_ARCH_IPQ806x is not set
+# CONFIG_ARCH_IPQ807x is not set
+# CONFIG_ARCH_IPQ6018 is not set
+# CONFIG_ARCH_IPQ5018 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_QCOM=y
+CONFIG_QSEECOM=m
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PMU=y
+CONFIG_ARM_CCI_PMU=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_LPAE is not set
+CONFIG_ARM_MODULE_PLTS=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_QCOM_CPUFREQ=y
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+# CONFIG_ATA is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_VIRTIO_BLK is not set
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_BOUNCE=y
+CONFIG_BUILD_BIN2C=y
+# CONFIG_CNSS_QCN9000 is not set
+# CONFIG_CNSS2 is not set
+# CONFIG_CNSS2_GENL is not set
+# CONFIG_CNSS2_DEBUG is not set
+# CONFIG_CNSS2_PM is not set
+# CONFIG_CNSS2_PCI_DRIVER is not set
+# CONFIG_CNSS2_CALIBRATION_SUPPORT is not set
+# CONFIG_CNSS2_SMMU is not set
+# CONFIG_CNSS2_RAMDUMP is not set
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_CC_STACKPROTECTOR_NONE is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+# CONFIG_CHARGER_QCOM_SMBB is not set
+CONFIG_CLEANCACHE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_COREDUMP=y
+# CONFIG_CORESIGHT is not set
+# CONFIG_CORESIGHT_CSR is not set
+# CONFIG_CORESIGHT_CTI is not set
+# NFIG_CORESIGHT_EVENT is not set
+# CONFIG_CORESIGHT_HWEVENT is not set
+# CONFIG_CORESIGHT_LINKS_AND_SINKS is not set
+# CONFIG_CORESIGHT_LINK_AND_SINK_TMC is not set
+# CONFIG_CORESIGHT_QCOM_REPLICATOR is not set
+# CONFIG_CORESIGHT_QPDI is not set
+# CONFIG_CORESIGHT_SINK_ETBV10 is not set
+# CONFIG_CORESIGHT_SINK_TPIU is not set
+# CONFIG_CORESIGHT_SOURCE_DUMMY is not set
+# CONFIG_CORESIGHT_SOURCE_ETM3X is not set
+# CONFIG_CORESIGHT_SOURCE_ETM4X is not set
+# CONFIG_CORESIGHT_REMOTE_ETM is not set
+# CONFIG_CORESIGHT_STM is not set
+# CONFIG_CORESIGHT_TPDA is not set
+# CONFIG_CORESIGHT_TPDM is not set
+# CONFIG_CORESIGHT_TPDM_DEFAULT_ENABLE is not set
+# CONFIG_CORESIGHT_STREAM is not set
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_SW_DOMAIN_PAN is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+# CONFIG_CPU_THERMAL is not set
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CRYPTO_DEV_QCOM_MSM_QCE is not set
+# CONFIG_CRYPTO_DEV_OTA_CRYPTO is not set
+# CONFIG_FIPS_ENABLE is not set
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_CMAC=y
+# CONFIG_CRYPTO_DEV_QCOM_ICE is not set
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_XZ=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_MEM_USAGE is not set
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DEVMEM=y
+# CONFIG_DIAG_OVER_USB is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+# CONFIG_DWMAC_GENERIC is not set
+# CONFIG_DWMAC_IPQ806X is not set
+# CONFIG_DWMAC_SUNXI is not set
+# CONFIG_DW_DMAC_PCI is not set
+# CONFIG_VHOST_NET is not set
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_USE_FOR_EXT2 is not set
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_QCOM_QPIC=y
+CONFIG_FB_QCOM_QPIC_ER_SSD1963_PANEL=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_MBCACHE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+# CONFIG_GENERIC_CPUFREQ_KRAIT is not set
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_DEVRES=y
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_NXP_74HC153 is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+# CONFIG_SRD_TRACE is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_XZ=y
+# CONFIG_HAVE_KPROBES is not set
+# CONFIG_HAVE_KRETPROBES is not set
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_OPTPROBES is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_QUP=y
+# CONFIG_IIO is not set
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_INPUT_PM8941_PWRKEY is not set
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+# CONFIG_IPQ_DWC3_QTI_EXTCON is not set
+# CONFIG_IPQ_GCC_4019 is not set
+# CONFIG_IPQ_GCC_5018 is not set
+# CONFIG_IPQ_APSS_5018 is not set
+# CONFIG_IPQ_GCC_6018 is not set
+# CONFIG_IPQ_APSS_6018 is not set
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_ADSS_807x is not set
+# CONFIG_IPQ_APSS_807x is not set
+# CONFIG_IPQ_GCC_807x is not set
+# CONFIG_IPQ_ADCC_4019 is not set
+# CONFIG_IPQ_LCC_806X is not set
+# CONFIG_IPQ_REMOTEPROC_ADSP is not set
+# CONFIG_IPQ_SUBSYSTEM_RESTART is not set
+# CONFIG_IPQ_SUBSYSTEM_RESTART_TEST is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+# CONFIG_IPC_ROUTER is not set
+# CONFIG_IPC_ROUTER_SECURITY is not set
+# CONFIG_IPC_LOGGING is not set
+CONFIG_KPSS_XCC=y
+# CONFIG_KRAITCC is not set
+# CONFIG_KRAIT_CLOCKS is not set
+# CONFIG_KRAIT_L2_ACCESSORS is not set
+CONFIG_LEDS_IPQ=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TLC591XX=y
+# CONFIG_LEDS_PCA9956B is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MDIO_GPIO=y
+# CONFIG_MDIO_QCA is not set
+CONFIG_MFD_QCOM_RPM=y
+CONFIG_MFD_SPMI_PMIC=y
+# CONFIG_SLIMBUS is not set
+# CONFIG_SLIMBUS_MSM_CTRL is not set
+# CONFIG_SLIMBUS_MSM_NGD is not set
+# CONFIG_OF_SLIMBUS is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_QCOM_DML=y
+CONFIG_MMC_QCOM_TUNING=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MPLS_ROUTING is not set
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MHI is not set
+# CONFIG_MSM_IPC_ROUTER_MHI_XPRT is not set
+# CONFIG_MSM_MHI_DEBUG is not set
+# CONFIG_MSM_MHI_DEV is not set
+# CONFIG_MSM_MHI_UCI is not set
+# CONFIG_DIAGFWD_BRIDGE_CODE is not set
+# CONFIG_MSM_BUS_SCALING is not set
+# CONFIG_BUS_TOPOLOGY_ADHOC is not set
+# CONFIG_QPNP_REVID is not set
+# CONFIG_SPS is not set
+# CONFIG_SPS_SUPPORT_NDP_BAM is not set
+# CONFIG_USB_BAM is not set
+# CONFIG_SPS_SUPPORT_BAMDMA is not set
+# CONFIG_IPA is not set
+# CONFIG_IPA3 is not set
+# CONFIG_EP_PCIE is not set
+# CONFIG_GSI is not set
+# CONFIG_PFT is not set
+# CONFIG_SEEMP_CORE is not set
+# CONFIG_GPIO_USB_DETECT is not set
+# CONFIG_MSM_GLINK is not set
+# CONFIG_MSM_GLINK_LOOPBACK_SERVER is not set
+# CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT is not set
+# CONFIG_MSM_GLINK_PKT is not set
+# CONFIG_MSM_IPC_ROUTER_GLINK_XPRT is not set
+# CONFIG_MSM_QMI_INTERFACE is not set
+# CONFIG_MSM_TEST_QMI_CLIENT is not set
+# CONFIG_GLINK_DEBUG_FS is not set
+# CONFIG_MSM_RPM_SMD is not set
+# CONFIG_MSM_RPM_GLINK is not set
+CONFIG_MSM_RPM_LOG=y
+# CONFIG_MSM_SMEM is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_QCOM_SMEM_PARTS=y
+CONFIG_MTD_SPINAND_GIGADEVICE=y
+CONFIG_MTD_SPINAND_MT29F=y
+CONFIG_MTD_SPINAND_ONDIEECC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET=y
+# CONFIG_NET_DSA_MV88E6063 is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NUM_ALT_PARTITION=8
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_ON_OOPS_VALUE=1
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_PCI=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIE_DW=y
+# CONFIG_PCIE_DW_PLAT is not set
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+# CONFIG_PHY_IPQ_BALDUR_USB is not set
+# CONFIG_PHY_IPQ_UNIPHY_USB is not set
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+CONFIG_PHY_QCA_PCIE_QMP=y
+# CONFIG_PHY_QCOM_UFS is not set
+# CONFIG_PHY_IPQ_UNIPHY_PCIE is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+# CONFIG_PINCTRL_IPQ4019 is not set
+# CONFIG_PINCTRL_IPQ6018 is not set
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_IPQ807x is not set
+# CONFIG_PINCTRL_IPQ5018 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PL330_DMA is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROC_STRIPPED is not set
+CONFIG_PSTORE=y
+CONFIG_PSTORE_RAM=y
+# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_PMSG is not set
+CONFIG_PWM=y
+CONFIG_PWM_IPQ4019=y
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_QCOM_ADM=y
+# CONFIG_QCOM_APM is not set
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QTI_BT_TTY is not set
+# CONFIG_QCOM_COINCELL is not set
+# CONFIG_QCOM_DCC is not set
+CONFIG_QCOM_GDSC=y
+CONFIG_QCOM_GSBI=y
+# CONFIG_QCOM_HFPLL is not set
+# CONFIG_QCOM_MEMORY_DUMP_V2 is not set
+# CONFIG_QCOM_MDT_LOADER is not set
+CONFIG_QCOM_QFPROM=y
+# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
+CONFIG_QCOM_RPM_CLK=y
+# CONFIG_QCOM_RTB is not set
+# CONFIG_QCOM_PM is not set
+CONFIG_QCOM_SCM=y
+CONFIG_QCOM_SCM_32=y
+# CONFIG_HAVE_ARM_SMCCC is not set
+CONFIG_QCA_SCM_RESTART_REASON=y
+CONFIG_IPQ_TCSR=y
+CONFIG_QCOM_QFPROM=y
+# CONFIG_QCOM_SMD is not set
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMEM_STATE=y
+# CONFIG_QCOM_SMD is not set
+CONFIG_QCOM_SMP2P=y
+# CONFIG_QCOM_SPMI_VADC is not set
+CONFIG_QCOM_TSENS=y
+CONFIG_QCOM_TZ_LOG=y
+CONFIG_QCOM_WDT=y
+CONFIG_QMI_ENCDEC=y
+CONFIG_RATIONAL=y
+# CONFIG_RCU_BOOST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_GZIP=y
+CONFIG_REGMAP=y
+# CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS is not set
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_CPR3 is not set
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_QCOM_RPM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+# CONFIG_REGULATOR_IPQ40XX is not set
+# CONFIG_REGULATOR_RPM_SMD is not set
+# CONFIG_REGULATOR_RPM_GLINK is not set
+CONFIG_RELAY=y
+CONFIG_REMOTEPROC=y
+# CONFIG_IPQ807X_REMOTEPROC is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_NET_L3_MASTER_DEV=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_PM8XXX is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_SATA_AHCI is not set
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCSI is not set
+# CONFIG_SCHED_INFO is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_DMA is not set
+# CONFIG_SERIAL_AMBA_PL010 is not set
+# CONFIG_SERIAL_AMBA_PL011 is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+# CONFIG_VIRTIO_CONSOLE is not set
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SND is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=32
+CONFIG_SND_PROC_FS=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_APQ8016_SBC is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_IPQ is not set
+# CONFIG_SND_SOC_IPQ806X_LPAIF is not set
+# CONFIG_SND_SOC_IPQ806X_PCM_RAW is not set
+CONFIG_SND_SOC_IPQ_ADSS=y
+CONFIG_SND_SOC_IPQ_CODEC=y
+CONFIG_SND_SOC_IPQ_CPU_DAI=y
+CONFIG_SND_SOC_IPQ_MBOX=y
+CONFIG_SND_SOC_IPQ_PCM_I2S=y
+CONFIG_SND_SOC_IPQ_PCM_RAW=y
+CONFIG_SND_SOC_IPQ_PCM_SPDIF=y
+CONFIG_SND_SOC_IPQ_PCM_TDM=y
+CONFIG_SND_SOC_IPQ_STEREO=y
+CONFIG_SND_SOC_QCOM=y
+# CONFIG_SND_SOC_STORM is not set
+CONFIG_SOUND=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_VSC7385 is not set
+CONFIG_SPMI=y
+CONFIG_SPMI_MSM_PMIC_ARB=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_STOPWATCH is not set
+CONFIG_SUSPEND=y
+CONFIG_SWCONFIG=y
+CONFIG_SWIOTLB=y
+# CONFIG_SWAP is not set
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_THUMB2_KERNEL is not set
+# CONFIG_TICK_CPU_ACCOUNTING is not set
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_TRACING_EVENTS_GPIO=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_XZ=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_USB_GADGET=n
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+# CONFIG_USB_QCOM_8X16_PHY is not set
+# CONFIG_USB_QCOM_KS_BRIDGE is not set
+# CONFIG_USB_QCOM_QUSB_PHY is not set
+# CONFIG_USB_QCOM_QMP_PHY is not set
+# CONFIG_USB_QCA_M31_PHY is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
+CONFIG_USE_OF=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WL_TI is not set
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_QCOM_CACHE_DUMP=y
+CONFIG_QCOM_CACHE_DUMP_ON_PANIC=y
+# CONFIG_QCOM_RESTART_REASON is not set
+# CONFIG_QCOM_DLOAD_MODE is not set
+CONFIG_FW_AUTH=y
+CONFIG_FW_AUTH_TEST=m
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_PUBLIC_KEY_ALGO_RSA=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_PKCS7_MESSAGE_PARSER=n
+CONFIG_KEYS=y
+# CONFIG_SKB_RECYCLER is not set
+CONFIG_SKB_RECYCLER_MULTI_CPU=y
+# CONFIG_SKB_RECYCLER_PREALLOC is not set
+# CONFIG_U_SERIAL_CONSOLE is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_NF_IPV6_DUMMY_HEADER is not set
+# CONFIG_RMNET is not set
+# CONFIG_RMNET_DATA is not set
+# CONFIG_RMNET_CTL is not set
+# CONFIG_MSM_SECURE_BUFFER is not set
+# CONFIG_STAGING is not set
+# CONFIG_ANDROID is not set
+# CONFIG_ION is not set
+# CONFIG_ION_DUMMY is not set
+# CONFIG_ION_MSM is not set
+# CONFIG_ION_TEST is not set
+# CONFIG_CMA is not set
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+# CONFIG_DMA_CMA is not set
+# CONFIG_CMA_AREAS is not set
+# CONFIG_CMA_SIZE_MBYTES is not set
+# CONFIG_CMA_SIZE_SEL_MBYTES is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+# CONFIG_CMA_ALIGNMENT is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_ANDROID_TIMED_OUTPUT is not set
+# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
+# CONFIG_SYNC is not set
+# CONFIG_SW_SYNC is not set
+# CONFIG_FSL_MC_BUS is not set
+# CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS is not set
+CONFIG_ALLOC_SKB_PAGE_FRAG_DISABLE=y
+# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set
+# CONFIG_MAILBOX is not set
+# CONFIG_MAILBOX_TEST is not set
+# CONFIG_QCOM_APCS_IPC is not set
+# CONFIG_QCOM_GLINK_SSR is not set
+# CONFIG_QCOM_Q6V5_WCSS is not set
+# CONFIG_QCOM_SYSMON is not set
+# CONFIG_QRTR is not set
+# CONFIG_QRTR_SMD is not set
+# CONFIG_QRTR_TUN is not set
+# CONFIG_RPMSG is not set
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_RPMSG_VIRTIO is not set
+# CONFIG_RPMSG_CHAR is not set
+# CONFIG_RPMSG_QCOM_GLINK_SMEM is not set
+# CONFIG_RPMSG_QCOM_SMD is not set
+CONFIG_QCA_MINIDUMP=y
+# CONFIG_QCA_MINIDUMP_DEBUG is not set
+# CONFIG_QRTR_USB is not set
+# CONFIG_QRTR_FIFO is not set
+CONFIG_QRTR_MHI=y
+CONFIG_MHI_BUS=y
+# CONFIG_MHI_QTI is not set
+# CONFIG_MHI_NETDEV is not set
+# CONFIG_MHI_DEBUG is not set
+# CONFIG_MHI_UCI is not set
+# CONFIG_MHI_SATELLITE is not set
+# CONFIG_DIAG_OVER_QRTR is not set
+# CONFIG_MSM_ADSPRPC is not set
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_ARCH_HAS_KCOV is not set
+# CONFIG_KCOV is not set
+# CONFIG_GCC_PLUGINS is not set
+# CONFIG_QTI_Q6V5_ADSP is not set
+# CONFIG_MSM_RPM_RPMSG is not set
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
+# CONFIG_REGULATOR_RPM_GLINK is not set
+# CONFIG_MTD_NAND_SERIAL is not set
+# CONFIG_ARM_QTI_IPQ60XX_CPUFREQ is not set
+# CONFIG_PAGE_SCOPE_MULTI_PAGE_READ is not set
+# CONFIG_CRYPTO_NO_ZERO_LEN_HASH is not set
+# CONFIG_CRYPTO_DISABLE_AES192_TEST is not set
+# CONFIG_QTI_EUD is not set
+# CONFIG_EUD_EXTCON_SUPPORT is not set
+# CONFIG_CLK_TEST_5018 is not set
+CONFIG_MAP_E_SUPPORT=y
+# CONFIG_IPQ_FLASH_16M_PROFILE is not set
+# CONFIG_QGIC2_MSI is not set
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_ARCH_IPQ256M is not set
+CONFIG_SKB_FIXED_SIZE_2K=y
+# CONFIG_IPQ_MEM_PROFILE is not set
+# CONFIG_VIRTIO_NET is not set
+# CONFIG_QCA_85XX_SWITCH is not set
+CONFIG_AQ_PHY=y
+CONFIG_DIAG_CHAR=y
+# CONFIG_HW_RANDOM_VIRTIO is not set
+# CONFIG_BOOTCONFIG_PARTITION is not set
+# CONFIG_CRYPTO_DEV_QCEDEV is not set
+# CONFIG_CRYPTO_DEV_QCRYPTO is not set
+# CONFIG_MHI_BUS_TEST is not set

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/ipq8074-hk14.dts

@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2020 The Linux Foundation. All rights reserved.
-
-#include "../../../arm64/boot/dts/qcom/ipq8074-hk14.dts"
-#include "ipq8074.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq5018-eap104.dts

@@ -15,4 +15,9 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq5018-eap104.dts"
-#include "ipq5018.dtsi"
+
+/ {
+	pmuv8: pmu {
+		compatible = "arm,cortex-a7-pmu";
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-cig-wf188n.dts

@@ -15,4 +15,4 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq6018-cig-wf188n.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-edgecore-eap101.dts

@@ -15,4 +15,4 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq6018-edgecore-eap101.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-gl-ax1800.dts

@@ -15,4 +15,4 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-gl-axt1800.dts

@@ -15,4 +15,4 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq6018-gl-axt1800.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4xe.dts

@@ -14,10 +14,5 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4x.dts"
+#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4xe.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"
-
-/ {
-	model = "HFCL ION4Xe";
-	compatible = "hfcl,ion4xe", "qcom,ipq6018-cp01", "qcom,ipq6018";
-};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-hfcl-ion4xi.dts

@@ -14,10 +14,5 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4x.dts"
+#include "../../../arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4xi.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"
-
-/ {
-	model = "HFCL ION4Xi";
-	compatible = "hfcl,ion4xi", "qcom,ipq6018-cp01", "qcom,ipq6018";
-};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq6018-yuncore-ax840.dts

@@ -15,4 +15,4 @@
  */
 
 #include "../../../arm64/boot/dts/qcom/qcom-ipq6018-yuncore-ax840.dts"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-eap102.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-eap106.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-eap106.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-ex227.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-ex227.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-ex447.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-ex447.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf194c.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf194c.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf194c4.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf194c4.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm/boot/dts/qcom-ipq807x-wf196.dts

@@ -14,4 +14,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include "../../../arm64/boot/dts/qcom/qcom-ipq807x-wf196.dts"
-#include "ipq8074.dtsi"
+
+/ {
+	soc {
+		pmu {
+			compatible = "arm,cortex-a7-pmu";
+			interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+					IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eap104.dts

@@ -1,7 +1,5 @@
 /dts-v1/;
-/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
- *
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,7 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ipq5018.dtsi"
+#include "qcom-ipq5018.dtsi"
 
 / {
 	#address-cells = <0x2>;
@@ -40,7 +38,11 @@
 
 	chosen {
 		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+		bootargs-append = " swiotlb=1";
+	#else
 		bootargs-append = " swiotlb=1 coherent_pool=2M";
+	#endif
 		stdout-path = "serial0";
 	};
 
@@ -78,22 +80,22 @@
 	 * |   QDSS   |  0x4D200000  |           1MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_1|              |                         |
-	 * |   data   |  0x4D300000  |          13MB           |
+	 * |   data   |  0x4D300000  |          15MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_1|              |                         |
-	 * |  M3 Dump |  0x4E000000  |           1MB           |
+	 * |  M3 Dump |  0x4E200000  |           1MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_1|              |                         |
-	 * |   QDSS   |  0x4E100000  |           1MB           |
+	 * |   QDSS   |  0x4E300000  |           1MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_2|              |                         |
-	 * |   data   |  0x4E200000  |          13MB           |
+	 * |   data   |  0x4E400000  |          15MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_2|              |                         |
-	 * |  M3 Dump |  0x4EF00000  |           1MB           |
+	 * |  M3 Dump |  0x4F300000  |           1MB           |
 	 * +----------+--------------+-------------------------+
 	 * | QCN6122_2|              |                         |
-	 * |   QDSS   |  0x4F000000  |           1MB           |
+	 * |   QDSS   |  0x4F400000  |           1MB           |
 	 * +----------+--------------+-------------------------+
 	 * |                                                   |
 	 * |            Rest of the memory for Linux           |
@@ -102,7 +104,7 @@
 	 */
 		q6_mem_regions: q6_mem_regions@4B000000 {
 			no-map;
-			reg = <0x0 0x4B000000 0x0 0x4100000>;
+			reg = <0x0 0x4B000000 0x0 0x4500000>;
 		};
 
 		q6_code_data: q6_code_data@4B000000 {
@@ -127,32 +129,32 @@
 
 		q6_qcn6122_data1: q6_qcn6122_data1@4D300000 {
 			no-map;
-			reg = <0x0 0x4D300000 0x0 0xD00000>;
+			reg = <0x0 0x4D300000 0x0 0xF00000>;
 		};
 
-		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E000000 {
+		m3_dump_qcn6122_1: m3_dump_qcn6122_1@4E200000 {
 			no-map;
-			reg = <0x0 0x4E000000 0x0 0x100000>;
+			reg = <0x0 0x4E200000 0x0 0x100000>;
 		};
 
-		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E100000 {
+		q6_qcn6122_etr_1: q6_qcn6122_etr_1@4E300000 {
 			no-map;
-			reg = <0x0 0x4E100000 0x0 0x100000>;
+			reg = <0x0 0x4E300000 0x0 0x100000>;
 		};
 
-		q6_qcn6122_data2: q6_qcn6122_data2@4E200000 {
+		q6_qcn6122_data2: q6_qcn6122_data2@4E400000 {
 			no-map;
-			reg = <0x0 0x4E200000 0x0 0xD00000>;
+			reg = <0x0 0x4E400000 0x0 0xF00000>;
 		};
 
-		m3_dump_qcn6122_2: m3_dump_qcn6122_2@4EF00000 {
+		m3_dump_qcn6122_2: m3_dump_qcn6122_2@4F300000 {
 			no-map;
-			reg = <0x0 0x4EF00000 0x0 0x100000>;
+			reg = <0x0 0x4F300000 0x0 0x100000>;
 		};
 
-		q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F000000 {
+		q6_qcn6122_etr_2: q6_qcn6122_etr_2@4F400000 {
 			no-map;
-			reg = <0x0 0x4F000000 0x0 0x100000>;
+			reg = <0x0 0x4F400000 0x0 0x100000>;
 		};
 	#else
 	/*                 512MB/1GB Profiles
@@ -299,6 +301,7 @@
 		blsp1_uart2: serial@78b0000 {
 			pinctrl-0 = <&blsp1_uart_pins>;
 			pinctrl-names = "default";
+			status = "ok";
 		};
 
 		qpic_bam: dma@7984000{
@@ -341,6 +344,7 @@
 			pinctrl-0 = <&mdio1_pins>;
 			pinctrl-names = "default";
 			phy-reset-gpio = <&tlmm 39 0>;
+
 			ethernet-phy@0 {
 				reg = <0>;
 			};
@@ -376,6 +380,8 @@
 						forced-duplex = <1>;
 					};
 				};
+				
+				/*
 				led_source@0 {
 					source = <0>;
 					mode = "normal";
@@ -383,13 +389,15 @@
 					blink_en = "enable";
 					active = "high";
 				};
+				*/
+				
 			};
 			ess-switch1@1 {
 				compatible = "qcom,ess-switch-qca83xx";
 				device_id = <1>;
 				switch_access_mode = "mdio";
 				mdio-bus = <&mdio1>;
-				reset_gpio = <&tlmm 0x27 0>;
+				reset_gpio = <0x27>;
 				switch_cpu_bmp = <0x40>;  /* cpu port bitmap */
 				switch_lan_bmp = <0x1e>; /* lan port bitmap */
 				switch_wan_bmp = <0x0>;  /* wan port bitmap */
@@ -424,8 +432,8 @@
 			};
 		};
 
-		ess-uniphy@98000 {
+		wifi0: wifi@c000000 {
-			status = "disabled";
+			status = "ok";
 		};
 
 		dp1 {
@@ -442,7 +450,6 @@
 			mdio-bus = <&mdio0>;
 			local-mac-address = [000000000000];
 			phy-mode = "sgmii";
-			qcom,rx-page-mode = <0>;
 		};
 
 		dp2 {
@@ -456,13 +463,14 @@
 			qcom,mactype = <2>;
 			local-mac-address = [000000000000];
 			phy-mode = "sgmii";
-			qcom,rx-page-mode = <0>;
 		};
 
-		nss-macsec1 {
+		qcom,test@0 {
-			compatible = "qcom,nss-macsec";
+			status = "ok";
-			phy_addr = <0x1c>;
+		};
-			mdiobus = <&mdio1>;
+
+		lpass: lpass@0xA000000{
+			status = "disabled";
 		};
 
 		pcm: pcm@0xA3C0000{
@@ -471,6 +479,29 @@
 			status = "disabled";
 		};
 
+		pcm_lb: pcm_lb@0 {
+			status = "disabled";
+		};
+	};
+
+	thermal-zones {
+		status = "ok";
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		wps {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-0 = <&leds_pins>;
@@ -481,141 +512,39 @@
 			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led@3 {
 			label = "green:wifi2";
 			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led_power: led@30 {
 			label = "green:power";
 			gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
-
 		led@42 {
 			label = "orange:uplink";
 			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led@43 {
 			label = "yellow:uplink";
 			gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led@46 {
 			label = "green:cloud";
 			gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 	};
-	};
-
-	qcom,test@0 {
-		status = "ok";
-	};
-
-	thermal-zones {
-		status = "ok";
-	};
 };
 
 &tlmm {
-	pinctrl-0 = <&blsp0_uart_pins>;
+	/* pinctrl-0 = <&blsp0_uart_pins &phy_led_pins>; */
+	pinctrl-0 = <&blsp0_uart_pins &phy_led_pins &ble_pins>;
 	pinctrl-names = "default";
 
-	blsp0_uart_pins: uart_pins {
-		blsp0_uart_rx_tx {
-			pins = "gpio20", "gpio21";
-			function = "blsp0_uart0";
-			bias-disable;
-		};
-	};
-
-	blsp1_uart_pins: blsp1_uart_pins {
-		blsp1_uart_rx_tx {
-			pins = "gpio23", "gpio25", "gpio24", "gpio26";
-			function = "blsp1_uart2";
-			bias-disable;
-		};
-	};
-
-	blsp0_spi_pins: blsp0_spi_pins {
-		mux {
-			pins = "gpio10", "gpio11", "gpio12", "gpio13";
-			function = "blsp0_spi";
-			drive-strength = <2>;
-			bias-disable;
-		};
-	};
-
-	qspi_nand_pins: qspi_nand_pins {
-		qspi_clock {
-			pins = "gpio9";
-			function = "qspi_clk";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		qspi_cs {
-			pins = "gpio8";
-			function = "qspi_cs";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		qspi_data {
-			pins = "gpio4", "gpio5", "gpio6", "gpio7";
-			function = "qspi_data";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-
-	mdio1_pins: mdio_pinmux {
-		mux_0 {
-			pins = "gpio36";
-			function = "mdc";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-
-		mux_1 {
-			pins = "gpio37";
-			function = "mdio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
-
-	i2c_pins: i2c_pins {
-		i2c_scl {
-			pins = "gpio25";
-			function = "blsp2_i2c1";
-			drive-strength = <8>;
-			bias-disable;
-		};
-
-		i2c_sda {
-			pins = "gpio26";
-			function = "blsp2_i2c1";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-
-	button_pins: button_pins {
-		wps_button {
-			pins = "gpio38";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
-
 	leds_pins: leds_pins {
 		led_5g {
 			pins = "gpio2";
@@ -654,6 +583,131 @@
 			bias-pull-down;
 		};
 	};
+	blsp0_uart_pins: uart_pins {
+		blsp0_uart_rx_tx {
+			pins = "gpio20", "gpio21";
+			function = "blsp0_uart0";
+			bias-disable;
+		};
+	};
+
+	blsp1_uart_pins: blsp1_uart_pins {
+		blsp1_uart_rx_tx {
+			pins = "gpio23", "gpio25", "gpio24", "gpio26";
+			function = "blsp1_uart2";
+			bias-disable;
+		};
+	};
+
+	blsp0_spi_pins: blsp0_spi_pins {
+		mux {
+			pins = "gpio10", "gpio11", "gpio12", "gpio13";
+			function = "blsp0_spi";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	qspi_nand_pins: qspi_nand_pins {
+		qspi_clock {
+			pins = "gpio9";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qspi_cs {
+			pins = "gpio8";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qspi_data_0 {
+			pins = "gpio7";
+			function = "qspi0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qspi_data_1 {
+			pins = "gpio6";
+			function = "qspi1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qspi_data_2 {
+			pins = "gpio5";
+			function = "qspi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qspi_data_3 {
+			pins = "gpio4";
+			function = "qspi3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	mdio1_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mux_1 {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	phy_led_pins: phy_led_pins {
+		gephy_led_pin {
+			pins = "gpio46";
+			/* function = "led0"; */
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+	
+	ble_pins: ble_pins {
+		ble_coex_grant {
+			pins = "gpio19";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	i2c_pins: i2c_pins {
+		i2c_scl {
+			pins = "gpio33";
+			function = "blsp2_i2c0";
+			drive-strength = <8>;
+			/* bias-disable; */
+			bias-pull-up;
+		};
+
+		i2c_sda {
+			pins = "gpio34";
+			function = "blsp2_i2c0";
+			drive-strength = <8>;
+			/* bias-disable; */
+			bias-pull-up;
+		};
+	};
+
+	button_pins: button_pins {
+		wps_button {
+			pins = "gpio38";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
 
 	audio_pins: audio_pinmux {
 		mux_1 {
@@ -705,8 +759,10 @@
 			bias-pull-down;
 		};
 	};
+
 };
 
+/* Disable gpio 38 and 24 
 &soc {
 	gpio_keys {
 		compatible = "gpio-keys";
@@ -714,244 +770,36 @@
 		pinctrl-names = "default";
 
 		button@1 {
-			label = "reset";
+			label = "wps";
-			linux,code = <KEY_RESTART>;
+			linux,code = <KEY_WPS_BUTTON>;
-			gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+			gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
 			linux,input-type = <1>;
 			debounce-interval = <60>;
 		};
 	};
 };
 
-&q6v5_wcss {
-	compatible = "qcom,ipq5018-q6-mpd";
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges;
-	firmware = "IPQ5018/q6_fw.mdt";
-	reg = <0x0cd00000 0x4040>,
-		<0x1938000 0x8>,
-		<0x193d204 0x4>;
-	reg-names = "qdsp6",
-			"tcsr-msip",
-			"tcsr-q6";
-	resets = <&gcc GCC_WCSSAON_RESET>,
-			<&gcc GCC_WCSS_Q6_BCR>;
-
-	reset-names = "wcss_aon_reset",
-			"wcss_q6_reset";
-
-	clocks = <&gcc GCC_Q6_AXIS_CLK>,
-		<&gcc GCC_WCSS_ECAHB_CLK>,
-		<&gcc GCC_Q6_AXIM_CLK>,
-		<&gcc GCC_Q6_AXIM2_CLK>,
-		<&gcc GCC_Q6_AHB_CLK>,
-		<&gcc GCC_Q6_AHB_S_CLK>,
-		<&gcc GCC_WCSS_AXI_S_CLK>;
-	clock-names = "gcc_q6_axis_clk",
-		"gcc_wcss_ecahb_clk",
-		"gcc_q6_axim_clk",
-		"gcc_q6_axim2_clk",
-		"gcc_q6_ahb_clk",
-		"gcc_q6_ahb_s_clk",
-		"gcc_wcss_axi_s_clk";
-
-	#ifdef __IPQ_MEM_PROFILE_256_MB__
-		memory-region = <&q6_mem_regions>, <&q6_etr_region>;
-	#else
-		memory-region = <&q6_mem_regions>, <&q6_etr_region>,
-				<&q6_caldb_region>;
-	#endif
-
-	qcom,rproc = <&q6v5_wcss>;
-	qcom,bootargs_smem = <507>;
-	boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
-			<0x2 0x4 0x2 0x12 0x0 0x0>;
-	status = "ok";
-	q6_wcss_pd1: remoteproc_pd1@4ab000 {
-		compatible = "qcom,ipq5018-wcss-ahb-mpd";
-		reg = <0x4ab000 0x20>;
-		reg-names = "rmb";
-		firmware = "IPQ5018/q6_fw.mdt";
-		m3_firmware = "IPQ5018/m3_fw.mdt";
-		interrupts-extended = <&wcss_smp2p_in 8 0>,
-					<&wcss_smp2p_in 9 0>,
-					<&wcss_smp2p_in 12 0>,
-					<&wcss_smp2p_in 11 0>;
-		interrupt-names = "fatal",
-					"ready",
-					"spawn-ack",
-					"stop-ack";
-
-		resets = <&gcc GCC_WCSSAON_RESET>,
-				<&gcc GCC_WCSS_BCR>,
-				<&gcc GCC_CE_BCR>;
-		reset-names = "wcss_aon_reset",
-				"wcss_reset",
-				"ce_reset";
-
-		clocks = <&gcc GCC_WCSS_AHB_S_CLK>,
-				<&gcc GCC_WCSS_ACMT_CLK>,
-				<&gcc GCC_WCSS_AXI_M_CLK>;
-		clock-names = "gcc_wcss_ahb_s_clk",
-					"gcc_wcss_acmt_clk",
-					"gcc_wcss_axi_m_clk";
-
-		qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
-
-		qcom,smem-states = <&wcss_smp2p_out 8>,
-					<&wcss_smp2p_out 9>,
-					<&wcss_smp2p_out 10>;
-		qcom,smem-state-names = "shutdown",
-					"stop",
-					"spawn";
-	#ifdef __IPQ_MEM_PROFILE_256_MB__
-		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
-				<&q6_etr_region>;
-	#else
-		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
-				<&q6_etr_region>, <&q6_caldb_region>;
-	#endif
-
-	};
-
-	q6_wcss_pd2: remoteproc_pd2 {
-		compatible = "qcom,ipq5018-wcss-pcie-mpd";
-		firmware = "IPQ5018/q6_fw.mdt";
-		m3_firmware = "qcn6122/m3_fw.mdt";
-		interrupts-extended = <&wcss_smp2p_in 16 0>,
-					<&wcss_smp2p_in 17 0>,
-					<&wcss_smp2p_in 20 0>,
-					<&wcss_smp2p_in 19 0>;
-		interrupt-names = "fatal",
-					"ready",
-					"spawn-ack",
-					"stop-ack";
-
-		qcom,smem-states = <&wcss_smp2p_out 16>,
-					<&wcss_smp2p_out 17>,
-					<&wcss_smp2p_out 18>;
-		qcom,smem-state-names = "shutdown",
-					"stop",
-					"spawn";
-	#ifdef __IPQ_MEM_PROFILE_256_MB__
-		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
-				<&q6_qcn6122_etr_1>;
-	#else
-		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
-				<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
-	#endif
-
-	};
-
-	q6_wcss_pd3: remoteproc_pd3 {
-		compatible = "qcom,ipq5018-wcss-pcie-mpd";
-		firmware = "IPQ5018/q6_fw.mdt";
-		interrupts-extended = <&wcss_smp2p_in 24 0>,
-					<&wcss_smp2p_in 25 0>,
-					<&wcss_smp2p_in 28 0>,
-					<&wcss_smp2p_in 27 0>;
-		interrupt-names = "fatal",
-					"ready",
-					"spawn-ack",
-					"stop-ack";
-
-		qcom,smem-states = <&wcss_smp2p_out 24>,
-					<&wcss_smp2p_out 25>,
-					<&wcss_smp2p_out 26>;
-		qcom,smem-state-names = "shutdown",
-					"stop",
-					"spawn";
-	#ifdef	__IPQ_MEM_PROFILE_256_MB__
-		memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
-				<&q6_qcn6122_etr_2>;
-	#else
-		memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
-				<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
-	#endif
-	};
-};
-
-&i2c_0 {
-	pinctrl-0 = <&i2c_pins>;
-	pinctrl-names = "default";
-	status = "disabled";
-};
-
-&wifi0 {
-	/* IPQ5018 */
-	qcom,multipd_arch;
-	qcom,rproc = <&q6_wcss_pd1>;
-	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-	qcom,tgt-mem-mode = <2>;
-#else
-	qcom,tgt-mem-mode = <1>;
-#endif
-	qcom,board_id = <0x23>;
-	qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
-#ifdef __CNSS2__
-	qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
-#else
-	qcom,caldb-addr = <0x4D400000>;
-	m3-dump-addr = <0x4D200000>;
-#endif
-	qcom,caldb-size = <0x200000>;
-	mem-region = <&q6_ipq5018_data>;
-	status = "ok";
-};
-
-&wifi1 {
-	/* QCN6122 5G */
-	qcom,multipd_arch;
-	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
-	qcom,rproc = <&q6_wcss_pd2>;
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-	qcom,tgt-mem-mode = <2>;
-#else
-	qcom,tgt-mem-mode = <1>;
-#endif
-	qcom,board_id = <0x60>;
-	qcom,bdf-addr = <0x4D600000 0x4D600000 0x4D300000 0x0 0x0>;
-#ifdef __CNSS2__
-	qcom,caldb-addr = <0x4E800000 0x4E800000 0 0 0>;
-#else
-	qcom,caldb-addr = <0x4E800000>;
-	m3-dump-addr = <0x4E600000>;
-#endif
-	qcom,caldb-size = <0x500000>;
-	mem-region = <&q6_qcn6122_data1>;
-	status = "disabled";
-};
-
-&wifi2 {
-	/* QCN6122 6G */
-	qcom,multipd_arch;
-	qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
-	qcom,rproc = <&q6_wcss_pd3>;
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-	qcom,tgt-mem-mode = <2>;
-#else
-	qcom,tgt-mem-mode = <1>;
-#endif
-	qcom,board_id = <0xb0>;
-	qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E200000 0x0 0x0>;
-#ifdef __CNSS2__
-	qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
-#else
-	qcom,caldb-addr = <0x4FF00000>;
-	m3-dump-addr = <0x4FD00000>;
-#endif
-	qcom,caldb-size = <0x500000>;
-	mem-region = <&q6_qcn6122_data2>;
-	status = "disabled";
-};
-
 &usb3 {
 	status = "ok";
 	device-power-gpio = <&tlmm 24 1>;
 };
 
+*/
+
+&eud {
+	status = "ok";
+};
+
+&pcie_x1 {
+	status = "disabled";
+	perst-gpio = <&tlmm 18 1>;
+};
+
+&pcie_x2 {
+	status = "disabled";
+	perst-gpio = <&tlmm 15 1>;
+};
+
 &dwc_0 {
 	/delete-property/ #phy-cells;
 	/delete-property/ phys;
@@ -962,20 +810,6 @@
 	status = "ok";
 };
 
-&eud {
-	status = "ok";
-};
-
-&pcie_x1 {
-	status = "disabled";
-	perst-gpio = <&tlmm 18 GPIO_ACTIVE_LOW>;
-};
-
-&pcie_x2 {
-	status = "disabled";
-	perst-gpio = <&tlmm 15 GPIO_ACTIVE_LOW>;
-};
-
 &pcie_x1phy {
 	status = "disabled";
 };
@@ -1000,3 +834,182 @@
 
 	};
 };
+
+&qfprom {
+	status = "ok";
+};
+
+&tsens {
+	status = "ok";
+};
+
+&qcom_q6v5_wcss {
+	qcom,multipd_arch;
+	memory-region = <&q6_mem_regions>;
+	qcom,share_bootargs;
+	qcom,bootargs_smem = <507>;
+	boot-args = <0x1 0x4 0x3 0x0F 0x0 0x0>,
+			<0x2 0x4 0x2 0x12 0x0 0x0>;
+	/* IPQ5018 */
+	q6v5_wcss_userpd1 {
+		m3_firmware = "IPQ5018/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names ="fatal",
+			"ready",
+			"spawn_ack",
+			"stop-ack";
+		qcom,smem-states = <&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names = "shutdown",
+			"stop",
+			"spawn";
+		qca,asid = <1>;
+		qca,auto-restart;
+		qca,int_radio;
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
+				<&q6_etr_region>;
+		#else
+		memory-region = <&q6_ipq5018_data>, <&m3_dump>,
+				<&q6_etr_region>, <&q6_caldb_region>;
+		#endif
+	};
+
+	/* QCN6122 6G */
+	q6v5_wcss_userpd2 {
+		m3_firmware = "qcn6122/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 16 0>,
+			<&wcss_smp2p_in 17 0>,
+			<&wcss_smp2p_in 20 0>,
+			<&wcss_smp2p_in 19 0>;
+		interrupt-names ="fatal",
+			"ready",
+			"spawn_ack",
+			"stop-ack";
+		qcom,smem-states = <&wcss_smp2p_out 16>,
+			<&wcss_smp2p_out 17>,
+			<&wcss_smp2p_out 18>;
+		qcom,smem-state-names = "shutdown",
+			"stop",
+			"spawn";
+		qca,asid = <2>;
+		qca,auto-restart;
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
+				<&q6_qcn6122_etr_1>;
+		#else
+		memory-region = <&q6_qcn6122_data1>, <&m3_dump_qcn6122_1>,
+				<&q6_qcn6122_etr_1>, <&q6_qcn6122_caldb_1>;
+		#endif
+	};
+
+	/* QCN6122 5G */
+	q6v5_wcss_userpd3 {
+		m3_firmware = "qcn6122/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 24 0>,
+			<&wcss_smp2p_in 25 0>,
+			<&wcss_smp2p_in 28 0>,
+			<&wcss_smp2p_in 27 0>;
+		interrupt-names ="fatal",
+			"ready",
+			"spawn_ack",
+			"stop-ack";
+		qcom,smem-states = <&wcss_smp2p_out 24>,
+			<&wcss_smp2p_out 25>,
+			<&wcss_smp2p_out 26>;
+		qcom,smem-state-names = "shutdown",
+			"stop",
+			"spawn";
+		qca,asid = <3>;
+		qca,auto-restart;
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+		memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
+				<&q6_qcn6122_etr_2>;
+		#else
+		memory-region = <&q6_qcn6122_data2>, <&m3_dump_qcn6122_2>,
+				<&q6_qcn6122_etr_2>, <&q6_qcn6122_caldb_2>;
+		#endif
+	};
+};
+
+&i2c_0 {
+	pinctrl-0 = <&i2c_pins>;
+	pinctrl-names = "default";
+	/* status = "disabled"; */
+	status = "ok";
+};
+
+&qgic_msi_0 {
+	status = "ok";
+};
+
+&qgic_msi_1 {
+	status = "ok";
+};
+
+&wifi0 {
+	/* IPQ5018 */
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	qcom,tgt-mem-mode = <2>;
+#else
+	qcom,tgt-mem-mode = <1>;
+#endif
+	qcom,board_id = <0x23>;
+	qcom,bdf-addr = <0x4C400000 0x4C400000 0x4C400000 0x0 0x0>;
+#ifdef __CNSS2__
+	qcom,caldb-addr = <0x4D400000 0x4D400000 0 0 0>;
+#else
+	qcom,caldb-addr = <0x4D400000>;
+	m3-dump-addr = <0x4D200000>;
+#endif
+	qcom,caldb-size = <0x200000>;
+	status = "ok";
+};
+
+&wifi1 {
+	/* QCN6122 5G */
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	qcom,tgt-mem-mode = <2>;
+#else
+	qcom,tgt-mem-mode = <1>;
+#endif
+	qcom,board_id = <0x50>;
+	qcom,bdf-addr = <0x4D600000 0x4D600000 0x4D300000 0x0 0x0>;
+#ifdef __CNSS2__
+	qcom,caldb-addr = <0x4E800000 0x4E800000 0 0 0>;
+#else
+	qcom,caldb-addr = <0x4E800000>;
+	m3-dump-addr = <0x4E600000>;
+#endif
+	qcom,caldb-size = <0x500000>;
+	status = "disabled";
+};
+
+&wifi2 {
+	/* QCN6122 6G */
+	qcom,multipd_arch;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd3";
+#ifdef __IPQ_MEM_PROFILE_256_MB__
+	qcom,tgt-mem-mode = <2>;
+#else
+	qcom,tgt-mem-mode = <1>;
+#endif
+	qcom,board_id = <0xb0>;
+	qcom,bdf-addr = <0x4ED00000 0x4ED00000 0x4E400000 0x0 0x0>;
+#ifdef __CNSS2__
+	qcom,caldb-addr = <0x4FF00000 0x4FF00000 0 0 0>;
+#else
+	qcom,caldb-addr = <0x4FF00000>;
+	m3-dump-addr = <0x4FD00000>;
+#endif
+	qcom,caldb-size = <0x500000>;
+	status = "ok";
+};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq5018-eww622-a1.dts

@@ -1,7 +1,5 @@
 /dts-v1/;
-/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
- *
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,14 +14,17 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ipq5018.dtsi"
+#include "qcom-ipq5018.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03.1";
-	compatible = "qcom,ipq5018-ap-mp03.1", "qcom,ipq5018-mp03.1", "qcom,ipq5018";
+	compatible = "qcom,ipq5018-mp03.1", "qcom,ipq5018";
 	interrupt-parent = <&intc>;
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+	AUTO_MOUNT;
+	#endif
 
 	aliases {
 		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
@@ -31,11 +32,19 @@
 		serial1 = &blsp1_uart2;
 		ethernet0 = "/soc/dp1";
 		ethernet1 = "/soc/dp2";
+	        led-boot = &led_sys;
+		led-failsafe = &led_sys;
+		led-running = &led_sys;
+		led-upgrade = &led_sys;
 	};
 
 	chosen {
 		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
+	#ifdef __IPQ_MEM_PROFILE_256_MB__
+		bootargs-append = " swiotlb=1";
+	#else
 		bootargs-append = " swiotlb=1 coherent_pool=2M";
+	#endif
 		stdout-path = "serial0";
 	};
 
@@ -92,7 +101,7 @@
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |        |              |                         |
-	 * |  MHI1  |  0x4DA00000  |           9MB           |
+	 * |  MHI1  |  0x4DA00000  |          16MB           |
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |                                                 |
@@ -100,7 +109,7 @@
 	 * |                                                 |
 	 * +=================================================+
 	 */
-		q6_region: memory@4b000000 {
+		q6_region: wcnss@4b000000 {
 			no-map;
 			reg = <0x0 0x4b000000 0x0 0x01700000>;
 		};
@@ -115,18 +124,16 @@
 			reg = <0x0 0x4c800000 0x0 0x100000>;
 		};
 
-		qcn9000_pcie0: qcn9000_pcie0@4c900000 {
+		qcn9000_pcie0@4c900000 {
 			no-map;
 			reg = <0x0 0x4C900000 0x0 0x01100000>;
 		};
 
-	#if defined(__CNSS2__)
 		mhi_region1: dma_pool1@4da00000 {
 			compatible = "shared-dma-pool";
 			no-map;
-			reg = <0x0 0x4DA00000 0x0 0x00900000>;
+			reg = <0x0 0x4da00000 0x0 0x01000000>;
 		};
-	#endif
 	#elif __IPQ_MEM_PROFILE_512_MB__
 	/*                      512 MB Profile
 	 * +=========+==============+========================+
@@ -176,11 +183,11 @@
 	 * | caldb  |  0x4CA00000  |           2MB           |
 	 * +--------+--------------+-------------------------+
 	 * |        |              |                         |
-	 * |QCN9000 |  0x4CC00000  |          38MB           |
+	 * |QCN9000 |  0x4CC00000  |          30MB           |
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |        |              |                         |
-	 * |  MHI1  |  0x4F200000  |           9MB           |
+	 * |  MHI1  |  0x4EA00000  |          16MB           |
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |                                                 |
@@ -188,7 +195,7 @@
 	 * |                                                 |
 	 * +=================================================+
 	 */
-		q6_region: memory@4b000000 {
+		q6_region: wcnss@4b000000 {
 			no-map;
 			reg = <0x0 0x4b000000 0x0 0x01800000>;
 		};
@@ -208,18 +215,16 @@
 			reg = <0x0 0x4ca00000 0x0 0x200000>;
 		};
 
-		qcn9000_pcie0: qcn9000_pcie0@4cc00000 {
+		qcn9000_pcie0@4cc00000 {
 			no-map;
-			reg = <0x0 0x4CC00000 0x0 0x02600000>;
+			reg = <0x0 0x4CC00000 0x0 0x01E00000>;
 		};
 
-	#if defined(__CNSS2__)
+		mhi_region1: dma_pool1@4ea00000 {
-		mhi_region1: dma_pool1@4f200000 {
 			compatible = "shared-dma-pool";
 			no-map;
-			reg = <0x0 0x4f200000 0x0 0x00900000>;
+			reg = <0x0 0x4ea00000 0x0 0x01000000>;
 		};
-	#endif
 	#else
 	/*                      1G Profile
 	 * +=========+==============+========================+
@@ -269,11 +274,11 @@
 	 * | caldb  |  0x4CA00000  |           2MB           |
 	 * +--------+--------------+-------------------------+
 	 * |        |              |                         |
-	 * |QCN9000 |  0x4CC00000  |          53MB           |
+	 * |QCN9000 |  0x4CC00000  |          45MB           |
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |        |              |                         |
-	 * |  MHI1  |  0x50100000  |           9MB           |
+	 * |  MHI1  |  0x4F900000  |          24MB           |
 	 * |        |              |                         |
 	 * +--------+--------------+-------------------------+
 	 * |                                                 |
@@ -281,7 +286,7 @@
 	 * |                                                 |
 	 * +=================================================+
 	 */
-		q6_region: memory@4b000000 {
+		q6_region: wcnss@4b000000 {
 			no-map;
 			reg = <0x0 0x4b000000 0x0 0x01800000>;
 		};
@@ -301,19 +306,17 @@
 			reg = <0x0 0x4ca00000 0x0 0x200000>;
 		};
 
-		qcn9000_pcie0: qcn9000_pcie0@4cc00000 {
+		qcn9000_pcie0@4cc00000 {
 			no-map;
-			reg = <0x0 0x4CC00000 0x0 0x03500000>;
+			reg = <0x0 0x4CC00000 0x0 0x02D00000>;
 		};
 
-	#if defined(__CNSS2__)
+		mhi_region1: dma_pool1@4F900000 {
-		mhi_region1: dma_pool1@50100000 {
 			compatible = "shared-dma-pool";
 			no-map;
-			reg = <0x0 0x50100000 0x0 0x00900000>;
+			reg = <0x0 0x4F900000 0x0 0x01800000>;
 		};
 	#endif
-	#endif
 	};
 
 	soc {
@@ -425,7 +428,7 @@
 				device_id = <1>;
 				switch_access_mode = "mdio";
 				mdio-bus = <&mdio1>;
-				reset_gpio = <&tlmm 0x27 0>;
+				reset_gpio = <0x27>;
 				switch_cpu_bmp = <0x40>;  /* cpu port bitmap */
 				switch_lan_bmp = <0x3c>; /* lan port bitmap */
 				switch_wan_bmp = <0x0>;  /* wan port bitmap */
@@ -464,6 +467,15 @@
 			};
 		};
 
+		wifi0: wifi@c000000 {
+			qcom,bdf-addr = <0x4BA00000 0x4BA00000 0x4BA00000
+						0x0 0x0>;
+			qcom,caldb-addr = <0x4CA00000 0x4CA00000 0x4CA00000
+						0x0 0x0>;
+			qcom,caldb-size = <0x200000>;
+			status = "ok";
+		};
+
 		ess-uniphy@98000 {
 			status = "disabled";
 		};
@@ -472,6 +484,10 @@
 			status = "ok";
 		};
 
+		qcom,usbbam@8B04000 {
+			status = "ok";
+		};
+
 		qcom,diag@0 {
 			status = "ok";
 		};
@@ -490,7 +506,6 @@
 			mdio-bus = <&mdio0>;
 			local-mac-address = [000000000000];
 			phy-mode = "sgmii";
-			qcom,rx-page-mode = <0>;
 		};
 
 		dp2 {
@@ -504,74 +519,16 @@
 			qcom,mactype = <2>;
 			local-mac-address = [000000000000];
 			phy-mode = "sgmii";
-			qcom,rx-page-mode = <0>;
 		};
 
 		rpm_etm0 {
 			status = "disabled";
 		};
-
-		pcm: pcm@0xA3C0000{
-			pinctrl-0 = <&audio_pins>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		gpio_keys {
-			compatible = "gpio-keys";
-			pinctrl-0 = <&button_pins>;
-			pinctrl-names = "default";
-
-			button@1 {
-				label = "wps";
-				linux,code = <KEY_WPS_BUTTON>;
-				gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
-				linux,input-type = <1>;
-				debounce-interval = <60>;
-			};
-
-			button@2 {
-				label = "reset";
-				linux,code = <KEY_RESTART>;
-				gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
-				linux,input-type = <1>;
-				debounce-interval = <60>;
-			};
-		};
-
-		gpio_leds {
-			compatible = "gpio-leds";
-			pinctrl-0 = <&leds_pins>;
-			pinctrl-names = "default";
-
-			led_sys: led@1 {
-				label = "sys:blue";
-				gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;  /* GPIO_1 */
-				default-state="on";
-			};
-
-			led@35 {
-				label = "sys:green";
-				gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;  /* GPIO_35 */
-				default-state="off";
-			};
-
-			led@31 {
-				label = "sys:red";
-				gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;  /* GPIO_31 */
-				default-state="off";
-			};
-		};
-	};
-
-	qcom,test@0 {
-		status = "ok";
 	};
 
 	thermal-zones {
 		status = "ok";
 	};
-
 };
 
 &tlmm {
@@ -610,17 +567,33 @@
 				drive-strength = <8>;
 				bias-disable;
 			};
-
 		qspi_cs {
 				pins = "gpio8";
 				function = "qspi_cs";
 				drive-strength = <8>;
 				bias-disable;
 			};
-
+		qspi_data_0 {
-		qspi_data {
+				pins = "gpio7";
-				pins = "gpio4", "gpio5", "gpio6", "gpio7";
+				function = "qspi0";
-				function = "qspi_data";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		qspi_data_1 {
+				pins = "gpio6";
+				function = "qspi1";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		qspi_data_2 {
+				pins = "gpio5";
+				function = "qspi2";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		qspi_data_3 {
+				pins = "gpio4";
+				function = "qspi3";
 				drive-strength = <8>;
 				bias-disable;
 			};
@@ -643,7 +616,13 @@
 	};
 
 	phy_led_pins: phy_led_pins {
-		gephy_led_pin {
+                gephy_led_pin_1g {
+                        pins = "gpio30";
+                        function = "led2";
+                        drive-strength = <8>;
+                        bias-pull-down;
+                };
+                gephy_led_pin_100 {
                         pins = "gpio46";
                         function = "led0";
                         drive-strength = <8>;
@@ -704,59 +683,51 @@
 		};
 	};
 
-	audio_pins: audio_pinmux {
-		mux_1 {
-			pins = "gpio24";
-			function = "audio_rxbclk";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_2 {
-			pins = "gpio25";
-			function = "audio_rxfsync";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_3 {
-			pins = "gpio26";
-			function = "audio_rxd";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_4 {
-			pins = "gpio27";
-			function = "audio_txmclk";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_5 {
-			pins = "gpio28";
-			function = "audio_txbclk";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_6 {
-			pins = "gpio29";
-			function = "audio_txfsync";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-
-		mux_7 {
-			pins = "gpio30";
-			function = "audio_txd";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-	};
 };
 
 &soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+	
+		button@2 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
+	};
+	gpio_leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+
+		led_sys: led@1 {
+			label = "sys:blue";
+			gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;  /* GPIO_1 */
+			default-state="on";
+		};
+		led@35 {
+			label = "sys:green";
+			gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;  /* GPIO_35 */
+			default-state="off";
+		};
+		led@31 {
+			label = "sys:red";
+			gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;  /* GPIO_31 */
+			default-state="off";
+		};
+	};
 };
 
 &usb3 {
@@ -772,22 +743,42 @@
 
 &pcie_x1 {
 	status = "disabled";
-	perst-gpio = <&tlmm 18 GPIO_ACTIVE_LOW>;
+	perst-gpio = <&tlmm 18 1>;
 };
 
 &pcie_x2 {
 	status = "ok";
-	perst-gpio = <&tlmm 15 GPIO_ACTIVE_LOW>;
+	perst-gpio = <&tlmm 15 1>;
+};
+
+&bt {
+	status = "ok";
 };
 
 &wcss {
 	status = "ok";
 };
 
+&q6v5_wcss {
+	status = "disabled";
+};
+
+&q6v5_m3 {
+	status = "disabled";
+};
+
+&tcsr_mutex_block {
+	status = "ok";
+};
+
 &tcsr_mutex {
 	status = "ok";
 };
 
+&smem {
+	status = "ok";
+};
+
 &apcs_glb {
 	status = "ok";
 };
@@ -796,13 +787,34 @@
 	status = "ok";
 };
 
-&q6v5_wcss {
+&qcom_q6v5_wcss {
 	#ifdef __IPQ_MEM_PROFILE_256_MB__
 		memory-region = <&q6_region>, <&q6_etr_region>;
 	#else
 		memory-region = <&q6_region>, <&q6_etr_region>,
 				<&q6_caldb_region>;
 	#endif
+	/* IPQ5018 */
+	q6v5_wcss_userpd1 {
+		m3_firmware = "IPQ5018/m3_fw.mdt";
+		interrupts-extended = <&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names ="fatal",
+			"ready",
+			"spawn_ack",
+			"stop-ack";
+		qcom,smem-states = <&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names = "shutdown",
+			"stop",
+			"spawn";
+		qca,asid = <1>;
+		qca,auto-restart;
+		qca,int_radio;
+	};
 };
 
 &i2c_0 {
@@ -811,6 +823,14 @@
 	status = "disabled";
 };
 
+&dbm_1p5 {
+	status = "ok";
+};
+
+&msm_imem {
+	status = "ok";
+};
+
 &blsp1_uart1 {
 	status = "ok";
 };
@@ -847,108 +867,35 @@
 		qrtr_instance_id = <0x20>;
 		#address-cells = <0x2>;
 		#size-cells = <0x2>;
-#if defined(__CNSS2__)
 		memory-region = <&mhi_region1>;
-#else
+#if !defined(__CNSS2__)
 		base-addr = <0x4CC00000>;
 		m3-dump-addr = <0x4E000000>;
 		etr-addr = <0x4E100000>;
 		qcom,caldb-addr = <0x4E200000>;
-		pageable-addr = <0x4EA00000>;
 		qcom,tgt-mem-mode = <0x1>;
+		mhi,max-channels = <30>;
+		mhi,timeout = <10000>;
 #endif
 	};
 };
 
 &wifi0 {
 	/* IPQ5018 */
-	mem-region = <&q6_region>;
 	qcom,board_id = <0x24>;
-
-	qcom,bdf-addr = <0x4BA00000 0x4BA00000 0x4BA00000
-		0x0 0x0>;
-	qcom,caldb-addr = <0x4CA00000 0x4CA00000 0x0 0x0 0x0>;
-	qcom,caldb-size = <0x200000>;
 	status = "ok";
 };
 
 &wifi3 {
 	/* QCN9000 5G */
 	board_id = <0xa0>;
-	hremote_node = <&qcn9000_pcie0>;
+	status = "ok";
-#ifdef __IPQ_MEM_PROFILE_256_MB__
+};
-	/* QCN9000 tgt-mem-mode=2 layout - 17MB
+
-	 * +=========+==============+=========+
+&qfprom {
-	 * |  Region | Start Offset |   Size  |
+	status = "ok";
-	 * +---------+--------------+---------+
+};
-	 * | HREMOTE |  0x4C900000  |   11MB  |
+
-	 * +---------+--------------+---------+
+&tsens {
-	 * | M3 Dump |  0x4D400000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * |   ETR   |  0x4D500000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * | Pageable|  0x4D600000  |   4MB   |
-	 * +==================================+
-	 */
-	base-addr = <0x4C900000>;
-	m3-dump-addr = <0x4D400000>;
-	etr-addr = <0x4D500000>;
-	caldb-addr = <0>;
-	pageable-addr = <0x4D600000>;
-	caldb-size = <0>;
-	hremote-size = <0xB00000>;
-	tgt-mem-mode = <0x2>;
-	pageable-size = <0x400000>;
-#elif __IPQ_MEM_PROFILE_512_MB__
-	/* QCN9000 tgt-mem-mode=1 layout - 38MB
-	 * +=========+==============+=========+
-	 * |  Region | Start Offset |   Size  |
-	 * +---------+--------------+---------+
-	 * | HREMOTE |  0x4CC00000  |   20MB  |
-	 * +---------+--------------+---------+
-	 * | M3 Dump |  0x4E000000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * |   ETR   |  0x4E100000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * |  Caldb  |  0x4E200000  |   8MB   |
-	 * +---------+--------------+---------+
-	 * | Pageable|  0x4EA00000  |   8MB   |
-	 * +==================================+
-	 */
-	base-addr = <0x4CC00000>;
-	m3-dump-addr = <0x4E000000>;
-	etr-addr = <0x4E100000>;
-	caldb-addr = <0x4E200000>;
-	pageable-addr = <0x4EA00000>;
-	caldb-size = <0x800000>;
-	hremote-size = <0x1400000>;
-	tgt-mem-mode = <0x1>;
-	pageable-size = <0x800000>;
-#else
-	/* QCN9000 tgt-mem-mode=0 layout - 53MB
-	 * +=========+==============+=========+
-	 * |  Region | Start Offset |   Size  |
-	 * +---------+--------------+---------+
-	 * | HREMOTE |  0x4CC00000  |   35MB  |
-	 * +---------+--------------+---------+
-	 * | M3 Dump |  0x4EF00000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * |   ETR   |  0x4F000000  |   1MB   |
-	 * +---------+--------------+---------+
-	 * |  Caldb  |  0x4F100000  |   8MB   |
-	 * +---------+--------------+---------+
-	 * | Pageable|  0x4F900000  |   8MB   |
-	 * +==================================+
-	 */
-	base-addr = <0x4CC00000>;
-	m3-dump-addr = <0x4EF00000>;
-	etr-addr = <0x4F000000>;
-	caldb-addr = <0x4F100000>;
-	pageable-addr = <0x4F900000>;
-	hremote-size = <0x2300000>;
-	caldb-size = <0x800000>;
-	tgt-mem-mode = <0x0>;
-	pageable-size = <0x800000>;
-#endif
 	status = "ok";
 };

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-cig-wf188n.dts

@@ -1,6 +1,6 @@
 /dts-v1/;
 /*
- * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,9 +15,12 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"
-#include "ipq6018-cpr-regulator.dtsi"
+#include "qcom-ipq6018-rpm-regulator.dtsi"
+#include "qcom-ipq6018-cpr-regulator.dtsi"
+#include "qcom-ipq6018-cp-cpu.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <0x2>;
@@ -25,9 +28,11 @@
 	model = "Cigtech WF-188n";
 	compatible = "cig,wf188n", "qcom,ipq6018-cp03", "qcom,ipq6018";
 	interrupt-parent = <&intc>;
-	qcom,msm-id = <0x1A5 0x0>;
 
 	aliases {
+		serial0 = &blsp1_uart3;
+		serial1 = &blsp1_uart2;
+
 		/*
 		 * Aliases as required by u-boot
 		 * to patch MAC addresses
@@ -43,11 +48,7 @@
 
 	chosen {
 		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-		bootargs-append = " swiotlb=1";
-#else
 		bootargs-append = " swiotlb=1 coherent_pool=2M";
-#endif
 	};
 
 	/*
@@ -105,13 +106,71 @@
 		};
 	};
 
-	button_pins: button_pins {
+	qpic_pins: qpic_pins {
-		wps_button {
+		data_0 {
-			pins = "gpio9";
+			pins = "gpio15";
-			function = "gpio";
+			function = "qpic_pad0";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	button_pins: button_pins {
+		wps_button {
+			pins = "gpio22";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
 	};
 
 	mdio_pins: mdio_pinmux {
@@ -136,17 +195,37 @@
 
 	leds_pins: leds_pins {
 		led_5g {
-			pins = "gpio35";
+			pins = "gpio25";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
 		led_2g {
-			pins = "gpio37";
+			pins = "gpio24";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+		led_eth {
+			pins = "gpio18";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+                led_pwr {
+                        pins = "gpio16";
+                        function = "gpio";
+                        drive-strength = <8>;
+                        bias-pull-down;
+                };
+	};
+	uart2_pins: uart2_pins {
+		mux {
+			pins = "gpio57", "gpio58";
+			function = "blsp4_uart";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
 	};
 };
 
@@ -164,6 +243,7 @@
 		};
 	};
 
+	
 	ess-switch@3a000000 {
 		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
 		switch_lan_bmp = <0x08>; /* lan port bitmap */
@@ -206,6 +286,7 @@
 		qcom,link-poll = <1>;
 		qcom,phy-mdio-addr = <3>;
 		phy-mode = "sgmii";
+	
 	};
 
 	gpio_keys {
@@ -285,22 +366,22 @@
 	};
 };
 
+&blsp1_uart2 {
+	pinctrl-0 = <&uart2_pins>;
+	pinctrl-names = "default";
+	dmas = <&blsp_dma 2>,
+		<&blsp_dma 3>;
+	dma-names = "tx", "rx";
+	status = "ok";
+};
 &qpic_bam {
 	status = "ok";
 };
 
-&qpic_nand {
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
 	status = "ok";
-
-	nand@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		nand-bus-width = <8>;
-	};
 };
 
 &ssphy_0 {
@@ -318,3 +399,25 @@
 &nss_crypto {
 	status = "ok";
 };
+
+&cpu0_opp_table {
+	compatible = "operating-points-v2";
+	opp-shared;
+	opp03 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <3>;
+		clock-latency-ns = <200000>;
+	};
+	/delete-node/ opp04;
+	/delete-node/ opp05;
+	/delete-node/ opp06;
+};
+
+/* TZAPP is enabled in default memory profile only */
+#if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__)
+&qseecom {
+	mem-start = <0x49B00000>;
+	mem-size = <0x600000>;
+	status = "ok";
+};
+#endif

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-edgecore-eap101.dts

@@ -1,23 +1,38 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/dts-v1/;
 /*
- * IPQ6018 CP01 board device tree source
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  *
- * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-/dts-v1/;
+#include "qcom-ipq6018.dtsi"
-
+#include "qcom-ipq6018-rpm-regulator.dtsi"
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018-cpr-regulator.dtsi"
-#include "ipq6018-cpr-regulator.dtsi"
+#include "qcom-ipq6018-cp-cpu.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
 	model = "EdgeCore EAP101";
 	compatible = "edgecore,eap101", "qcom,ipq6018-cp01", "qcom,ipq6018";
+	interrupt-parent = <&intc>;
 
 	aliases {
 		serial0 = &blsp1_uart3;
 		serial1 = &blsp1_uart2;
+
 		/*
 		 * Aliases as required by u-boot
 		 * to patch MAC addresses
@@ -33,84 +48,130 @@
 	};
 
 	chosen {
-		stdout-path = "serial0:115200n8";
+		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
-		bootargs-append = " swiotlb=1";
+		bootargs-append = " console=ttyMSM0,115200,n8 swiotlb=1 coherent_pool=2M";
 	};
-};
 
-&blsp1_uart3 {
+	/*
-	pinctrl-0 = <&serial_3_pins>;
+	 * +=========+==============+========================+
-	pinctrl-names = "default";
+	 * |        |              |                         |
-	status = "ok";
+	 * | Region | Start Offset |          Size           |
-};
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * | Linux  |  0x41000000  |         139MB           |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * |        |              |                         |
+	 * +--------+--------------+-------------------------+
+	 * | TZ App |  0x49B00000  |           6MB           |
+	 * +--------+--------------+-------------------------+
+	 *
+	 * From the available 145 MB for Linux in the first 256 MB,
+	 * we are reserving 6 MB for TZAPP.
+	 *
+	 * Refer arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
+	 * for memory layout.
+	 */
 
-&spi_0 {
+/* TZAPP is enabled only in default memory profile */
-	pinctrl-0 = <&spi_0_pins>;
+#if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__)
-	pinctrl-names = "default";
+	reserved-memory {
-	cs-select = <0>;
+		tzapp:tzapp@49B00000 {	/* TZAPPS */
-	status = "ok";
+			no-map;
-
+			reg = <0x0 0x49B00000 0x0 0x00600000>;
-	m25p80@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		compatible = "n25q128a11";
-		linux,modalias = "m25p80", "n25q128a11";
-		spi-max-frequency = <50000000>;
-		use-default-sizes;
 		};
-};
+	};
-
+#endif
-&blsp1_uart2 {
-	pinctrl-0 = <&hsuart_pins &btcoex_pins>;
-	pinctrl-names = "default";
-	dmas = <&blsp_dma 2>,
-		<&blsp_dma 3>;
-	dma-names = "tx", "rx";
-	status = "ok";
 };
 
 &tlmm {
-	spi_0_pins: spi-0-pins {
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio44", "gpio45";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
 			pins = "gpio38", "gpio39", "gpio40", "gpio41";
 			function = "blsp0_spi";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+	};
 
-	spi_1_pins: spi_1_pins {
+	qpic_pins: qpic_pins {
-		mux {
+		data_0 {
-			pins = "gpio69", "gpio71", "gpio72";
+			pins = "gpio15";
-			function = "blsp1_spi";
+			function = "qpic_pad0";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
-		spi_cs {
+		data_1 {
-			pins = "gpio70";
+			pins = "gpio12";
-			function = "blsp1_spi";
+			function = "qpic_pad1";
 			drive-strength = <8>;
-			bias-disable;
+			bias-pull-down;
 		};
-		quartz_interrupt {
+		data_2 {
-			pins = "gpio78";
+			pins = "gpio13";
-			function = "gpio";
+			function = "qpic_pad2";
-			input;
+			drive-strength = <8>;
-			bias-disable;
+			bias-pull-down;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-pull-down;
 		};
-		quartz_reset {
-			pins = "gpio79";
-			function = "gpio";
-			output-low;
-			bias-disable;
 	};
 
+	extcon_usb_pins: extcon_usb_pins {
+		mux {
+			pins = "gpio26";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
 		};
-
-	sd_pins: sd-pinmux {
-		pins = "gpio62";
-		function = "sd_card";
-		drive-strength = <8>;
-		bias-pull-up;
 	};
 
 	button_pins: button_pins {
@@ -140,26 +201,6 @@
 			function = "gpio";
 			bias-pull-up;
 		};
-		mux_3 {
-			pins = "gpio77";
-			function = "gpio";
-			bias-pull-up;
-		};
-	};
-
-	pwm_pins: pwm_pinmux {
-		pins = "gpio18";
-		function = "pwm00";
-		drive-strength = <8>;
-	};
-
-	hsuart_pins: hsuart_pins {
-		mux {
-			pins = "gpio71", "gpio72", "gpio69", "gpio70";
-			function = "blsp1_uart";
-			drive-strength = <8>;
-			bias-disable;
-		};
 	};
 
 	leds_pins: leds_pins {
@@ -182,42 +223,22 @@
 			bias-pull-down;
 		};
 	};
-
+	uart2_pins: uart2_pins {
-	btcoex_pins: btcoex_pins {
+		mux {
-		mux_0 {
+			pins = "gpio57", "gpio58";
-			pins = "gpio51";
+			function = "blsp4_uart";
-			function = "pta1_1";
+			drive-strength = <8>;
-			drive-strength = <6>;
-			bias-pull-down;
-		};
-		mux_1 {
-			pins = "gpio53";
-			function = "pta1_0";
-			drive-strength = <6>;
-			bias-pull-down;
-		};
-		mux_2 {
-			pins = "gpio52";
-			function = "pta1_2";
-			drive-strength = <6>;
 			bias-pull-down;
 		};
 	};
 };
 
 &soc {
-	gpio_keys {
+	extcon_usb: extcon_usb {
-		compatible = "gpio-keys";
+		pinctrl-0 = <&extcon_usb_pins>;
-		pinctrl-0 = <&button_pins>;
 		pinctrl-names = "default";
-
+		id-gpio = <&tlmm 26 GPIO_ACTIVE_LOW>;
-		wps {
+		status = "ok";
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-			linux,input-type = <1>;
-			debounce-interval = <60>;
-		};
 	};
 
 	mdio: mdio@90000 {
@@ -297,11 +318,18 @@
 		};
 	};
 
-	nss-macsec0 {
+	gpio_keys {
-		compatible = "qcom,nss-macsec";
+		compatible = "gpio-keys";
-		phy_addr = <0x18>;
+		pinctrl-0 = <&button_pins>;
-		phy_access_mode = <0>;
+		pinctrl-names = "default";
-		mdiobus = <&mdio>;
+
+		wps {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			debounce-interval = <60>;
+		};
 	};
 
 	leds {
@@ -348,29 +376,52 @@
 	};
 };
 
+&blsp1_uart3 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 {
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
+	};
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&uart2_pins>;
+	pinctrl-names = "default";
+	dmas = <&blsp_dma 2>,
+		<&blsp_dma 3>;
+	dma-names = "tx", "rx";
+	status = "ok";
+};
 &qpic_bam {
 	status = "ok";
 };
 
-&qpic_nand {
+&nand {
-	status = "ok";
+	pinctrl-0 = <&qpic_pins>;
-
+	pinctrl-names = "default";
-	nand@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		nand-bus-width = <8>;
-	};
-};
-
-&pcie_phy {
 	status = "ok";
 };
 
-&pcie0 {
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
 	status = "ok";
 };
 
@@ -382,14 +433,6 @@
 	status = "ok";
 };
 
-&qusb_phy_0 {
-	status = "ok";
-};
-
-&ssphy_0 {
-	status = "ok";
-};
-
 &usb3 {
 	status = "ok";
 };

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-gl-ax1800.dtsi

@@ -1,6 +1,5 @@
-/dts-v1/;
 /*
- * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,7 +14,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
@@ -37,47 +36,8 @@
 
 	chosen {
 		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-		bootargs-append = " swiotlb=1";
-#else
 		bootargs-append = " swiotlb=1 coherent_pool=2M";
-#endif
 	};
-
-	/*
-	 * +=========+==============+========================+
-	 * |        |              |                         |
-	 * | Region | Start Offset |          Size           |
-	 * |        |              |                         |
-	 * +--------+--------------+-------------------------+
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * | Linux  |  0x41000000  |         139MB           |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * +--------+--------------+-------------------------+
-	 * | TZ App |  0x49B00000  |           6MB           |
-	 * +--------+--------------+-------------------------+
-	 *
-	 * From the available 145 MB for Linux in the first 256 MB,
-	 * we are reserving 6 MB for TZAPP.
-	 *
-	 * Refer arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
-	 * for memory layout.
-	 */
-
-/* TZAPP is enabled only in default memory profile */
-#if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__)
-	reserved-memory {
-		tzapp:tzapp@49B00000 {	/* TZAPPS */
-			no-map;
-			reg = <0x0 0x49B00000 0x0 0x00600000>;
-		};
-	};
-#endif
 };
 
 &tlmm {
@@ -90,10 +50,59 @@
 		};
 	};
 
-	spi_0_pins: spi_0_pins {
+	qpic_pins: qpic_pins {
-		mux {
+		data_0 {
-			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			pins = "gpio15";
-			function = "blsp0_spi";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
@@ -286,18 +295,10 @@
 	status = "ok";
 };
 
-&qpic_nand {
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
 	status = "ok";
-
-	nand@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		nand-bus-width = <8>;
-	};
 };
 
 &ssphy_0 {
@@ -318,13 +319,16 @@
 	status = "ok";
 };
 
+&q6_region {
+	reg = <0x0 0x4ab00000 0x0 0x05500000>;
+};
+
 &CPU0 {
 	operating-points = <
 		/* kHz   uV (fixed) */
 		864000   1100000
 		1056000  1100000
 		1200000  1100000
-		1608000  1100000
 	>;
 	clock-latency = <200000>;
 };
@@ -335,7 +339,6 @@
 		864000   1100000
 		1056000  1100000
 		1200000  1100000
-		1608000  1100000
 	>;
 	clock-latency = <200000>;
 };
@@ -346,7 +349,6 @@
 		864000   1100000
 		1056000  1100000
 		1200000  1100000
-		1608000  1100000
 	>;
 	clock-latency = <200000>;
 };
@@ -357,7 +359,6 @@
 		864000   1100000
 		1056000  1100000
 		1200000  1100000
-		1608000  1100000
 	>;
 	clock-latency = <200000>;
 };

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-hfcl-ion4x.dts

@@ -1,305 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * IPQ6018 CP01 board device tree source
- *
- * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "ipq6018.dtsi"
-#include "ipq6018-cpr-regulator.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
-	aliases {
-		serial0 = &blsp1_uart3;
-		serial1 = &blsp1_uart2;
-		/*
-		 * Aliases as required by u-boot
-		 * to patch MAC addresses
-		 */
-		ethernet0 = "/soc/dp1";
-		ethernet1 = "/soc/dp2";
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-		bootargs-append = " swiotlb=1";
-	};
-};
-
-&blsp1_uart3 {
-	pinctrl-0 = <&serial_3_pins>;
-	pinctrl-names = "default";
-	status = "ok";
-};
-
-&spi_0 {
-	pinctrl-0 = <&spi_0_pins>;
-	pinctrl-names = "default";
-	cs-select = <0>;
-	status = "ok";
-
-	m25p80@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		compatible = "n25q128a11";
-		linux,modalias = "m25p80", "n25q128a11";
-		spi-max-frequency = <50000000>;
-		use-default-sizes;
-	};
-};
-
-&blsp1_uart2 {
-	pinctrl-0 = <&hsuart_pins &btcoex_pins>;
-	pinctrl-names = "default";
-	dmas = <&blsp_dma 2>,
-		<&blsp_dma 3>;
-	dma-names = "tx", "rx";
-	status = "ok";
-};
-
-&tlmm {
-	spi_0_pins: spi-0-pins {
-		pins = "gpio38", "gpio39", "gpio40", "gpio41";
-		function = "blsp0_spi";
-		drive-strength = <8>;
-		bias-pull-down;
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_0 {
-			pins = "gpio64";
-			function = "mdc";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		mux_1 {
-			pins = "gpio65";
-			function = "mdio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio75";
-			function = "gpio";
-			bias-pull-up;
-		};
-		mux_3 {
-			pins = "gpio77";
-			function = "gpio";
-			bias-pull-up;
-		};
-	};
-
-	hsuart_pins: hsuart_pins {
-		mux {
-			pins = "gpio71", "gpio72", "gpio69", "gpio70";
-			function = "blsp1_uart";
-			drive-strength = <8>;
-			bias-disable;
-		};
-	};
-
-	button_pins: button_pins {
-		reset_button {
-			pins = "gpio53";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
-
-	leds_pins: leds_pins {
-		led_5g {
-			pins = "gpio60";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-		led_2g {
-			pins = "gpio61";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-pull-down;
-		};
-	};
-
-	mdio_pins: mdio_pinmux {
-		mux_0 {
-			pins = "gpio64";
-			function = "mdc";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		mux_1 {
-			pins = "gpio65";
-			function = "mdio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-		mux_2 {
-			pins = "gpio75";
-			function = "gpio";
-			bias-pull-up;
-		};
-		mux_3 {
-			pins = "gpio77";
-			function = "gpio";
-			bias-pull-up;
-		};
-	};
-
-	btcoex_pins: btcoex_pins {
-		mux_0 {
-			pins = "gpio51";
-			function = "pta1_1";
-			drive-strength = <6>;
-			bias-pull-down;
-		};
-		mux_1 {
-			pins = "gpio53";
-			function = "pta1_0";
-			drive-strength = <6>;
-			bias-pull-down;
-		};
-		mux_2 {
-			pins = "gpio52";
-			function = "pta1_2";
-			drive-strength = <6>;
-			bias-pull-down;
-		};
-	};
-};
-
-&soc {
-	mdio: mdio@90000 {
-		pinctrl-0 = <&mdio_pins>;
-		pinctrl-names = "default";
-		phy-reset-gpio = <&tlmm 77 0>;
-		status = "ok";
-		phy0: ethernet-phy@0 {
-			reg = <4>;
-		};
-		phy1: ethernet-phy@1 {
-			reg = <30>;
-		};
-	};
-
-	dp1 {
-		device_type = "network";
-		compatible = "qcom,nss-dp";
-		qcom,id = <4>;
-		reg = <0x3a001600 0x200>;
-		qcom,mactype = <0>;
-		local-mac-address = [000000000000];
-		qcom,link-poll = <1>;
-		qcom,phy-mdio-addr = <4>;
-		phy-mode = "sgmii";
-	};
-
-	dp2 {
-		device_type = "network";
-		compatible = "qcom,nss-dp";
-		qcom,id = <5>;
-		reg = <0x3a003000 0x3fff>;
-		qcom,mactype = <1>;
-		local-mac-address = [000000000000];
-		qcom,link-poll = <1>;
-		qcom,phy-mdio-addr = <30>;
-		phy-mode = "sgmii";
-	};
-
-	ess-switch@3a000000 {
-		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
-		switch_lan_bmp = <0x10>; /* lan port bitmap */
-		switch_wan_bmp = <0x20>; /* wan port bitmap */
-		switch_inner_bmp = <0xc0>; /*inner port bitmap*/
-		switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/
-		switch_mac_mode1 = <0x14>; /* mac mode for uniphy instance1*/
-		switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
-		qcom,port_phyinfo {
-			port@4 {
-				port_id = <4>;
-				phy_address = <4>;
-			};
-			port@5 {
-				port_id = <5>;
-				phy_address = <30>;
-				port_mac_sel = "QGMAC_PORT";
-			};
-		};
-	};
-
-	nss-macsec0 {
-		compatible = "qcom,nss-macsec";
-		phy_addr = <30>;
-		phy_access_mode = <0>;
-		mdiobus = <&mdio>;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		pinctrl-0 = <&button_pins>;
-		pinctrl-names = "default";
-
-		reset {
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
-			linux,input-type = <1>;
-			debounce-interval = <60>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-0 = <&leds_pins>;
-		pinctrl-names = "default";
-
-		led@60 {
-			label = "blue:wifi5";
-			gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "led_5g";
-			default-state = "off";
-		};
-		led@61 {
-			label = "blue:wifi2";
-			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "led_2g";
-			default-state = "off";
-		};
-	};
-};
-
-&qpic_bam {
-	status = "ok";
-};
-
-&qpic_nand {
-	status = "ok";
-
-	nand@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		nand-bus-width = <8>;
-	};
-};
-
-&pcie_phy {
-	status = "ok";
-};
-
-&pcie0 {
-	status = "ok";
-};
-
-&nss_crypto {
-	status = "ok";
-};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq6018-yuncore-ax840.dts

@@ -1,39 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
-/*
- * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
 
-#include "ipq6018.dtsi"
+#include "qcom-ipq6018.dtsi"
-#include "ipq6018-cpr-regulator.dtsi"
+#include "qcom-ipq6018-rpm-regulator.dtsi"
+#include "qcom-ipq6018-cpr-regulator.dtsi"
+#include "qcom-ipq6018-cp-cpu.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
-	#address-cells = <0x2>;
-	#size-cells = <0x2>;
 	model = "YunCore AX840";
 	compatible = "yuncore,ax840", "qcom,ipq6018-cp03", "qcom,ipq6018";
+
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
 	interrupt-parent = <&intc>;
-	qcom,msm-id = <0x1A5 0x0>;
 
 	aliases {
-		/*
+		/* Aliases as required by u-boot to patch MAC addresses */
-		 * Aliases as required by u-boot
-		 * to patch MAC addresses
-		 */
 		ethernet0 = "/soc/dp2";
 		ethernet1 = "/soc/dp1";
+
+		serial0 = &blsp1_uart3;
+		serial1 = &blsp1_uart2;
+
 		led-boot = &led_system;
 		led-failsafe = &led_system;
 		led-running = &led_system;
@@ -42,47 +32,15 @@
 
 	chosen {
 		bootargs = "console=ttyMSM0,115200,n8 rw init=/init";
-#ifdef __IPQ_MEM_PROFILE_256_MB__
-		bootargs-append = " swiotlb=1";
-#else
 		bootargs-append = " swiotlb=1 coherent_pool=2M";
-#endif
 	};
 
-	/*
-	 * +=========+==============+========================+
-	 * |        |              |                         |
-	 * | Region | Start Offset |          Size           |
-	 * |        |              |                         |
-	 * +--------+--------------+-------------------------+
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * | Linux  |  0x41000000  |         139MB           |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * |        |              |                         |
-	 * +--------+--------------+-------------------------+
-	 * | TZ App |  0x49B00000  |           6MB           |
-	 * +--------+--------------+-------------------------+
-	 *
-	 * From the available 145 MB for Linux in the first 256 MB,
-	 * we are reserving 6 MB for TZAPP.
-	 *
-	 * Refer arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
-	 * for memory layout.
-	 */
-
-/* TZAPP is enabled only in default memory profile */
-#if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__)
 	reserved-memory {
 		tzapp:tzapp@49B00000 {	/* TZAPPS */
 			no-map;
 			reg = <0x0 0x49B00000 0x0 0x00600000>;
 		};
 	};
-#endif
 };
 
 &tlmm {
@@ -104,13 +62,79 @@
 		};
 	};
 
-	button_pins: button_pins {
+	qpic_pins: qpic_pins {
-		wps_button {
+		data_0 {
-			pins = "gpio9";
+			pins = "gpio15";
-			function = "gpio";
+			function = "qpic_pad0";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		qpic_pad {
+			pins = "gpio1",  "gpio3",  "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	button_pins: button_pins {
+		rst_button {
+			pins = "gpio19";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
 	};
 
 	mdio_pins: mdio_pinmux {
@@ -120,12 +144,14 @@
 			drive-strength = <8>;
 			bias-pull-up;
 		};
+
 		mux_1 {
 			pins = "gpio65";
 			function = "mdio";
 			drive-strength = <8>;
 			bias-pull-up;
 		};
+
 		mux_2 {
 			pins = "gpio75";
 			function = "gpio";
@@ -155,28 +181,22 @@
 			bias-pull-down;
 		};
 	};
-
-	button_pins: button_pins {
-		rst_button {
-			pins = "gpio19";
-			function = "gpio";
-			drive-strength = <8>;
-			bias-pull-up;
-		};
-	};
 };
 
 &soc {
-	mdio@90000 {
+	mdio: mdio@90000 {
+		status = "ok";
+
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 75 0>;
-		status = "ok";
+
-		phy0: ethernet-phy@0 {
+		ethernet-phy@0 {
-			reg = <3>;
+			reg = <0x03>;
 		};
-		phy1: ethernet-phy@1 {
+
-			reg = <4>;
+		ethernet-phy@1 {
+			reg = <0x04>;
 		};
 	};
 
@@ -243,6 +263,7 @@
 
 	leds {
 		compatible = "gpio-leds";
+
 		pinctrl-0 = <&leds_pins>;
 		pinctrl-names = "default";
 
@@ -290,32 +311,33 @@
 	status = "ok";
 };
 
-&qpic_nand {
+&nand {
-	status = "ok";
+	pinctrl-0 = <&qpic_pins>;
-
+	pinctrl-names = "default";
-	nand@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		nand-bus-width = <8>;
-	};
-};
-
-&ssphy_0 {
-	status = "ok";
-};
-
-&qusb_phy_0 {
-	status = "ok";
-};
-
-&usb3 {
 	status = "ok";
 };
 
 &nss_crypto {
 	status = "ok";
 };
+
+&cpu0_opp_table {
+	compatible = "operating-points-v2";
+	opp-shared;
+
+	opp03 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <3>;
+		clock-latency-ns = <200000>;
+	};
+
+	/delete-node/ opp04;
+	/delete-node/ opp05;
+	/delete-node/ opp06;
+};
+
+&qseecom {
+	mem-start = <0x49B00000>;
+	mem-size = <0x600000>;
+	status = "ok";
+};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts

@@ -1,9 +1,21 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-ac-cpu.dtsi"
+#include "qcom-ipq807x-ac-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
@@ -12,10 +24,14 @@
 	compatible = "edgecore,eap102", "qcom,ipq807x-ac02", "qcom,ipq807x";
 	qcom,msm-id = <0x178 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet1 = "/soc/dp5";
 		ethernet0 = "/soc/dp6";
 
@@ -26,40 +42,31 @@
 	};
 
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
+			init=/init";
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+			bootargs-append = " swiotlb=1";
+		#else
+			bootargs-append = " swiotlb=1 coherent_pool=2M";
+		#endif
 	};
+};
 
-	soc {
+&tlmm {
-		pinctrl@1000000 {
+	pinctrl-0 = <&btcoex_pins>;
-			button_pins: button_pins {
+	pinctrl-names = "default";
-				reset_button {
-					pins = "gpio66";
-					function = "gpio";
-					drive-strength = <8>;
-					bias-pull-up;
-				};
-			};
 
-			usb_mux_sel_pins: usb_mux_pins {
+	btcoex_pins: btcoex_pins {
-				mux {
+		mux_0 {
-					pins = "gpio27";
+			pins = "gpio64";
-					function = "gpio";
+			function = "pta1_1";
-					drive-strength = <8>;
+			drive-strength = <6>;
 			bias-pull-down;
 		};
-			};
+		mux_1 {
-
+			pins = "gpio65";
-			pcie0_pins: pcie_pins {
+			function = "pta1_2";
-				pcie0_rst {
+			drive-strength = <6>;
-					pins = "gpio58";
-					function = "pcie0_rst";
-					drive-strength = <8>;
-					bias-pull-down;
-				};
-				pcie0_wake {
-					pins = "gpio59";
-					function = "pcie0_wake";
-					drive-strength = <8>;
 			bias-pull-down;
 		};
 	};
@@ -88,109 +95,166 @@
 			bias-pull-up;
 		};
 	};
+
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	button_pins: button_pins {
+
+		reset_button {
+			pins = "gpio66";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
 	led_pins: led_pins {
+		led_pwr {
+			pins = "gpio46";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
 		led_2g {
-					pins = "gpio42";
+			pins = "gpio47";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
 
 		led_5g {
-					pins = "gpio43";
+			pins = "gpio48";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_bt {
+			pins = "gpio50";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
 	};
-		};
 
-		serial@78b3000 {
+	usb_mux_sel_pins: usb_mux_pins {
-			status = "ok";
+		mux {
-		};
+			pins = "gpio27";
-
+			function = "gpio";
-		spi@78b5000 {
+			drive-strength = <8>;
-			status = "ok";
+			bias-pull-down;
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			cs-select = <0>;
-
-			m25p80@0 {
-				  compatible = "n25q128a11";
-				  #address-cells = <1>;
-				  #size-cells = <1>;
-				  reg = <0>;
-				  spi-max-frequency = <50000000>;
 		};
 	};
 
-		dma@7984000 {
+	pcie0_pins: pcie_pins {
-			 status = "ok";
+		pcie0_rst {
+			pins = "gpio58";
+			function = "pcie0_rst";
+			drive-strength = <8>;
+			bias-pull-down;
 		};
-
+		pcie0_wake {
-		nand@79b0000 {
+			pins = "gpio59";
-			status = "ok";
+			function = "pcie0_wake";
-
+			drive-strength = <8>;
-			nand@0 {
+			bias-pull-down;
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				nand-ecc-strength = <4>;
-				nand-ecc-step-size = <512>;
-				nand-bus-width = <8>;
 		};
 	};
 
-		qusb@79000 {
+};
-			status = "ok";
-		};
-
-		ssphy@78000 {
-			status = "ok";
-		};
-
-		usb3@8A00000 {
-			status = "ok";
-		};
-
-		usb3@8C00000 {
-			status = "ok";
-		};
-
-		qusb@59000 {
-			status = "ok";
-		};
-
-		ssphy@58000 {
-			status = "ok";
-		};
-
-		usb3@8C00000 {
-			status = "ok";
-		};
-
-		phy@84000 {
-			status = "ok";
-		};
-
-		phy@86000 {
-			status = "ok";
-		};
-
-		pci@20000000 {
-			perst-gpio = <&tlmm 58 1>;
-			status = "ok";
-		};
 
+&soc {
 	gpio_keys {
 		compatible = "gpio-keys";
 		pinctrl-0 = <&button_pins>;
 		pinctrl-names = "default";
-			status = "ok";
 
 		button@1 {
-				label = "reset";
+			label = "reset_button";
 			linux,code = <KEY_RESTART>;
 			gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 			linux,input-type = <1>;
@@ -202,6 +266,7 @@
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 37 0 &tlmm 25 1 &tlmm 44 1>;
+		compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
 		phy0: ethernet-phy@0 {
 			reg = <0>;
 		};
@@ -516,15 +581,10 @@
 						sp = <60>;
 						cfg = <0 32 0 32>;
 					};
-						group@1 {
-							sp = <61>;
-							cfg = <1 33 1 33>;
-						};
 				};
 				l0scheduler {
 					group@0 {
 						ucast_queue = <240>;
-							ucast_loop_pri = <16>;
 						mcast_queue = <296>;
 						cfg = <60 0 144 0 144>;
 					};
@@ -532,7 +592,55 @@
 			};
 		};
 	};
+/*
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
+	};
 
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <1>;
+		phy-mode = "sgmii";
+	};
+
+	dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <2>;
+		phy-mode = "sgmii";
+	};
+
+	dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <3>;
+		phy-mode = "sgmii";
+	};
+*/
 	dp6 {
 		device_type = "network";
 		compatible = "qcom,nss-dp";
@@ -591,16 +699,130 @@
 	nss-macsec0 {
 		compatible = "qcom,nss-macsec";
 		phy_addr = <0x18>;
+		phy_access_mode = <0>;
 		mdiobus = <&mdio>;
 	};
 	nss-macsec1 {
 		compatible = "qcom,nss-macsec";
 		phy_addr = <0x1c>;
+		phy_access_mode = <0>;
 		mdiobus = <&mdio>;
 	};
+};
+
+&serial_blsp4 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
 	};
 };
 
+&serial_blsp2 {
+	pinctrl-0 = <&hsuart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&nss0 {
+	qcom,low-frequency = <187200000>;
+	qcom,mid-frequency = <748800000>;
+	qcom,max-frequency = <1497600000>;
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	status = "disabled";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "disabled";
+};
+
+&qpic_lcd_panel {
+	status = "disabled";
+};
+
+&ledc {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "ok";
+};
+
+&pcie1 {
+	status = "disabled";
+};
+
+&glink_rpm {
+	status = "disabled";
+};
+
 &apc_cpr {
 	/* Same CPR configuration as OAK */
 	compatible = "qcom,cpr4-ipq817x-apss-regulator";
@@ -682,12 +904,6 @@
 	status = "disabled";
 };
 
-&nss0 {
-        qcom,low-frequency = <187200000>;
-        qcom,mid-frequency = <748800000>;
-        qcom,max-frequency = <1497600000>;
-};
-
 &nss0 {
 	npu-supply = <&dummy_reg>;
 	mx-supply = <&dummy_reg>;

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap106.dts

@@ -1,65 +1,76 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-hk-cpu.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "Edgecore EAP106";
 	compatible = "edgecore,eap106", "qcom,ipq807x-hk02", "qcom,ipq807x";
-	qcom,msm-id = <0x158 0x0>, <0x188 0x0>;
+	qcom,msm-id = <0x143 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet0 = "/soc/dp1";
 		ethernet1 = "/soc/dp2";
 	};
-
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
-#ifndef __IPQ_MEM_PROFILE_256_MB__
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
-//		bootargs-append = " vmalloc=600M";
+			bootargs-append = " swiotlb=1";
-#endif
+		#else
+			bootargs-append = " swiotlb=1 coherent_pool=2M";
+		#endif
 	};
+};
 
-	soc {
+&tlmm {
+	leds_pins: leds_pinmux {
 
-		dp1 {
+		led1_yellow {
-			device_type = "network";
+			pins = "gpio25";
-			compatible = "qcom,nss-dp";
-			qcom,id = <4>;
-			reg = <0x3a001600 0x200>;
-			qcom,mactype = <4>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <3>;
-			phy-mode = "sgmii";
-		};
-
-		dp2 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <6>;
-			reg = <0x3a007000 0x3fff>;
-			qcom,mactype = <1>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <8>;
-			phy-mode = "sgmii";
-		};
-
-		pinctrl@1000000 {
-			button_pins: button_pins {
-				wps_button {
-					pins = "gpio57";
 			function = "gpio";
 			drive-strength = <8>;
-					bias-pull-up;
+			bias-pull-down;
+		};
+		led1_green {
+			pins = "gpio28";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		led2_amber {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		led2_blue {
+			pins = "gpio32";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
 		};
 	};
 
@@ -78,6 +89,123 @@
 		};
 	};
 
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	i2c_0_pins: i2c_0_pinmux {
+		mux {
+			pins = "gpio42", "gpio43";
+			function = "blsp1_i2c";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_8 {
+			pins = "gpio16";
+			function = "qpic_pad8";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4",
+			       "gpio9", "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio46", "gpio47", "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+			output-low;
+		};
+		mux_1 {
+			pins = "gpio51";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	button_pins: button_pins {
+		wps_button {
+			pins = "gpio57";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
 	uniphy_pins: uniphy_pinmux {
 		mux {
 			pins = "gpio60";
@@ -85,119 +213,74 @@
 			bias-disable;
 		};
 	};
-
+	cnss_wlan_en_active: cnss_wlan_en_active {
-			leds_pins: leds_pinmux {
+		mux {
-				led1_yellow {
+			pins = "gpio57";
-					pins = "gpio25";
 			function = "gpio";
-					drive-strength = <8>;
+			drive-strength = <16>;
-					bias-pull-down;
+			output-high;
+			bias-pull-up;
+		};
 	};
 
-				led1_green {
+	cnss_wlan_en_sleep: cnss_wlan_en_sleep {
-					pins = "gpio28";
+		mux {
+			pins = "gpio57";
 			function = "gpio";
-					drive-strength = <8>;
+			drive-strength = <2>;
-					bias-pull-down;
+			output-low;
-				};
-
-				led2_amber {
-					pins = "gpio29";
-					function = "gpio";
-					drive-strength = <8>;
-					bias-pull-down;
-				};
-
-				led2_blue {
-					pins = "gpio32";
-					function = "gpio";
-					drive-strength = <8>;
 			bias-pull-down;
 		};
 	};
-		};
+};
 
-		serial@78b3000 {
+&soc {
-			status = "ok";
+	gpio_keys {
-		};
+		compatible = "gpio-keys";
-
+		pinctrl-0 = <&button_pins>;
-		spi@78b5000 {
-			status = "ok";
-			pinctrl-0 = <&spi_0_pins>;
 		pinctrl-names = "default";
-			cs-select = <0>;
 
-			m25p80@0 {
+		button@1 {
-				  compatible = "n25q128a11";
+			label = "wps";
-				  #address-cells = <1>;
+			linux,code = <KEY_WPS_BUTTON>;
-				  #size-cells = <1>;
+			gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
-				  reg = <0>;
+			linux,input-type = <1>;
-				  spi-max-frequency = <50000000>;
+			debounce-interval = <60>;
 		};
 	};
 
-		dma@7984000 {
+	leds {
-			 status = "ok";
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+
+		led@25 {
+			label = "led1_yellow";
+			gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "led1_yellow";
+			default-state = "off";
 		};
 
-		nand@79b0000 {
+		led@28 {
-			status = "ok";
+			label = "led1_green";
-
+			gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-			nand@0 {
+			linux,default-trigger = "led1_green";
-				reg = <0>;
+			default-state = "off";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				nand-ecc-strength = <4>;
-				nand-ecc-step-size = <512>;
-				nand-bus-width = <8>;
-			};
 		};
 
-		qusb@79000 {
+		led@29 {
-			status = "ok";
+			label = "led2_amber";
+			gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "led2_amber";
+			default-state = "off";
 		};
 
-		ssphy@78000 {
+		led@32 {
-			status = "ok";
+			label = "led2_blue";
+			gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "led2_blue";
+			default-state = "off";
 		};
-
-		usb3@8A00000 {
-			status = "ok";
-		};
-
-		qusb@59000 {
-			status = "ok";
-		};
-
-		ssphy@58000 {
-			status = "ok";
-		};
-
-		usb3@8C00000 {
-			status = "ok";
-		};
-
-		phy@84000 {
-			status = "ok";
-		};
-
-		phy@86000 {
-			status = "ok";
-		};
-
-		pci@20000000 {
-			perst-gpio = <&tlmm 58 1>;
-			status = "ok";
-		};
-
-		phy@8e000 {
-			status = "ok";
-		};
-
-		pci@10000000 {
-			perst-gpio = <&tlmm 61 0x1>;
-			status = "ok";
 	};
 
 	mdio@90000 {
@@ -510,53 +593,124 @@
 		};
 	};
 
-		gpio_keys {
+	dp1 {
-			compatible = "gpio-keys";
+		device_type = "network";
-			pinctrl-0 = <&button_pins>;
+		compatible = "qcom,nss-dp";
-			pinctrl-names = "default";
+		qcom,id = <4>;
-			status = "ok";
+		reg = <0x3a001600 0x200>;
-
+		qcom,mactype = <0>;
-			button@1 {
+		local-mac-address = [000000000000];
-				label = "reset";
+		qcom,link-poll = <1>;
-				linux,code = <KEY_RESTART>;
+		qcom,phy-mdio-addr = <3>;
-				gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+		phy-mode = "sgmii";
-				linux,input-type = <1>;
-				debounce-interval = <60>;
-			};
 	};
 
-		leds {
+	dp2 {
-			compatible = "gpio-leds";
+		device_type = "network";
-			pinctrl-0 = <&leds_pins>;
+		compatible = "qcom,nss-dp";
-			pinctrl-names = "default";
+		qcom,id = <6>;
-
+		reg = <0x3a007000 0x3fff>;
-			led@25 {
+		qcom,mactype = <1>;
-				label = "led1_yellow";
+		local-mac-address = [000000000000];
-				gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+		qcom,link-poll = <1>;
-				linux,default-trigger = "led1_yellow";
+		qcom,phy-mdio-addr = <8>;
-				default-state = "off";
+		phy-mode = "sgmii";
-			};
-
-			led@28 {
-				label = "led1_green";
-				gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "led1_green";
-				default-state = "off";
-			};
-
-			led@29 {
-				label = "led2_amber";
-				gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "led2_amber";
-				default-state = "off";
-			};
-
-			led@32 {
-				label = "led2_blue";
-				gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "led2_blue";
-				default-state = "off";
-			};
 	};
+	wifi3: wifi3@f00000 {
+		compatible  = "qcom,cnss-qcn9000";
+		wlan-en-gpio = <&tlmm 57 0>;
+		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
+		pinctrl-0 = <&cnss_wlan_en_active>;
+		pinctrl-1 = <&cnss_wlan_en_sleep>;
+		status = "disabled";
 	};
 };
+
+&serial_blsp4 {
+       pinctrl-0 = <&uart_pins>;
+       pinctrl-names = "default";
+       status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
+	};
+};
+
+&serial_blsp2 {
+	pinctrl-0 = <&hsuart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&pcie0 {
+	status = "disabled";
+};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-ex227.dts

@@ -1,21 +1,37 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-hk-cpu.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "TP-Link EX227";
-        compatible = "tplink,ex227", "qcom,ipq8074-ap-hk07", "qcom,ipq8074";
+	compatible = "tplink,ex227", "qcom,ipq807x";
-	qcom,msm-id = <0x156 0x0>, <0x185 0x0>;
+	qcom,msm-id = <0x143 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet0 = "/soc/dp1";
 		led-boot = &led_power;
 		led-failsafe = &led_power;
@@ -24,17 +40,34 @@
 	};
 
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
+			init=/init";
+		bootargs-append = " swiotlb=1";
 	};
+};
 
-	soc {
+&tlmm {
-		pinctrl@1000000 {
+	pinctrl-0 = <&btcoex_pins>;
-			button_pins: button_pins {
+	pinctrl-names = "default";
-				wps_button {
+
-					pins = "gpio50";
+	btcoex_pins: btcoex_pins {
-					function = "gpio";
+		mux_0 {
-					drive-strength = <8>;
+			pins = "gpio64";
-					bias-pull-up;
+			function = "pta1_1";
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+		mux_1 {
+			pins = "gpio65";
+			function = "pta1_2";
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+		mux_2 {
+			pins = "gpio66";
+			function = "pta1_0";
+			drive-strength = <6>;
+			bias-pull-down;
 		};
 	};
 
@@ -52,107 +85,181 @@
 			bias-pull-up;
 		};
 		mux_2 {
-					pins = "gpio37";
+			pins = "gpio25";
 			function = "gpio";
 			bias-pull-up;
 		};
 		mux_3 {
-					pins = "gpio25";
+			pins = "gpio37";
 			function = "gpio";
 			bias-pull-up;
 		};
 	};
 
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_3_pins: spi_3_pins {
+		mux {
+			pins = "gpio52", "gpio53";
+			function = "blsp3_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		spi_cs {
+			pins = "gpio22";
+			function = "blsp3_spi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		quartz_interrupt {
+			pins = "gpio47";
+			function = "gpio";
+			input;
+			bias-disable;
+		};
+		quartz_reset {
+			pins = "gpio21";
+			function = "gpio";
+			output-low;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio46", "gpio47", "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	/* POWER_LED, TP-Link */
 	led_pins: led_pins {
 		led_power {
 			pins = "gpio42";
 			function = "gpio";
 			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	/* BUTTON, TP-Link */
+	button_pins: button_pins {
+		reset_button {
+			pins = "gpio50";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	usb_mux_sel_pins: usb_mux_pins {
+		mux {
+			pins = "gpio27";
+			function = "gpio";
+			drive-strength = <8>;
 			bias-pull-down;
 		};
 	};
+
+	pcie0_pins: pcie_pins {
+		pcie0_rst {
+			pins = "gpio58";
+			function = "pcie0_rst";
+			drive-strength = <8>;
+			bias-pull-down;
 		};
-
+		pcie0_wake {
-		serial@78b3000 {
+			pins = "gpio59";
-			status = "ok";
+			function = "pcie0_wake";
-		};
+			drive-strength = <8>;
-
+			bias-pull-down;
-		dp1 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <6>;
-			reg = <0x3a001000 0x200>;
-			qcom,mactype = <0>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <4>;
-			phy-mode = "sgmii";
-		};
-
-		spi@78b5000 {
-			status = "ok";
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			cs-select = <0>;
-
-			m25p80@0 {
-				  compatible = "n25q128a11";
-				  #address-cells = <1>;
-				  #size-cells = <1>;
-				  reg = <0>;
-				  spi-max-frequency = <50000000>;
 		};
 	};
 
-		dma@7984000 {
+};
-			 status = "ok";
-		};
-
-		nand@79b0000 {
-			status = "ok";
-
-			nand@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				nand-ecc-strength = <4>;
-				nand-ecc-step-size = <512>;
-				nand-bus-width = <8>;
-			};
-		};
-
-		gpio_keys {
-			compatible = "gpio-keys";
-			pinctrl-0 = <&button_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-
-			button@1 {
-				label = "reset";
-				linux,code = <KEY_RESTART>;
-				gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-				linux,input-type = <1>;
-				debounce-interval = <60>;
-			};
-		};
-
-		leds {
-			compatible = "gpio-leds";
-			pinctrl-0 = <&led_pins>;
-			pinctrl-names = "default";
-
-			led_power: led_power {
-				label = "led_2g";
-				gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-				default-state = "off";
-			};
-		};
 
+&soc {
 	mdio: mdio@90000 {
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 37 0 &tlmm 25 1>;
+		compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
 		phy0: ethernet-phy@0 {
 			reg = <0>;
 		};
@@ -178,7 +285,7 @@
 		switch_lan_bmp = <0x3e>; /* lan port bitmap */
 		switch_wan_bmp = <0x40>; /* wan port bitmap */
 		switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
-			switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
+		switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
 		switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
 		bm_tick_mode = <0>; /* bm tick mode */
 		tm_tick_mode = <0>; /* tm tick mode */
@@ -466,15 +573,10 @@
 						sp = <60>;
 						cfg = <0 32 0 32>;
 					};
-						group@1 {
-							sp = <61>;
-							cfg = <1 33 1 33>;
-						};
 				};
 				l0scheduler {
 					group@0 {
 						ucast_queue = <240>;
-							ucast_loop_pri = <16>;
 						mcast_queue = <296>;
 						cfg = <60 0 144 0 144>;
 					};
@@ -482,11 +584,171 @@
 			};
 		};
 	};
+
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <4>;
+		phy-mode = "sgmii";
+	};
+
+	/* POWER LED, TP-Link */
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_power: led_power {
+			label = "blue:power";
+			gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	/* BUTTON, TP-Link */
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+		};
+	};
+
+	nss-macsec0 {
+		compatible = "qcom,nss-macsec";
+		phy_addr = <0x18>;
+		phy_access_mode = <0>;
+		mdiobus = <&mdio>;
+	};
 	nss-macsec1 {
 		compatible = "qcom,nss-macsec";
 		phy_addr = <0x1c>;
 		phy_access_mode = <0>;
 		mdiobus = <&mdio>;
 	};
+};
+
+&serial_blsp4 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
 	};
 };
+
+&spi_4 { /* BLSP1 QUP3 */
+	pinctrl-0 = <&spi_3_pins>;
+	pinctrl-names = "default";
+	cs-select = <2>;
+	quartz-reset-gpio = <&tlmm 21 1>;
+	status = "disabled";
+	spidev3: spi@3 {
+		compatible = "qca,spidev";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+	};
+};
+
+&serial_blsp2 {
+	status = "disabled";
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	status = "disabled";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "disabled";
+};
+
+&qpic_lcd_panel {
+	status = "disabled";
+};
+
+&ledc {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "ok";
+};
+
+&pcie1 {
+	status = "disabled";
+};
+

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-ex447.dts

@@ -1,36 +1,226 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-hk-cpu.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "TP-Link EX447";
 	compatible = "tplink,ex447", "qcom,ipq807x";
-	qcom,msm-id = <0x157 0x0>, <0x187 0x0>;
+	qcom,msm-id = <0x143 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet0 = "/soc/dp1";
 	};
 
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
+			init=/init";
+		bootargs-append = " swiotlb=1";
 		led-boot = &led_power;
 		led-failsafe = &led_power;
 		led-running = &led_power;
 		led-upgrade = &led_power;
 	};
+};
 
-	soc {
+&tlmm {
-		pinctrl@1000000 {
+	pinctrl-0 = <&btcoex_pins>;
+	pinctrl-names = "default";
+
+	btcoex_pins: btcoex_pins {
+		mux_0 {
+			pins = "gpio64";
+			function = "pta1_1";
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+		mux_1 {
+			pins = "gpio65";
+			function = "pta1_2";
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+		mux_2 {
+			pins = "gpio66";
+			function = "pta1_0";
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+	};
+
+	mdio_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio68";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_1 {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_2 {
+			pins = "gpio25";
+			function = "gpio";
+			bias-pull-up;
+		};
+		mux_3 {
+			pins = "gpio37";
+			function = "gpio";
+			bias-pull-up;
+		};
+	};
+
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_3_pins: spi_3_pins {
+		mux {
+			pins = "gpio52", "gpio53";
+			function = "blsp3_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		spi_cs {
+			pins = "gpio22";
+			function = "blsp3_spi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		quartz_interrupt {
+			pins = "gpio47";
+			function = "gpio";
+			input;
+			bias-disable;
+		};
+		quartz_reset {
+			pins = "gpio21";
+			function = "gpio";
+			output-low;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio46", "gpio47", "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	/* POWER_LED, TP-Link */
+	led_pins: led_pins {
+		led_power {
+			pins = "gpio42";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	/* BUTTON, TP-Link */
 	button_pins: button_pins {
-				wps_button {
+		reset_button {
 			pins = "gpio50";
 			function = "gpio";
 			drive-strength = <8>;
@@ -62,161 +252,14 @@
 		};
 	};
 
-			mdio_pins: mdio_pinmux {
+};
-				mux_0 {
-					pins = "gpio68";
-					function = "mdc";
-					drive-strength = <8>;
-					bias-pull-up;
-				};
-				mux_1 {
-					pins = "gpio69";
-					function = "mdio";
-					drive-strength = <8>;
-					bias-pull-up;
-				};
-				mux_2 {
-					pins = "gpio25";
-					function = "gpio";
-					bias-pull-up;
-				};
-				mux_3 {
-					pins = "gpio37";
-					function = "gpio";
-					bias-pull-up;
-				};
-			};
-
-			led_pins: led_pins {
-				led_power {
-					pins = "gpio42";
-					function = "gpio";
-					drive-strength = <8>;
-					bias-pull-down;
-				};
-			};
-
-			spi_3_pins: spi_3_pins {
-				mux {
-					pins = "gpio50", "gpio52", "gpio53";
-					function = "blsp3_spi";
-					drive-strength = <8>;
-					bias-disable;
-				};
-				spi_cs {
-					pins = "gpio22";
-					function = "blsp3_spi2";
-					drive-strength = <8>;
-					bias-disable;
-				};
-				quartz_interrupt {
-					pins = "gpio47";
-					function = "gpio";
-					input;
-					bias-disable;
-				};
-				quartz_reset {
-					pins = "gpio21";
-					function = "gpio";
-					output-low;
-					bias-disable;
-				};
-			};
-		};
-
-		serial@78b3000 {
-			status = "ok";
-		};
-
-		dp1 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <5>;
-			reg = <0x3a001000 0x200>;
-			qcom,mactype = <0>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <28>;
-			phy-mode = "sgmii";
-		};
-
-		spi@78b5000 {
-			status = "ok";
-			pinctrl-0 = <&spi_0_pins>;
-			pinctrl-names = "default";
-			cs-select = <0>;
-
-			m25p80@0 {
-				  compatible = "w25q256jw";
-				  #address-cells = <1>;
-				  #size-cells = <1>;
-				  reg = <0>;
-				  spi-max-frequency = <50000000>;
-			};
-		};
-
-		dma@7984000 {
-			 status = "ok";
-		};
-
-		nand@79b0000 {
-			status = "ok";
-
-			nand@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				nand-ecc-strength = <4>;
-				nand-ecc-step-size = <512>;
-				nand-bus-width = <8>;
-			};
-		};
-
-		phy@84000 {
-			status = "ok";
-		};
-
-		phy@86000 {
-			status = "ok";
-		};
-
-		pci@20000000 {
-			perst-gpio = <&tlmm 58 1>;
-			status = "ok";
-		};
-
-		gpio_keys {
-			compatible = "gpio-keys";
-			pinctrl-0 = <&button_pins>;
-			pinctrl-names = "default";
-			status = "ok";
-
-			button@1 {
-				label = "reset";
-				linux,code = <KEY_RESTART>;
-				gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-				linux,input-type = <1>;
-				debounce-interval = <60>;
-			};
-		};
-
-		leds {
-			compatible = "gpio-leds";
-			pinctrl-0 = <&led_pins>;
-			pinctrl-names = "default";
-
-			led_power: led_power {
-				label = "blue:power";
-				gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-				default-state = "off";
-			};
-		};
 
+&soc {
 	mdio: mdio@90000 {
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 37 0 &tlmm 25 1>;
+		compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
 		phy0: ethernet-phy@0 {
 			reg = <0>;
 		};
@@ -530,15 +573,10 @@
 						sp = <60>;
 						cfg = <0 32 0 32>;
 					};
-						group@1 {
-							sp = <61>;
-							cfg = <1 33 1 33>;
-						};
 				};
 				l0scheduler {
 					group@0 {
 						ucast_queue = <240>;
-							ucast_loop_pri = <16>;
 						mcast_queue = <296>;
 						cfg = <60 0 144 0 144>;
 					};
@@ -547,6 +585,45 @@
 		};
 	};
 
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <28>;
+		phy-mode = "sgmii";
+	};
+	
+	/* POWER LED, TP-Link */
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_power: led_power {
+			label = "power:blue";
+			gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	/* BUTTON, TP-Link */
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		button@1 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+		};
+	};
+
 	nss-macsec0 {
 		compatible = "qcom,nss-macsec";
 		phy_addr = <0x18>;
@@ -559,5 +636,119 @@
 		phy_access_mode = <0>;
 		mdiobus = <&mdio>;
 	};
+};
+
+&serial_blsp4 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
 	};
 };
+
+&spi_4 { /* BLSP1 QUP3 */
+	pinctrl-0 = <&spi_3_pins>;
+	pinctrl-names = "default";
+	cs-select = <2>;
+	quartz-reset-gpio = <&tlmm 21 1>;
+	status = "disabled";
+	spidev3: spi@3 {
+		compatible = "qca,spidev";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+	};
+};
+
+&serial_blsp2 {
+	status = "disabled";
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	status = "disabled";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "disabled";
+};
+
+&qpic_lcd_panel {
+	status = "disabled";
+};
+
+&ledc {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "ok";
+};
+
+&pcie1 {
+	status = "disabled";
+};
+

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-wf194c.dts

@@ -1,33 +1,197 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074-hk01.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-audio.dtsi"
+#include "qcom-ipq807x-audio.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
 	model = "CIG WF194C";
 	compatible = "cig,wf194c", "qcom,ipq807x";
+	qcom,msm-id = <0x143 0x0>, <0x158 0x0>, <0x186 0x0>, <0x188 0x0>;
+	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		/delete-property/ ethernet2;
+		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
-		/delete-property/ ethernet3;
+		sdhc2 = &sdhc_2; /* SDC2 SD slot */
-		/delete-property/ ethernet4;
+		/*
-		/delete-property/ ethernet5;
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
+		ethernet0 = "/soc/dp1";
+		ethernet1 = "/soc/dp2";
 	};
 
-	soc {
+	chosen {
-		/delete-node/ ledc@191E000;
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
-		/delete-node/ qti,scm_restart_reason;
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+			bootargs-append = " swiotlb=1";
+		#else
+			bootargs-append = " swiotlb=1 coherent_pool=2M";
+		#endif
+	};
+};
 
-		pinctrl@1000000 {
+&tlmm {
-			button_pins: button_pins {
+	pinctrl-0 = <&btcoex_pins>;
-				wps_button {
+	pinctrl-names = "default";
-					pins = "gpio57";
+
+	btcoex_pins: btcoex_pins {
+		mux_0 {
+			pins = "gpio34";
 			function = "gpio";
+			drive-strength = <6>;
+			bias-pull-up;
+			output-high;
+		};
+		mux_1 {
+			pins = "gpio62";
+			function = "gpio";
+			drive-strength = <6>;
+			bias-pull-up;
+			output-high;
+		};
+	};
+
+	mdio_pins: mdio_pinmux {
+		mux_0 {
+			pins = "gpio68";
+			function = "mdc";
 			drive-strength = <8>;
 			bias-pull-up;
 		};
+		mux_1 {
+			pins = "gpio69";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	i2c_0_pins: i2c_0_pinmux {
+		mux {
+			pins = "gpio42", "gpio43";
+			function = "blsp1_i2c";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_8 {
+			pins = "gpio16";
+			function = "qpic_pad8";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4",
+			       "gpio9", "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	sd_pins: sd_pins {
+		mux {
+			pins = "gpio63";
+			function = "sd_card";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+		};
 	};
 
 	leds_pins: leds_pinmux {
@@ -37,28 +201,66 @@
 			drive-strength = <8>;
 			bias-pull-down;
 		};
-
 		led1_g {
 			pins = "gpio55";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
-
 		led2_r {
 			pins = "gpio56";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
-
 		led2_g {
 			pins = "gpio64";
 			function = "gpio";
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+
 	};
+
+	button_pins: button_pins {
+		wps_button {
+			pins = "gpio67";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	uniphy_pins: uniphy_pinmux {
+		mux_2 {
+			pins = "gpio37";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		mux_3 {
+			pins = "gpio44";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	pwm_pins: pwm_pinmux {
+		mux_1 {
+			pins = "gpio25";
+			function = "pwm02";
+			drive-strength = <8>;
+		};
+	};
+};
+
+&soc {
+	pwm {
+		pinctrl-0 = <&pwm_pins>;
+		pinctrl-names = "default";
+		used-pwm-indices = <1>, <0>, <0>, <0>;
+		status = "disabled";
 	};
 
 	gpio_keys {
@@ -86,56 +288,28 @@
 			gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led@55 {
 			label = "wf194c:green:lan";
 			gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
-
 		led@56 {
 			label = "wf194c:red:wan";
 			gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
-
 		led@64 {
 			label = "wf194c:green:wan";
 			gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
 		};
 	};
-
-		dp1 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <4>;
-			reg = <0x3a001600 0x200>;
-			qcom,mactype = <0>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <3>;
-			phy-mode = "sgmii";
-		};
-
-		dp2 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <6>;
-			reg = <0x3a007000 0x3fff>;
-			qcom,mactype = <1>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <0>;
-			phy-mode = "sgmii";
-		};
-
 	mdio@90000 {
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 37 0 &tlmm 44 0>;
 		phy0: ethernet-phy@0 {
-				reg = <0xf>;
+			reg = <0xf>;	/*<0>*/
 		};
 		phy1: ethernet-phy@1 {
 			reg = <0xf>;
@@ -156,8 +330,10 @@
 	};
 
 	ess-switch@3a000000 {
+		pinctrl-0 = <&uniphy_pins>;
+		pinctrl-names = "default";
 		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
-			switch_lan_bmp = <0x30>; /* lan port bitmap */
+		switch_lan_bmp = <0x30>; /*..0x3e lan port bitmap */
 		switch_wan_bmp = <0x40>; /* wan port bitmap */
 		switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
 		switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
@@ -437,25 +613,139 @@
 			};
 		};
 	};
-
+	dp1 {
-		pwm {
+		device_type = "network";
-			status = "disabled";
+		compatible = "qcom,nss-dp";
-		};
+		qcom,id = <4>;
-
+		reg = <0x3a001600 0x200>;
-		qti_mdss_qpic@7980000 {
+		qcom,mactype = <0>;
-			status = "disabled";
+		local-mac-address = [000000000000];
-		};
+		qcom,link-poll = <1>;
-
+		qcom,phy-mdio-addr = <3>;
-		qti_mdss_qpic_panel {
+		phy-mode = "sgmii";
-			status = "disabled";
-		};
-
-		i2c@78b6000 {
-			status = "disabled";
-		};
-
-		sdhci@7824900 {
-			status = "disabled";
 	};
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a007000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
 	};
 };
+
+&serial_blsp4 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
+	};
+};
+
+&serial_blsp2 {
+	pinctrl-0 = <&hsuart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&msm_imem {
+	status = "enabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	pinctrl-0 = <&i2c_0_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&sdhc_1 {
+	qcom,clk-rates = <400000 25000000 50000000 100000000 \
+			 192000000 384000000>;
+	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+	qcom,nonremovable;
+	status = "ok";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&sdhc_2 {
+	qcom,clk-rates = <400000 25000000 50000000 100000000 \
+			 192000000>;
+	qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+	pinctrl-0 = <&sd_pins>;
+	pinctrl-names = "default";
+	cd-gpios = <&tlmm 63 1>;
+	sd-ldo-gpios = <&tlmm 21 0>;
+	vqmmc-supply = <&ldo11>;
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "ok";
+};
+
+&qpic_lcd_panel {
+	status = "ok";
+};

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-wf194c4.dts

@@ -1,110 +1,113 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-hk-cpu.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "CIG WF194c4";
 	compatible = "cig,wf194c4", "qcom,ipq807x";
-	qcom,msm-id = <0x157 0x0>, <0x187 0x0>;
+	qcom,msm-id = <0x156 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet0 = "/soc/dp1";
 		ethernet1 = "/soc/dp2";
+	/*	ethernet2 = "/soc/dp3";
+		ethernet3 = "/soc/dp4";
+		ethernet4 = "/soc/dp5";
+		ethernet5 = "/soc/dp6";
+	*/
 	};
 
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
+			init=/init";
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+			bootargs-append = " swiotlb=1";
+		#else
+			bootargs-append = " swiotlb=1 coherent_pool=2M";
+		#endif
 	};
+};
 
-	soc {
+&tlmm {
-		gpio_keys {
+	pinctrl-0 = <&btcoex_pins>;
-			compatible = "gpio-keys";
-			pinctrl-0 = <&button_pins>;
 	pinctrl-names = "default";
 
-			button@1 {
+	btcoex_pins: btcoex_pins {
-				label = "reset";
+/*	
-				linux,code = <KEY_RESTART>;
+		mux_0 {
-				gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+			pins = "gpio64";
-				linux,input-type = <1>;
+			function = "pta1_1";
-				debounce-interval = <60>;
+			drive-strength = <6>;
+			bias-pull-down;
 		};
+		mux_1 {
+			pins = "gpio65";
+			function = "pta1_2";
+			drive-strength = <6>;
+			bias-pull-down;
 		};
-
+		mux_2 {
-		leds {
+			pins = "gpio66";
-			compatible = "gpio-leds";
+			function = "pta1_0";
-			pinctrl-0 = <&leds_pins>;
+			drive-strength = <6>;
-			pinctrl-names = "default";
+			bias-pull-down;
-			status = "ok";
-
-			led@54 {
-				label = "red:lan";
-				gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-				linux,default-trigger = "led1_r";
-				default-state = "off";
 		};
-
+		mux_3 {
-			led@55 {
+			pins = "gpio54";
-				label = "green:lan";
+			function = "pta2_0";
-				gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+			drive-strength = <6>;
-				linux,default-trigger = "led1_g";
+			bias-pull-down;
-				default-state = "off";
 		};
-
+		mux_4 {
-			led@56 {
+			pins = "gpio55";
-				label = "red:wan";
+			function = "pta2_1";
-				gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+			drive-strength = <6>;
-				linux,default-trigger = "led2_r";
+			bias-pull-down;
-				default-state = "off";
 		};
-
+		mux_5 {
-			led@64 {
+			pins = "gpio56";
-				label = "green:wan";
+			function = "pta2_2";
-				gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+			drive-strength = <6>;
-				linux,default-trigger = "led2_g";
+			bias-pull-down;
-				default-state = "off";
 		};
-		};
+*/		
-
+		mux_0 {
-		pinctrl@1000000 {
-			button_pins: button_pins {
-				wps_button {
 			pins = "gpio34";
 			function = "gpio";
-					drive-strength = <8>;
+			drive-strength = <6>;
 			bias-pull-up;
+			output-high;
 		};
-			};
+		mux_1 {
-
+			pins = "gpio62";
-			usb_mux_sel_pins: usb_mux_pins {
-				mux {
-					pins = "gpio27";
 			function = "gpio";
-					drive-strength = <8>;
+			drive-strength = <6>;
-					bias-pull-down;
+			bias-pull-up;
-				};
+			output-high;
-			};
-
-			pcie0_pins: pcie_pins {
-				pcie0_rst {
-					pins = "gpio58";
-					function = "pcie0_rst";
-					drive-strength = <8>;
-					bias-pull-down;
-				};
-				pcie0_wake {
-					pins = "gpio59";
-					function = "pcie0_wake";
-					drive-strength = <8>;
-					bias-pull-down;
 		};
 	};
 
@@ -121,15 +124,117 @@
 			drive-strength = <8>;
 			bias-pull-up;
 		};
-				mux_2 {
-					pins = "gpio25";
-					function = "gpio";
-					bias-pull-up;
 	};
-				mux_3 {
+
-					pins = "gpio44";
+	uart_pins: uart_pins {
+		mux {
+			pins = "gpio23", "gpio24";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	/*spi_3_pins: spi_3_pins {
+		mux {
+			pins = "gpio50", "gpio52", "gpio53";
+			function = "blsp3_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		spi_cs {
+			pins = "gpio22";
+			function = "blsp3_spi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		quartz_interrupt {
+			pins = "gpio47";
 			function = "gpio";
-					bias-pull-up;
+			input;
+			bias-disable;
+		};
+		quartz_reset {
+			pins = "gpio21";
+			function = "gpio";
+			output-low;
+			bias-disable;
+		};
+	};*/
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
 		};
 	};
 
@@ -167,141 +272,101 @@
 			drive-strength = <8>;
 			bias-pull-down;
 		};
+
 	};
 
-			spi_3_pins: spi_3_pins {
+	/*usb_mux_sel_pins: usb_mux_pins {
 		mux {
-					pins = "gpio50", "gpio52", "gpio53";
+			pins = "gpio27";
-					function = "blsp3_spi";
-					drive-strength = <8>;
-					bias-disable;
-				};
-				spi_cs {
-					pins = "gpio22";
-					function = "blsp3_spi2";
-					drive-strength = <8>;
-					bias-disable;
-				};
-				quartz_interrupt {
-					pins = "gpio47";
 			function = "gpio";
-					input;
+			drive-strength = <8>;
-					bias-disable;
+			bias-pull-down;
 		};
-				quartz_reset {
+	};
-					pins = "gpio21";
+
+	pcie0_pins: pcie_pins {
+		pcie0_rst {
+			pins = "gpio58";
+			function = "pcie0_rst";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		pcie0_wake {
+			pins = "gpio59";
+			function = "pcie0_wake";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};*/
+	uniphy_pins: uniphy_pinmux {	
+		mux_2 {
+			pins = "gpio37";
 			function = "gpio";
-					output-low;
+			drive-strength = <8>;
-					bias-disable;
+			bias-pull-up;
 		};
+		mux_3 {
+			pins = "gpio44";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
 		};
 	};
 
-		serial@78b3000 {
+};
-			status = "ok";
-		};
 
-		dp1 {
+&soc {
-			device_type = "network";
+	gpio_keys {
-			compatible = "qcom,nss-dp";
+		compatible = "gpio-keys";
-			qcom,id = <4>;
+		pinctrl-0 = <&button_pins>;
-			reg = <0x3a001600 0x200>;
-			qcom,mactype = <0>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <0x13>;
-			phy-mode = "sgmii";
-			};
-			
-		dp2 {
-			device_type = "network";
-			compatible = "qcom,nss-dp";
-			qcom,id = <6>;
-			reg = <0x3a007000 0x3fff>;
-			qcom,mactype = <1>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <0>;
-			phy-mode = "sgmii";
-		};
-
-		spi@78b5000 {
-			status = "ok";
-			pinctrl-0 = <&spi_0_pins>;
 		pinctrl-names = "default";
-			cs-select = <0>;
 
-			m25p80@0 {
+		button@1 {
-				  compatible = "n25q128a11";
+			label = "reset";
-				  #address-cells = <1>;
+			linux,code = <KEY_RESTART>;
-				  #size-cells = <1>;
+			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
-				  reg = <0>;
+			linux,input-type = <1>;
-				  spi-max-frequency = <50000000>;
+			debounce-interval = <60>;
 		};
 	};
 
-
+  	leds {
-		dma@7984000 {
+   		 compatible = "gpio-leds";
-			 status = "ok";
+	  	 pinctrl-0 = <&leds_pins>;
-		};
+	  	 pinctrl-names = "default";
-
-		nand@79b0000 {
 	  	 status = "ok";
 	  
-			nand@0 {
+    	  		led@54 {
-				reg = <0>;
+      	  			label = "red:lan";
-				#address-cells = <1>;
+     	  			gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-				#size-cells = <1>;
+      	  			linux,default-trigger = "led1_r";
-
+      	  			default-state = "off";
-				nand-ecc-strength = <4>;
+    	  		};
-				nand-ecc-step-size = <512>;
+    	  		led@55 {
-				nand-bus-width = <8>;
+      	  			 label = "green:lan";
+          			 gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+          			 linux,default-trigger = "led1_g";
+         			 default-state = "off";
+          		};
+         		led@56 {
+         			label = "red:wan";
+         			gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+         			linux,default-trigger = "led2_r";
+         			default-state = "off";
+         		};  
+    			led@64 {
+      				label = "green:wan";
+      				gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
+      				linux,default-trigger = "led2_g";
+      				default-state = "off";
     			};
 	};
-
-		qusb@79000 {
-			status = "ok";
-		};
-
-		ssphy@78000 {
-			status = "ok";
-		};
-
-		usb3@8A00000 {
-			status = "ok";
-		};
-
-		qusb@59000 {
-			status = "ok";
-		};
-
-		ssphy@58000 {
-			status = "ok";
-		};
-
-		usb3@8C00000 {
-			status = "ok";
-		};
-
-		phy@84000 {
-			status = "ok";
-		};
-
-		phy@86000 {
-			status = "ok";
-		};
-
-		pci@20000000 {
-			perst-gpio = <&tlmm 58 1>;
-			status = "ok";
-		};
-
 	mdio: mdio@90000 {
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
-			phy-reset-gpio = <&tlmm 37 0 &tlmm 25 0 &tlmm 44 0>;
+		phy-reset-gpio = <&tlmm 37 0 &tlmm 44 0>;
 		phy0: ethernet-phy@0 {
-				reg = <0x10>;
+			reg = <0x10>;	/*<0>*/
 		};
 		phy1: ethernet-phy@1 {
 			reg = <0x11>;
@@ -316,19 +381,50 @@
 			reg = <0x14>;
 		};
 		phy5: ethernet-phy@5 {
+			compatible ="ethernet-phy-ieee802.3-c45";
 			reg = <0>;
 		};
 	};
 
 	ess-switch@3a000000 {
+		pinctrl-0 = <&uniphy_pins>;
+		pinctrl-names = "default";
 		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
-			switch_lan_bmp = <0x32>; /* lan port bitmap */
+		switch_lan_bmp = <0x32>; /*..0x3e lan port bitmap */
 		switch_wan_bmp = <0x40>; /* wan port bitmap */
 		switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
 		switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
 		switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
 		bm_tick_mode = <0>; /* bm tick mode */
 		tm_tick_mode = <0>; /* tm tick mode */
+		/*qcom,port_phyinfo {
+			port@0 {
+				port_id = <1>;
+				phy_address = <0>;
+			};
+			port@1 {
+				port_id = <2>;
+				phy_address = <1>;
+			};
+			port@2 {
+				port_id = <3>;
+				phy_address = <2>;
+			};
+			port@3 {
+				port_id = <4>;
+				phy_address = <3>;
+			};
+			port@4 {
+				port_id = <5>;
+				phy_address = <24>;
+				port_mac_sel = "QGMAC_PORT";
+			};
+			port@5 {
+				port_id = <6>;
+				phy_address = <28>;
+				port_mac_sel = "QGMAC_PORT";
+			};
+		};*/
 		port_scheduler_resource {
 			port@0 {
 				port_id = <0>;
@@ -586,15 +682,10 @@
 						sp = <60>;
 						cfg = <0 32 0 32>;
 					};
-						group@1 {
-							sp = <61>;
-							cfg = <1 33 1 33>;
-						};
 				};
 				l0scheduler {
 					group@0 {
 						ucast_queue = <240>;
-							ucast_loop_pri = <16>;
 						mcast_queue = <296>;
 						cfg = <60 0 144 0 144>;
 					};
@@ -602,6 +693,121 @@
 			};
 		};
 	};
+/*
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <1>;
+		reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
+	};
+
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <1>;
+		phy-mode = "sgmii";
+	};
+
+	dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <2>;
+		phy-mode = "sgmii";
+	};
+
+	dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <3>;
+		phy-mode = "sgmii";
+	};
+
+	dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a003000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <24>;
+		phy-mode = "sgmii";
+	};
+
+	dp6 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a007000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <28>;
+		phy-mode = "sgmii";
+	};
+*/
+	dp1 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+	//	qcom,id = <1>;
+	//	reg = <0x3a001000 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0x13>;
+		phy-mode = "sgmii";
+	};
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a007000 0x3fff>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
+	};
+/*	
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&led_pins>;
+		pinctrl-names = "default";
+
+		led_2g {
+			label = "led_2g";
+			gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led_5g {
+			label = "led_5g";
+			gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
 
 	nss-macsec0 {
 		compatible = "qcom,nss-macsec";
@@ -615,5 +821,122 @@
 		phy_access_mode = <0>;
 		mdiobus = <&mdio>;
 	};
+*/
+};
+
+&serial_blsp4 {
+	pinctrl-0 = <&uart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&spi_0 { /* BLSP1 QUP1 */
+	pinctrl-0 = <&spi_0_pins>;
+	pinctrl-names = "default";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
 	};
 };
+/*
+&spi_4 { 
+	pinctrl-0 = <&spi_3_pins>;
+	pinctrl-names = "default";
+	cs-select = <2>;
+	quartz-reset-gpio = <&tlmm 21 1>;
+	status = "ok";
+	spidev3: spi@3 {
+		compatible = "qca,spidev";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+	};
+};*/
+
+&serial_blsp2 {
+	pinctrl-0 = <&hsuart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&ssphy_1 {
+	status = "ok";
+};
+
+&qusb_phy_1 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&usb3_1 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	status = "disabled";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "disabled";
+};
+
+&qpic_lcd_panel {
+	status = "disabled";
+};
+
+&ledc {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "disabled";
+};
+
+&pcie1 {
+	status = "disabled";
+};
+

feeds/ipq807x/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-wf196.dts

@@ -1,24 +1,45 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /dts-v1/;
-/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+/*
- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
-#include "ipq8074.dtsi"
+#include "qcom-ipq807x-soc.dtsi"
-#include "ipq8074-hk-cpu.dtsi"
+#include "qcom-ipq807x-audio.dtsi"
+#include "qcom-ipq807x-hk-cpu.dtsi"
 
 / {
 	#address-cells = <0x2>;
 	#size-cells = <0x2>;
 	model = "CIG WF196";
 	compatible = "cig,wf196", "qcom,ipq807x";
-	qcom,msm-id = <0x157 0x0>, <0x187 0x0>;
+	qcom,msm-id = <0x187 0x0>;
 	interrupt-parent = <&intc>;
+	qcom,board-id = <0x8 0x0>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0>;
 
 	aliases {
-		serial0 = &blsp1_uart5;
+		/*
-		/* Aliases as required by u-boot to patch MAC addresses */
+		 * Aliases as required by u-boot
+		 * to patch MAC addresses
+		 */
 		ethernet0 = "/soc/dp1";
 		ethernet1 = "/soc/dp2";
+		ethernet2 = "/soc/dp3";
+		ethernet3 = "/soc/dp4";
+		ethernet4 = "/soc/dp5";
+		ethernet5 = "/soc/dp6";
+
 		led-boot = &led_power;
 		led-failsafe = &led_power;
 		led-running = &led_power;
@@ -26,7 +47,12 @@
 	};
 
 	chosen {
-		stdout-path = "serial0";
+		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
+		#ifdef __IPQ_MEM_PROFILE_256_MB__
+			bootargs-append = " swiotlb=1";
+		#else
+			bootargs-append = " swiotlb=1 coherent_pool=2M vmalloc=600M";
+		#endif
 	};
 
 	reserved-memory {
@@ -57,27 +83,26 @@
 	 * +--------+--------------+-------------------------+
 	 * | M3 Dump|  0x4E800000  |           1MB           |
 	 * +--------+--------------+-------------------------+
-	 * |  Pine  |  0x4E900000  |          38MB           |
+	 * |  Pine0 |  0x4E900000  |          30MB           |
 	 * +--------+--------------+-------------------------+
-	 * |  MHI0  |  0x50F00000  |          9MB            |
+	 * |  MHI0  |  0x50700000  |          16MB           |
 	 * +--------+--------------+-------------------------+
 	 * |                                                 |
 	 * |      Rest of the memory for Linux               |
 	 * |                                                 |
 	 * +=================================================+
 	 */
-		qcn9000_pcie0: qcn9000_pcie0@4e900000 {
+		/delete-node/ wifi_dump@4e900000;
+		qcn9000_pcie0@4e900000 {
 			no-map;
-			reg = <0x0 0x4e900000 0x0 0x02600000>;
+			reg = <0x0 0x4e900000 0x0 0x01e00000>;
 		};
 
-#if defined(__CNSS2__)
+		mhi_region0: dma_pool0@50700000 {
-		mhi_region0: dma_pool0@50F00000 {
 			compatible = "shared-dma-pool";
 			no-map;
-			reg = <0x0 0x50F00000 0x0 0x00900000>;
+			reg = <0x0 0x50700000 0x0 0x01000000>;
 		};
-#endif
 #else
 	/*                   Default Profile
 	 * +========+==============+=========================+
@@ -103,53 +128,53 @@
 	 * +--------+--------------+-------------------------+
 	 * | M3 Dump|  0x51000000  |           1MB           |
 	 * +--------+--------------+-------------------------+
-	 * |  Pine0 |  0x51100000  |          53MB           |
+	 * |  Pine0 |  0x51100000  |          45MB           |
 	 * +--------+--------------+-------------------------+
-	 * |  MHI0  |  0x54600000  |           9MB           |
+	 * |  MHI0  |  0x53E00000  |          24MB           |
 	 * +--------+--------------+-------------------------+
 	 * |                                                 |
 	 * |          Rest of the memory for Linux           |
 	 * |                                                 |
 	 * +=================================================+
 	 */
-		qcn9000_pcie0: qcn9000_pcie0@51100000 {
+		qcn9000_pcie0@51100000 {
 			no-map;
-			reg = <0x0 0x51100000 0x0 0x03500000>;
+			reg = <0x0 0x51100000 0x0 0x02D00000>;
 		};
+		/delete-node/ wifi_dump@51100000;
+		/delete-node/ wigig_dump@51300000;
 
-#if defined(__CNSS2__)
+		mhi_region0: dma_pool0@53e00000 {
-		mhi_region0: dma_pool0@54600000 {
 			compatible = "shared-dma-pool";
 			no-map;
-			reg = <0x0 0x54600000 0x0 0x00900000>;
+			reg = <0x0 0x53E00000 0x0 0x01800000>;
 		};
 #endif
-#endif
 #endif
 	};
+};
 
-	soc {
+&tlmm {
-		pinctrl@1000000 {
+	pinctrl-0 = <&btcoex_pins>;
-			button_pins: button_pins {
+	pinctrl-names = "default";
-				wps_button {
-					pins = "gpio67";
-					function = "gpio";
-					drive-strength = <8>;
-					bias-pull-up;
-				};
-			};
 
-			pcie0_pins: pcie_pins {
+	btcoex_pins: btcoex_pins {
-				pcie0_rst {
+		mux_0 {
-					pins = "gpio58";
+			pins = "gpio64";
-					function = "pcie0_rst";
+			function = "pta1_1";
-					drive-strength = <8>;
+			drive-strength = <6>;
 			bias-pull-down;
 		};
-				pcie0_wake {
+		mux_1 {
-					pins = "gpio59";
+			pins = "gpio65";
-					function = "pcie0_wake";
+			function = "pta1_2";
-					drive-strength = <8>;
+			drive-strength = <6>;
+			bias-pull-down;
+		};
+		mux_2 {
+			pins = "gpio66";
+			function = "pta1_0";
+			drive-strength = <6>;
 			bias-pull-down;
 		};
 	};
@@ -167,20 +192,142 @@
 			drive-strength = <8>;
 			bias-pull-up;
 		};
-				mux_2 {
+		mux_3 {
 			pins = "gpio44";
 			function = "gpio";
 			bias-pull-up;
 		};
 	};
 
-			uniphy_pins: uniphy_pinmux {
+	uart_pins: uart_pins {
 		mux {
-					pins = "gpio60";
+			pins = "gpio23", "gpio24";
-					function = "rx2";
+			function = "blsp4_uart1";
+			drive-strength = <8>;
 			bias-disable;
 		};
 	};
+	i2c_5_pins: i2c_5_pinmux {
+                mux {
+                        pins = "gpio0", "gpio2";
+                        function = "blsp5_i2c";
+                        drive-strength = <8>;
+                        bias-disable;
+                };
+        };
+
+	spi_0_pins: spi_0_pins {
+		mux {
+			pins = "gpio38", "gpio39", "gpio40", "gpio41";
+			function = "blsp0_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	spi_3_pins: spi_3_pins {
+		mux {
+			pins = "gpio50", "gpio52", "gpio53";
+			function = "blsp3_spi";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		spi_cs {
+			pins = "gpio22";
+			function = "blsp3_spi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		quartz_interrupt {
+			pins = "gpio47";
+			function = "gpio";
+			input;
+			bias-disable;
+		};
+		quartz_reset {
+			pins = "gpio21";
+			function = "gpio";
+			output-low;
+			bias-disable;
+		};
+	};
+
+	qpic_pins: qpic_pins {
+		data_0 {
+			pins = "gpio15";
+			function = "qpic_pad0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_1 {
+			pins = "gpio12";
+			function = "qpic_pad1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_2 {
+			pins = "gpio13";
+			function = "qpic_pad2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_3 {
+			pins = "gpio14";
+			function = "qpic_pad3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_4 {
+			pins = "gpio5";
+			function = "qpic_pad4";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_5 {
+			pins = "gpio6";
+			function = "qpic_pad5";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_6 {
+			pins = "gpio7";
+			function = "qpic_pad6";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		data_7 {
+			pins = "gpio8";
+			function = "qpic_pad7";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		qpic_pad {
+			pins = "gpio1", "gpio3", "gpio4",
+			       "gpio10", "gpio11", "gpio17";
+			function = "qpic_pad";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	hsuart_pins: hsuart_pins {
+		mux {
+			pins = "gpio46", "gpio47", "gpio48", "gpio49";
+			function = "blsp2_uart";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	button_pins: button_pins {
+
+		wps_button {
+			pins = "gpio67";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
 
 	led_pins: led_pins {
 		led_red {
@@ -204,91 +351,67 @@
 			bias-pull-down;
 		};
 	};
+
+	pcie0_pins: pcie_pins {
+		pcie0_rst {
+			pins = "gpio58";
+			function = "pcie0_rst";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+		pcie0_wake {
+			pins = "gpio59";
+			function = "pcie0_wake";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+	pwm_pins: pwm_pinmux {
+                mux_1 {
+                        pins = "gpio25";
+                        function = "pwm02";
+                        drive-strength = <8>;
+                };
+		mux_2 {
+                        pins = "gpio26";
+                        function = "pwm12";
+                        drive-strength = <8>;
+                };
+		mux_3 {
+                        pins = "gpio27";
+                        function = "pwm22";
+                        drive-strength = <8>;
+                };
 	};
 
-		serial@78b3000 {
+};
-			status = "ok";
-		};
 
-		spi@78b5000 {
+&soc {
-			status = "ok";
+	 pwm {
-			pinctrl-0 = <&spi_0_pins>;
+                pinctrl-0 = <&pwm_pins>;
+                pinctrl-names = "default";
+                used-pwm-indices = <1>, <1>, <1>, <0>;
+         //       status = "ok";
+        };
+	gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
 		pinctrl-names = "default";
-			cs-select = <0>;
 
-			m25p80@0 {
+		button@1 {
-				  compatible = "n25q128a11";
+			label = "reset";
-				  #address-cells = <1>;
+			linux,code = <KEY_RESTART>;
-				  #size-cells = <1>;
+			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
-				  reg = <0>;
+			linux,input-type = <1>;
-				  spi-max-frequency = <50000000>;
+			debounce-interval = <60>;
 		};
 	};
 
-		dma@7984000 {
+	mdio: mdio@90000 {
-			 status = "ok";
-		};
-
-		nand@79b0000 {
-			status = "ok";
-
-			nand@0 {
-				reg = <0>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				nand-ecc-strength = <4>;
-				nand-ecc-step-size = <512>;
-				nand-bus-width = <8>;
-			};
-		};
-
-		qusb@79000 {
-			status = "ok";
-		};
-
-		ssphy@78000 {
-			status = "ok";
-		};
-
-		usb3@8A00000 {
-			status = "ok";
-		};
-
-		qcom,test@0 {
-			status = "ok";
-		};
-
-		phy@84000 {
-			status = "ok";
-		};
-
-		phy@86000 {
-			status = "ok";
-		};
-
-		pci@20000000 {
-			perst-gpio = <&tlmm 58 1>;
-			status = "ok";
-
-			pcie0_rp: pcie0_rp {
-				reg = <0 0 0 0 0>;
-			};
-		};
-
-		phy@8e000 {
-			status = "ok";
-		};
-
-		pci@10000000 {
-			perst-gpio = <&tlmm 61 0x1>;
-			status = "ok";
-		};
-
-		mdio@90000 {
 		pinctrl-0 = <&mdio_pins>;
 		pinctrl-names = "default";
 		phy-reset-gpio = <&tlmm 64 0 &tlmm 66 0>;
+		compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
 		phy0: ethernet-phy@0 {
 			reg = <16>;
 		};
@@ -311,8 +434,6 @@
 	};
 
 	ess-switch@3a000000 {
-			pinctrl-0 = <&uniphy_pins>;
-			pinctrl-names = "default";
 		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
 		switch_lan_bmp = <0x3e>; /* lan port bitmap */
 		switch_wan_bmp = <0xc0>; /* wan port bitmap */
@@ -623,19 +744,77 @@
 			};
 		};
 	};
-		gpio_keys {
-			compatible = "gpio-keys";
-			pinctrl-0 = <&button_pins>;
-			pinctrl-names = "default";
-			status = "ok";
 
-			button@1 {
+	dp1 {
-				label = "reset";
+		device_type = "network";
-				linux,code = <KEY_RESTART>;
+		compatible = "qcom,nss-dp";
-				gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+		qcom,id = <1>;
-				linux,input-type = <1>;
+		reg = <0x3a001000 0x200>;
-				debounce-interval = <60>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <16>;
+		phy-mode = "sgmii";
 	};
+
+	dp2 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <2>;
+		reg = <0x3a001200 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <17>;
+		phy-mode = "sgmii";
+	};
+
+	dp3 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <3>;
+		reg = <0x3a001400 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <18>;
+		phy-mode = "sgmii";
+	};
+
+	dp4 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <4>;
+		reg = <0x3a001600 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <19>;
+		phy-mode = "sgmii";
+	};
+
+	dp5 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <5>;
+		reg = <0x3a001800 0x200>;
+		qcom,mactype = <1>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <0>;
+		phy-mode = "sgmii";
+	};
+
+	dp6 {
+		device_type = "network";
+		compatible = "qcom,nss-dp";
+		qcom,id = <6>;
+		reg = <0x3a001a00 0x200>;
+		qcom,mactype = <0>;
+		local-mac-address = [000000000000];
+		qcom,link-poll = <1>;
+		qcom,phy-mdio-addr = <28>;
+		phy-mode = "sgmii";
 	};
 
 	leds {
@@ -661,29 +840,157 @@
 			default-state = "off";
 		};
 	};
-
+	nss-macsec0 {
-		dp1 {
+		compatible = "qcom,nss-macsec";
-			device_type = "network";
+		phy_addr = <0>;
-			compatible = "qcom,nss-dp";
+		phy_access_mode = <0>;
-			qcom,id = <5>;
+		mdiobus = <&mdio>;
-			reg = <0x3a001800 0x200>;
-			qcom,mactype = <1>;
-			local-mac-address = [000000000000];
-			qcom,link-poll = <1>;
-			qcom,phy-mdio-addr = <0>;
-			phy-mode = "sgmii";
 	};
+	nss-macsec1 {
+		compatible = "qcom,nss-macsec";
+		phy_addr = <0x1c>;
+		phy_access_mode = <0>;
+		mdiobus = <&mdio>;
+	};
+	i2c_5: i2c@78ba000 {
+		compatible = "qcom,i2c-qup-v2.2.1";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x78ba000 0x600>;
+		interrupts = <GIC_SPI 300 0x4>;
+		clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+			<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+		clock-names = "iface", "core";
+		clock-frequency  = <100000>;
+		dmas = <&blsp_dma 23>, <&blsp_dma 22>;
+		dma-names = "rx", "tx";
+	};
+};
 
-		dp2 {
+&serial_blsp4 {
-			device_type = "network";
+	pinctrl-0 = <&uart_pins>;
-			compatible = "qcom,nss-dp";
+	pinctrl-names = "default";
-			qcom,id = <6>;
+	status = "ok";
-			reg = <0x3a001a00 0x200>;
+};
-			qcom,mactype = <0>;
+
-			local-mac-address = [000000000000];
+&spi_0 { /* BLSP1 QUP1 */
-			qcom,link-poll = <1>;
+	pinctrl-0 = <&spi_0_pins>;
-			qcom,phy-mdio-addr = <28>;
+	pinctrl-names = "default";
-			phy-mode = "sgmii";
+	cs-select = <0>;
+	status = "ok";
+
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "n25q128a11";
+		linux,modalias = "m25p80", "n25q128a11";
+		spi-max-frequency = <50000000>;
+		use-default-sizes;
+	};
+};
+
+&serial_blsp2 {
+	pinctrl-0 = <&hsuart_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&msm_imem {
+	status = "disabled";
+};
+
+&ssphy_0 {
+	status = "ok";
+};
+
+&qusb_phy_0 {
+	status = "ok";
+};
+
+&usb3_0 {
+	status = "ok";
+};
+
+&cryptobam {
+	status = "ok";
+};
+
+&crypto {
+	status = "ok";
+};
+
+&i2c_0 {
+	status = "disabled";
+};
+
+&i2c_1 {
+	status = "disabled";
+};
+
+&i2c_5 {
+	pinctrl-0 = <&i2c_5_pins>;
+        pinctrl-names = "default";
+        status = "ok";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qpic_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_lcd {
+	status = "disabled";
+};
+
+&qpic_lcd_panel {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "ok";
+};
+
+
+&pcie0_rp {
+	status = "ok";
+
+	mhi_0: qcom,mhi@0 {
+		reg = <0 0 0 0 0 >;
+		qrtr_instance_id = <0x20>;
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+#if !defined(__IPQ_MEM_PROFILE_256_MB__)
+		memory-region = <&mhi_region0>;
+#endif
+
+#if !defined(__CNSS2__)
+		base-addr = <0x51100000>;
+		m3-dump-addr = <0x53400000>;
+		etr-addr = <0x53500000>;
+		qcom,caldb-addr = <0x53600000>;
+		mhi,max-channels = <30>;
+		mhi,timeout = <10000>;
+		qcom,board_id= <0xa4>;
+
+		pcie0_mhi: pcie0_mhi {
+			status = "ok";
+		};
+#endif
+	};
+};
+
+&pcie1_rp {
+	status = "disabled";
+
+	mhi_1: qcom,mhi@1 {
+		pcie1_mhi: pcie1_mhi {
+			status = "disabled";
 		};
 	};
 };
@@ -704,15 +1011,12 @@
 };
 #endif
 
-&wifi0 {
-	status = "disabled";
-};
-
 &wifi1 {
 	qcom,board_id = <0x294>;
 	status = "ok";
 };
 
+/* No support for QCN9000 in 256M profile */
 #if !defined(__IPQ_MEM_PROFILE_256_MB__)
 &wifi2 {
 #ifdef __IPQ_MEM_PROFILE_512_MB__
@@ -727,15 +1031,12 @@
        * |   ETR   |  0x4FE00000  |   1MB   |
        * +---------+--------------+---------+
        * |  Caldb  |  0x4FF00000  |   8MB   |
-       * +---------+--------------+---------+
-       * | Pageable|  0x50700000  |   8MB   |
        * +==================================+
        */
 	base-addr = <0x4E900000>;
 	m3-dump-addr = <0x4FD00000>;
 	etr-addr = <0x4FE00000>;
 	caldb-addr = <0x4FF00000>;
-	pageable-addr = <0x50700000>;
 	hremote-size = <0x1400000>;
 	tgt-mem-mode = <0x1>;
 #else
@@ -745,66 +1046,32 @@
        * +---------+--------------+---------+
        * | HREMOTE |  0x51100000  |   35MB  |
        * +---------+--------------+---------+
-       * | M3 DUMP |  0x53400000  |   1MB   |
+       * | M3 Dump |  0x53400000  |   1MB   |
        * +---------+--------------+---------+
        * |   ETR   |  0x53500000  |   1MB   |
        * +---------+--------------+---------+
        * |  Caldb  |  0x53600000  |   8MB   |
-       * +---------+--------------+---------+
-       * | Pageable|  0x53E00000  |   8MB   |
        * +==================================+
        */
 	base-addr = <0x51100000>;
 	m3-dump-addr = <0x53400000>;
 	etr-addr = <0x53500000>;
 	caldb-addr = <0x53600000>;
-	pageable-addr = <0x53E00000>;
 	hremote-size = <0x2300000>;
 	tgt-mem-mode = <0x0>;
 #endif
 	caldb-size = <0x800000>;
-	hremote_node = <&qcn9000_pcie0>;
-	pageable-size = <0x800000>;
 	board_id = <0xa4>;
 	status = "ok";
-};
-#endif
-
-&wifi3 {
-	status = "disabled";
-};
-
-&pcie0_rp {
-	status = "ok";
-
-	mhi_0: qcom,mhi@0 {
-		reg = <0 0 0 0 0 >;
-		qrtr_instance_id = <0x20>;
-		#address-cells = <0x2>;
-		#size-cells = <0x2>;
 #if defined(__CNSS2__)
-#if !defined(__IPQ_MEM_PROFILE_256_MB__)
-		memory-region = <&mhi_region0>;
-#endif
-#else
-#ifdef __IPQ_MEM_PROFILE_512_MB__
-		base-addr = <0x4E900000>;
-		m3-dump-addr = <0x4FD00000>;
-		etr-addr = <0x4FE00000>;
-		qcom,caldb-addr = <0x4FF00000>;
-		pageable-addr = <0x50700000>;
-#else
-		base-addr = <0x51100000>;
-		m3-dump-addr = <0x53400000>;
-		etr-addr = <0x53500000>;
-		qcom,caldb-addr = <0x53600000>;
-		pageable-addr = <0x53E00000>;
-#endif
-		qcom,board_id= <0xa4>;
-
 	pcie0_mhi: pcie0_mhi {
 		status = "ok";
 	};
 #endif
-	};
 };
+&wifi3 {
+	status = "disabled";
+};
+
+#include "qcom-ipq807x-mhi.dtsi"
+#endif

feeds/ipq807x/ipq807x/image/ipq50xx.mk

@@ -18,6 +18,17 @@ define Device/edgecore_eap104
 endef
 TARGET_DEVICES += edgecore_eap104
 
+define Device/motorola_q14
+  DEVICE_TITLE := Motorola Q14
+  DEVICE_DTS := qcom-ipq5018-q14
+  SUPPORTED_DEVICES := motorola,q14
+  DEVICE_PACKAGES := ath11k-wifi-motorola-q14 ath11k-firmware-ipq50xx-spruce ath11k-firmware-qcn6122
+  DEVICE_DTS_CONFIG := config@mp03.5-c1
+  IMAGES := sysupgrade.tar mmc-factory.bin
+  IMAGE/mmc-factory.bin := append-ubi | qsdk-ipq-factory-mmc
+endef
+#TARGET_DEVICES += motorola_q14
+
 define Device/qcom_mp03_1
   DEVICE_TITLE := Qualcomm Maple 03.1
   DEVICE_DTS := qcom-ipq5018-mp03.1
@@ -25,7 +36,7 @@ define Device/qcom_mp03_1
   DEVICE_PACKAGES := ath11k-wifi-qcom-ipq5018
   DEVICE_DTS_CONFIG := config@mp03.1
 endef
-#TARGET_DEVICES += qcom_mp03_1
+TARGET_DEVICES += qcom_mp03_1
 
 define Device/qcom_mp03_3
   DEVICE_TITLE := Qualcomm Maple 03.3
@@ -34,4 +45,4 @@ define Device/qcom_mp03_3
   DEVICE_PACKAGES := ath11k-wifi-qcom-ipq5018
   DEVICE_DTS_CONFIG := config@mp03.3
 endef
-#TARGET_DEVICES += qcom_mp03_3
+TARGET_DEVICES += qcom_mp03_3

feeds/ipq807x/ipq807x/image/ipq60xx.mk

@@ -41,9 +41,9 @@ define Device/wallys_dr6018
   DEVICE_DTS := qcom-ipq6018-wallys-dr6018
   DEVICE_DTS_CONFIG := config@cp01-c4
   SUPPORTED_DEVICES := wallys,dr6018
-  DEVICE_PACKAGES := ath11k-wifi-wallys-dr6018 uboot-envtools
+  DEVICE_PACKAGES := ath11k-wifi-wallys-dr6018 uboot-envtools -kmod-usb-dwc3-of-simple kmod-usb-dwc3-qcom kmod-usb3 kmod-usb2
 endef
-#TARGET_DEVICES += wallys_dr6018
+TARGET_DEVICES += wallys_dr6018
 
 define Device/wallys_dr6018_v4
   DEVICE_TITLE := Wallys DR6018 V4
@@ -52,7 +52,15 @@ define Device/wallys_dr6018_v4
   SUPPORTED_DEVICES := wallys,dr6018-v4
   DEVICE_PACKAGES := ath11k-wifi-wallys-dr6018-v4 uboot-envtools
 endef
-#TARGET_DEVICES += wallys_dr6018_v4
+TARGET_DEVICES += wallys_dr6018_v4
+
+define Device/qcom_cp01_c1
+  DEVICE_TITLE := Qualcomm Cypress C1
+  DEVICE_DTS := qcom-ipq6018-cp01-c1
+  SUPPORTED_DEVICES := qcom,ipq6018-cp01
+  DEVICE_PACKAGES := ath11k-wifi-qcom-ipq6018
+endef
+TARGET_DEVICES += qcom_cp01_c1
 
 define Device/glinet_ax1800
   DEVICE_TITLE := GL-iNet AX1800
@@ -68,7 +76,7 @@ define Device/glinet_axt1800
   DEVICE_DTS := qcom-ipq6018-gl-axt1800
   SUPPORTED_DEVICES := glinet,axt1800
   DEVICE_DTS_CONFIG := config@cp03-c1
-  DEVICE_PACKAGES := ath11k-wifi-gl-ax1800 -kmod-usb-dwc3-of-simple kmod-usb-dwc3-qcom kmod-usb3
+  DEVICE_PACKAGES := ath11k-wifi-gl-axt1800 -kmod-usb-dwc3-of-simple kmod-usb-dwc3-qcom kmod-usb3
 endef
 TARGET_DEVICES += glinet_axt1800
 

feeds/ipq807x/ipq807x/image/ipq807x.mk

@@ -2,16 +2,16 @@ KERNEL_LOADADDR := 0x41208000
 
 define Device/qcom_hk01
   DEVICE_TITLE := Qualcomm Hawkeye HK01
-  DEVICE_DTS := ipq8074-hk01
+  DEVICE_DTS := qcom-ipq807x-hk01
   DEVICE_DTS_CONFIG=config@hk01
   SUPPORTED_DEVICES := qcom,ipq807x-hk01
   DEVICE_PACKAGES := ath11k-wifi-qcom-ipq8074
 endef
-#TARGET_DEVICES += qcom_hk01
+TARGET_DEVICES += qcom_hk01
 
 define Device/qcom_hk14
   DEVICE_TITLE := Qualcomm Hawkeye HK14
-  DEVICE_DTS := ipq8074-hk14
+  DEVICE_DTS := qcom-ipq807x-hk14
   DEVICE_DTS_CONFIG=config@hk14
   SUPPORTED_DEVICES := qcom,ipq807x-hk14
   DEVICE_PACKAGES := ath11k-wifi-qcom-ipq8074 kmod-ath11k-pci ath11k-firmware-qcn9000
@@ -41,6 +41,8 @@ define Device/cig_wf196
   DEVICE_DTS := qcom-ipq807x-wf196
   DEVICE_DTS_CONFIG=config@hk14
   SUPPORTED_DEVICES := cig,wf196
+  BLOCKSIZE := 256k
+  PAGESIZE := 4096
   DEVICE_PACKAGES := ath11k-wifi-cig-wf196 aq-fw-download uboot-envtools kmod-usb3 kmod-usb2 \
   	ath11k-firmware-qcn9000 ath11k-wifi-cig-wf196_6g
 endef

feeds/ipq807x/ipq807x/ipq50xx/config-default

@@ -0,0 +1,85 @@
+# CONFIG_AHCI_IPQ is not set
+CONFIG_ARCH_IPQ5018=y
+# CONFIG_DIAGFWD_BRIDGE_CODE is not set
+CONFIG_IPQ_ADSS_5018=y
+CONFIG_IPQ_APSS_5018=y
+CONFIG_IPQ_GCC_5018=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NUM_ALT_PARTITION=16
+CONFIG_PINCTRL_IPQ5018=y
+# CONFIG_IPC_LOGGING is not set
+CONFIG_IPQ_SUBSYSTEM_DUMP=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_CSR=y
+CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_EVENT=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_LINKS_AND_SINKS=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_QCOM_REPLICATOR=y
+# CONFIG_INPUT_PM8941_PWRKEY is not set
+CONFIG_MDIO_QCA=y
+# CONFIG_CRYPTO_ALL_CASES is not set
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CORESIGHT_QPDI is not set
+# CONFIG_CORESIGHT_SINK_ETBV10 is not set
+CONFIG_CORESIGHT_SINK_TPIU=y
+# CONFIG_CORESIGHT_SOURCE_DUMMY is not set
+CONFIG_CORESIGHT_SOURCE_ETM3X=y
+CONFIG_CORESIGHT_SOURCE_ETM4X=y
+# CONFIG_CORESIGHT_REMOTE_ETM is not set
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+# CONFIG_CORESIGHT_TPDM_DEFAULT_ENABLE is not set
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PHY_IPQ_UNIPHY_PCIE=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_PPS=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_DP83640_PHY is not set
+CONFIG_PWM_IPQ5018=y
+CONFIG_QCOM_APM=y
+CONFIG_QCOM_DCC=y
+# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
+CONFIG_MMC_SDHCI_MSM_ICE=y
+CONFIG_USB_BAM=y
+CONFIG_MAILBOX=y
+# CONFIG_USB_QCOM_DIAG_BRIDGE is not set
+# CONFIG_USB_CONFIGFS_F_DIAG is not set
+# CONFIG_NF_IPV6_DUMMY_HEADER is not set
+CONFIG_RMNET_DATA=y
+CONFIG_RMNET_DATA_DEBUG_PKT=y
+CONFIG_MTD_NAND_SERIAL=y
+CONFIG_PAGE_SCOPE_MULTI_PAGE_READ=y
+# CONFIG_RMNET_DATA_FC is not set
+CONFIG_CRYPTO_NO_ZERO_LEN_HASH=y
+CONFIG_CRYPTO_DISABLE_AES192_TEST=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_QTI_EUD=y
+CONFIG_USB_QCA_M31_PHY=y
+CONFIG_QGIC2_MSI=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_PWM_IPQ4019=y
+CONFIG_RMNET=y
+CONFIG_QCOM_QMI_RMNET=y
+CONFIG_QCOM_QMI_DFC=y
+CONFIG_QCOM_QMI_POWER_COLLAPSE=y
+CONFIG_RMNET_CTL=y
+CONFIG_RMNET_CTL_DEBUG=y
+CONFIG_SND_SOC_IPQ_LPASS=y
+CONFIG_SND_SOC_IPQ_LPASS_PCM_RAW=y
+# CONFIG_SND_SOC_IPQ_PCM_RAW is not set
+CONFIG_QCOM_RESTART_REASON=y

feeds/ipq807x/ipq807x/ipq50xx/config-lowmem

@@ -0,0 +1,73 @@
+# CONFIG_AHCI_IPQ is not set
+CONFIG_ARCH_IPQ5018=y
+# CONFIG_DIAGFWD_BRIDGE_CODE is not set
+CONFIG_IPQ_ADSS_5018=y
+CONFIG_IPQ_APSS_5018=y
+CONFIG_IPQ_GCC_5018=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NUM_ALT_PARTITION=16
+CONFIG_PINCTRL_IPQ5018=y
+# CONFIG_IPC_LOGGING is not set
+CONFIG_IPQ_SUBSYSTEM_DUMP=y
+# CONFIG_SPS is not set
+# CONFIG_SPS_SUPPORT_NDP_BAM is not set
+# CONFIG_CORESIGHT is not set
+# CONFIG_INPUT_PM8941_PWRKEY is not set
+CONFIG_MDIO_QCA=y
+# CONFIG_CRYPTO_ALL_CASES is not set
+# CONFIG_CRYPTO_DEV_QCOM_ICE is not set
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_IIO is not set
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_PCIE_DW_PLAT=y
+CONFIG_PHY_IPQ_UNIPHY_PCIE=y
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_3G is not set
+# CONFIG_PPS is not set
+# CONFIG_PTP_1588_CLOCK is not set
+# CONFIG_DP83640_PHY is not set
+CONFIG_PWM_IPQ5018=y
+CONFIG_QCOM_APM=y
+# CONFIG_QCOM_DCC is not set
+# CONFIG_QCOM_SPMI_TEMP_ALARM is not set
+CONFIG_MMC_SDHCI_MSM_ICE=y
+CONFIG_USB_BAM=y
+CONFIG_MAILBOX=y
+# CONFIG_USB_QCOM_DIAG_BRIDGE is not set
+# CONFIG_USB_CONFIGFS_F_DIAG is not set
+# CONFIG_NF_IPV6_DUMMY_HEADER is not set
+# CONFIG_RMNET_DATA is not set
+# CONFIG_RMNET_DATA_DEBUG_PKT is not set
+CONFIG_MTD_NAND_SERIAL=y
+CONFIG_PAGE_SCOPE_MULTI_PAGE_READ=y
+# CONFIG_RMNET_DATA_FC is not set
+# CONFIG_CRYPTO_NO_ZERO_LEN_HASH is not set
+# CONFIG_CRYPTO_DISABLE_AES192_TEST is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_QTI_EUD=y
+CONFIG_USB_QCA_M31_PHY=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_ZLIB is not set
+# CONFIG_JFFS2_LZMA is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_LZO_COMPRESS is not set
+# CONFIG_LZO_DECOMPRESS is not set
+CONFIG_XZ_DEC=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+CONFIG_XZ_DEC_ARM=y
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_LZO_COMPRESS is not set
+# CONFIG_LZO_DECOMPRESS is not set
+# CONFIG_CRYPTO is not set
+CONFIG_QGIC2_MSI=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y

feeds/ipq807x/ipq807x/ipq60xx/target.mk

@@ -1,8 +1,6 @@
 SUBTARGET:=ipq60xx
 BOARDNAME:=IPQ60xx based boards
 
-KERNEL_PATCHVER:=5.4
-
 DEFAULT_PACKAGES += ath11k-firmware-ipq60xx qca-nss-fw-ipq60xx
 
 define Target/Description

feeds/ipq807x/ipq807x/modules.mk

@@ -2,15 +2,12 @@ define KernelPackage/usb-phy-ipq807x
   TITLE:=DWC3 USB QCOM PHY driver for IPQ807x
   DEPENDS:=@TARGET_ipq807x
   KCONFIG:= \
-	CONFIG_PHY_QCOM_QUSB2 \
-	CONFIG_PHY_QCOM_QMP=y \
 	CONFIG_USB_QCOM_QUSB_PHY \
 	CONFIG_USB_QCOM_QMP_PHY
   FILES:= \
-	$(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-qusb2.ko@ge5.4 \
+	$(LINUX_DIR)/drivers/usb/phy/phy-msm-qusb.ko \
-	$(LINUX_DIR)/drivers/usb/phy/phy-msm-qusb.ko@le4.4 \
+	$(LINUX_DIR)/drivers/usb/phy/phy-msm-ssusb-qmp.ko
-	$(LINUX_DIR)/drivers/usb/phy/phy-msm-ssusb-qmp.ko@le4.4
+  AUTOLOAD:=$(call AutoLoad,45,phy-msm-qusb phy-msm-ssusb-qmp,1)
-  AUTOLOAD:=$(call AutoLoad,45,phy-qcom-qusb2 phy-msm-qusb phy-msm-ssusb-qmp,1)
   $(call AddDepends/usb)
 endef
 
@@ -22,45 +19,46 @@ endef
 $(eval $(call KernelPackage,usb-phy-ipq807x))
 
 
-define KernelPackage/usb-dwc3-internal
+define KernelPackage/qrtr_mproc
-  TITLE:=DWC3 USB controller driver
+  TITLE:= Ath11k Specific kernel configs for IPQ807x and IPQ60xx
-  DEPENDS:=+USB_GADGET_SUPPORT:kmod-usb-gadget +kmod-usb-core
+  DEPENDS+= @TARGET_ipq807x
   KCONFIG:= \
-        CONFIG_USB_DWC3 \
+          CONFIG_QRTR=y \
-        CONFIG_USB_DWC3_HOST=n \
+          CONFIG_QRTR_MHI=y \
-        CONFIG_USB_DWC3_GADGET=n \
+          CONFIG_MHI_BUS=y \
-        CONFIG_USB_DWC3_DUAL_ROLE=y \
+          CONFIG_MHI_QTI=y \
-        CONFIG_EXTCON=y \
+          CONFIG_QCOM_APCS_IPC=y \
-        CONFIG_USB_DWC3_DEBUG=n \
+          CONFIG_QCOM_GLINK_SSR=y \
-        CONFIG_USB_DWC3_VERBOSE=n
+          CONFIG_QCOM_Q6V5_WCSS=y \
-  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3.ko
+          CONFIG_MSM_RPM_RPMSG=y \
-  AUTOLOAD:=$(call AutoLoad,54,dwc3,1)
+          CONFIG_RPMSG_QCOM_GLINK_RPM=y \
-  $(call AddPlatformDepends/usb)
+          CONFIG_REGULATOR_RPM_GLINK=y \
+          CONFIG_QCOM_SYSMON=y \
+          CONFIG_RPMSG=y \
+          CONFIG_RPMSG_CHAR=y \
+          CONFIG_RPMSG_QCOM_GLINK_SMEM=y \
+          CONFIG_RPMSG_QCOM_SMD=y \
+          CONFIG_QRTR_SMD=y \
+          CONFIG_QCOM_QMI_HELPERS=y \
+          CONFIG_SAMPLES=y \
+          CONFIG_SAMPLE_QMI_CLIENT=m \
+          CONFIG_SAMPLE_TRACE_EVENTS=n \
+          CONFIG_SAMPLE_KOBJECT=n \
+          CONFIG_SAMPLE_KPROBES=n \
+          CONFIG_SAMPLE_KRETPROBES=n \
+          CONFIG_SAMPLE_HW_BREAKPOINT=n \
+          CONFIG_SAMPLE_KFIFO=n \
+          CONFIG_SAMPLE_CONFIGFS=n \
+          CONFIG_SAMPLE_RPMSG_CLIENT=n \
+          CONFIG_MAILBOX=y \
+          CONFIG_DIAG_OVER_QRTR=y
 endef
 
-define KernelPackage/usb-dwc3-internal/description
+define KernelPackage/qrtr_mproc/description
- This driver provides support for the Dual Role SuperSpeed
+Kernel configs for ath11k support specific to ipq807x and IPQ60xx
- USB Controller based on the Synopsys DesignWare USB3 IP Core
 endef
 
-$(eval $(call KernelPackage,usb-dwc3-internal))
+$(eval $(call KernelPackage,qrtr_mproc))
-
-define KernelPackage/usb-dwc3-qcom-internal
-  TITLE:=DWC3 QTI USB driver
-  DEPENDS:=@!LINUX_4_14 @(TARGET_ipq807x||TARGET_ipq60xx||TARGET_ipq95xx||TARGET_ipq50xx) +kmod-usb-dwc3-internal
-  KCONFIG:= CONFIG_USB_DWC3_QCOM
-  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-qcom.ko
-  AUTOLOAD:=$(call AutoLoad,53,dwc3-qcom,1)
-  $(call AddPlatformDepends/usb)
-endef
-
-define KernelPackage/usb-dwc3-qcom-internal/description
- Some QTI SoCs use DesignWare Core IP for USB2/3 functionality.
- This driver also handles Qscratch wrapper which is needed for
- peripheral mode support.
-endef
-
-$(eval $(call KernelPackage,usb-dwc3-qcom-internal))
 
 define KernelPackage/bt_tty
   TITLE:= BT Inter-processor Communication
@@ -86,7 +84,7 @@ define KernelPackage/usb-phy-ipq5018
         CONFIG_PHY_IPQ_UNIPHY_USB
   FILES:= \
         $(LINUX_DIR)/drivers/usb/phy/phy-qca-m31.ko \
-        $(LINUX_DIR)/drivers/phy/qualcomm/phy-qca-uniphy.ko
+        $(LINUX_DIR)/drivers/phy/phy-qca-uniphy.ko
   AUTOLOAD:=$(call AutoLoad,45,phy-qca-m31 phy-qca-uniphy,1)
   $(call AddDepends/usb)
 endef
@@ -98,30 +96,13 @@ endef
 
 $(eval $(call KernelPackage,usb-phy-ipq5018))
 
-define KernelPackage/usb-f-diag
-  TITLE:=USB DIAG
-  KCONFIG:=CONFIG_USB_F_DIAG \
-        CONFIG_USB_CONFIGFS_F_DIAG=y \
-        CONFIG_DIAG_OVER_USB=y
-  DEPENDS:=+kmod-usb-lib-composite +kmod-usb-configfs
-  FILES:=$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_diag.ko
-  AUTOLOAD:=$(call AutoLoad,52,usb_f_diag)
-  $(call AddPlatformDepends/usb)
-endef
-
-define KernelPackage/usb-f-diag/description
- USB DIAG
-endef
-
-$(eval $(call KernelPackage,usb-f-diag))
-
 define KernelPackage/diag-char
   TITLE:=CHAR DIAG
   KCONFIG:= CONFIG_DIAG_MHI=y@ge5.4 \
           CONFIG_DIAG_OVER_PCIE=n@ge5.4 \
           CONFIG_DIAGFWD_BRIDGE_CODE=y \
-          CONFIG_DIAG_CHAR
+          CONFIG_DIAG_CHAR=m
-  DEPENDS:=+kmod-lib-crc-ccitt +kmod-usb-f-diag
+  DEPENDS:=+kmod-lib-crc-ccitt
   FILES:=$(LINUX_DIR)/drivers/char/diag/diagchar.ko
 endef
 
@@ -131,34 +112,21 @@ endef
 
 $(eval $(call KernelPackage,diag-char))
 
-define KernelPackage/usb-configfs
+define KernelPackage/usb-dwc3-qcom
- TITLE:= USB functions
+  TITLE:=DWC3 Qualcomm USB driver
-  KCONFIG:=CONFIG_USB_CONFIGFS \
+  DEPENDS:=@(!LINUX_4_14) @TARGET_ipq807x +kmod-usb-dwc3
-        CONFIG_USB_CONFIGFS_SERIAL=n \
+  KCONFIG:= CONFIG_USB_DWC3_QCOM
-        CONFIG_USB_CONFIGFS_ACM=n \
+  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-qcom.ko \
-        CONFIG_USB_CONFIGFS_OBEX=n \
+        $(LINUX_DIR)/drivers/usb/dwc3/dbm.ko
-        CONFIG_USB_CONFIGFS_NCM=n \
+  AUTOLOAD:=$(call AutoLoad,53,dwc3-qcom dbm,1)
-        CONFIG_USB_CONFIGFS_ECM=n \
+  $(call AddDepends/usb)
-        CONFIG_USB_CONFIGFS_ECM_SUBSET=n \
-        CONFIG_USB_CONFIGFS_RNDIS=n \
-        CONFIG_USB_CONFIGFS_EEM=n \
-        CONFIG_USB_CONFIGFS_MASS_STORAGE=n \
-        CONFIG_USB_CONFIGFS_F_LB_SS=n \
-        CONFIG_USB_CONFIGFS_F_FS=n \
-        CONFIG_USB_CONFIGFS_F_UAC1=n \
-        CONFIG_USB_CONFIGFS_F_UAC2=n \
-        CONFIG_USB_CONFIGFS_F_MIDI=n \
-        CONFIG_USB_CONFIGFS_F_HID=n \
-        CONFIG_USB_CONFIGFS_F_PRINTER=n \
-        CONFIG_USB_CONFIGFS_F_QDSS=n
-  $(call AddPlatformDepends/usb)
 endef
 
-define KernelPackage/usb-configfs/description
+define KernelPackage/usb-dwc3-qcom/description
- USB functions
+ Some Qualcomm SoCs use DesignWare Core IP for USB2/3 functionality.
+ This driver also handles Qscratch wrapper which is needed for
+ peripheral mode support.
 endef
 
-$(eval $(call KernelPackage,usb-configfs))
-
-
 
+$(eval $(call KernelPackage,usb-dwc3-qcom))

feeds/ipq807x/ipq807x/patches/001-backport_kbuild_fix.patch

@@ -0,0 +1,25 @@
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -96,10 +96,10 @@ obj-dirs	:= $(addprefix $(obj)/,$(obj-di
+ # Note: Files that end up in two or more modules are compiled without the
+ #       KBUILD_MODNAME definition. The reason is that any made-up name would
+ #       differ in different configs.
+-name-fix = $(subst $(comma),_,$(subst -,_,$1))
+-basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))"
++name-fix = $(squote)$(quote)$(subst $(comma),_,$(subst -,_,$1))$(quote)$(squote)
++basename_flags = -DKBUILD_BASENAME=$(call name-fix,$(basetarget))
+ modname_flags  = $(if $(filter 1,$(words $(modname))),\
+-                 -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))")
++                 -DKBUILD_MODNAME=$(call name-fix,$(modname)))
+ 
+ orig_c_flags   = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \
+                  $(ccflags-y) $(CFLAGS_$(basetarget).o)
+@@ -155,7 +155,7 @@ endif
+ 
+ c_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE)     \
+ 		 $(__c_flags) $(modkern_cflags)                           \
+-		 -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags)
++		 $(basename_flags) $(modname_flags)
+ 
+ a_flags        = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE)     \
+ 		 $(__a_flags) $(modkern_aflags)

feeds/ipq807x/ipq807x/patches/100-dts.patch

@@ -1,26 +0,0 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -1587,7 +1587,7 @@
- 		};
- 
- 		wifi1: wifi1@c0000000 {
--			compatible = "qcom,cnss-qca8074v2", "qcom,ipq8074-wifi";
-+			compatible = "qcom,ipq8074-wifi";
- 			reg = <0xc000000 0x2000000>;
- 			qcom,hw-mode-id = <1>;
- 		#ifdef __IPQ_MEM_PROFILE_256_MB__
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -1561,7 +1561,7 @@
- 		};
- 
- 		wifi0: wifi@c000000 {
--			compatible = "qcom,cnss-qca6018", "qcom,ipq6018-wifi";
-+			compatible = "qcom,ipq6018-wifi";
- 			reg = <0xc000000 0x1000000>;
- 			qcom,hw-mode-id = <1>;
- #ifdef __IPQ_MEM_PROFILE_256_MB__

feeds/ipq807x/ipq807x/patches/100-qrtr-ns.patch

@@ -0,0 +1,976 @@
+Index: linux-4.4.60/net/qrtr/ns.c
+===================================================================
+--- /dev/null
++++ linux-4.4.60/net/qrtr/ns.c
+@@ -0,0 +1,760 @@
++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
++/*
++ * Copyright (c) 2015, Sony Mobile Communications Inc.
++ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
++ * Copyright (c) 2020, Linaro Ltd.
++ */
++
++#include <linux/module.h>
++#include <linux/qrtr.h>
++#include <linux/workqueue.h>
++#include <net/sock.h>
++
++#include "qrtr.h"
++
++#define CREATE_TRACE_POINTS
++#include <trace/events/qrtr.h>
++
++static RADIX_TREE(nodes, GFP_KERNEL);
++
++static struct {
++	struct socket *sock;
++	struct sockaddr_qrtr bcast_sq;
++	struct list_head lookups;
++	struct workqueue_struct *workqueue;
++	struct work_struct work;
++	int local_node;
++} qrtr_ns;
++
++static const char * const qrtr_ctrl_pkt_strings[] = {
++	[QRTR_TYPE_HELLO]	= "hello",
++	[QRTR_TYPE_BYE]		= "bye",
++	[QRTR_TYPE_NEW_SERVER]	= "new-server",
++	[QRTR_TYPE_DEL_SERVER]	= "del-server",
++	[QRTR_TYPE_DEL_CLIENT]	= "del-client",
++	[QRTR_TYPE_RESUME_TX]	= "resume-tx",
++	[QRTR_TYPE_EXIT]	= "exit",
++	[QRTR_TYPE_PING]	= "ping",
++	[QRTR_TYPE_NEW_LOOKUP]	= "new-lookup",
++	[QRTR_TYPE_DEL_LOOKUP]	= "del-lookup",
++};
++
++struct qrtr_server_filter {
++	unsigned int service;
++	unsigned int instance;
++	unsigned int ifilter;
++};
++
++struct qrtr_lookup {
++	unsigned int service;
++	unsigned int instance;
++
++	struct sockaddr_qrtr sq;
++	struct list_head li;
++};
++
++struct qrtr_server {
++	unsigned int service;
++	unsigned int instance;
++
++	unsigned int node;
++	unsigned int port;
++
++	struct list_head qli;
++};
++
++struct qrtr_node {
++	unsigned int id;
++	struct radix_tree_root servers;
++};
++
++static struct qrtr_node *node_get(unsigned int node_id)
++{
++	struct qrtr_node *node;
++
++	node = radix_tree_lookup(&nodes, node_id);
++	if (node)
++		return node;
++
++	/* If node didn't exist, allocate and insert it to the tree */
++	node = kzalloc(sizeof(*node), GFP_KERNEL);
++	if (!node)
++		return NULL;
++
++	node->id = node_id;
++
++	radix_tree_insert(&nodes, node_id, node);
++
++	return node;
++}
++
++static int server_match(const struct qrtr_server *srv,
++			const struct qrtr_server_filter *f)
++{
++	unsigned int ifilter = f->ifilter;
++
++	if (f->service != 0 && srv->service != f->service)
++		return 0;
++	if (!ifilter && f->instance)
++		ifilter = ~0;
++
++	return (srv->instance & ifilter) == f->instance;
++}
++
++static int service_announce_new(struct sockaddr_qrtr *dest,
++				struct qrtr_server *srv)
++{
++	struct qrtr_ctrl_pkt pkt;
++	struct msghdr msg = { };
++	struct kvec iv;
++
++	trace_qrtr_ns_service_announce_new(srv->service, srv->instance,
++					   srv->node, srv->port);
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = cpu_to_le32(QRTR_TYPE_NEW_SERVER);
++	pkt.server.service = cpu_to_le32(srv->service);
++	pkt.server.instance = cpu_to_le32(srv->instance);
++	pkt.server.node = cpu_to_le32(srv->node);
++	pkt.server.port = cpu_to_le32(srv->port);
++
++	msg.msg_name = (struct sockaddr *)dest;
++	msg.msg_namelen = sizeof(*dest);
++
++	return kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++}
++
++static int service_announce_del(struct sockaddr_qrtr *dest,
++				struct qrtr_server *srv)
++{
++	struct qrtr_ctrl_pkt pkt;
++	struct msghdr msg = { };
++	struct kvec iv;
++	int ret;
++
++	trace_qrtr_ns_service_announce_del(srv->service, srv->instance,
++					   srv->node, srv->port);
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_SERVER);
++	pkt.server.service = cpu_to_le32(srv->service);
++	pkt.server.instance = cpu_to_le32(srv->instance);
++	pkt.server.node = cpu_to_le32(srv->node);
++	pkt.server.port = cpu_to_le32(srv->port);
++
++	msg.msg_name = (struct sockaddr *)dest;
++	msg.msg_namelen = sizeof(*dest);
++
++	ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++	if (ret < 0)
++		pr_err("failed to announce del service\n");
++
++	return ret;
++}
++
++static void lookup_notify(struct sockaddr_qrtr *to, struct qrtr_server *srv,
++			  bool new)
++{
++	struct qrtr_ctrl_pkt pkt;
++	struct msghdr msg = { };
++	struct kvec iv;
++	int ret;
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = new ? cpu_to_le32(QRTR_TYPE_NEW_SERVER) :
++			cpu_to_le32(QRTR_TYPE_DEL_SERVER);
++	if (srv) {
++		pkt.server.service = cpu_to_le32(srv->service);
++		pkt.server.instance = cpu_to_le32(srv->instance);
++		pkt.server.node = cpu_to_le32(srv->node);
++		pkt.server.port = cpu_to_le32(srv->port);
++	}
++
++	msg.msg_name = (struct sockaddr *)to;
++	msg.msg_namelen = sizeof(*to);
++
++	ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++	if (ret < 0)
++		pr_err("failed to send lookup notification\n");
++}
++
++static int announce_servers(struct sockaddr_qrtr *sq)
++{
++	struct radix_tree_iter iter;
++	struct qrtr_server *srv;
++	struct qrtr_node *node;
++	void __rcu **slot;
++	int ret;
++
++	node = node_get(qrtr_ns.local_node);
++	if (!node)
++		return 0;
++
++	/* Announce the list of servers registered in this node */
++	radix_tree_for_each_slot(slot, &node->servers, &iter, 0) {
++		srv = radix_tree_deref_slot(slot);
++
++		ret = service_announce_new(sq, srv);
++		if (ret < 0) {
++			pr_err("failed to announce new service\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static struct qrtr_server *server_add(unsigned int service,
++				      unsigned int instance,
++				      unsigned int node_id,
++				      unsigned int port)
++{
++	struct qrtr_server *srv;
++	struct qrtr_server *old;
++	struct qrtr_node *node;
++
++	if (!service || !port)
++		return NULL;
++
++	srv = kzalloc(sizeof(*srv), GFP_KERNEL);
++	if (!srv)
++		return NULL;
++
++	srv->service = service;
++	srv->instance = instance;
++	srv->node = node_id;
++	srv->port = port;
++
++	node = node_get(node_id);
++	if (!node)
++		goto err;
++
++	/* Delete the old server on the same port */
++	old = radix_tree_lookup(&node->servers, port);
++	if (old) {
++		radix_tree_delete(&node->servers, port);
++		kfree(old);
++	}
++
++	radix_tree_insert(&node->servers, port, srv);
++
++	trace_qrtr_ns_server_add(srv->service, srv->instance,
++				 srv->node, srv->port);
++
++	return srv;
++
++err:
++	kfree(srv);
++	return NULL;
++}
++
++static int server_del(struct qrtr_node *node, unsigned int port)
++{
++	struct qrtr_lookup *lookup;
++	struct qrtr_server *srv;
++	struct list_head *li;
++
++	srv = radix_tree_lookup(&node->servers, port);
++	if (!srv)
++		return -ENOENT;
++
++	radix_tree_delete(&node->servers, port);
++
++	/* Broadcast the removal of local servers */
++	if (srv->node == qrtr_ns.local_node)
++		service_announce_del(&qrtr_ns.bcast_sq, srv);
++
++	/* Announce the service's disappearance to observers */
++	list_for_each(li, &qrtr_ns.lookups) {
++		lookup = container_of(li, struct qrtr_lookup, li);
++		if (lookup->service && lookup->service != srv->service)
++			continue;
++		if (lookup->instance && lookup->instance != srv->instance)
++			continue;
++
++		lookup_notify(&lookup->sq, srv, false);
++	}
++
++	kfree(srv);
++
++	return 0;
++}
++
++static int say_hello(struct sockaddr_qrtr *dest)
++{
++	struct qrtr_ctrl_pkt pkt;
++	struct msghdr msg = { };
++	struct kvec iv;
++	int ret;
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = cpu_to_le32(QRTR_TYPE_HELLO);
++
++	msg.msg_name = (struct sockaddr *)dest;
++	msg.msg_namelen = sizeof(*dest);
++
++	ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++	if (ret < 0)
++		pr_err("failed to send hello msg\n");
++
++	return ret;
++}
++
++/* Announce the list of servers registered on the local node */
++static int ctrl_cmd_hello(struct sockaddr_qrtr *sq)
++{
++	int ret;
++
++	ret = say_hello(sq);
++	if (ret < 0)
++		return ret;
++
++	return announce_servers(sq);
++}
++
++static int ctrl_cmd_bye(struct sockaddr_qrtr *from)
++{
++	struct qrtr_node *local_node;
++	struct radix_tree_iter iter;
++	struct qrtr_ctrl_pkt pkt;
++	struct qrtr_server *srv;
++	struct sockaddr_qrtr sq;
++	struct msghdr msg = { };
++	struct qrtr_node *node;
++	void __rcu **slot;
++	struct kvec iv;
++	int ret;
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	node = node_get(from->sq_node);
++	if (!node)
++		return 0;
++
++	/* Advertise removal of this client to all servers of remote node */
++	radix_tree_for_each_slot(slot, &node->servers, &iter, 0) {
++		srv = radix_tree_deref_slot(slot);
++		server_del(node, srv->port);
++	}
++
++	/* Advertise the removal of this client to all local servers */
++	local_node = node_get(qrtr_ns.local_node);
++	if (!local_node)
++		return 0;
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = cpu_to_le32(QRTR_TYPE_BYE);
++	pkt.client.node = cpu_to_le32(from->sq_node);
++
++	radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) {
++		srv = radix_tree_deref_slot(slot);
++
++		sq.sq_family = AF_QIPCRTR;
++		sq.sq_node = srv->node;
++		sq.sq_port = srv->port;
++
++		msg.msg_name = (struct sockaddr *)&sq;
++		msg.msg_namelen = sizeof(sq);
++
++		ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++		if (ret < 0) {
++			pr_err("failed to send bye cmd\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int ctrl_cmd_del_client(struct sockaddr_qrtr *from,
++			       unsigned int node_id, unsigned int port)
++{
++	struct qrtr_node *local_node;
++	struct radix_tree_iter iter;
++	struct qrtr_lookup *lookup;
++	struct qrtr_ctrl_pkt pkt;
++	struct msghdr msg = { };
++	struct qrtr_server *srv;
++	struct sockaddr_qrtr sq;
++	struct qrtr_node *node;
++	struct list_head *tmp;
++	struct list_head *li;
++	void __rcu **slot;
++	struct kvec iv;
++	int ret;
++
++	iv.iov_base = &pkt;
++	iv.iov_len = sizeof(pkt);
++
++	/* Don't accept spoofed messages */
++	if (from->sq_node != node_id)
++		return -EINVAL;
++
++	/* Local DEL_CLIENT messages comes from the port being closed */
++	if (from->sq_node == qrtr_ns.local_node && from->sq_port != port)
++		return -EINVAL;
++
++	/* Remove any lookups by this client */
++	list_for_each_safe(li, tmp, &qrtr_ns.lookups) {
++		lookup = container_of(li, struct qrtr_lookup, li);
++		if (lookup->sq.sq_node != node_id)
++			continue;
++		if (lookup->sq.sq_port != port)
++			continue;
++
++		list_del(&lookup->li);
++		kfree(lookup);
++	}
++
++	/* Remove the server belonging to this port */
++	node = node_get(node_id);
++	if (node)
++		server_del(node, port);
++
++	/* Advertise the removal of this client to all local servers */
++	local_node = node_get(qrtr_ns.local_node);
++	if (!local_node)
++		return 0;
++
++	memset(&pkt, 0, sizeof(pkt));
++	pkt.cmd = cpu_to_le32(QRTR_TYPE_DEL_CLIENT);
++	pkt.client.node = cpu_to_le32(node_id);
++	pkt.client.port = cpu_to_le32(port);
++
++	radix_tree_for_each_slot(slot, &local_node->servers, &iter, 0) {
++		srv = radix_tree_deref_slot(slot);
++
++		sq.sq_family = AF_QIPCRTR;
++		sq.sq_node = srv->node;
++		sq.sq_port = srv->port;
++
++		msg.msg_name = (struct sockaddr *)&sq;
++		msg.msg_namelen = sizeof(sq);
++
++		ret = kernel_sendmsg(qrtr_ns.sock, &msg, &iv, 1, sizeof(pkt));
++		if (ret < 0) {
++			pr_err("failed to send del client cmd\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int ctrl_cmd_new_server(struct sockaddr_qrtr *from,
++			       unsigned int service, unsigned int instance,
++			       unsigned int node_id, unsigned int port)
++{
++	struct qrtr_lookup *lookup;
++	struct qrtr_server *srv;
++	struct list_head *li;
++	int ret = 0;
++
++	/* Ignore specified node and port for local servers */
++	if (from->sq_node == qrtr_ns.local_node) {
++		node_id = from->sq_node;
++		port = from->sq_port;
++	}
++
++	/* Don't accept spoofed messages */
++	if (from->sq_node != node_id)
++		return -EINVAL;
++
++	srv = server_add(service, instance, node_id, port);
++	if (!srv)
++		return -EINVAL;
++
++	if (srv->node == qrtr_ns.local_node) {
++		ret = service_announce_new(&qrtr_ns.bcast_sq, srv);
++		if (ret < 0) {
++			pr_err("failed to announce new service\n");
++			return ret;
++		}
++	}
++
++	/* Notify any potential lookups about the new server */
++	list_for_each(li, &qrtr_ns.lookups) {
++		lookup = container_of(li, struct qrtr_lookup, li);
++		if (lookup->service && lookup->service != service)
++			continue;
++		if (lookup->instance && lookup->instance != instance)
++			continue;
++
++		lookup_notify(&lookup->sq, srv, true);
++	}
++
++	return ret;
++}
++
++static int ctrl_cmd_del_server(struct sockaddr_qrtr *from,
++			       unsigned int service, unsigned int instance,
++			       unsigned int node_id, unsigned int port)
++{
++	struct qrtr_node *node;
++
++	/* Ignore specified node and port for local servers*/
++	if (from->sq_node == qrtr_ns.local_node) {
++		node_id = from->sq_node;
++		port = from->sq_port;
++	}
++
++	/* Don't accept spoofed messages */
++	if (from->sq_node != node_id)
++		return -EINVAL;
++
++	/* Local servers may only unregister themselves */
++	if (from->sq_node == qrtr_ns.local_node && from->sq_port != port)
++		return -EINVAL;
++
++	node = node_get(node_id);
++	if (!node)
++		return -ENOENT;
++
++	return server_del(node, port);
++}
++
++static int ctrl_cmd_new_lookup(struct sockaddr_qrtr *from,
++			       unsigned int service, unsigned int instance)
++{
++	struct radix_tree_iter node_iter;
++	struct qrtr_server_filter filter;
++	struct radix_tree_iter srv_iter;
++	struct qrtr_lookup *lookup;
++	struct qrtr_node *node;
++	void __rcu **node_slot;
++	void __rcu **srv_slot;
++
++	/* Accept only local observers */
++	if (from->sq_node != qrtr_ns.local_node)
++		return -EINVAL;
++
++	lookup = kzalloc(sizeof(*lookup), GFP_KERNEL);
++	if (!lookup)
++		return -ENOMEM;
++
++	lookup->sq = *from;
++	lookup->service = service;
++	lookup->instance = instance;
++	list_add_tail(&lookup->li, &qrtr_ns.lookups);
++
++	memset(&filter, 0, sizeof(filter));
++	filter.service = service;
++	filter.instance = instance;
++
++	radix_tree_for_each_slot(node_slot, &nodes, &node_iter, 0) {
++		node = radix_tree_deref_slot(node_slot);
++
++		radix_tree_for_each_slot(srv_slot, &node->servers,
++					 &srv_iter, 0) {
++			struct qrtr_server *srv;
++
++			srv = radix_tree_deref_slot(srv_slot);
++			if (!server_match(srv, &filter))
++				continue;
++
++			lookup_notify(from, srv, true);
++		}
++	}
++
++	/* Empty notification, to indicate end of listing */
++	lookup_notify(from, NULL, true);
++
++	return 0;
++}
++
++static void ctrl_cmd_del_lookup(struct sockaddr_qrtr *from,
++				unsigned int service, unsigned int instance)
++{
++	struct qrtr_lookup *lookup;
++	struct list_head *tmp;
++	struct list_head *li;
++
++	list_for_each_safe(li, tmp, &qrtr_ns.lookups) {
++		lookup = container_of(li, struct qrtr_lookup, li);
++		if (lookup->sq.sq_node != from->sq_node)
++			continue;
++		if (lookup->sq.sq_port != from->sq_port)
++			continue;
++		if (lookup->service != service)
++			continue;
++		if (lookup->instance && lookup->instance != instance)
++			continue;
++
++		list_del(&lookup->li);
++		kfree(lookup);
++	}
++}
++
++static void qrtr_ns_worker(struct work_struct *work)
++{
++	const struct qrtr_ctrl_pkt *pkt;
++	size_t recv_buf_size = 4096;
++	struct sockaddr_qrtr sq;
++	struct msghdr msg = { };
++	unsigned int cmd;
++	ssize_t msglen;
++	void *recv_buf;
++	struct kvec iv;
++	int ret;
++
++	msg.msg_name = (struct sockaddr *)&sq;
++	msg.msg_namelen = sizeof(sq);
++
++	recv_buf = kzalloc(recv_buf_size, GFP_KERNEL);
++	if (!recv_buf)
++		return;
++
++	for (;;) {
++		iv.iov_base = recv_buf;
++		iv.iov_len = recv_buf_size;
++
++		msglen = kernel_recvmsg(qrtr_ns.sock, &msg, &iv, 1,
++					iv.iov_len, MSG_DONTWAIT);
++
++		if (msglen == -EAGAIN)
++			break;
++
++		if (msglen < 0) {
++			pr_err("error receiving packet: %zd\n", msglen);
++			break;
++		}
++
++		pkt = recv_buf;
++		cmd = le32_to_cpu(pkt->cmd);
++		if (cmd < ARRAY_SIZE(qrtr_ctrl_pkt_strings) &&
++		    qrtr_ctrl_pkt_strings[cmd])
++			trace_qrtr_ns_message(qrtr_ctrl_pkt_strings[cmd],
++					      sq.sq_node, sq.sq_port);
++
++		ret = 0;
++		switch (cmd) {
++		case QRTR_TYPE_HELLO:
++			ret = ctrl_cmd_hello(&sq);
++			break;
++		case QRTR_TYPE_BYE:
++			ret = ctrl_cmd_bye(&sq);
++			break;
++		case QRTR_TYPE_DEL_CLIENT:
++			ret = ctrl_cmd_del_client(&sq,
++					le32_to_cpu(pkt->client.node),
++					le32_to_cpu(pkt->client.port));
++			break;
++		case QRTR_TYPE_NEW_SERVER:
++			ret = ctrl_cmd_new_server(&sq,
++					le32_to_cpu(pkt->server.service),
++					le32_to_cpu(pkt->server.instance),
++					le32_to_cpu(pkt->server.node),
++					le32_to_cpu(pkt->server.port));
++			break;
++		case QRTR_TYPE_DEL_SERVER:
++			ret = ctrl_cmd_del_server(&sq,
++					 le32_to_cpu(pkt->server.service),
++					 le32_to_cpu(pkt->server.instance),
++					 le32_to_cpu(pkt->server.node),
++					 le32_to_cpu(pkt->server.port));
++			break;
++		case QRTR_TYPE_EXIT:
++		case QRTR_TYPE_PING:
++		case QRTR_TYPE_RESUME_TX:
++			break;
++		case QRTR_TYPE_NEW_LOOKUP:
++			ret = ctrl_cmd_new_lookup(&sq,
++					 le32_to_cpu(pkt->server.service),
++					 le32_to_cpu(pkt->server.instance));
++			break;
++		case QRTR_TYPE_DEL_LOOKUP:
++			ctrl_cmd_del_lookup(&sq,
++				    le32_to_cpu(pkt->server.service),
++				    le32_to_cpu(pkt->server.instance));
++			break;
++		}
++
++		if (ret < 0)
++			pr_err("failed while handling packet from %d:%d",
++			       sq.sq_node, sq.sq_port);
++	}
++
++	kfree(recv_buf);
++}
++
++static void qrtr_ns_data_ready(struct sock *sk)
++{
++	queue_work(qrtr_ns.workqueue, &qrtr_ns.work);
++}
++
++void qrtr_ns_init(void)
++{
++	struct sockaddr_qrtr sq;
++	int sl = sizeof(sq);
++	int ret;
++
++	INIT_LIST_HEAD(&qrtr_ns.lookups);
++	INIT_WORK(&qrtr_ns.work, qrtr_ns_worker);
++
++	ret = sock_create_kern(&init_net, AF_QIPCRTR, SOCK_DGRAM,
++			       PF_QIPCRTR, &qrtr_ns.sock);
++	if (ret < 0)
++		return;
++
++	ret = kernel_getsockname(qrtr_ns.sock, (struct sockaddr *)&sq, &sl);
++	if (ret < 0) {
++		pr_err("failed to get socket name\n");
++		goto err_sock;
++	}
++
++	qrtr_ns.workqueue = alloc_workqueue("qrtr_ns_handler", WQ_UNBOUND, 1);
++	if (!qrtr_ns.workqueue)
++		goto err_sock;
++
++	qrtr_ns.sock->sk->sk_data_ready = qrtr_ns_data_ready;
++
++	sq.sq_port = QRTR_PORT_CTRL;
++	qrtr_ns.local_node = sq.sq_node;
++
++	ret = kernel_bind(qrtr_ns.sock, (struct sockaddr *)&sq, sizeof(sq));
++	if (ret < 0) {
++		pr_err("failed to bind to socket\n");
++		goto err_wq;
++	}
++
++	qrtr_ns.bcast_sq.sq_family = AF_QIPCRTR;
++	qrtr_ns.bcast_sq.sq_node = QRTR_NODE_BCAST;
++	qrtr_ns.bcast_sq.sq_port = QRTR_PORT_CTRL;
++
++	ret = say_hello(&qrtr_ns.bcast_sq);
++	if (ret < 0)
++		goto err_wq;
++
++	return;
++
++err_wq:
++	destroy_workqueue(qrtr_ns.workqueue);
++err_sock:
++	sock_release(qrtr_ns.sock);
++}
++EXPORT_SYMBOL_GPL(qrtr_ns_init);
++
++void qrtr_ns_remove(void)
++{
++	cancel_work_sync(&qrtr_ns.work);
++	destroy_workqueue(qrtr_ns.workqueue);
++	sock_release(qrtr_ns.sock);
++}
++EXPORT_SYMBOL_GPL(qrtr_ns_remove);
++
++MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
++MODULE_DESCRIPTION("Qualcomm IPC Router Nameservice");
++MODULE_LICENSE("Dual BSD/GPL");
+Index: linux-4.4.60/net/qrtr/qrtr.c
+===================================================================
+--- linux-4.4.60.orig/net/qrtr/qrtr.c
++++ linux-4.4.60/net/qrtr/qrtr.c
+@@ -135,6 +135,8 @@ static DEFINE_IDR(qrtr_ports);
+ static DEFINE_MUTEX(qrtr_port_lock);
+ static DEFINE_MUTEX(qrtr_node_locking);
+ 
++static struct delayed_work qrtr_ns_work;
++
+ /**
+  * struct qrtr_node - endpoint node
+  * @ep_lock: lock for endpoint management and callbacks
+@@ -1765,33 +1767,6 @@ static int qrtr_create(struct net *net,
+ 	return 0;
+ }
+ 
+-static const struct nla_policy qrtr_policy[IFA_MAX + 1] = {
+-	[IFA_LOCAL] = { .type = NLA_U32 },
+-};
+-
+-static int qrtr_addr_doit(struct sk_buff *skb, struct nlmsghdr *nlh)
+-{
+-	struct nlattr *tb[IFA_MAX + 1];
+-	struct ifaddrmsg *ifm;
+-	int rc;
+-
+-	if (!netlink_capable(skb, CAP_NET_ADMIN))
+-		return -EPERM;
+-
+-	ASSERT_RTNL();
+-
+-	rc = nlmsg_parse(nlh, sizeof(*ifm), tb, IFA_MAX, qrtr_policy);
+-	if (rc < 0)
+-		return rc;
+-
+-	ifm = nlmsg_data(nlh);
+-	if (!tb[IFA_LOCAL])
+-		return -EINVAL;
+-
+-	qrtr_local_nid = nla_get_u32(tb[IFA_LOCAL]);
+-	return 0;
+-}
+-
+ static const struct net_proto_family qrtr_family = {
+ 	.owner	= THIS_MODULE,
+ 	.family	= AF_QIPCRTR,
+@@ -1811,7 +1786,8 @@ static int __init qrtr_proto_init(void)
+ 		proto_unregister(&qrtr_proto);
+ 		return rc;
+ 	}
+-	rtnl_register(PF_QIPCRTR, RTM_NEWADDR, qrtr_addr_doit, NULL, NULL);
++
++	qrtr_ns_init();
+ 
+ 	return 0;
+ }
+@@ -1819,7 +1795,8 @@ postcore_initcall(qrtr_proto_init);
+ 
+ static void __exit qrtr_proto_fini(void)
+ {
+-	rtnl_unregister(PF_QIPCRTR, RTM_NEWADDR);
++	cancel_delayed_work_sync(&qrtr_ns_work);
++	qrtr_ns_remove();
+ 	sock_unregister(qrtr_family.family);
+ 	proto_unregister(&qrtr_proto);
+ }
+Index: linux-4.4.60/net/qrtr/qrtr.h
+===================================================================
+--- linux-4.4.60.orig/net/qrtr/qrtr.h
++++ linux-4.4.60/net/qrtr/qrtr.h
+@@ -33,4 +33,9 @@ void qrtr_endpoint_unregister(struct qrt
+ int qrtr_endpoint_post(struct qrtr_endpoint *ep, const void *data, size_t len);
+ 
+ int qrtr_peek_pkt_size(const void *data);
++
++void qrtr_ns_init(void);
++
++void qrtr_ns_remove(void);
++
+ #endif
+Index: linux-4.4.60/net/qrtr/Makefile
+===================================================================
+--- linux-4.4.60.orig/net/qrtr/Makefile
++++ linux-4.4.60/net/qrtr/Makefile
+@@ -1,4 +1,4 @@
+-obj-$(CONFIG_QRTR) := qrtr.o
++obj-$(CONFIG_QRTR) := qrtr.o ns.o
+ 
+ obj-$(CONFIG_QRTR_SMD) += qrtr-smd.o
+ qrtr-smd-y	:= smd.o
+Index: linux-4.4.60/include/trace/events/qrtr.h
+===================================================================
+--- /dev/null
++++ linux-4.4.60/include/trace/events/qrtr.h
+@@ -0,0 +1,115 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM qrtr
++
++#if !defined(_TRACE_QRTR_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_QRTR_H
++
++#include <linux/qrtr.h>
++#include <linux/tracepoint.h>
++
++TRACE_EVENT(qrtr_ns_service_announce_new,
++
++	TP_PROTO(__le32 service, __le32 instance, __le32 node, __le32 port),
++
++	TP_ARGS(service, instance, node, port),
++
++	TP_STRUCT__entry(
++		__field(__le32, service)
++		__field(__le32, instance)
++		__field(__le32, node)
++		__field(__le32, port)
++	),
++
++	TP_fast_assign(
++		__entry->service = service;
++		__entry->instance = instance;
++		__entry->node = node;
++		__entry->port = port;
++	),
++
++	TP_printk("advertising new server [%d:%x]@[%d:%d]",
++		  __entry->service, __entry->instance, __entry->node,
++		  __entry->port
++	)
++);
++
++TRACE_EVENT(qrtr_ns_service_announce_del,
++
++	TP_PROTO(__le32 service, __le32 instance, __le32 node, __le32 port),
++
++	TP_ARGS(service, instance, node, port),
++
++	TP_STRUCT__entry(
++		__field(__le32, service)
++		__field(__le32, instance)
++		__field(__le32, node)
++		__field(__le32, port)
++	),
++
++	TP_fast_assign(
++		__entry->service = service;
++		__entry->instance = instance;
++		__entry->node = node;
++		__entry->port = port;
++	),
++
++	TP_printk("advertising removal of server [%d:%x]@[%d:%d]",
++		  __entry->service, __entry->instance, __entry->node,
++		  __entry->port
++	)
++);
++
++TRACE_EVENT(qrtr_ns_server_add,
++
++	TP_PROTO(__le32 service, __le32 instance, __le32 node, __le32 port),
++
++	TP_ARGS(service, instance, node, port),
++
++	TP_STRUCT__entry(
++		__field(__le32, service)
++		__field(__le32, instance)
++		__field(__le32, node)
++		__field(__le32, port)
++	),
++
++	TP_fast_assign(
++		__entry->service = service;
++		__entry->instance = instance;
++		__entry->node = node;
++		__entry->port = port;
++	),
++
++	TP_printk("add server [%d:%x]@[%d:%d]",
++		  __entry->service, __entry->instance, __entry->node,
++		  __entry->port
++	)
++);
++
++TRACE_EVENT(qrtr_ns_message,
++
++	TP_PROTO(const char * const ctrl_pkt_str, __u32 sq_node, __u32 sq_port),
++
++	TP_ARGS(ctrl_pkt_str, sq_node, sq_port),
++
++	TP_STRUCT__entry(
++		__string(ctrl_pkt_str, ctrl_pkt_str)
++		__field(__u32, sq_node)
++		__field(__u32, sq_port)
++	),
++
++	TP_fast_assign(
++		__assign_str(ctrl_pkt_str, ctrl_pkt_str);
++		__entry->sq_node = sq_node;
++		__entry->sq_port = sq_port;
++	),
++
++	TP_printk("%s from %d:%d",
++		  __get_str(ctrl_pkt_str), __entry->sq_node, __entry->sq_port
++	)
++);
++
++#endif /* _TRACE_QRTR_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>

feeds/ipq807x/ipq807x/patches/101-aq_phy.patch

@@ -1,78 +0,0 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/net/phy/aquantia_main.c
-===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/drivers/net/phy/aquantia_main.c
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/net/phy/aquantia_main.c
-@@ -25,9 +25,11 @@
- #define PHY_ID_AQR109	0x03a1b502
- #define PHY_ID_AQR111	0x03a1b610
- #define PHY_ID_AQR111B0	0x03a1b612
-+#define PHY_ID_AQR111C 0x03a1b7e2
- #define PHY_ID_AQR112	0x03a1b660
- #define PHY_ID_AQR112C	0x03a1b792
- #define PHY_ID_AQR113C	0x31c31C10
-+#define PHY_ID_AQR114C	0x31c31C22
- #define PHY_ID_AQCS109	0x03a1b5c2
- #define PHY_ID_AQR405	0x03a1b4b0
- 
-@@ -1011,6 +1013,24 @@ static struct phy_driver aqr_driver[] =
- 	.link_change_notify = aqr107_link_change_notify,
- },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR111C),
-+	.name		= "Aquantia AQR111C",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr107_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.ack_interrupt	= aqr_ack_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
- 	.name		= "Aquantia AQR112",
- 	.probe		= aqr107_probe,
-@@ -1065,6 +1085,24 @@ static struct phy_driver aqr_driver[] =
- 	.link_change_notify = aqr107_link_change_notify,
- },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
-+	.name		= "Aquantia AQR114C",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr107_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.ack_interrupt	= aqr_ack_interrupt,
-+	.read_status	= aqr107_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
- 	.name		= "Aquantia AQCS109",
- 	.probe		= aqr107_probe,
-@@ -1104,9 +1142,11 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR109) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
- 	{ }

feeds/ipq807x/ipq807x/patches/101-squashfs.patch

@@ -0,0 +1,16 @@
+Index: linux-4.4.60/fs/squashfs/xz_wrapper.c
+===================================================================
+--- linux-4.4.60.orig/fs/squashfs/xz_wrapper.c
++++ linux-4.4.60/fs/squashfs/xz_wrapper.c
+@@ -40,10 +40,8 @@ struct squashfs_xz {
+ };
+ 
+ struct disk_comp_opts {
+-	__le32 flags;
+-	__le16 bit_opts;
+-	__le16 fb;
+ 	__le32 dictionary_size;
++	__le32 flags;
+ };
+ 
+ struct comp_opts {

feeds/ipq807x/ipq807x/patches/102-aq-phy.patch

@@ -0,0 +1,90 @@
+Index: linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/drivers/net/phy/aquantia.c
+===================================================================
+--- linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1.orig/drivers/net/phy/aquantia.c
++++ linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/drivers/net/phy/aquantia.c
+@@ -32,6 +32,7 @@
+ #define PHY_ID_AQR112	0x03a1b660
+ #define PHY_ID_AQR113C	0x31c31C10
+ #define PHY_ID_AQR112C	0x03a1b792
++#define PHY_ID_AQR114C	0x31c31C22
+ 
+ #define AQ_PHY_MAX_VALID_MMD_REG		0xff01
+ #define AQ_PHY_MAX_INVALID_MMD_REG		0xffff
+@@ -756,6 +757,25 @@ static struct phy_driver aquantia_driver
+ 	.update_link	= aquantia_update_link,
+ 	.driver		= { .owner = THIS_MODULE,},
+ },
++{
++	.phy_id		= PHY_ID_AQR114C,
++	.phy_id_mask	= 0xfffffff0,
++	.name		= "Aquantia AQR114C",
++	.features	= PHY_AQUANTIA_FEATURES,
++	.flags		= PHY_HAS_INTERRUPT,
++	.probe		= aquantia_phy_probe,
++	.soft_reset	= aquantia_soft_reset,
++	.config_init	= aquantia_config_init,
++	.aneg_done	= aquantia_aneg_done,
++	.config_aneg	= aquantia_config_aneg,
++	.config_intr	= aquantia_config_intr,
++	.ack_interrupt	= aquantia_ack_interrupt,
++	.read_status	= aquantia_read_status,
++	.suspend	= aquantia_suspend,
++	.resume		= aquantia_resume,
++	.update_link	= aquantia_update_link,
++	.driver		= { .owner = THIS_MODULE,},
++},
+ };
+ 
+ module_phy_driver(aquantia_driver);
+@@ -773,6 +793,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_AQR112, 0xfffffff0 },
+ 	{ PHY_ID_AQR113C, 0xfffffff0 },
+ 	{ PHY_ID_AQR112C, 0xfffffff0 },
++	{ PHY_ID_AQR114C, 0xfffffff0 },
+ 	{ }
+ };
+ 
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/net/phy/aquantia.c
+===================================================================
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/drivers/net/phy/aquantia.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/net/phy/aquantia.c
+@@ -29,6 +29,7 @@
+ #define PHY_ID_AQR109	0x03a1b502
+ #define PHY_ID_AQR111	0x03a1b610
+ #define PHY_ID_AQR111B0	0x03a1b612
++#define PHY_ID_AQR111C	0x03a1b7e2
+ #define PHY_ID_AQR112	0x03a1b660
+ #define PHY_ID_AQR113C	0x31c31C10
+ #define PHY_ID_AQR112C	0x03a1b792
+@@ -701,6 +702,23 @@ static struct phy_driver aquantia_driver
+ 	.driver         = { .owner = THIS_MODULE,},
+ },
+ {
++	.phy_id         = PHY_ID_AQR111C,
++	.phy_id_mask    = 0xfffffff0,
++	.name           = "Aquantia AQR111C",
++	.features       = PHY_AQUANTIA_FEATURES,
++	.flags          = PHY_HAS_INTERRUPT,
++	.probe          = aquantia_phy_probe,
++	.soft_reset     = aquantia_soft_reset,
++	.config_init    = aquantia_config_init,
++	.aneg_done      = aquantia_aneg_done,
++	.config_aneg    = aquantia_config_aneg,
++	.config_intr    = aquantia_config_intr,
++	.ack_interrupt  = aquantia_ack_interrupt,
++	.read_status    = aquantia_read_status,
++	.update_link    = aquantia_update_link,
++	.driver         = { .owner = THIS_MODULE,},
++},
++{
+ 	.phy_id		= PHY_ID_AQR112,
+ 	.phy_id_mask	= 0xfffffff0,
+ 	.name		= "Aquantia AQR112",
+@@ -790,6 +808,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_AQR109, 0xfffffff0 },
+ 	{ PHY_ID_AQR111, 0xfffffff0 },
+ 	{ PHY_ID_AQR111B0, 0xfffffff0 },
++	{ PHY_ID_AQR111C, 0xfffffff0 },
+ 	{ PHY_ID_AQR112, 0xfffffff0 },
+ 	{ PHY_ID_AQR113C, 0xfffffff0 },
+ 	{ PHY_ID_AQR112C, 0xfffffff0 },

feeds/ipq807x/ipq807x/patches/103-fix-dtc-gcc10-build.patch

@@ -0,0 +1,11 @@
+--- a/scripts/dtc/dtc-lexer.lex.c_shipped
++++ b/scripts/dtc/dtc-lexer.lex.c_shipped
+@@ -637,7 +637,7 @@ char *yytext;
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+ 
+-YYLTYPE yylloc;
++extern YYLTYPE yylloc;
+ extern bool treesource_error;
+ 
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */

feeds/ipq807x/ipq807x/patches/104-log-spam.patch

@@ -1,17 +1,17 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/clk/qcom/clk-branch.c
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/clk/qcom/clk-branch.c
 ===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/drivers/clk/qcom/clk-branch.c
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/drivers/clk/qcom/clk-branch.c
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/clk/qcom/clk-branch.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/clk/qcom/clk-branch.c
-@@ -67,7 +67,7 @@ static int clk_branch_wait(const struct
+@@ -75,7 +75,7 @@ static int clk_branch_wait(const struct
  		bool (check_halt)(const struct clk_branch *, bool))
  {
  	bool voted = br->halt_check & BRANCH_VOTED;
 -	const char *name = clk_hw_get_name(&br->clkr.hw);
 +	//const char *name = clk_hw_get_name(&br->clkr.hw);
  
- 	/*
+ 	/* Skip checking halt bit if the clock is in hardware gated mode */
- 	 * Skip checking halt bit if we're explicitly ignoring the bit or the
+ 	if (clk_branch_in_hwcg_mode(br))
-@@ -88,8 +88,8 @@ static int clk_branch_wait(const struct
+@@ -93,8 +93,8 @@ static int clk_branch_wait(const struct
  				return 0;
  			udelay(1);
  		}
@@ -22,3 +22,16 @@ Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/clk/q
  		return -EBUSY;
  	}
  	return 0;
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/usb/phy/phy-msm-qusb.c
+===================================================================
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/drivers/usb/phy/phy-msm-qusb.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/usb/phy/phy-msm-qusb.c
+@@ -491,7 +491,7 @@ static int qusb_phy_init(struct usb_phy
+ 		dev_err(phy->dev, "QUSB PHY PLL LOCK fails:%x\n",
+ 			readb_relaxed(qphy->base
+ 				+ QUSB2PHY_PLL_STATUS));
+-		WARN_ON(1);
++		//WARN_ON(1);
+ 	}
+ 
+ 	/* Set OTG VBUS Valid from HSPHY to controller */

feeds/ipq807x/ipq807x/patches/105-add-esmt-nand.patch

@@ -1,15 +1,37 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/mtd/nand/raw/nand_ids.c
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/mtd/nand/nand_ids.c
 ===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/drivers/mtd/nand/raw/nand_ids.c
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/drivers/mtd/nand/nand_ids.c
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/mtd/nand/raw/nand_ids.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/drivers/mtd/nand/nand_ids.c
-@@ -114,6 +114,10 @@ struct nand_flash_dev nand_flash_ids[] =
+@@ -62,6 +62,12 @@ struct nand_flash_dev nand_flash_ids[] =
- 		{ .id = {0xc8, 0x42} },
+ 	{"TH58NYG3S0H 8G 1.8V 8-bit",
- 		SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512), 0},
+ 		{ .id = {0x98, 0xa3, 0x91, 0x26} },
- 
+ 		  SZ_4K, SZ_1K, SZ_256K, 0, 4, 256, NAND_ECC_INFO(8, SZ_512) },
++
 +	{"F59D2G81KA 2G 1.8V 8-bit",
 +		{ .id = {0xc8, 0x5a, 0x90, 0x04} },
 +		SZ_2K, SZ_256, SZ_128K, 0, 4, 128, NAND_ECC_INFO(8, SZ_512) },
++
 +
  	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
+@@ -190,6 +196,7 @@ struct nand_manufacturers nand_manuf_ids
+ 	{NAND_MFR_SANDISK, "SanDisk"},
+ 	{NAND_MFR_INTEL, "Intel"},
+ 	{NAND_MFR_ATO, "ATO"},
++	{NAND_MFR_ESMT, "ESMT"},
+ 	{NAND_MFR_GIGA, "GigaDevice"},
+ 	{NAND_MFR_ATO, "ATO"},
+ 	{NAND_MFR_WINBOND, "Winbond"},
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/include/linux/mtd/nand.h
+===================================================================
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/include/linux/mtd/nand.h
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/include/linux/mtd/nand.h
+@@ -778,6 +778,7 @@ static inline struct mtd_info *nand_to_m
+ #define NAND_MFR_ATO		0x9b
+ #define NAND_MFR_WINBOND	0xef
+ #define NAND_MFR_FIDELIX	0xe5
++#define NAND_MFR_ESMT		0xc8
+ 
+ /* The maximum expected count of bytes in the NAND ID sequence */
+ #define NAND_MAX_ID_LEN 8

feeds/ipq807x/ipq807x/patches/106-pstore.patch

@@ -0,0 +1,147 @@
+Index: linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
+===================================================================
+--- linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016.orig/arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
++++ linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi
+@@ -92,6 +92,12 @@
+ 			reg = <0x0 0x40000000 0x0 0x00800000>;
+ 		};
+ 
++		ramoops@4A0f0000 {
++			compatible = "ramoops";
++			reg = <0 0x4A0f0000 0 0x10000>;
++			record-size = <0x1000>;
++		};
++
+ 		uboot@4A100000 {
+ 			no-map;
+ 			reg = <0x0 0x4A100000 0x0 0x00400000>;
+@@ -211,6 +217,12 @@
+ 			reg = <0x0 0x40000000 0x0 0x01000000>;
+ 		};
+ 
++		ramoops@4A0f0000 {
++			compatible = "ramoops";
++			reg = <0 0x4A0f0000 0 0x10000>;
++			record-size = <0x1000>;
++		};
++
+ 		uboot@4A100000 {
+ 			no-map;
+ 			reg = <0x0 0x4A100000 0x0 0x00400000>;
+@@ -330,6 +342,12 @@
+ 			reg = <0x0 0x40000000 0x0 0x01000000>;
+ 		};
+ 
++		ramoops@4A0f0000 {
++			compatible = "ramoops";
++			reg = <0 0x4A0f0000 0 0x10000>;
++			record-size = <0x1000>;
++		};
++
+ 		uboot@4A100000 {
+ 			no-map;
+ 			reg = <0x0 0x4A100000 0x0 0x00400000>;
+Index: linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/fs/pstore/ram.c
+===================================================================
+--- linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016.orig/fs/pstore/ram.c
++++ linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/fs/pstore/ram.c
+@@ -466,15 +466,46 @@ static int ramoops_init_prz(struct devic
+ 	return 0;
+ }
+ 
++static int ramoops_parse_dt(struct platform_device *pdev,
++                            struct ramoops_platform_data *pdata)
++{
++	struct resource *res;
++
++	dev_dbg(&pdev->dev, "using Device Tree\n");
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev,
++			"failed to locate DT /reserved-memory resource\n");
++		return -EINVAL;
++	}
++
++	pdata->mem_size = resource_size(res);
++	pdata->mem_address = res->start;
++	pdata->dump_oops = true;
++	pdata->record_size = 0x1000;
++	return 0;
++}
++
+ static int ramoops_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+ 	struct ramoops_platform_data *pdata = pdev->dev.platform_data;
++	struct ramoops_platform_data pdata_local;
+ 	struct ramoops_context *cxt = &oops_cxt;
+ 	size_t dump_mem_sz;
+ 	phys_addr_t paddr;
+ 	int err = -EINVAL;
+ 
++	if (dev_of_node(dev) && !pdata) {
++		pdata = &pdata_local;
++		memset(pdata, 0, sizeof(*pdata));
++
++		err = ramoops_parse_dt(pdev, pdata);
++		if (err < 0)
++		goto fail_out;
++	}
++
+ 	/* Only a single ramoops area allowed at a time, so fail extra
+ 	 * probes.
+ 	 */
+@@ -603,11 +634,17 @@ static int ramoops_remove(struct platfor
+ 	return 0;
+ }
+ 
++static const struct of_device_id dt_match[] = {
++	{ .compatible = "ramoops" },
++	{}
++};
++
+ static struct platform_driver ramoops_driver = {
+ 	.probe		= ramoops_probe,
+ 	.remove		= ramoops_remove,
+ 	.driver		= {
+ 		.name	= "ramoops",
++		.of_match_table = dt_match,
+ 	},
+ };
+ 
+Index: linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/drivers/of/platform.c
+===================================================================
+--- linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016.orig/drivers/of/platform.c
++++ linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/drivers/of/platform.c
+@@ -53,6 +53,30 @@ struct platform_device *of_find_device_b
+ }
+ EXPORT_SYMBOL(of_find_device_by_node);
+ 
++static const struct of_device_id reserved_mem_matches[] = {
++        { .compatible = "ramoops" },
++        {}
++};
++
++static int __init of_platform_default_populate_init(void)
++{
++	struct device_node *node;
++
++	if (!of_have_populated_dt())
++		return -ENODEV;
++
++	/*
++	 * Handle certain compatibles explicitly, since we don't want to create
++	 * platform_devices for every node in /reserved-memory with a
++	 * "compatible",
++	 */
++	for_each_matching_node(node, reserved_mem_matches)
++		of_platform_device_create(node, NULL, NULL);
++
++	return 0;
++}
++arch_initcall_sync(of_platform_default_populate_init);
++
+ #ifdef CONFIG_OF_ADDRESS
+ /*
+  * The following routines scan a subtree and registers a device for

feeds/ipq807x/ipq807x/patches/107-bridge-allow-bcast-mcast-same-port-hairpinmode.patch

@@ -1,13 +1,14 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/net/bridge/br_forward.c
+Index: linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/net/bridge/br_forward.c
 ===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/net/bridge/br_forward.c
+--- linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce.orig/net/bridge/br_forward.c
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/net/bridge/br_forward.c
++++ linux-4.4.60-qsdk-10fd7d14853b7020b804acae690c8acec5d954ce/net/bridge/br_forward.c
-@@ -24,7 +24,7 @@ static inline int should_deliver(const s
+@@ -33,8 +33,7 @@ static inline int should_deliver(const s
  	struct net_bridge_vlan_group *vg;
  
  	vg = nbp_vlan_group_rcu(p);
--	return (((p->flags & BR_HAIRPIN_MODE) && !is_multicast_ether_addr(eth_hdr(skb)->h_dest))
+-	return ((skb->dev != p->dev) || ((p->flags & BR_HAIRPIN_MODE) &&
-+	return (((p->flags & BR_HAIRPIN_MODE))
+-		(!is_multicast_ether_addr(eth_hdr(skb)->h_dest)))) &&
- 		|| (skb->dev != p->dev)) &&
++	return ((skb->dev != p->dev) || (p->flags & BR_HAIRPIN_MODE)) &&
- 		br_allowed_egress(vg, skb) && (p->state == BR_STATE_FORWARDING) &&
+ 		br_allowed_egress(vg, skb) && p->state == BR_STATE_FORWARDING;
- 		nbp_switchdev_allowed_egress(p, skb) &&
+ }
+ 

feeds/ipq807x/ipq807x/patches/108-add-W25N01GW.patch

@@ -1,15 +1,14 @@
-Index: linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/mtd/nand/raw/nand_ids.c
+Index: linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/drivers/mtd/nand/qcom_nandc.c
 ===================================================================
---- linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac.orig/drivers/mtd/nand/raw/nand_ids.c
+--- linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016.orig/drivers/mtd/nand/qcom_nandc.c
-+++ linux-5.4.164-qsdk-d5fcb18e5420670c8734c6a659873e73adab6dac/drivers/mtd/nand/raw/nand_ids.c
++++ linux-4.4.60-qsdk-11f09717303ecd83c3a64e9efe23f25921dc1016/drivers/mtd/nand/qcom_nandc.c
-@@ -118,6 +118,10 @@ struct nand_flash_dev nand_flash_ids[] =
+@@ -405,6 +405,9 @@ struct nand_flash_dev qspinand_flash_ids
- 		{ .id = {0xc8, 0x5a, 0x90, 0x04} },
+ 	{"MX35UF1GE4AC SPI NAND 1G 1.8V",
- 		SZ_2K, SZ_256, SZ_128K, 0, 4, 128, NAND_ECC_INFO(8, SZ_512) },
+ 		{ .id = {0xc2, 0x92} },
- 
+ 		SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512), 0},
 +	{"W25N01GW SPI NAND 1.8V 1G-BIT",
 +		{ .id = {0xef, 0xba} },
 +		SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512), 0},
-+
+ 	{NULL}
- 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
+ };
- 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+ 
- 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),

feeds/ipq807x/ipq807x/patches/109-net-bridge-clear-bridge-s-private-skb-space-on-xmit.patch

@@ -0,0 +1,36 @@
+From fd65e5a95d08389444e8591a20538b3edece0e15 Mon Sep 17 00:00:00 2001
+From: Nikolay Aleksandrov <nikolay@cumulusnetworks.com>
+Date: Fri, 31 Jul 2020 19:26:16 +0300
+Subject: [PATCH] net: bridge: clear bridge's private skb space on xmit
+
+We need to clear all of the bridge private skb variables as they can be
+stale due to the packet being recirculated through the stack and then
+transmitted through the bridge device. Similar memset is already done on
+bridge's input. We've seen cases where proxyarp_replied was 1 on routed
+multicast packets transmitted through the bridge to ports with neigh
+suppress which were getting dropped. Same thing can in theory happen with
+the port isolation bit as well.
+
+Fixes: 821f1b21cabb ("bridge: add new BR_NEIGH_SUPPRESS port flag to suppress arp and nd flood")
+Signed-off-by: Nikolay Aleksandrov <nikolay@cumulusnetworks.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ net/bridge/br_device.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c
+index 8c7b78f8bc23..9a2fb4aa1a10 100644
+--- a/net/bridge/br_device.c
++++ b/net/bridge/br_device.c
+@@ -36,6 +36,8 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev)
+ 	const unsigned char *dest;
+ 	u16 vid = 0;
+ 
++	memset(skb->cb, 0, sizeof(struct br_input_skb_cb));
++
+ 	rcu_read_lock();
+ 	nf_ops = rcu_dereference(nf_br_ops);
+ 	if (nf_ops && nf_ops->br_dev_xmit_hook(skb)) {
+-- 
+2.25.1
+

feeds/ipq807x/ipq807x/patches/190-revert-threaded-NAPI.patch

@@ -1,306 +0,0 @@
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -338,7 +338,6 @@ struct napi_struct {
- 	struct list_head	dev_list;
- 	struct hlist_node	napi_hash_node;
- 	unsigned int		napi_id;
--	struct work_struct	work;
- };
- 
- enum {
-@@ -349,7 +348,6 @@ enum {
- 	NAPI_STATE_HASHED,	/* In NAPI hash (busy polling possible) */
- 	NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */
- 	NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */
--	NAPI_STATE_THREADED,	/* Use threaded NAPI */
- };
- 
- enum {
-@@ -360,7 +358,6 @@ enum {
- 	NAPIF_STATE_HASHED	 = BIT(NAPI_STATE_HASHED),
- 	NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),
- 	NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),
--	NAPIF_STATE_THREADED	 = BIT(NAPI_STATE_THREADED),
- };
- 
- enum gro_result {
-@@ -2320,26 +2317,6 @@ void netif_napi_add(struct net_device *d
- 		    int (*poll)(struct napi_struct *, int), int weight);
- 
- /**
-- *	netif_threaded_napi_add - initialize a NAPI context
-- *	@dev:  network device
-- *	@napi: NAPI context
-- *	@poll: polling function
-- *	@weight: default weight
-- *
-- * This variant of netif_napi_add() should be used from drivers using NAPI
-- * with CPU intensive poll functions.
-- * This will schedule polling from a high priority workqueue
-- */
--static inline void netif_threaded_napi_add(struct net_device *dev,
--					   struct napi_struct *napi,
--					   int (*poll)(struct napi_struct *, int),
--					   int weight)
--{
--	set_bit(NAPI_STATE_THREADED, &napi->state);
--	netif_napi_add(dev, napi, poll, weight);
--}
--
--/**
-  *	netif_tx_napi_add - initialize a NAPI context
-  *	@dev:  network device
-  *	@napi: NAPI context
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -157,7 +157,6 @@ static DEFINE_SPINLOCK(offload_lock);
- struct list_head ptype_base[PTYPE_HASH_SIZE] __read_mostly;
- struct list_head ptype_all __read_mostly;	/* Taps */
- static struct list_head offload_base __read_mostly;
--static struct workqueue_struct *napi_workq __read_mostly;
- 
- static int netif_rx_internal(struct sk_buff *skb);
- static int call_netdevice_notifiers_info(unsigned long val,
-@@ -5969,11 +5968,6 @@ void __napi_schedule(struct napi_struct
- {
- 	unsigned long flags;
- 
--	if (test_bit(NAPI_STATE_THREADED, &n->state)) {
--		queue_work(napi_workq, &n->work);
--		return;
--	}
--
- 	local_irq_save(flags);
- 	____napi_schedule(this_cpu_ptr(&softnet_data), n);
- 	local_irq_restore(flags);
-@@ -6289,84 +6283,6 @@ static void init_gro_hash(struct napi_st
- 	napi->gro_bitmask = 0;
- }
- 
--static int __napi_poll(struct napi_struct *n, bool *repoll)
--{
--	int work, weight;
--
--	weight = n->weight;
--
--	/* This NAPI_STATE_SCHED test is for avoiding a race
--	 * with netpoll's poll_napi().  Only the entity which
--	 * obtains the lock and sees NAPI_STATE_SCHED set will
--	 * actually make the ->poll() call.  Therefore we avoid
--	 * accidentally calling ->poll() when NAPI is not scheduled.
--	 */
--	work = 0;
--	if (test_bit(NAPI_STATE_SCHED, &n->state)) {
--		work = n->poll(n, weight);
--		trace_napi_poll(n, work, weight);
--	}
--
--	WARN_ON_ONCE(work > weight);
--
--	if (likely(work < weight))
--		return work;
--
--	/* Drivers must not modify the NAPI state if they
--	 * consume the entire weight.  In such cases this code
--	 * still "owns" the NAPI instance and therefore can
--	 * move the instance around on the list at-will.
--	 */
--	if (unlikely(napi_disable_pending(n))) {
--		napi_complete(n);
--		return work;
--	}
--
--	if (n->gro_bitmask) {
--		/* flush too old packets
--		 * If HZ < 1000, flush all packets.
--		 */
--		napi_gro_flush(n, HZ >= 1000);
--	}
--
--	gro_normal_list(n);
--
--	*repoll = true;
--
--	return work;
--}
--
--static void napi_workfn(struct work_struct *work)
--{
--	struct napi_struct *n = container_of(work, struct napi_struct, work);
--	void *have;
--
--	for (;;) {
--		bool repoll = false;
--
--		local_bh_disable();
--
--		have = netpoll_poll_lock(n);
--		__napi_poll(n, &repoll);
--		netpoll_poll_unlock(have);
--
--		local_bh_enable();
--
--		if (!repoll)
--			return;
--
--		if (!need_resched())
--			continue;
--
--		/*
--		 * have to pay for the latency of task switch even if
--		 * napi is scheduled
--		 */
--		queue_work(napi_workq, work);
--		return;
--	}
--}
--
- void netif_napi_add(struct net_device *dev, struct napi_struct *napi,
- 		    int (*poll)(struct napi_struct *, int), int weight)
- {
-@@ -6386,7 +6302,6 @@ void netif_napi_add(struct net_device *d
- #ifdef CONFIG_NETPOLL
- 	napi->poll_owner = -1;
- #endif
--	INIT_WORK(&napi->work, napi_workfn);
- 	set_bit(NAPI_STATE_SCHED, &napi->state);
- 	set_bit(NAPI_STATE_NPSVC, &napi->state);
- 	list_add_rcu(&napi->dev_list, &dev->napi_list);
-@@ -6427,7 +6342,6 @@ static void flush_gro_hash(struct napi_s
- void netif_napi_del(struct napi_struct *napi)
- {
- 	might_sleep();
--	cancel_work_sync(&napi->work);
- 	if (napi_hash_del(napi))
- 		synchronize_net();
- 	list_del_init(&napi->dev_list);
-@@ -6440,19 +6354,51 @@ EXPORT_SYMBOL(netif_napi_del);
- 
- static int napi_poll(struct napi_struct *n, struct list_head *repoll)
- {
--	bool do_repoll = false;
- 	void *have;
--	int work;
-+	int work, weight;
- 
- 	list_del_init(&n->poll_list);
- 
- 	have = netpoll_poll_lock(n);
- 
--	work = __napi_poll(n, &do_repoll);
-+	weight = n->weight;
- 
--	if (!do_repoll)
-+	/* This NAPI_STATE_SCHED test is for avoiding a race
-+	 * with netpoll's poll_napi().  Only the entity which
-+	 * obtains the lock and sees NAPI_STATE_SCHED set will
-+	 * actually make the ->poll() call.  Therefore we avoid
-+	 * accidentally calling ->poll() when NAPI is not scheduled.
-+	 */
-+	work = 0;
-+	if (test_bit(NAPI_STATE_SCHED, &n->state)) {
-+		work = n->poll(n, weight);
-+		trace_napi_poll(n, work, weight);
-+	}
-+
-+	WARN_ON_ONCE(work > weight);
-+
-+	if (likely(work < weight))
- 		goto out_unlock;
- 
-+	/* Drivers must not modify the NAPI state if they
-+	 * consume the entire weight.  In such cases this code
-+	 * still "owns" the NAPI instance and therefore can
-+	 * move the instance around on the list at-will.
-+	 */
-+	if (unlikely(napi_disable_pending(n))) {
-+		napi_complete(n);
-+		goto out_unlock;
-+	}
-+
-+	if (n->gro_bitmask) {
-+		/* flush too old packets
-+		 * If HZ < 1000, flush all packets.
-+		 */
-+		napi_gro_flush(n, HZ >= 1000);
-+	}
-+
-+	gro_normal_list(n);
-+
- 	/* Some drivers may have called napi_schedule
- 	 * prior to exhausting their budget.
- 	 */
-@@ -10428,10 +10374,6 @@ static int __init net_dev_init(void)
- 		sd->backlog.weight = weight_p;
- 	}
- 
--	napi_workq = alloc_workqueue("napi_workq", WQ_UNBOUND | WQ_HIGHPRI,
--				     WQ_UNBOUND_MAX_ACTIVE | WQ_SYSFS);
--	BUG_ON(!napi_workq);
--
- 	dev_boot_phase = 0;
- 
- 	/* The loopback device is special if any other network devices
---- a/net/core/net-sysfs.c
-+++ b/net/core/net-sysfs.c
-@@ -470,52 +470,6 @@ static ssize_t proto_down_store(struct d
- }
- NETDEVICE_SHOW_RW(proto_down, fmt_dec);
- 
--static int change_napi_threaded(struct net_device *dev, unsigned long val)
--{
--	struct napi_struct *napi;
--
--	if (list_empty(&dev->napi_list))
--		return -EOPNOTSUPP;
--
--	list_for_each_entry(napi, &dev->napi_list, dev_list) {
--		if (val)
--			set_bit(NAPI_STATE_THREADED, &napi->state);
--		else
--			clear_bit(NAPI_STATE_THREADED, &napi->state);
--	}
--
--	return 0;
--}
--
--static ssize_t napi_threaded_store(struct device *dev,
--				struct device_attribute *attr,
--				const char *buf, size_t len)
--{
--	return netdev_store(dev, attr, buf, len, change_napi_threaded);
--}
--
--static ssize_t napi_threaded_show(struct device *dev,
--				  struct device_attribute *attr,
--				  char *buf)
--{
--	struct net_device *netdev = to_net_dev(dev);
--	struct napi_struct *napi;
--	bool enabled = false;
--
--	if (!rtnl_trylock())
--		return restart_syscall();
--
--	list_for_each_entry(napi, &netdev->napi_list, dev_list) {
--		if (test_bit(NAPI_STATE_THREADED, &napi->state))
--			enabled = true;
--	}
--
--	rtnl_unlock();
--
--	return sprintf(buf, fmt_dec, enabled);
--}
--static DEVICE_ATTR_RW(napi_threaded);
--
- static ssize_t phys_port_id_show(struct device *dev,
- 				 struct device_attribute *attr, char *buf)
- {
-@@ -627,7 +581,6 @@ static struct attribute *net_class_attrs
- 	&dev_attr_flags.attr,
- 	&dev_attr_tx_queue_len.attr,
- 	&dev_attr_gro_flush_timeout.attr,
--	&dev_attr_napi_threaded.attr,
- 	&dev_attr_phys_port_id.attr,
- 	&dev_attr_phys_port_name.attr,
- 	&dev_attr_phys_switch_id.attr,

feeds/ipq807x/ipq807x/patches/210-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch

@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6352,15 +6352,10 @@ void netif_napi_del(struct napi_struct *
+@@ -6322,15 +6322,10 @@ void netif_napi_del(struct napi_struct *
  }
  EXPORT_SYMBOL(netif_napi_del);
  
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	weight = n->weight;
  
  	/* This NAPI_STATE_SCHED test is for avoiding a race
-@@ -6378,7 +6373,7 @@ static int napi_poll(struct napi_struct
+@@ -6348,7 +6343,7 @@ static int napi_poll(struct napi_struct
  	WARN_ON_ONCE(work > weight);
  
  	if (likely(work < weight))
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/* Drivers must not modify the NAPI state if they
  	 * consume the entire weight.  In such cases this code
-@@ -6387,7 +6382,7 @@ static int napi_poll(struct napi_struct
+@@ -6357,7 +6352,7 @@ static int napi_poll(struct napi_struct
  	 */
  	if (unlikely(napi_disable_pending(n))) {
  		napi_complete(n);
@@ -53,7 +53,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	if (n->gro_bitmask) {
-@@ -6405,12 +6400,29 @@ static int napi_poll(struct napi_struct
+@@ -6375,12 +6370,29 @@ static int napi_poll(struct napi_struct
  	if (unlikely(!list_empty(&n->poll_list))) {
  		pr_warn_once("%s: Budget exhausted after napi rescheduled\n",
  			     n->dev ? n->dev->name : "backlog");

feeds/ipq807x/ipq807x/patches/211-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch

@@ -30,7 +30,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -338,6 +338,7 @@ struct napi_struct {
+@@ -319,6 +319,7 @@ struct napi_struct {
  	struct list_head	dev_list;
  	struct hlist_node	napi_hash_node;
  	unsigned int		napi_id;
@@ -38,33 +38,18 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  enum {
-@@ -348,6 +349,7 @@ enum {
+@@ -326,6 +327,7 @@ enum {
- 	NAPI_STATE_HASHED,	/* In NAPI hash (busy polling possible) */
+ 	NAPI_STATE_DISABLE,	/* Disable pending */
- 	NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */
+ 	NAPI_STATE_NPSVC,	/* Netpoll - don't dequeue from poll_list */
- 	NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */
+ 	NAPI_STATE_HASHED,	/* In NAPI hash */
 +	NAPI_STATE_THREADED,	/* The poll is performed inside its own thread*/
  };
  
- enum {
-@@ -358,6 +360,7 @@ enum {
- 	NAPIF_STATE_HASHED	 = BIT(NAPI_STATE_HASHED),
- 	NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),
- 	NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),
-+	NAPIF_STATE_THREADED	 = BIT(NAPI_STATE_THREADED),
- };
- 
  enum gro_result {
-@@ -502,20 +505,7 @@ bool napi_hash_del(struct napi_struct *n
+@@ -501,13 +503,7 @@ void napi_disable(struct napi_struct *n)
+  * Resume NAPI from being scheduled on this context.
+  * Must be paired with napi_disable.
   */
- void napi_disable(struct napi_struct *n);
- 
--/**
-- *	napi_enable - enable NAPI scheduling
-- *	@n: NAPI context
-- *
-- * Resume NAPI from being scheduled on this context.
-- * Must be paired with napi_disable.
-- */
 -static inline void napi_enable(struct napi_struct *n)
 -{
 -	BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state));
@@ -76,34 +61,34 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  /**
   *	napi_synchronize - wait until NAPI is not running
-@@ -1834,6 +1824,8 @@ enum netdev_ml_priv_type {
+@@ -1573,6 +1569,8 @@ enum netdev_priv_flags_ext {
-  *
+  *			switch driver and used to set the phys state of the
-  *	@wol_enabled:	Wake-on-LAN is enabled
+  *			switch port.
   *
 + *	@threaded:	napi threaded mode is enabled
 + *
   *	FIXME: cleanup struct net_device such that network protocol info
   *	moves out.
   */
-@@ -2137,6 +2129,7 @@ struct net_device {
+@@ -1852,6 +1850,7 @@ struct net_device {
- 	struct lock_class_key	addr_list_lock_key;
+ 	struct phy_device *phydev;
+ 	struct lock_class_key *qdisc_tx_busylock;
  	bool proto_down;
- 	unsigned		wol_enabled:1;
 +	unsigned		threaded:1;
  };
  #define to_net_dev(d) container_of(d, struct net_device, dev)
  
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -91,6 +91,7 @@
+@@ -94,6 +94,7 @@
- #include <linux/etherdevice.h>
  #include <linux/ethtool.h>
+ #include <linux/notifier.h>
  #include <linux/skbuff.h>
 +#include <linux/kthread.h>
- #include <linux/bpf.h>
- #include <linux/bpf_trace.h>
  #include <net/net_namespace.h>
-@@ -1286,6 +1287,27 @@ void netdev_notify_peers(struct net_devi
+ #include <net/sock.h>
+ #include <linux/rtnetlink.h>
+@@ -1304,6 +1305,27 @@ void netdev_notify_peers(struct net_devi
  }
  EXPORT_SYMBOL(netdev_notify_peers);
  
@@ -128,10 +113,10 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	return err;
 +}
 +
- static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack)
+ static int __dev_open(struct net_device *dev)
  {
  	const struct net_device_ops *ops = dev->netdev_ops;
-@@ -3898,6 +3920,21 @@ int gro_normal_batch __read_mostly = 8;
+@@ -3248,6 +3270,21 @@ int weight_p __read_mostly = 64;
  static inline void ____napi_schedule(struct softnet_data *sd,
  				     struct napi_struct *napi)
  {
@@ -153,10 +138,10 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	list_add_tail(&napi->poll_list, &sd->poll_list);
  	__raise_softirq_irqoff(NET_RX_SOFTIRQ);
  }
-@@ -6306,6 +6343,12 @@ void netif_napi_add(struct net_device *d
+@@ -4828,9 +4865,33 @@ void netif_napi_add(struct net_device *d
- 	set_bit(NAPI_STATE_NPSVC, &napi->state);
+ 	napi->poll_owner = -1;
- 	list_add_rcu(&napi->dev_list, &dev->napi_list);
+ #endif
- 	napi_hash_add(napi);
+ 	set_bit(NAPI_STATE_SCHED, &napi->state);
 +	/* Create kthread for this napi if dev->threaded is set.
 +	 * Clear dev->threaded if kthread creation failed so that
 +	 * threaded mode will not be enabled in napi_enable().
@@ -166,14 +151,6 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  EXPORT_SYMBOL(netif_napi_add);
  
-@@ -6322,9 +6365,28 @@ void napi_disable(struct napi_struct *n)
- 	hrtimer_cancel(&n->timer);
- 
- 	clear_bit(NAPI_STATE_DISABLE, &n->state);
-+	clear_bit(NAPI_STATE_THREADED, &n->state);
- }
- EXPORT_SYMBOL(napi_disable);
- 
 +/**
 + *	napi_enable - enable NAPI scheduling
 + *	@n: NAPI context
@@ -192,13 +169,21 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +}
 +EXPORT_SYMBOL(napi_enable);
 +
- static void flush_gro_hash(struct napi_struct *napi)
+ void napi_disable(struct napi_struct *n)
  {
- 	int i;
+ 	might_sleep();
-@@ -6349,6 +6411,11 @@ void netif_napi_del(struct napi_struct *
+@@ -4844,6 +4905,7 @@ void napi_disable(struct napi_struct *n)
+ 	hrtimer_cancel(&n->timer);
  
- 	flush_gro_hash(napi);
+ 	clear_bit(NAPI_STATE_DISABLE, &n->state);
- 	napi->gro_bitmask = 0;
++	clear_bit(NAPI_STATE_THREADED, &n->state);
+ }
+ EXPORT_SYMBOL(napi_disable);
+ 
+@@ -4855,6 +4917,11 @@ void netif_napi_del(struct napi_struct *
+ 	kfree_skb_list(napi->gro_list);
+ 	napi->gro_list = NULL;
+ 	napi->gro_count = 0;
 +
 +	if (napi->thread) {
 +		kthread_stop(napi->thread);
@@ -207,7 +192,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  EXPORT_SYMBOL(netif_napi_del);
  
-@@ -6428,6 +6495,51 @@ static int napi_poll(struct napi_struct
+@@ -4940,6 +5007,50 @@ static int napi_poll(struct napi_struct
  	return work;
  }
  
@@ -244,7 +229,6 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +			__napi_poll(napi, &repoll);
 +			netpoll_poll_unlock(have);
 +
-+			__kfree_skb_flush();
 +			local_bh_enable();
 +
 +			if (!repoll)
@@ -256,6 +240,6 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	return 0;
 +}
 +
- static __latent_entropy void net_rx_action(struct softirq_action *h)
+ static void net_rx_action(struct softirq_action *h)
  {
  	struct softnet_data *sd = this_cpu_ptr(&softnet_data);

feeds/ipq807x/ipq807x/patches/212-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch

@@ -23,41 +23,20 @@ Reviewed-by: Alexander Duyck <alexanderduyck@fb.com>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 
---- a/Documentation/ABI/testing/sysfs-class-net
-+++ b/Documentation/ABI/testing/sysfs-class-net
-@@ -301,3 +301,18 @@ Contact:	netdev@vger.kernel.org
- Description:
- 		32-bit unsigned integer counting the number of times the link has
- 		been down
-+
-+What:		/sys/class/net/<iface>/threaded
-+Date:		Jan 2021
-+KernelVersion:	5.12
-+Contact:	netdev@vger.kernel.org
-+Description:
-+		Boolean value to control the threaded mode per device. User could
-+		set this value to enable/disable threaded mode for all napi
-+		belonging to this device, without the need to do device up/down.
-+
-+		Possible values:
-+		== ==================================
-+		0  threaded mode disabled for this dev
-+		1  threaded mode enabled for this dev
-+		== ==================================
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -496,6 +496,8 @@ static inline bool napi_complete(struct
+@@ -496,6 +496,8 @@ void napi_hash_del(struct napi_struct *n
   */
- bool napi_hash_del(struct napi_struct *napi);
+ void napi_disable(struct napi_struct *n);
  
 +int dev_set_threaded(struct net_device *dev, bool threaded);
 +
  /**
-  *	napi_disable - prevent NAPI from scheduling
+  *	napi_enable - enable NAPI scheduling
-  *	@n: NAPI context
+  *	@n: napi context
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3924,8 +3924,9 @@ static inline void ____napi_schedule(str
+@@ -3274,8 +3274,9 @@ static inline void ____napi_schedule(str
  
  	if (test_bit(NAPI_STATE_THREADED, &napi->state)) {
  		/* Paired with smp_mb__before_atomic() in
@@ -69,8 +48,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		 * wake_up_process() when it's not NULL.
  		 */
  		thread = READ_ONCE(napi->thread);
-@@ -6320,6 +6321,49 @@ static void init_gro_hash(struct napi_st
+@@ -4844,6 +4845,49 @@ static enum hrtimer_restart napi_watchdo
- 	napi->gro_bitmask = 0;
+ 	return HRTIMER_NORESTART;
  }
  
 +int dev_set_threaded(struct net_device *dev, bool threaded)
@@ -121,7 +100,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  {
 --- a/net/core/net-sysfs.c
 +++ b/net/core/net-sysfs.c
-@@ -557,6 +557,45 @@ static ssize_t phys_switch_id_show(struc
+@@ -486,6 +486,45 @@ static ssize_t phys_switch_id_show(struc
  }
  static DEVICE_ATTR_RO(phys_switch_id);
  
@@ -164,13 +143,13 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +}
 +static DEVICE_ATTR_RW(threaded);
 +
- static struct attribute *net_class_attrs[] __ro_after_init = {
+ static struct attribute *net_class_attrs[] = {
  	&dev_attr_netdev_group.attr,
  	&dev_attr_type.attr,
-@@ -587,6 +626,7 @@ static struct attribute *net_class_attrs
+@@ -514,6 +553,7 @@ static struct attribute *net_class_attrs
+ 	&dev_attr_phys_port_name.attr,
+ 	&dev_attr_phys_switch_id.attr,
  	&dev_attr_proto_down.attr,
- 	&dev_attr_carrier_up_count.attr,
- 	&dev_attr_carrier_down_count.attr,
 +	&dev_attr_threaded.attr,
  	NULL,
  };

feeds/ipq807x/ipq807x/patches/213-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch

@@ -27,25 +27,17 @@ Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -350,6 +350,7 @@ enum {
+@@ -328,6 +328,7 @@ enum {
- 	NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */
+ 	NAPI_STATE_NPSVC,	/* Netpoll - don't dequeue from poll_list */
- 	NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */
+ 	NAPI_STATE_HASHED,	/* In NAPI hash */
  	NAPI_STATE_THREADED,	/* The poll is performed inside its own thread*/
 +	NAPI_STATE_SCHED_THREADED,	/* Napi is currently scheduled in threaded mode */
  };
  
- enum {
-@@ -361,6 +362,7 @@ enum {
- 	NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),
- 	NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),
- 	NAPIF_STATE_THREADED	 = BIT(NAPI_STATE_THREADED),
-+	NAPIF_STATE_SCHED_THREADED	= BIT(NAPI_STATE_SCHED_THREADED),
- };
- 
  enum gro_result {
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3931,6 +3931,8 @@ static inline void ____napi_schedule(str
+@@ -3281,6 +3281,8 @@ static inline void ____napi_schedule(str
  		 */
  		thread = READ_ONCE(napi->thread);
  		if (thread) {
@@ -54,17 +46,50 @@ Cc: Hannes Frederic Sowa <hannes@stressinduktion.org>
  			wake_up_process(thread);
  			return;
  		}
-@@ -6108,7 +6110,8 @@ bool napi_complete_done(struct napi_stru
+@@ -4745,12 +4747,14 @@ void __napi_complete(struct napi_struct
+ 	list_del_init(&n->poll_list);
+ 	smp_mb__before_atomic();
+ 	clear_bit(NAPI_STATE_SCHED, &n->state);
++	clear_bit(NAPI_STATE_SCHED_THREADED, &n->state);
+ }
+ EXPORT_SYMBOL(__napi_complete);
  
- 		WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED));
+ void napi_complete_done(struct napi_struct *n, int work_done)
+ {
+ 	unsigned long flags;
++	unsigned long val, new;
  
--		new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED);
+ 	/*
-+		new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED |
+ 	 * don't let napi dequeue from the cpu poll list
-+			      NAPIF_STATE_SCHED_THREADED);
+@@ -4771,14 +4775,19 @@ void napi_complete_done(struct napi_stru
+ 		else
+ 			napi_gro_flush(n, false);
+ 	}
+-	if (likely(list_empty(&n->poll_list))) {
+-		WARN_ON_ONCE(!test_and_clear_bit(NAPI_STATE_SCHED, &n->state));
+-	} else {
+-		/* If n->poll_list is not empty, we need to mask irqs */
+-		local_irq_save(flags);
+-		__napi_complete(n);
+-		local_irq_restore(flags);
+-	}
++
++	/* If n->poll_list is not empty, we need to mask irqs */
++	local_irq_save(flags);
++	list_del_init(&n->poll_list);
++	local_irq_restore(flags);
++
++	do {
++		val = READ_ONCE(n->state);
++
++		WARN_ON_ONCE(!(val & BIT(NAPI_STATE_SCHED)));
++		new = val & ~(BIT(NAPI_STATE_SCHED) |
++			      BIT(NAPI_STATE_SCHED_THREADED));
++	} while (cmpxchg(&n->state, val, new) != val);
+ }
+ EXPORT_SYMBOL(napi_complete_done);
  
- 		/* If STATE_MISSED was set, leave STATE_SCHED set,
+@@ -5053,16 +5062,25 @@ static int napi_poll(struct napi_struct
- 		 * because we will call napi->poll() one more time.
-@@ -6541,16 +6544,25 @@ static int napi_poll(struct napi_struct
  
  static int napi_thread_wait(struct napi_struct *napi)
  {

feeds/ipq807x/ipq807x/patches/214-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch

@@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6548,7 +6548,7 @@ static int napi_thread_wait(struct napi_
+@@ -5066,7 +5066,7 @@ static int napi_thread_wait(struct napi_
  
  	set_current_state(TASK_INTERRUPTIBLE);
  
@@ -43,7 +43,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* Testing SCHED_THREADED bit here to make sure the current
  		 * kthread owns this napi and could poll on this napi.
  		 * Testing SCHED bit is not enough because SCHED bit might be
-@@ -6566,6 +6566,7 @@ static int napi_thread_wait(struct napi_
+@@ -5084,6 +5084,7 @@ static int napi_thread_wait(struct napi_
  		set_current_state(TASK_INTERRUPTIBLE);
  	}
  	__set_current_state(TASK_RUNNING);

feeds/ipq807x/ipq807x/patches/220-net-sched-add-clsact-qdisc.patch

@@ -0,0 +1,439 @@
+From: Daniel Borkmann <daniel@iogearbox.net>
+Date: Thu, 7 Jan 2016 22:29:47 +0100
+Subject: [PATCH] net, sched: add clsact qdisc
+
+This work adds a generalization of the ingress qdisc as a qdisc holding
+only classifiers. The clsact qdisc works on ingress, but also on egress.
+In both cases, it's execution happens without taking the qdisc lock, and
+the main difference for the egress part compared to prior version of [1]
+is that this can be applied with _any_ underlying real egress qdisc (also
+classless ones).
+
+Besides solving the use-case of [1], that is, allowing for more programmability
+on assigning skb->priority for the mqprio case that is supported by most
+popular 10G+ NICs, it also opens up a lot more flexibility for other tc
+applications. The main work on classification can already be done at clsact
+egress time if the use-case allows and state stored for later retrieval
+f.e. again in skb->priority with major/minors (which is checked by most
+classful qdiscs before consulting tc_classify()) and/or in other skb fields
+like skb->tc_index for some light-weight post-processing to get to the
+eventual classid in case of a classful qdisc. Another use case is that
+the clsact egress part allows to have a central egress counterpart to
+the ingress classifiers, so that classifiers can easily share state (e.g.
+in cls_bpf via eBPF maps) for ingress and egress.
+
+Currently, default setups like mq + pfifo_fast would require for this to
+use, for example, prio qdisc instead (to get a tc_classify() run) and to
+duplicate the egress classifier for each queue. With clsact, it allows
+for leaving the setup as is, it can additionally assign skb->priority to
+put the skb in one of pfifo_fast's bands and it can share state with maps.
+Moreover, we can access the skb's dst entry (f.e. to retrieve tclassid)
+w/o the need to perform a skb_dst_force() to hold on to it any longer. In
+lwt case, we can also use this facility to setup dst metadata via cls_bpf
+(bpf_skb_set_tunnel_key()) without needing a real egress qdisc just for
+that (case of IFF_NO_QUEUE devices, for example).
+
+The realization can be done without any changes to the scheduler core
+framework. All it takes is that we have two a-priori defined minors/child
+classes, where we can mux between ingress and egress classifier list
+(dev->ingress_cl_list and dev->egress_cl_list, latter stored close to
+dev->_tx to avoid extra cacheline miss for moderate loads). The egress
+part is a bit similar modelled to handle_ing() and patched to a noop in
+case the functionality is not used. Both handlers are now called
+sch_handle_ingress() and sch_handle_egress(), code sharing among the two
+doesn't seem practical as there are various minor differences in both
+paths, so that making them conditional in a single handler would rather
+slow things down.
+
+Full compatibility to ingress qdisc is provided as well. Since both
+piggyback on TC_H_CLSACT, only one of them (ingress/clsact) can exist
+per netdevice, and thus ingress qdisc specific behaviour can be retained
+for user space. This means, either a user does 'tc qdisc add dev foo ingress'
+and configures ingress qdisc as usual, or the 'tc qdisc add dev foo clsact'
+alternative, where both, ingress and egress classifier can be configured
+as in the below example. ingress qdisc supports attaching classifier to any
+minor number whereas clsact has two fixed minors for muxing between the
+lists, therefore to not break user space setups, they are better done as
+two separate qdiscs.
+
+I decided to extend the sch_ingress module with clsact functionality so
+that commonly used code can be reused, the module is being aliased with
+sch_clsact so that it can be auto-loaded properly. Alternative would have been
+to add a flag when initializing ingress to alter its behaviour plus aliasing
+to a different name (as it's more than just ingress). However, the first would
+end up, based on the flag, choosing the new/old behaviour by calling different
+function implementations to handle each anyway, the latter would require to
+register ingress qdisc once again under different alias. So, this really begs
+to provide a minimal, cleaner approach to have Qdisc_ops and Qdisc_class_ops
+by its own that share callbacks used by both.
+
+Example, adding qdisc:
+
+   # tc qdisc add dev foo clsact
+   # tc qdisc show dev foo
+   qdisc mq 0: root
+   qdisc pfifo_fast 0: parent :1 bands 3 priomap  1 2 2 2 1 2 0 0 1 1 1 1 1 1 1 1
+   qdisc pfifo_fast 0: parent :2 bands 3 priomap  1 2 2 2 1 2 0 0 1 1 1 1 1 1 1 1
+   qdisc pfifo_fast 0: parent :3 bands 3 priomap  1 2 2 2 1 2 0 0 1 1 1 1 1 1 1 1
+   qdisc pfifo_fast 0: parent :4 bands 3 priomap  1 2 2 2 1 2 0 0 1 1 1 1 1 1 1 1
+   qdisc clsact ffff: parent ffff:fff1
+
+Adding filters (deleting, etc works analogous by specifying ingress/egress):
+
+   # tc filter add dev foo ingress bpf da obj bar.o sec ingress
+   # tc filter add dev foo egress  bpf da obj bar.o sec egress
+   # tc filter show dev foo ingress
+   filter protocol all pref 49152 bpf
+   filter protocol all pref 49152 bpf handle 0x1 bar.o:[ingress] direct-action
+   # tc filter show dev foo egress
+   filter protocol all pref 49152 bpf
+   filter protocol all pref 49152 bpf handle 0x1 bar.o:[egress] direct-action
+
+A 'tc filter show dev foo' or 'tc filter show dev foo parent ffff:' will
+show an empty list for clsact. Either using the parent names (ingress/egress)
+or specifying the full major/minor will then show the related filter lists.
+
+Prior work on a mqprio prequeue() facility [1] was done mainly by John Fastabend.
+
+  [1] http://patchwork.ozlabs.org/patch/512949/
+
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: John Fastabend <john.r.fastabend@intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -1770,7 +1770,9 @@ struct net_device {
+ #ifdef CONFIG_XPS
+ 	struct xps_dev_maps __rcu *xps_maps;
+ #endif
+-
++#ifdef CONFIG_NET_CLS_ACT
++	struct tcf_proto __rcu  *egress_cl_list;
++#endif
+ #ifdef CONFIG_NET_SWITCHDEV
+ 	u32			offload_fwd_mark;
+ #endif
+--- a/include/linux/rtnetlink.h
++++ b/include/linux/rtnetlink.h
+@@ -84,6 +84,11 @@ void net_inc_ingress_queue(void);
+ void net_dec_ingress_queue(void);
+ #endif
+ 
++#ifdef CONFIG_NET_EGRESS
++void net_inc_egress_queue(void);
++void net_dec_egress_queue(void);
++#endif
++
+ extern void rtnetlink_init(void);
+ extern void __rtnl_unlock(void);
+ 
+--- a/include/uapi/linux/pkt_sched.h
++++ b/include/uapi/linux/pkt_sched.h
+@@ -72,6 +72,10 @@ struct tc_estimator {
+ #define TC_H_UNSPEC	(0U)
+ #define TC_H_ROOT	(0xFFFFFFFFU)
+ #define TC_H_INGRESS    (0xFFFFFFF1U)
++#define TC_H_CLSACT	TC_H_INGRESS
++
++#define TC_H_MIN_INGRESS	0xFFF2U
++#define TC_H_MIN_EGRESS		0xFFF3U
+ 
+ /* Need to corrospond to iproute2 tc/tc_core.h "enum link_layer" */
+ enum tc_link_layer {
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -1697,6 +1697,22 @@ void net_dec_ingress_queue(void)
+ EXPORT_SYMBOL_GPL(net_dec_ingress_queue);
+ #endif
+ 
++#ifdef CONFIG_NET_EGRESS
++static struct static_key egress_needed __read_mostly;
++
++void net_inc_egress_queue(void)
++{
++	static_key_slow_inc(&egress_needed);
++}
++EXPORT_SYMBOL_GPL(net_inc_egress_queue);
++
++void net_dec_egress_queue(void)
++{
++	static_key_slow_dec(&egress_needed);
++}
++EXPORT_SYMBOL_GPL(net_dec_egress_queue);
++#endif
++
+ static struct static_key netstamp_needed __read_mostly;
+ #ifdef HAVE_JUMP_LABEL
+ static atomic_t netstamp_needed_deferred;
+@@ -2936,7 +2952,6 @@ static inline int __dev_xmit_skb(struct
+ 	bool contended;
+ 	int rc;
+ 
+-	qdisc_pkt_len_init(skb);
+ 	qdisc_calculate_pkt_len(skb, q);
+ 	/*
+ 	 * Heuristic to force contended enqueues to serialize on a
+@@ -3028,6 +3043,49 @@ int dev_loopback_xmit(struct net *net, s
+ }
+ EXPORT_SYMBOL(dev_loopback_xmit);
+ 
++#ifdef CONFIG_NET_EGRESS
++static struct sk_buff *
++sch_handle_egress(struct sk_buff *skb, int *ret, struct net_device *dev)
++{
++	struct tcf_proto *cl = rcu_dereference_bh(dev->egress_cl_list);
++	struct tcf_result cl_res;
++
++	if (!cl)
++		return skb;
++
++	/* skb->tc_verd and qdisc_skb_cb(skb)->pkt_len were already set
++	 * earlier by the caller.
++	 */
++	qdisc_bstats_cpu_update(cl->q, skb);
++
++	switch (tc_classify(skb, cl, &cl_res, false)) {
++	case TC_ACT_OK:
++	case TC_ACT_RECLASSIFY:
++		skb->tc_index = TC_H_MIN(cl_res.classid);
++		break;
++	case TC_ACT_SHOT:
++		qdisc_qstats_cpu_drop(cl->q);
++		*ret = NET_XMIT_DROP;
++		goto drop;
++	case TC_ACT_STOLEN:
++	case TC_ACT_QUEUED:
++		*ret = NET_XMIT_SUCCESS;
++drop:
++		kfree_skb(skb);
++		return NULL;
++	case TC_ACT_REDIRECT:
++		/* No need to push/pop skb's mac_header here on egress! */
++		skb_do_redirect(skb);
++		*ret = NET_XMIT_SUCCESS;
++		return NULL;
++	default:
++		break;
++	}
++
++	return skb;
++}
++#endif /* CONFIG_NET_EGRESS */
++
+ static inline int get_xps_queue(struct net_device *dev, struct sk_buff *skb)
+ {
+ #ifdef CONFIG_XPS
+@@ -3152,6 +3210,17 @@ static int __dev_queue_xmit(struct sk_bu
+ 
+ 	skb_update_prio(skb);
+ 
++	qdisc_pkt_len_init(skb);
++#ifdef CONFIG_NET_CLS_ACT
++	skb->tc_verd = SET_TC_AT(skb->tc_verd, AT_EGRESS);
++# ifdef CONFIG_NET_EGRESS
++	if (static_key_false(&egress_needed)) {
++		skb = sch_handle_egress(skb, &rc, dev);
++		if (!skb)
++			goto out;
++	}
++# endif
++#endif
+ 	/* If device/qdisc don't need skb->dst, release it right now while
+ 	 * its hot in this cpu cache.
+ 	 */
+@@ -3173,9 +3242,6 @@ static int __dev_queue_xmit(struct sk_bu
+ 	txq = netdev_pick_tx(dev, skb, accel_priv);
+ 	q = rcu_dereference_bh(txq->qdisc);
+ 
+-#ifdef CONFIG_NET_CLS_ACT
+-	skb->tc_verd = SET_TC_AT(skb->tc_verd, AT_EGRESS);
+-#endif
+ 	trace_net_dev_queue(skb);
+ 	if (q->enqueue) {
+ 		rc = __dev_xmit_skb(skb, q, dev, txq);
+@@ -3750,9 +3816,9 @@ int (*br_fdb_test_addr_hook)(struct net_
+ EXPORT_SYMBOL_GPL(br_fdb_test_addr_hook);
+ #endif
+ 
+-static inline struct sk_buff *handle_ing(struct sk_buff *skb,
+-					 struct packet_type **pt_prev,
+-					 int *ret, struct net_device *orig_dev)
++static inline struct sk_buff *
++sch_handle_ingress(struct sk_buff *skb, struct packet_type **pt_prev, int *ret,
++		   struct net_device *orig_dev)
+ {
+ #ifdef CONFIG_NET_CLS_ACT
+ 	struct tcf_proto *cl = rcu_dereference_bh(skb->dev->ingress_cl_list);
+@@ -3974,7 +4040,7 @@ another_round:
+ skip_taps:
+ #ifdef CONFIG_NET_INGRESS
+ 	if (static_key_false(&ingress_needed)) {
+-		skb = handle_ing(skb, &pt_prev, &ret, orig_dev);
++		skb = sch_handle_ingress(skb, &pt_prev, &ret, orig_dev);
+ 		if (!skb)
+ 			goto out;
+ 
+--- a/net/Kconfig
++++ b/net/Kconfig
+@@ -54,6 +54,9 @@ config COMPAT_NETLINK_MESSAGES
+ config NET_INGRESS
+ 	bool
+ 
++config NET_EGRESS
++	bool
++
+ menu "Networking options"
+ 
+ source "net/packet/Kconfig"
+--- a/net/sched/cls_bpf.c
++++ b/net/sched/cls_bpf.c
+@@ -291,7 +291,7 @@ static int cls_bpf_prog_from_efd(struct
+ 	prog->bpf_name = name;
+ 	prog->filter = fp;
+ 
+-	if (fp->dst_needed)
++	if (fp->dst_needed && !(tp->q->flags & TCQ_F_INGRESS))
+ 		netif_keep_dst(qdisc_dev(tp->q));
+ 
+ 	return 0;
+--- a/net/sched/Kconfig
++++ b/net/sched/Kconfig
+@@ -342,15 +342,21 @@ config NET_SCH_PIE
+ 	  If unsure, say N.
+ 
+ config NET_SCH_INGRESS
+-	tristate "Ingress Qdisc"
++	tristate "Ingress/classifier-action Qdisc"
+ 	depends on NET_CLS_ACT
+ 	select NET_INGRESS
++	select NET_EGRESS
+ 	---help---
+-	  Say Y here if you want to use classifiers for incoming packets.
++	  Say Y here if you want to use classifiers for incoming and/or outgoing
++	  packets. This qdisc doesn't do anything else besides running classifiers,
++	  which can also have actions attached to them. In case of outgoing packets,
++	  classifiers that this qdisc holds are executed in the transmit path
++	  before real enqueuing to an egress qdisc happens.
++
+ 	  If unsure, say Y.
+ 
+-	  To compile this code as a module, choose M here: the
+-	  module will be called sch_ingress.
++	  To compile this code as a module, choose M here: the module will be
++	  called sch_ingress with alias of sch_clsact.
+ 
+ config NET_SCH_PLUG
+ 	tristate "Plug network traffic until release (PLUG)"
+--- a/net/sched/sch_ingress.c
++++ b/net/sched/sch_ingress.c
+@@ -1,4 +1,5 @@
+-/* net/sched/sch_ingress.c - Ingress qdisc
++/* net/sched/sch_ingress.c - Ingress and clsact qdisc
++ *
+  *              This program is free software; you can redistribute it and/or
+  *              modify it under the terms of the GNU General Public License
+  *              as published by the Free Software Foundation; either version
+@@ -98,17 +99,100 @@ static struct Qdisc_ops ingress_qdisc_op
+ 	.owner		=	THIS_MODULE,
+ };
+ 
++static unsigned long clsact_get(struct Qdisc *sch, u32 classid)
++{
++	switch (TC_H_MIN(classid)) {
++	case TC_H_MIN(TC_H_MIN_INGRESS):
++	case TC_H_MIN(TC_H_MIN_EGRESS):
++		return TC_H_MIN(classid);
++	default:
++		return 0;
++	}
++}
++
++static unsigned long clsact_bind_filter(struct Qdisc *sch,
++					unsigned long parent, u32 classid)
++{
++	return clsact_get(sch, classid);
++}
++
++static struct tcf_proto __rcu **clsact_find_tcf(struct Qdisc *sch,
++						unsigned long cl)
++{
++	struct net_device *dev = qdisc_dev(sch);
++
++	switch (cl) {
++	case TC_H_MIN(TC_H_MIN_INGRESS):
++		return &dev->ingress_cl_list;
++	case TC_H_MIN(TC_H_MIN_EGRESS):
++		return &dev->egress_cl_list;
++	default:
++		return NULL;
++	}
++}
++
++static int clsact_init(struct Qdisc *sch, struct nlattr *opt)
++{
++	net_inc_ingress_queue();
++	net_inc_egress_queue();
++
++	sch->flags |= TCQ_F_CPUSTATS;
++
++	return 0;
++}
++
++static void clsact_destroy(struct Qdisc *sch)
++{
++	struct net_device *dev = qdisc_dev(sch);
++
++	tcf_destroy_chain(&dev->ingress_cl_list);
++	tcf_destroy_chain(&dev->egress_cl_list);
++
++	net_dec_ingress_queue();
++	net_dec_egress_queue();
++}
++
++static const struct Qdisc_class_ops clsact_class_ops = {
++	.leaf		=	ingress_leaf,
++	.get		=	clsact_get,
++	.put		=	ingress_put,
++	.walk		=	ingress_walk,
++	.tcf_chain	=	clsact_find_tcf,
++	.bind_tcf	=	clsact_bind_filter,
++	.unbind_tcf	=	ingress_put,
++};
++
++static struct Qdisc_ops clsact_qdisc_ops __read_mostly = {
++	.cl_ops		=	&clsact_class_ops,
++	.id		=	"clsact",
++	.init		=	clsact_init,
++	.destroy	=	clsact_destroy,
++	.dump		=	ingress_dump,
++	.owner		=	THIS_MODULE,
++};
++
+ static int __init ingress_module_init(void)
+ {
+-	return register_qdisc(&ingress_qdisc_ops);
++	int ret;
++
++	ret = register_qdisc(&ingress_qdisc_ops);
++	if (!ret) {
++		ret = register_qdisc(&clsact_qdisc_ops);
++		if (ret)
++			unregister_qdisc(&ingress_qdisc_ops);
++	}
++
++	return ret;
+ }
+ 
+ static void __exit ingress_module_exit(void)
+ {
+ 	unregister_qdisc(&ingress_qdisc_ops);
++	unregister_qdisc(&clsact_qdisc_ops);
+ }
+ 
+ module_init(ingress_module_init);
+ module_exit(ingress_module_exit);
+ 
++MODULE_ALIAS("sch_clsact");
+ MODULE_LICENSE("GPL");

feeds/ipq807x/ipq807x/patches/221-net-sched-act_mirred-Rename-tcfm_ok_push-to-tcfm_mac.patch

@@ -0,0 +1,75 @@
+From: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Date: Thu, 13 Oct 2016 09:06:41 +0300
+Subject: [PATCH] net/sched: act_mirred: Rename tcfm_ok_push to
+ tcfm_mac_header_xmit and make it a bool
+
+'tcfm_ok_push' specifies whether a mac_len sized push is needed upon
+egress to the target device (if action is performed at ingress).
+
+Rename it to 'tcfm_mac_header_xmit' as this is actually an attribute of
+the target device (and use a bool instead of int).
+
+This allows to decouple the attribute from the action to be taken.
+
+Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/include/net/tc_act/tc_mirred.h
++++ b/include/net/tc_act/tc_mirred.h
+@@ -7,7 +7,7 @@ struct tcf_mirred {
+ 	struct tcf_common	common;
+ 	int			tcfm_eaction;
+ 	int			tcfm_ifindex;
+-	int			tcfm_ok_push;
++	bool			tcfm_mac_header_xmit;
+ 	struct net_device __rcu	*tcfm_dev;
+ 	struct list_head	tcfm_list;
+ };
+--- a/net/sched/act_mirred.c
++++ b/net/sched/act_mirred.c
+@@ -55,10 +55,11 @@ static int tcf_mirred_init(struct net *n
+ 			   int bind)
+ {
+ 	struct nlattr *tb[TCA_MIRRED_MAX + 1];
++	bool mac_header_xmit = false;
+ 	struct tc_mirred *parm;
+ 	struct tcf_mirred *m;
+ 	struct net_device *dev;
+-	int ret, ok_push = 0;
++	int ret;
+ 
+ 	if (nla == NULL)
+ 		return -EINVAL;
+@@ -86,10 +87,10 @@ static int tcf_mirred_init(struct net *n
+ 		case ARPHRD_IPGRE:
+ 		case ARPHRD_VOID:
+ 		case ARPHRD_NONE:
+-			ok_push = 0;
++			mac_header_xmit = false;
+ 			break;
+ 		default:
+-			ok_push = 1;
++			mac_header_xmit = true;
+ 			break;
+ 		}
+ 	} else {
+@@ -123,7 +124,7 @@ static int tcf_mirred_init(struct net *n
+ 			dev_put(rcu_dereference_protected(m->tcfm_dev, 1));
+ 		dev_hold(dev);
+ 		rcu_assign_pointer(m->tcfm_dev, dev);
+-		m->tcfm_ok_push = ok_push;
++		m->tcfm_mac_header_xmit = mac_header_xmit;
+ 	}
+ 
+ 	if (ret == ACT_P_CREATED) {
+@@ -169,7 +170,7 @@ static int tcf_mirred(struct sk_buff *sk
+ 		goto out;
+ 
+ 	if (!(at & AT_EGRESS)) {
+-		if (m->tcfm_ok_push)
++		if (m->tcfm_mac_header_xmit)
+ 			skb_push_rcsum(skb2, skb->mac_len);
+ 	}
+ 

feeds/ipq807x/ipq807x/patches/222-net-sched-act_mirred-Refactor-detection-whether-dev-.patch

@@ -0,0 +1,36 @@
+From: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Date: Thu, 13 Oct 2016 09:06:42 +0300
+Subject: [PATCH] net/sched: act_mirred: Refactor detection whether dev needs
+ xmit at mac header
+
+Move detection logic that tests whether device expects skb data to point
+at mac_header upon xmit into a function.
+
+Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/net/sched/act_mirred.c
++++ b/net/sched/act_mirred.c
+@@ -80,19 +80,7 @@ static int tcf_mirred_init(struct net *n
+ 		dev = __dev_get_by_index(net, parm->ifindex);
+ 		if (dev == NULL)
+ 			return -ENODEV;
+-		switch (dev->type) {
+-		case ARPHRD_TUNNEL:
+-		case ARPHRD_TUNNEL6:
+-		case ARPHRD_SIT:
+-		case ARPHRD_IPGRE:
+-		case ARPHRD_VOID:
+-		case ARPHRD_NONE:
+-			mac_header_xmit = false;
+-			break;
+-		default:
+-			mac_header_xmit = true;
+-			break;
+-		}
++		mac_header_xmit = dev_is_mac_header_xmit(dev);
+ 	} else {
+ 		dev = NULL;
+ 	}

feeds/ipq807x/ipq807x/patches/223-net-sched-act_mirred-Implement-ingress-actions.patch

@@ -0,0 +1,125 @@
+From: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Date: Thu, 13 Oct 2016 09:06:44 +0300
+Subject: [PATCH] net/sched: act_mirred: Implement ingress actions
+
+Up until now, 'action mirred' supported only egress actions (either
+TCA_EGRESS_REDIR or TCA_EGRESS_MIRROR).
+
+This patch implements the corresponding ingress actions
+TCA_INGRESS_REDIR and TCA_INGRESS_MIRROR.
+
+This allows attaching filters whose target is to hand matching skbs into
+the rx processing of a specified device.
+
+Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
+Cc: Jamal Hadi Salim <jhs@mojatatu.com>
+Cc: Eric Dumazet <eric.dumazet@gmail.com>
+Cc: Cong Wang <xiyou.wangcong@gmail.com>
+Tested-by: Jamal Hadi Salim <jhs@mojatatu.com>
+Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/net/sched/act_mirred.c
++++ b/net/sched/act_mirred.c
+@@ -33,6 +33,25 @@
+ static LIST_HEAD(mirred_list);
+ static DEFINE_SPINLOCK(mirred_list_lock);
+ 
++static bool tcf_mirred_is_act_redirect(int action)
++{
++	return action == TCA_EGRESS_REDIR || action == TCA_INGRESS_REDIR;
++}
++
++static u32 tcf_mirred_act_direction(int action)
++{
++	switch (action) {
++	case TCA_EGRESS_REDIR:
++	case TCA_EGRESS_MIRROR:
++		return AT_EGRESS;
++	case TCA_INGRESS_REDIR:
++	case TCA_INGRESS_MIRROR:
++		return AT_INGRESS;
++	default:
++		BUG();
++	}
++}
++
+ static void tcf_mirred_release(struct tc_action *a, int bind)
+ {
+ 	struct tcf_mirred *m = to_mirred(a);
+@@ -72,6 +91,8 @@ static int tcf_mirred_init(struct net *n
+ 	switch (parm->eaction) {
+ 	case TCA_EGRESS_MIRROR:
+ 	case TCA_EGRESS_REDIR:
++	case TCA_INGRESS_REDIR:
++	case TCA_INGRESS_MIRROR:
+ 		break;
+ 	default:
+ 		return -EINVAL;
+@@ -129,9 +150,12 @@ static int tcf_mirred(struct sk_buff *sk
+ 		      struct tcf_result *res)
+ {
+ 	struct tcf_mirred *m = a->priv;
++	bool m_mac_header_xmit;
+ 	struct net_device *dev;
+ 	struct sk_buff *skb2;
+-	int retval, err;
++	int retval, err = 0;
++	int m_eaction;
++	int mac_len;
+ 	u32 at;
+ 
+ 	tcf_lastuse_update(&m->tcf_tm);
+@@ -139,6 +163,8 @@ static int tcf_mirred(struct sk_buff *sk
+ 	bstats_cpu_update(this_cpu_ptr(m->common.cpu_bstats), skb);
+ 
+ 	rcu_read_lock();
++	m_mac_header_xmit = READ_ONCE(m->tcfm_mac_header_xmit);
++	m_eaction = READ_ONCE(m->tcfm_eaction);
+ 	retval = READ_ONCE(m->tcf_action);
+ 	dev = rcu_dereference(m->tcfm_dev);
+ 	if (unlikely(!dev)) {
+@@ -157,24 +183,37 @@ static int tcf_mirred(struct sk_buff *sk
+ 	if (!skb2)
+ 		goto out;
+ 
+-	if (!(at & AT_EGRESS)) {
+-		if (m->tcfm_mac_header_xmit)
++	/* If action's target direction differs than filter's direction,
++	 * and devices expect a mac header on xmit, then mac push/pull is
++	 * needed.
++	 */
++	if (at != tcf_mirred_act_direction(m_eaction) && m_mac_header_xmit) {
++		if (at & AT_EGRESS) {
++			/* caught at egress, act ingress: pull mac */
++			mac_len = skb_network_header(skb) - skb_mac_header(skb);
++			skb_pull_rcsum(skb2, mac_len);
++		} else {
++			/* caught at ingress, act egress: push mac */
+ 			skb_push_rcsum(skb2, skb->mac_len);
++		}
+ 	}
+ 
+ 	/* mirror is always swallowed */
+-	if (m->tcfm_eaction != TCA_EGRESS_MIRROR)
++	if (tcf_mirred_is_act_redirect(m_eaction))
+ 		skb2->tc_verd = SET_TC_FROM(skb2->tc_verd, at);
+ 
+ 	skb2->skb_iif = skb->dev->ifindex;
+ 	skb2->dev = dev;
+ 	skb_sender_cpu_clear(skb2);
+-	err = dev_queue_xmit(skb2);
++	if (tcf_mirred_act_direction(m_eaction) & AT_EGRESS)
++		err = dev_queue_xmit(skb2);
++	else
++		err = netif_receive_skb(skb2);
+ 
+ 	if (err) {
+ out:
+ 		qstats_overlimit_inc(this_cpu_ptr(m->common.cpu_qstats));
+-		if (m->tcfm_eaction != TCA_EGRESS_MIRROR)
++		if (tcf_mirred_is_act_redirect(m_eaction))
+ 			retval = TC_ACT_SHOT;
+ 	}
+ 	rcu_read_unlock();

feeds/ipq807x/kmod-sched-cake/Makefile

@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2016 LEDE
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=sched-cake
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=https://github.com/dtaht/sch_cake.git
+PKG_MIRROR_HASH:=8bb4fa43368be5b5839a350419701b0bb3881b1641e037affea42630d75e56e6
+PKG_SOURCE_DATE:=2021-07-09
+PKG_SOURCE_VERSION:=d9e1398cc9091e9e7c7a740361e4617b75c24427
+#PKG_MIRROR_HASH:=5bf06a804824db36ae393fc174aeec7b12633176e05a765c0931b39df5bd34df
+PKG_MAINTAINER:=Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
+
+include $(INCLUDE_DIR)/package.mk
+
+define KernelPackage/sched-cake
+  SUBMENU:=Network Support
+  TITLE:=Cake fq_codel/blue derived shaper
+  URL:=https://github.com/dtaht/sch_cake
+  FILES:=$(PKG_BUILD_DIR)/sch_cake.ko
+  AUTOLOAD:=$(call AutoLoad,75,sch_cake)
+  DEPENDS:=+kmod-ipt-conntrack
+endef
+
+include $(INCLUDE_DIR)/kernel-defaults.mk
+
+define KernelPackage/sched-cake/description
+  Common Applications Kept Enhanced fq_codel/blue derived shaper
+endef
+
+define Build/Compile
+	$(KERNEL_MAKE) SUBDIRS="$(PKG_BUILD_DIR)" modules
+endef
+
+$(eval $(call KernelPackage,sched-cake))

feeds/ipq807x/kmod-sched-cake/patches/100-compat.patch

@@ -0,0 +1,20 @@
+Index: sched-cake-2021-07-09-d9e1398c/cobalt_compat.h
+===================================================================
+--- sched-cake-2021-07-09-d9e1398c.orig/cobalt_compat.h
++++ sched-cake-2021-07-09-d9e1398c/cobalt_compat.h
+@@ -95,15 +95,6 @@ static inline unsigned int __tcp_hdrlen(
+ }
+ #endif
+ 
+-#if KERNEL_VERSION(4, 6, 0) > LINUX_VERSION_CODE
+-static inline int skb_try_make_writable(struct sk_buff *skb,
+-					unsigned int write_len)
+-{
+-	return skb_cloned(skb) && !skb_clone_writable(skb, write_len) &&
+-	       pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
+-}
+-#endif
+-
+ #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
+ static inline int skb_mac_offset(const struct sk_buff *skb)
+ {

feeds/ipq807x/qca-nss-clients/Makefile

@@ -5,9 +5,9 @@ PKG_NAME:=qca-nss-clients
 PKG_SOURCE_PROTO:=git
 PKG_BRANCH:=master
 PKG_RELEASE:=2
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-clients
+PKG_SOURCE_URL:=https://source.codeaurora.org/quic/qsdk/oss/lklm/nss-clients/
-PKG_MIRROR_HASH:=95bae8cc23fe950aae5d6b6fd402b6ab4339782ffb08eb29d249105fcb9022bf
+PKG_MIRROR_HASH:=802bf8b2dac8da0549e108b873afd982d127370c07d6574ece71f902eafe7698
-PKG_VERSION:=30742bb1decd5fe7b4e01be8081ab0a99c1f6888
+PKG_VERSION:=153998d70fdba508a59a28c13a606032cbf32686
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
@@ -602,7 +602,6 @@ define Build/Compile
 		SoC="$(subtarget)" \
 		DTLSMGR_DIR="$(DTLSMGR_DIR)" \
 		IPSECMGR_DIR="$(IPSECMGR_DIR)" \
-		KBUILD_MODPOST_WARN=1 \
 		modules
 endef
 

feeds/ipq807x/qca-nss-dp/Makefile

@@ -5,13 +5,6 @@ PKG_NAME:=qca-nss-dp
 PKG_SOURCE_PROTO:=git
 PKG_BRANCH:=master
 PKG_RELEASE:=1
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp
-PKG_MIRROR_HASH:=dc5e870bf781d052399e8bbc0aa3d6593abeeff29304b64c685584f09fd29519
-PKG_VERSION:=480f036cc96d4e5faa426cfcf90fa7e64dff87e8
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=$(PKG_VERSION)
 
 include $(INCLUDE_DIR)/package.mk
 
@@ -19,8 +12,7 @@ define KernelPackage/qca-nss-dp
   SECTION:=kernel
   CATEGORY:=Kernel modules
   SUBMENU:=Network Devices
-  DEPENDS:=@TARGET_ipq807x||TARGET_ipq_ipq807x_64||TARGET_ipq807x||TARGET_ipq_ipq60xx||TARGET_ipq_ipq60xx_64||TARGET_ipq60xx||TARGET_ipq_ipq50xx||TARGET_ipq_ipq50xx_64||TARGET_ipq50xx\
+  DEPENDS:=@TARGET_ipq807x +kmod-qca-ssdk
-		+kmod-qca-ssdk
   TITLE:=Kernel driver for NSS data plane
   FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko
   AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp)
@@ -44,7 +36,7 @@ NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal
 hal_arch:=$(subtarget)
 
 define Build/Configure
-	$(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(hal_arch)/nss_$(hal_arch).h \
+	$(LN) $(NSS_DP_HAL_DIR)/arch/$(hal_arch)/nss_$(hal_arch).h \
 		$(PKG_BUILD_DIR)/exports/nss_dp_arch.h
 endef
 
@@ -53,8 +45,7 @@ define Build/Compile
 		CROSS_COMPILE="$(TARGET_CROSS)" \
 		ARCH="$(LINUX_KARCH)" \
 		M="$(PKG_BUILD_DIR)" \
-		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(hal_arch)" \
+		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC="$(subtarget)" \
-		KBUILD_MODPOST_WARN=1 \
 		modules
 endef
 

feeds/ipq807x/qca-nss-dp/Makefile.orig

@@ -1,59 +0,0 @@
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=qca-nss-dp
-PKG_SOURCE_PROTO:=git
-PKG_BRANCH:=master
-PKG_RELEASE:=1
-PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp
-PKG_MIRROR_HASH:=dc5e870bf781d052399e8bbc0aa3d6593abeeff29304b64c685584f09fd29519
-PKG_VERSION:=480f036cc96d4e5faa426cfcf90fa7e64dff87e8
-
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=$(PKG_VERSION)
-
-include $(INCLUDE_DIR)/package.mk
-
-define KernelPackage/qca-nss-dp
-  SECTION:=kernel
-  CATEGORY:=Kernel modules
-  SUBMENU:=Network Devices
-  DEPENDS:=@TARGET_ipq807x +kmod-qca-ssdk
-  TITLE:=Kernel driver for NSS data plane
-  FILES:=$(PKG_BUILD_DIR)/qca-nss-dp.ko
-  AUTOLOAD:=$(call AutoLoad,31,qca-nss-dp)
-endef
-
-define KernelPackage/qca-nss-dp/Description
-This package contains a NSS data plane driver for QCA chipset
-endef
-
-define Build/InstallDev
-	mkdir -p $(1)/usr/include/qca-nss-dp
-	$(CP) $(PKG_BUILD_DIR)/exports/* $(1)/usr/include/qca-nss-dp/
-endef
-
-EXTRA_CFLAGS+= \
-	-I$(STAGING_DIR)/usr/include/qca-ssdk
-
-subtarget:=$(SUBTARGET)
-
-NSS_DP_HAL_DIR:=$(PKG_BUILD_DIR)/hal
-hal_arch:=$(subtarget)
-
-define Build/Configure
-	$(LN) $(NSS_DP_HAL_DIR)/soc_ops/$(hal_arch)/nss_$(hal_arch).h \
-		$(PKG_BUILD_DIR)/exports/nss_dp_arch.h
-endef
-
-define Build/Compile
-	$(MAKE) -C "$(LINUX_DIR)" \
-		CROSS_COMPILE="$(TARGET_CROSS)" \
-		ARCH="$(LINUX_KARCH)" \
-		M="$(PKG_BUILD_DIR)" \
-		EXTRA_CFLAGS="$(EXTRA_CFLAGS)" SoC=""$(subtarget)"" \
-		modules
-endef
-
-$(eval $(call KernelPackage,qca-nss-dp))

feeds/ipq807x/qca-nss-dp/src/Makefile

@@ -0,0 +1,56 @@
+###################################################
+# Makefile for the NSS data plane driver
+###################################################
+
+obj ?= .
+
+obj-m += qca-nss-dp.o
+
+qca-nss-dp-objs += nss_dp_attach.o \
+		   nss_dp_ethtools.o \
+		   nss_dp_main.o
+
+ifneq ($(CONFIG_NET_SWITCHDEV),)
+qca-nss-dp-objs += nss_dp_switchdev.o
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+qca-nss-dp-objs += hal/edma/edma_cfg.o \
+		   hal/edma/edma_data_plane.o \
+		   hal/edma/edma_tx_rx.o \
+		   hal/gmac_hal_ops/qcom/qcom_if.o \
+		   hal/gmac_hal_ops/syn/xgmac/syn_if.o
+endif
+
+NSS_DP_INCLUDE = -I$(obj)/include -I$(obj)/exports -I$(obj)/gmac_hal_ops/include \
+		 -I$(obj)/hal/include
+
+ifeq ($(SoC),$(filter $(SoC),ipq50xx ipq50xx_64))
+NSS_DP_INCLUDE += -I$(obj)/hal/gmac_hal_ops/syn/gmac
+endif
+
+ccflags-y += $(NSS_DP_INCLUDE)
+ccflags-y += -Wall -Werror
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64 ipq60xx ipq60xx_64))
+ccflags-y += -DNSS_DP_PPE_SUPPORT
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64))
+qca-nss-dp-objs += hal/arch/ipq60xx/nss_ipq60xx.o
+ccflags-y += -DNSS_DP_IPQ60XX
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq807x ipq807x_64))
+qca-nss-dp-objs += hal/arch/ipq807x/nss_ipq807x.o
+ccflags-y += -DNSS_DP_IPQ807X -DNSS_DP_EDMA_TX_SMALL_PKT_WAR
+endif
+
+ifeq ($(SoC),$(filter $(SoC),ipq50xx ipq50xx_64))
+qca-nss-dp-objs += hal/arch/ipq50xx/nss_ipq50xx.o \
+		   hal/gmac_hal_ops/syn/gmac/syn_if.o \
+		   hal/syn_gmac_dp/syn_data_plane.o \
+		   hal/syn_gmac_dp/syn_dp_tx_rx.o \
+		   hal/syn_gmac_dp/syn_dp_cfg.o
+ccflags-y += -DNSS_DP_IPQ50XX
+endif

feeds/ipq807x/qca-nss-dp/src/exports/nss_dp_api_if.h

@@ -0,0 +1,219 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_dp_api_if.h
+ *	nss-dp exported structures/apis.
+ *
+ * This file declares all the public interfaces
+ * for NSS data-plane driver.
+ */
+
+#ifndef __NSS_DP_API_IF_H
+#define __NSS_DP_API_IF_H
+
+#include "nss_dp_arch.h"
+
+/**
+ * @addtogroup nss_dp_subsystem
+ * @{
+ */
+
+/*
+ * NSS DP status
+ */
+#define NSS_DP_SUCCESS	0
+#define NSS_DP_FAILURE	-1
+
+/*
+ * NSS DP platform specific defines
+ */
+#define NSS_DP_START_IFNUM	NSS_DP_HAL_START_IFNUM
+			/**< First GMAC interface number (0/1) depending on SoC. */
+#define NSS_DP_MAX_MTU_SIZE	NSS_DP_HAL_MAX_MTU_SIZE
+#define NSS_DP_MAX_PACKET_LEN	NSS_DP_HAL_MAX_PACKET_LEN
+#define NSS_DP_MAX_INTERFACES	(NSS_DP_HAL_MAX_PORTS + NSS_DP_HAL_START_IFNUM)
+			/**< Last interface index for the SoC, to be used by qca-nss-drv. */
+
+/*
+ * NSS PTP service code
+ */
+#define NSS_PTP_EVENT_SERVICE_CODE	0x9
+
+/**
+ * nss_dp_data_plane_ctx
+ *	Data plane context base class.
+ */
+struct nss_dp_data_plane_ctx {
+	struct net_device *dev;
+};
+
+/**
+ * nss_dp_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_gmac_stats {
+	struct nss_dp_hal_gmac_stats stats;
+};
+
+/**
+ * nss_dp_data_plane_ops
+ *	Per data-plane ops structure.
+ *
+ * Default would be slowpath and can be overridden by nss-drv
+ */
+struct nss_dp_data_plane_ops {
+	int (*init)(struct nss_dp_data_plane_ctx *dpc);
+	int (*open)(struct nss_dp_data_plane_ctx *dpc, uint32_t tx_desc_ring,
+		    uint32_t rx_desc_ring, uint32_t mode);
+	int (*close)(struct nss_dp_data_plane_ctx *dpc);
+	int (*link_state)(struct nss_dp_data_plane_ctx *dpc,
+			  uint32_t link_state);
+	int (*mac_addr)(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr);
+	int (*change_mtu)(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu);
+	netdev_tx_t (*xmit)(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *os_buf);
+	void (*set_features)(struct nss_dp_data_plane_ctx *dpc);
+	int (*pause_on_off)(struct nss_dp_data_plane_ctx *dpc,
+			    uint32_t pause_on);
+	int (*vsi_assign)(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi);
+	int (*vsi_unassign)(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi);
+	int (*rx_flow_steer)(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+				uint32_t cpu, bool is_add);
+	void (*get_stats)(struct nss_dp_data_plane_ctx *dpc, struct nss_dp_gmac_stats *stats);
+	int (*deinit)(struct nss_dp_data_plane_ctx *dpc);
+};
+
+/**
+ * nss_dp_receive
+ *	Called by overlay drivers to deliver packets to nss-dp.
+ *
+ * @datatypes
+ * net_device
+ * sk_buff
+ * napi_struct
+ *
+ * @param[in] netdev Pointer to netdev structure on which packet is received.
+ * @param[in] skb Pointer to the received packet.
+ * @param[in] napi Pointer to napi context.
+ */
+void nss_dp_receive(struct net_device *netdev, struct sk_buff *skb,
+						struct napi_struct *napi);
+
+/**
+ * nss_dp_is_in_open_state
+ *	Returns if a data plane is opened or not.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ *
+ * @return
+ * bool
+ */
+bool nss_dp_is_in_open_state(struct net_device *netdev);
+
+/**
+ * nss_dp_override_data_palne
+ *	API to allow overlay drivers to override the data plane.
+ *
+ * @datatypes
+ * net_device
+ * nss_dp_data_plane_ops
+ * nss_dp_data_plane_ctx
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ * @param[in] dp_ops Pointer to respective data plane ops structure.
+ * @param[in] dpc Pointer to data plane context.
+ *
+ * @return
+ * int
+ */
+int nss_dp_override_data_plane(struct net_device *netdev,
+			       struct nss_dp_data_plane_ops *dp_ops,
+			       struct nss_dp_data_plane_ctx *dpc);
+
+/**
+ * nss_dp_start_data_plane
+ *	Dataplane API to inform netdev when it is ready to start.
+ *
+ * @datatypes
+ * net_device
+ * nss_dp_data_plane_ctx
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ * @param[in] dpc Pointer to data plane context.
+ */
+void nss_dp_start_data_plane(struct net_device *netdev,
+			     struct nss_dp_data_plane_ctx *dpc);
+
+/**
+ * nss_dp_restore_data_plane
+ *	Called by overlay drivers to detach itself from nss-dp.
+ *
+ * @datatypes
+ * net_device
+ *
+ * @param[in] netdev Pointer to netdev structure.
+ */
+void nss_dp_restore_data_plane(struct net_device *netdev);
+
+/**
+ * nss_dp_get_netdev_by_nss_if_num
+ *	Returns the net device of the corresponding id if it exists.
+ *
+ * @datatypes
+ * int
+ *
+ * @param[in] interface ID of the physical mac port.
+ *
+ * @return
+ * Pointer to netdev structure.
+ */
+struct net_device *nss_dp_get_netdev_by_nss_if_num(int if_num);
+
+/**
+ * nss_phy_tstamp_rx_buf
+ *	Receive timestamp packet.
+ *
+ * @datatypes
+ * sk_buff
+ *
+ * @param[in] app_data Pointer to the application context of the message.
+ * @param[in] skb Pointer to the packet.
+ */
+void nss_phy_tstamp_rx_buf(void *app_data, struct sk_buff *skb);
+
+/**
+ * nss_phy_tstamp_tx_buf
+ *	Transmit timestamp packet
+ *
+ * @datatypes
+ * net_device
+ * sk_buff
+ *
+ * @param[in] net_device Pointer to netdev structure.
+ * @param[in] skb Pointer to the packet.
+ */
+void nss_phy_tstamp_tx_buf(struct net_device *ndev, struct sk_buff *skb);
+
+/**
+ *@}
+ */
+
+#endif	/** __NSS_DP_API_IF_H */

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq50xx/nss_ipq50xx.c

@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/ioport.h>
+#include <linux/qcom_scm.h>
+#include "nss_dp_hal.h"
+
+/*
+ * nss_dp_hal_tcsr_base_get
+ *	Reads TCSR base address from DTS
+ */
+static uint32_t nss_dp_hal_tcsr_base_get(void)
+{
+	uint32_t tcsr_base_addr = 0;
+	struct device_node *dp_cmn;
+
+	/*
+	 * Get reference to NSS dp common device node
+	 */
+	dp_cmn = of_find_node_by_name(NULL, "nss-dp-common");
+	if (!dp_cmn) {
+		pr_info("%s: NSS DP common node not found\n", __func__);
+		return 0;
+	}
+
+	if (of_property_read_u32(dp_cmn, "qcom,tcsr-base", &tcsr_base_addr)) {
+		pr_err("%s: error reading TCSR base\n", __func__);
+	}
+	of_node_put(dp_cmn);
+
+	return tcsr_base_addr;
+}
+
+/*
+ * nss_dp_hal_tcsr_set
+ *	Sets the TCSR axi cache override register
+ */
+static void nss_dp_hal_tcsr_set(void)
+{
+	void __iomem *tcsr_addr = NULL;
+	uint32_t tcsr_base;
+	int err;
+
+	tcsr_base = nss_dp_hal_tcsr_base_get();
+	if (!tcsr_base) {
+		pr_err("%s: Unable to get TCSR base address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Check if Trust Zone is enabled in the system.
+	 * If yes, we need to go through SCM API call to program TCSR register.
+	 * If TZ is not enabled, we can write to the register directly.
+	 */
+	if (qcom_scm_is_available()) {
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0))
+		err = qcom_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+#else
+		err = qti_scm_tcsr_reg_write((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE);
+#endif
+		if (err) {
+			pr_err("%s: SCM TCSR write error: %d\n", __func__, err);
+		}
+	} else {
+		tcsr_addr = ioremap_nocache((tcsr_base + TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET),
+						TCSR_GMAC_AXI_CACHE_OVERRIDE_REG_SIZE);
+		if (!tcsr_addr) {
+			pr_err("%s: ioremap failed\n", __func__);
+			return;
+		}
+		writel(TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE, tcsr_addr);
+		iounmap(tcsr_addr);
+	}
+}
+
+/*
+ * nss_dp_hal_get_data_plane_ops
+ *	Return the data plane ops for GMAC data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_gmac_ops;
+}
+
+/*
+ * nss_dp_hal_clk_enable
+ *	Function to enable GCC_SNOC_GMAC_AXI_CLK.
+ *
+ * These clocks are required for GMAC operations.
+ */
+void nss_dp_hal_clk_enable(struct nss_dp_dev *dp_priv)
+{
+	struct platform_device *pdev = dp_priv->pdev;
+	struct device *dev = &pdev->dev;
+	struct clk *gmac_clk = NULL;
+	int err;
+
+	gmac_clk = devm_clk_get(dev, NSS_SNOC_GMAC_AXI_CLK);
+	if (IS_ERR(gmac_clk)) {
+		pr_err("%s: cannot get clock: %s\n", __func__,
+						NSS_SNOC_GMAC_AXI_CLK);
+		return;
+	}
+
+	err = clk_prepare_enable(gmac_clk);
+	if (err) {
+		pr_err("%s: cannot enable clock: %s, err: %d\n", __func__,
+						NSS_SNOC_GMAC_AXI_CLK, err);
+		return;
+	}
+}
+
+/*
+ * nss_dp_hal_init
+ *	Sets the gmac ops based on the GMAC type.
+ */
+bool nss_dp_hal_init(void)
+{
+	nss_dp_hal_set_gmac_ops(&syn_hal_ops, GMAC_HAL_TYPE_SYN_GMAC);
+
+	/*
+	 * Program the global GMAC AXI Cache override register
+	 * for optimized AXI DMA operation.
+	 */
+	nss_dp_hal_tcsr_set();
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup
+ *	Sets the gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_GMAC);
+}

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq50xx/nss_ipq50xx.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS			2
+#define NSS_DP_HAL_CPU_NUM			2
+#define NSS_DP_HAL_START_IFNUM			0
+#define NSS_DP_GMAC_NORMAL_FRAME_MTU		1500
+#define NSS_DP_GMAC_MINI_JUMBO_FRAME_MTU	1978
+#define NSS_DP_GMAC_FULL_JUMBO_FRAME_MTU	9000
+#define NSS_DP_HAL_MAX_MTU_SIZE			NSS_DP_GMAC_FULL_JUMBO_FRAME_MTU
+#define NSS_DP_HAL_MAX_PACKET_LEN		65535
+
+/*
+ * TCSR_GMAC_AXI_CACHE_OVERRIDE register size
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_REG_SIZE	4
+
+/*
+ * TCSR_GMAC_AXI_CACHE_OVERRIDE Register offset
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_OFFSET	0x6224
+
+/*
+ * Value for TCSR_GMAC_AXI_CACHE_OVERRIDE register
+ */
+#define TCSR_GMAC_AXI_CACHE_OVERRIDE_VALUE	0x05050505
+
+/*
+ * GCC_SNOC_GMAC_AXI_CLOCK
+ */
+#define NSS_SNOC_GMAC_AXI_CLK			"nss-snoc-gmac-axi-clk"
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+	uint64_t rx_bytes;		/**< Number of RX bytes */
+	uint64_t rx_packets;		/**< Number of RX packets */
+	uint64_t rx_errors;		/**< Number of RX errors */
+	uint64_t rx_receive_errors;	/**< Number of RX receive errors */
+	uint64_t rx_descriptor_errors;	/**< Number of RX descriptor errors */
+	uint64_t rx_late_collision_errors;
+					/**< Number of RX late collision errors */
+	uint64_t rx_dribble_bit_errors;	/**< Number of RX dribble bit errors */
+	uint64_t rx_length_errors;	/**< Number of RX length errors */
+	uint64_t rx_ip_header_errors;	/**< Number of RX IP header errors read from rxdec */
+	uint64_t rx_ip_payload_errors;	/**< Number of RX IP payload errors */
+	uint64_t rx_no_buffer_errors;	/**< Number of RX no-buffer errors */
+	uint64_t rx_transport_csum_bypassed;
+					/**< Number of RX packets where the transport checksum was bypassed */
+	uint64_t tx_bytes;		/**< Number of TX bytes */
+	uint64_t tx_packets;		/**< Number of TX packets */
+	uint64_t tx_collisions;		/**< Number of TX collisions */
+	uint64_t tx_errors;		/**< Number of TX errors */
+	uint64_t tx_jabber_timeout_errors;
+					/**< Number of TX jabber timeout errors */
+	uint64_t tx_frame_flushed_errors;
+					/**< Number of TX frame flushed errors */
+	uint64_t tx_loss_of_carrier_errors;
+					/**< Number of TX loss of carrier errors */
+	uint64_t tx_no_carrier_errors;	/**< Number of TX no carrier errors */
+	uint64_t tx_late_collision_errors;
+					/**< Number of TX late collision errors */
+	uint64_t tx_excessive_collision_errors;
+					/**< Number of TX excessive collision errors */
+	uint64_t tx_excessive_deferral_errors;
+					/**< Number of TX excessive deferral errors */
+	uint64_t tx_underflow_errors;	/**< Number of TX underflow errors */
+	uint64_t tx_ip_header_errors;	/**< Number of TX IP header errors */
+	uint64_t tx_ip_payload_errors;	/**< Number of TX IP payload errors */
+	uint64_t tx_dropped;		/**< Number of TX dropped packets */
+	uint64_t hw_errs[10];		/**< GMAC DMA error counters */
+	uint64_t rx_missed;		/**< Number of RX packets missed by the DMA */
+	uint64_t fifo_overflows;	/**< Number of RX FIFO overflows signalled by the DMA */
+	uint64_t rx_scatter_errors;	/**< Number of scattered frames received by the DMA */
+	uint64_t tx_ts_create_errors;	/**< Number of tx timestamp creation errors */
+	uint64_t gmac_total_ticks;	/**< Total clock ticks spend inside the GMAC */
+	uint64_t gmac_worst_case_ticks;	/**< Worst case iteration of the GMAC in ticks */
+	uint64_t gmac_iterations;	/**< Number of iterations around the GMAC */
+	uint64_t tx_pause_frames;	/**< Number of pause frames sent by the GMAC */
+	uint64_t mmc_rx_overflow_errors;
+					/**< Number of RX overflow errors */
+	uint64_t mmc_rx_watchdog_timeout_errors;
+					/**< Number of RX watchdog timeout errors */
+	uint64_t mmc_rx_crc_errors;	/**< Number of RX CRC errors */
+	uint64_t mmc_rx_ip_header_errors;
+					/**< Number of RX IP header errors read from MMC counter*/
+	uint64_t mmc_rx_octets_g;
+					/**< Number of good octets received */
+	uint64_t mmc_rx_ucast_frames;	/**< Number of Unicast frames received */
+	uint64_t mmc_rx_bcast_frames;	/**< Number of Bcast frames received */
+	uint64_t mmc_rx_mcast_frames;	/**< Number of Mcast frames received */
+	uint64_t mmc_rx_undersize;
+					/**< Number of RX undersize frames */
+	uint64_t mmc_rx_oversize;
+					/**< Number of RX oversize frames */
+	uint64_t mmc_rx_jabber;		/**< Number of jabber frames */
+	uint64_t mmc_rx_octets_gb;
+					/**< Number of good/bad octets */
+	uint64_t mmc_rx_frag_frames_g;	/**< Number of good ipv4 frag frames */
+	uint64_t mmc_tx_octets_g;	/**< Number of good octets sent */
+	uint64_t mmc_tx_ucast_frames;	/**< Number of Unicast frames sent*/
+	uint64_t mmc_tx_bcast_frames;	/**< Number of Broadcast frames sent */
+	uint64_t mmc_tx_mcast_frames;	/**< Number of Multicast frames sent */
+	uint64_t mmc_tx_deferred;	/**< Number of Deferred frames sent */
+	uint64_t mmc_tx_single_col;	/**< Number of single collisions */
+	uint64_t mmc_tx_multiple_col;	/**< Number of multiple collisions */
+	uint64_t mmc_tx_octets_gb;	/**< Number of good/bad octets sent*/
+};
+
+extern struct nss_dp_data_plane_ops nss_dp_gmac_ops;
+
+#endif /* __NSS_DP_ARCH_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq60xx/nss_ipq60xx.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_dp_hal.h"
+#include "edma.h"
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for edma data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_edma_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Initialize EDMA and set gmac ops.
+ */
+bool nss_dp_hal_init(void)
+{
+	nss_dp_hal_set_gmac_ops(&qcom_hal_ops, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(&syn_hal_ops, GMAC_HAL_TYPE_SYN_XGMAC);
+
+	if (edma_init()) {
+		return false;
+	}
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Cleanup EDMA and set gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_XGMAC);
+	edma_cleanup(false);
+}

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq60xx/nss_ipq60xx.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS		5
+#define NSS_DP_HAL_CPU_NUM		4
+#define NSS_DP_HAL_START_IFNUM		1
+#define NSS_DP_HAL_MAX_MTU_SIZE		9216
+#define NSS_DP_HAL_MAX_PACKET_LEN	65535
+#define NSS_DP_PREHEADER_SIZE		32
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+};
+
+#endif /* __NSS_DP_ARCH_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq807x/nss_ipq807x.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "nss_dp_hal.h"
+#include "edma.h"
+
+/*
+ * nss_dp_hal_get_data_plane_ops()
+ *	Return the data plane ops for edma data plane.
+ */
+struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void)
+{
+	return &nss_dp_edma_ops;
+}
+
+/*
+ * nss_dp_hal_init()
+ *	Initialize EDMA and set gmac ops.
+ */
+bool nss_dp_hal_init(void)
+{
+	nss_dp_hal_set_gmac_ops(&qcom_hal_ops, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(&syn_hal_ops, GMAC_HAL_TYPE_SYN_XGMAC);
+
+	if (edma_init()) {
+		return false;
+	}
+	return true;
+}
+
+/*
+ * nss_dp_hal_cleanup()
+ *	Cleanup EDMA and set gmac ops to NULL.
+ */
+void nss_dp_hal_cleanup(void)
+{
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_QCOM);
+	nss_dp_hal_set_gmac_ops(NULL, GMAC_HAL_TYPE_SYN_XGMAC);
+	edma_cleanup(false);
+}

feeds/ipq807x/qca-nss-dp/src/hal/arch/ipq807x/nss_ipq807x.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_ARCH_H__
+#define __NSS_DP_ARCH_H__
+
+#define NSS_DP_HAL_MAX_PORTS		6
+#define NSS_DP_HAL_CPU_NUM		4
+#define NSS_DP_HAL_START_IFNUM		1
+#define NSS_DP_HAL_MAX_MTU_SIZE		9216
+#define NSS_DP_HAL_MAX_PACKET_LEN	65535
+#define NSS_DP_PREHEADER_SIZE		32
+
+/**
+ * nss_dp_hal_gmac_stats
+ *	The per-GMAC statistics structure.
+ */
+struct nss_dp_hal_gmac_stats {
+};
+
+#endif /* __NSS_DP_ARCH_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/edma/edma_cfg.c

@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <linux/reset.h>
+
+#include "nss_dp_dev.h"
+#include "edma_regs.h"
+#include "edma_data_plane.h"
+
+#define EDMA_HW_RESET_ID "edma_rst"
+
+/*
+ * edma_cleanup_rxfill_ring_res()
+ *	Cleanup resources for one RxFill ring
+ */
+static void edma_cleanup_rxfill_ring_res(struct edma_hw *ehw,
+				struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	uint16_t cons_idx, curr_idx;
+	struct edma_rxfill_desc *rxfill_desc;
+	uint32_t reg_data = 0;
+	struct edma_rx_preheader *rxph = NULL;
+	int store_idx;
+
+	/*
+	 * Read RXFILL ring producer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id));
+	curr_idx = reg_data & EDMA_RXFILL_PROD_IDX_MASK;
+
+	/*
+	 * Read RXFILL ring consumer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->id));
+	cons_idx = reg_data & EDMA_RXFILL_CONS_IDX_MASK;
+
+	while (curr_idx != cons_idx) {
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, cons_idx);
+
+		/*
+		 * Get Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxfill_desc->buffer_addr);
+
+		dma_unmap_single(&pdev->dev, rxfill_desc->buffer_addr,
+					EDMA_RX_BUFF_SIZE, DMA_FROM_DEVICE);
+
+		/*
+		 * Get sk_buff and free it
+		 */
+		store_idx = rxph->opaque;
+		skb = ehw->rx_skb_store[store_idx];
+		ehw->rx_skb_store[store_idx] = NULL;
+		dev_kfree_skb_any(skb);
+		cons_idx++;
+		if (cons_idx == rxfill_ring->count)
+			cons_idx = 0;
+	}
+
+	/*
+	 * Free RXFILL ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_rxfill_desc)
+				* rxfill_ring->count),
+				rxfill_ring->desc, rxfill_ring->dma);
+}
+
+/*
+ * edma_setup_rxfill_ring_res()
+ *	Setup resources for one RxFill ring
+ */
+static int edma_setup_rxfill_ring_res(struct edma_hw *ehw,
+				struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate RxFill ring descriptors
+	 */
+	rxfill_ring->desc = dma_alloc_coherent(&pdev->dev,
+				(sizeof(struct edma_rxfill_desc)
+				* rxfill_ring->count),
+				&rxfill_ring->dma, GFP_KERNEL);
+	if (!rxfill_ring->desc) {
+		pr_warn("Descriptor alloc for RXFILL ring %u failed\n",
+				rxfill_ring->id);
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&rxfill_ring->lock);
+	return 0;
+}
+
+/*
+ * edma_setup_rxdesc_ring_res()
+ *	Setup resources for one RxDesc ring
+ */
+static int edma_setup_rxdesc_ring_res(struct edma_hw *ehw,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	rxdesc_ring->desc = dma_alloc_coherent(&pdev->dev,
+				(sizeof(struct edma_rxdesc_desc)
+				* rxdesc_ring->count),
+				&rxdesc_ring->dma, GFP_KERNEL);
+	if (!rxdesc_ring->desc) {
+		pr_warn("Descriptor alloc for RXDESC ring %u failed\n",
+				rxdesc_ring->id);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cleanup_rxdesc_ring_res()
+ *	Cleanup resources for RxDesc ring
+ */
+static void edma_cleanup_rxdesc_ring_res(struct edma_hw *ehw,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	struct edma_rxdesc_desc *rxdesc_desc;
+	struct edma_rx_preheader *rxph = NULL;
+	uint16_t prod_idx = 0;
+	uint16_t cons_idx = 0;
+	int store_idx;
+
+	cons_idx = edma_reg_read(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id))
+					& EDMA_RXDESC_CONS_IDX_MASK;
+
+	prod_idx = edma_reg_read(EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id))
+					& EDMA_RXDESC_PROD_IDX_MASK;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	while (cons_idx != prod_idx) {
+		rxdesc_desc = EDMA_RXDESC_DESC(rxdesc_ring, cons_idx);
+
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxdesc_desc->buffer_addr);
+
+		dma_unmap_single(&pdev->dev, rxdesc_desc->buffer_addr,
+					EDMA_RX_BUFF_SIZE, DMA_FROM_DEVICE);
+		store_idx = rxph->opaque;
+		skb = ehw->rx_skb_store[store_idx];
+		ehw->rx_skb_store[store_idx] = NULL;
+		dev_kfree_skb_any(skb);
+
+		/*
+		 * Update consumer index
+		 */
+		if (++cons_idx == rxdesc_ring->count)
+			cons_idx = 0;
+	}
+
+	/*
+	 * Free RXDESC ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_rxdesc_desc)
+				* rxdesc_ring->count),
+				rxdesc_ring->desc, rxdesc_ring->dma);
+}
+
+/*
+ * edma_cleanup_txcmpl_ring_res()
+ *	Cleanup resources for one TxCmpl ring
+ */
+static void edma_cleanup_txcmpl_ring_res(struct edma_hw *ehw,
+				struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	edma_clean_tx(ehw, txcmpl_ring);
+
+	/*
+	 * Free TxCmpl ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+				(sizeof(struct edma_txcmpl_desc)
+				* txcmpl_ring->count),
+				txcmpl_ring->desc, txcmpl_ring->dma);
+}
+
+/*
+ * edma_setup_txcmpl_ring_res()
+ *	Setup resources for one TxCmpl ring
+ */
+static int edma_setup_txcmpl_ring_res(struct edma_hw *ehw,
+				struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate TxCmpl ring descriptors
+	 */
+	txcmpl_ring->desc = dma_alloc_coherent(&pdev->dev,
+					(sizeof(struct edma_txcmpl_desc)
+					* txcmpl_ring->count),
+					&txcmpl_ring->dma, GFP_KERNEL);
+
+	if (!txcmpl_ring->desc) {
+		pr_warn("Descriptor alloc for TXCMPL ring %u failed\n",
+				txcmpl_ring->id);
+
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_cleanup_txdesc_ring_res()
+ *	Cleanup resources for one TxDesc ring
+ */
+static void edma_cleanup_txdesc_ring_res(struct edma_hw *ehw,
+				struct edma_txdesc_ring *txdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb = NULL;
+	struct edma_txdesc_desc *txdesc = NULL;
+	uint16_t prod_idx, cons_idx;
+	size_t buf_len;
+	uint32_t data;
+	int store_idx;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	prod_idx = data & EDMA_TXDESC_PROD_IDX_MASK;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	cons_idx = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	while (cons_idx != prod_idx) {
+		txdesc = EDMA_TXDESC_DESC(txdesc_ring, cons_idx);
+		store_idx = txdesc->buffer_addr;
+		skb = ehw->tx_skb_store[store_idx];
+		ehw->tx_skb_store[store_idx] = NULL;
+
+		buf_len = (txdesc->word1 & EDMA_TXDESC_DATA_LENGTH_MASK) >>
+				EDMA_TXDESC_DATA_LENGTH_SHIFT;
+
+		dma_unmap_single(&pdev->dev, (dma_addr_t)skb->data,
+				buf_len + EDMA_TX_PREHDR_SIZE, DMA_TO_DEVICE);
+
+		dev_kfree_skb_any(skb);
+		cons_idx = (cons_idx + 1) & (txdesc_ring->count - 1);
+		cons_idx++;
+		if (cons_idx == txdesc_ring->count)
+			cons_idx = 0;
+
+	}
+
+	/*
+	 * Free Tx ring descriptors
+	 */
+	dma_free_coherent(&pdev->dev,
+			  (sizeof(struct edma_txdesc_desc)
+			   * txdesc_ring->count),
+			   txdesc_ring->desc, txdesc_ring->dma);
+
+}
+
+/*
+ * edma_setup_txdesc_ring_res()
+ *	Setup resources for one TxDesc ring
+ */
+static int edma_setup_txdesc_ring_res(struct edma_hw *ehw,
+				struct edma_txdesc_ring *txdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+
+	/*
+	 * Allocate Tx ring descriptors
+	 */
+	txdesc_ring->desc = dma_alloc_coherent(&pdev->dev,
+					(sizeof(struct edma_txdesc_desc)
+					* txdesc_ring->count),
+					&txdesc_ring->dma, GFP_KERNEL);
+	if (!txdesc_ring->desc) {
+		pr_warn("Descriptor alloc for TXDESC ring %u failed\n",
+				txdesc_ring->id);
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&txdesc_ring->tx_lock);
+
+	return 0;
+}
+
+/*
+ * edma_setup_ring_resources()
+ *	Allocate/setup resources for EDMA rings
+ */
+static int edma_setup_ring_resources(struct edma_hw *ehw)
+{
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_txdesc_ring *txdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	int i;
+	int ret;
+	int index;
+
+	/*
+	 * Allocate TxDesc ring descriptors
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++) {
+		txdesc_ring = &ehw->txdesc_ring[i];
+		txdesc_ring->count = EDMA_RING_SIZE;
+		txdesc_ring->id = ehw->txdesc_ring_start + i;
+
+		ret = edma_setup_txdesc_ring_res(ehw, txdesc_ring);
+		if (ret != 0) {
+			while (i-- >= 0)
+				edma_cleanup_txdesc_ring_res(ehw,
+					&ehw->txdesc_ring[i]);
+
+			return -ENOMEM;
+
+		}
+	}
+
+	/*
+	 * Allocate TxCmpl ring descriptors
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		txcmpl_ring->count = EDMA_RING_SIZE;
+		txcmpl_ring->id = ehw->txcmpl_ring_start + i;
+
+		ret = edma_setup_txcmpl_ring_res(ehw, txcmpl_ring);
+
+		if (ret != 0) {
+			while (i-- >= 0)
+				edma_cleanup_txcmpl_ring_res(ehw,
+						&ehw->txcmpl_ring[i]);
+
+			goto txcmpl_mem_alloc_fail;
+		}
+	}
+
+	/*
+	 * Allocate Rx fill ring descriptors
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		rxfill_ring->count = EDMA_RING_SIZE;
+		rxfill_ring->id = ehw->rxfill_ring_start + i;
+
+		ret = edma_setup_rxfill_ring_res(ehw, rxfill_ring);
+		if (ret != 0) {
+			while (--i >= 0)
+				edma_cleanup_rxfill_ring_res(ehw,
+					&ehw->rxfill_ring[i]);
+
+			goto rxfill_mem_alloc_fail;
+		}
+	}
+
+	/*
+	 * Allocate RxDesc ring descriptors
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		rxdesc_ring->count = EDMA_RING_SIZE;
+		rxdesc_ring->id = ehw->rxdesc_ring_start + i;
+
+		/*
+		 * Create a mapping between RX Desc ring and Rx fill ring.
+		 * Number of fill rings are lesser than the descriptor rings
+		 * Share the fill rings across descriptor rings.
+		 */
+
+		index = ehw->rxfill_ring_start + (i % ehw->rxfill_rings);
+		rxdesc_ring->rxfill =
+			&ehw->rxfill_ring[index - ehw->rxfill_ring_start];
+
+		ret = edma_setup_rxdesc_ring_res(ehw, rxdesc_ring);
+		if (ret != 0) {
+			while (--i >= 0)
+				edma_cleanup_rxdesc_ring_res(ehw,
+						&ehw->rxdesc_ring[i]);
+
+			goto rxdesc_mem_alloc_fail;
+		}
+	}
+
+	return 0;
+
+rxdesc_mem_alloc_fail:
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_cleanup_rxfill_ring_res(ehw, &ehw->rxfill_ring[i]);
+
+rxfill_mem_alloc_fail:
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_cleanup_txcmpl_ring_res(ehw, &ehw->txcmpl_ring[i]);
+
+txcmpl_mem_alloc_fail:
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_cleanup_txdesc_ring_res(ehw, &ehw->txdesc_ring[i]);
+
+	return -ENOMEM;
+}
+
+/*
+ * edma_free_rings()
+ *	Free EDMA software rings
+ */
+static void edma_free_rings(struct edma_hw *ehw)
+{
+	kfree(ehw->rxfill_ring);
+	kfree(ehw->rxdesc_ring);
+	kfree(ehw->txdesc_ring);
+	kfree(ehw->txcmpl_ring);
+}
+
+/*
+ * edma_alloc_rings()
+ *	Allocate EDMA software rings
+ */
+static int edma_alloc_rings(struct edma_hw *ehw)
+{
+	ehw->rxfill_ring = kzalloc((sizeof(struct edma_rxfill_ring) *
+				ehw->rxfill_rings), GFP_KERNEL);
+	if (!ehw->rxfill_ring)
+		return -ENOMEM;
+
+	ehw->rxdesc_ring = kzalloc((sizeof(struct edma_rxdesc_ring) *
+				ehw->rxdesc_rings), GFP_KERNEL);
+	if (!ehw->rxdesc_ring)
+		goto rxdesc_ring_alloc_fail;
+
+	ehw->txdesc_ring = kzalloc((sizeof(struct edma_txdesc_ring) *
+				ehw->txdesc_rings), GFP_KERNEL);
+	if (!ehw->txdesc_ring)
+		goto txdesc_ring_alloc_fail;
+
+	ehw->txcmpl_ring = kzalloc((sizeof(struct edma_txcmpl_ring) *
+				ehw->txcmpl_rings), GFP_KERNEL);
+	if (!ehw->txcmpl_ring)
+		goto txcmpl_ring_alloc_fail;
+
+	pr_info("Num rings - TxDesc:%u (%u-%u) TxCmpl:%u (%u-%u)\n",
+			ehw->txdesc_rings, ehw->txdesc_ring_start,
+			(ehw->txdesc_ring_start + ehw->txdesc_rings - 1),
+			ehw->txcmpl_rings, ehw->txcmpl_ring_start,
+			(ehw->txcmpl_ring_start + ehw->txcmpl_rings - 1));
+
+	pr_info("RxDesc:%u (%u-%u) RxFill:%u (%u-%u)\n",
+		ehw->rxdesc_rings, ehw->rxdesc_ring_start,
+		(ehw->rxdesc_ring_start + ehw->rxdesc_rings - 1),
+		ehw->rxfill_rings, ehw->rxfill_ring_start,
+		(ehw->rxfill_ring_start + ehw->rxfill_rings - 1));
+
+	return 0;
+txcmpl_ring_alloc_fail:
+	kfree(ehw->txdesc_ring);
+txdesc_ring_alloc_fail:
+	kfree(ehw->rxdesc_ring);
+rxdesc_ring_alloc_fail:
+	kfree(ehw->rxfill_ring);
+	return -ENOMEM;
+}
+
+/*
+ * edma_cleanup_rings()
+ *	Cleanup EDMA rings
+ */
+void edma_cleanup_rings(struct edma_hw *ehw)
+{
+	int i;
+
+	/*
+	 * Free any buffers assigned to any descriptors
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_cleanup_txdesc_ring_res(ehw, &ehw->txdesc_ring[i]);
+
+	/*
+	 * Free Tx completion descriptors
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_cleanup_txcmpl_ring_res(ehw, &ehw->txcmpl_ring[i]);
+
+	/*
+	 * Free Rx fill ring descriptors
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_cleanup_rxfill_ring_res(ehw, &ehw->rxfill_ring[i]);
+
+	/*
+	 * Free Rx completion ring descriptors
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++)
+		edma_cleanup_rxdesc_ring_res(ehw, &ehw->rxdesc_ring[i]);
+
+	edma_free_rings(ehw);
+}
+
+/*
+ * edma_init_rings()
+ *	Initialize EDMA rings
+ */
+static int edma_init_rings(struct edma_hw *ehw)
+{
+	int ret = 0;
+
+	ret = edma_alloc_rings(ehw);
+	if (ret)
+		return ret;
+
+	ret = edma_setup_ring_resources(ehw);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/*
+ * edma_configure_txdesc_ring()
+ *	Configure one TxDesc ring
+ */
+static void edma_configure_txdesc_ring(struct edma_hw *ehw,
+					struct edma_txdesc_ring *txdesc_ring)
+{
+	uint32_t data = 0;
+	uint16_t hw_cons_idx = 0;
+
+	/*
+	 * Configure TXDESC ring
+	 */
+	edma_reg_write(EDMA_REG_TXDESC_BA(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->dma &
+			EDMA_RING_DMA_MASK));
+
+	edma_reg_write(EDMA_REG_TXDESC_RING_SIZE(txdesc_ring->id),
+			(uint32_t)(txdesc_ring->count &
+			EDMA_TXDESC_RING_SIZE_MASK));
+
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	data &= ~(EDMA_TXDESC_CONS_IDX_MASK);
+	hw_cons_idx = data;
+
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	data &= ~(EDMA_TXDESC_PROD_IDX_MASK);
+	data |= hw_cons_idx & EDMA_TXDESC_PROD_IDX_MASK;
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id), data);
+}
+
+/*
+ * edma_configure_txcmpl_ring()
+ *	Configure one TxCmpl ring
+ */
+static void edma_configure_txcmpl_ring(struct edma_hw *ehw,
+					struct edma_txcmpl_ring *txcmpl_ring)
+{
+	uint32_t tx_mod_timer;
+
+	/*
+	 * Configure TxCmpl ring base address
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_BA(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->dma & EDMA_RING_DMA_MASK));
+	edma_reg_write(EDMA_REG_TXCMPL_RING_SIZE(txcmpl_ring->id),
+			(uint32_t)(txcmpl_ring->count
+			& EDMA_TXDESC_RING_SIZE_MASK));
+
+	/*
+	 * Set TxCmpl ret mode to opaque
+	 */
+	edma_reg_write(EDMA_REG_TXCMPL_CTRL(txcmpl_ring->id),
+			EDMA_TXCMPL_RETMODE_OPAQUE);
+
+	tx_mod_timer = (EDMA_TX_MOD_TIMER & EDMA_TX_MOD_TIMER_INIT_MASK)
+			<< EDMA_TX_MOD_TIMER_INIT_SHIFT;
+	edma_reg_write(EDMA_REG_TX_MOD_TIMER(txcmpl_ring->id),
+				tx_mod_timer);
+
+	edma_reg_write(EDMA_REG_TX_INT_CTRL(txcmpl_ring->id), 0x2);
+}
+
+/*
+ * edma_configure_rxdesc_ring()
+ *	Configure one RxDesc ring
+ */
+static void edma_configure_rxdesc_ring(struct edma_hw *ehw,
+					struct edma_rxdesc_ring *rxdesc_ring)
+{
+	uint32_t data;
+
+	edma_reg_write(EDMA_REG_RXDESC_BA(rxdesc_ring->id),
+			(uint32_t)(rxdesc_ring->dma & 0xffffffff));
+
+	data = rxdesc_ring->count & EDMA_RXDESC_RING_SIZE_MASK;
+	data |= (ehw->rx_payload_offset & EDMA_RXDESC_PL_OFFSET_MASK)
+		 << EDMA_RXDESC_PL_OFFSET_SHIFT;
+	edma_reg_write(EDMA_REG_RXDESC_RING_SIZE(rxdesc_ring->id), data);
+
+	data = (EDMA_RX_MOD_TIMER_INIT & EDMA_RX_MOD_TIMER_INIT_MASK)
+			<< EDMA_RX_MOD_TIMER_INIT_SHIFT;
+	edma_reg_write(EDMA_REG_RX_MOD_TIMER(rxdesc_ring->id), data);
+
+	/*
+	 * Enable ring. Set ret mode to 'opaque'.
+	 */
+	edma_reg_write(EDMA_REG_RX_INT_CTRL(rxdesc_ring->id), 0x2);
+}
+
+/*
+ * edma_configure_rxfill_ring()
+ *	Configure one RxFill ring
+ */
+static void edma_configure_rxfill_ring(struct edma_hw *ehw,
+					struct edma_rxfill_ring *rxfill_ring)
+{
+	uint32_t data = 0;
+
+	edma_reg_write(EDMA_REG_RXFILL_BA(rxfill_ring->id),
+			(uint32_t)(rxfill_ring->dma & EDMA_RING_DMA_MASK));
+
+	data = rxfill_ring->count & EDMA_RXFILL_RING_SIZE_MASK;
+	edma_reg_write(EDMA_REG_RXFILL_RING_SIZE(rxfill_ring->id), data);
+
+	/*
+	 * Alloc Rx buffers
+	 */
+	edma_alloc_rx_buffer(ehw, rxfill_ring);
+}
+
+/*
+ * edma_configure_rings()
+ *	Configure EDMA rings
+ */
+static void edma_configure_rings(struct edma_hw *ehw)
+{
+	int i = 0;
+
+	/*
+	 * Initialize the store
+	 */
+	for (i = 0; i < EDMA_RING_SIZE; i++) {
+		ehw->tx_skb_store[i] = NULL;
+		ehw->rx_skb_store[i] = NULL;
+	}
+
+	/*
+	 * Configure TXDESC ring
+	 */
+	for (i = 0; i < ehw->txdesc_rings; i++)
+		edma_configure_txdesc_ring(ehw, &ehw->txdesc_ring[i]);
+
+	/*
+	 * Configure TXCMPL ring
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++)
+		edma_configure_txcmpl_ring(ehw, &ehw->txcmpl_ring[i]);
+
+	/*
+	 * Configure RXFILL rings
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++)
+		edma_configure_rxfill_ring(ehw, &ehw->rxfill_ring[i]);
+
+	/*
+	 * Configure RXDESC ring
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++)
+		edma_configure_rxdesc_ring(ehw, &ehw->rxdesc_ring[i]);
+}
+
+/*
+ * edma_hw_reset()
+ *	Reset EDMA Hardware during initialization
+ */
+int edma_hw_reset(struct edma_hw *ehw)
+{
+	struct reset_control *rst;
+	struct platform_device *pdev = ehw->pdev;
+
+	rst = devm_reset_control_get(&pdev->dev, EDMA_HW_RESET_ID);
+	if (IS_ERR(rst)) {
+		pr_warn("DTS Node: %s does not exist\n", EDMA_HW_RESET_ID);
+		return -EINVAL;
+	}
+
+	reset_control_assert(rst);
+	udelay(100);
+
+	reset_control_deassert(rst);
+	udelay(100);
+
+	pr_info("EDMA HW Reset completed succesfully\n");
+
+	return 0;
+}
+
+/*
+ * edma_hw_init()
+ *	EDMA hw init
+ */
+int edma_hw_init(struct edma_hw *ehw)
+{
+	int ret = 0;
+	int desc_index;
+	uint32_t i, data, reg = 0;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+	data = edma_reg_read(EDMA_REG_MAS_CTRL);
+	pr_info("EDMA ver %d hw init\n", data);
+
+	/*
+	 * Setup private data structure
+	 */
+	ehw->misc_intr_mask = 0x0;
+	ehw->rxfill_intr_mask = EDMA_RXFILL_INT_MASK;
+	ehw->rxdesc_intr_mask = EDMA_RXDESC_INT_MASK_PKT_INT;
+	ehw->txcmpl_intr_mask = EDMA_TX_INT_MASK_PKT_INT |
+				EDMA_TX_INT_MASK_UGT_INT;
+	ehw->rx_payload_offset = EDMA_RX_PREHDR_SIZE;
+	ehw->active = 0;
+	ehw->edma_initialized = false;
+
+	/* Reset EDMA */
+	ret = edma_hw_reset(ehw);
+	if (ret)
+		return ret;
+
+	/*
+	 * Disable interrupts
+	 */
+	for (i = 0; i < EDMA_MAX_TXCMPL_RINGS; i++)
+		edma_reg_write(EDMA_REG_TX_INT_MASK(i), 0);
+
+	for (i = 0; i < EDMA_MAX_RXFILL_RINGS; i++)
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(i), 0);
+
+	for (i = 0; i < EDMA_MAX_RXDESC_RINGS; i++)
+		edma_reg_write(EDMA_REG_RX_INT_CTRL(i), 0);
+
+	/*
+	 * Disable Rx rings
+	 */
+	for (i = 0; i < EDMA_MAX_RXDESC_RINGS; i++) {
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(i));
+		data &= ~EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), data);
+	}
+
+	/*
+	 * Disable RxFill Rings
+	 */
+	for (i = 0; i < EDMA_MAX_RXFILL_RINGS; i++) {
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(i));
+		data &= ~EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), data);
+	}
+
+	/*
+	 * Disable Tx rings
+	 */
+	for (desc_index = 0; desc_index < EDMA_MAX_TXDESC_RINGS; desc_index++) {
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(desc_index));
+		data &= ~EDMA_TXDESC_TX_EN;
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(desc_index), data);
+	}
+
+#if defined(NSS_DP_IPQ807X)
+	/*
+	 * Clear the TXDESC2CMPL_MAP_xx reg before setting up
+	 * the mapping. This register holds TXDESC to TXFILL ring
+	 * mapping.
+	 */
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_1, 0);
+	edma_reg_write(EDMA_REG_TXDESC2CMPL_MAP_2, 0);
+	desc_index = ehw->txcmpl_ring_start;
+
+	/*
+	 * 3 registers to hold the completion mapping for total 24
+	 * TX desc rings (0-9,10-19 and rest). In each entry 3 bits hold
+	 * the mapping for a particular TX desc ring.
+	 */
+	for (i = ehw->txdesc_ring_start;
+		i < ehw->txdesc_ring_end; i++) {
+		if (i >= 0 && i <= 9)
+			reg = EDMA_REG_TXDESC2CMPL_MAP_0;
+		else if (i >= 10 && i <= 19)
+			reg = EDMA_REG_TXDESC2CMPL_MAP_1;
+		else
+			reg = EDMA_REG_TXDESC2CMPL_MAP_2;
+
+		pr_debug("Configure TXDESC:%u to use TXCMPL:%u\n",
+				i, desc_index);
+
+		data = edma_reg_read(reg);
+		data |= (desc_index & 0x7) << ((i % 10) * 3);
+		edma_reg_write(reg, data);
+
+		desc_index++;
+		if (desc_index == ehw->txcmpl_ring_end)
+				desc_index = ehw->txcmpl_ring_start;
+	}
+#endif
+
+	/*
+	 * Set PPE QID to EDMA Rx ring mapping.
+	 * When coming up use only queue 0.
+	 * HOST EDMA rings. FW EDMA comes up and overwrites as required.
+	 * Each entry can hold mapping for 8 PPE queues and entry size is
+	 * 4 bytes
+	 */
+	desc_index = ehw->rxdesc_ring_start;
+	data = 0;
+	data |= (desc_index & 0xF);
+	edma_reg_write(EDMA_QID2RID_TABLE_MEM(0), data);
+	pr_debug("Configure QID2RID reg:0x%x to 0x%x\n", reg, data);
+
+	ret = edma_init_rings(ehw);
+	if (ret)
+		return ret;
+
+	edma_configure_rings(ehw);
+
+	/*
+	 * Set RXDESC2FILL_MAP_xx reg.
+	 * There are two registers RXDESC2FILL_0 and RXDESC2FILL_1
+	 * 3 bits holds the rx fill ring mapping for each of the
+	 * rx descriptor ring.
+	 */
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_0, 0);
+	edma_reg_write(EDMA_REG_RXDESC2FILL_MAP_1, 0);
+	for (i = ehw->rxdesc_ring_start;
+			i < ehw->rxdesc_ring_end; i++) {
+		if ((i >= 0) && (i <= 9))
+			reg = EDMA_REG_RXDESC2FILL_MAP_0;
+		else
+			reg = EDMA_REG_RXDESC2FILL_MAP_1;
+
+		rxdesc_ring = &ehw->rxdesc_ring[i - ehw->rxdesc_ring_start];
+
+		pr_debug("Configure RXDESC:%u to use RXFILL:%u\n",
+				rxdesc_ring->id, rxdesc_ring->rxfill->id);
+
+		data = edma_reg_read(reg);
+		data |= (rxdesc_ring->rxfill->id & 0x7) << ((i % 10) * 3);
+		edma_reg_write(reg, data);
+	}
+
+	reg = EDMA_REG_RXDESC2FILL_MAP_0;
+	pr_debug("EDMA_REG_RXDESC2FILL_MAP_0: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_RXDESC2FILL_MAP_1;
+	pr_debug("EDMA_REG_RXDESC2FILL_MAP_1: 0x%x\n", edma_reg_read(reg));
+
+#if defined(NSS_DP_IPQ807X)
+	reg = EDMA_REG_TXDESC2CMPL_MAP_0;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_0: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_TXDESC2CMPL_MAP_1;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_1: 0x%x\n", edma_reg_read(reg));
+	reg = EDMA_REG_TXDESC2CMPL_MAP_2;
+	pr_debug("EDMA_REG_TXDESC2CMPL_MAP_2: 0x%x\n", edma_reg_read(reg));
+#endif
+
+	/*
+	 * Configure DMA request priority, DMA read burst length,
+	 * and AXI write size.
+	 */
+	data = EDMA_DMAR_BURST_LEN_SET(EDMA_BURST_LEN_ENABLE)
+		| EDMA_DMAR_REQ_PRI_SET(0)
+		| EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(31)
+		| EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(7)
+		| EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(7);
+	edma_reg_write(EDMA_REG_DMAR_CTRL, data);
+#if defined(NSS_DP_IPQ60XX)
+	data = edma_reg_read(EDMA_REG_AXIW_CTRL);
+	data |= EDMA_AXIW_MAX_WR_SIZE_EN;
+	edma_reg_write(EDMA_REG_AXIW_CTRL, data);
+#endif
+
+	/*
+	 * Misc error mask
+	 */
+	data = EDMA_MISC_AXI_RD_ERR_MASK_EN |
+		EDMA_MISC_AXI_WR_ERR_MASK_EN |
+		EDMA_MISC_RX_DESC_FIFO_FULL_MASK_EN |
+		EDMA_MISC_RX_ERR_BUF_SIZE_MASK_EN |
+		EDMA_MISC_TX_SRAM_FULL_MASK_EN |
+		EDMA_MISC_TX_CMPL_BUF_FULL_MASK_EN |
+		EDMA_MISC_DATA_LEN_ERR_MASK_EN;
+#if defined(NSS_DP_IPQ807X)
+	data |= EDMA_MISC_PKT_LEN_LA_64K_MASK_EN |
+		 EDMA_MISC_PKT_LEN_LE_40_MASK_EN;
+#else
+	data |= EDMA_MISC_TX_TIMEOUT_MASK_EN;
+#endif
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, data);
+
+	/*
+	 * Global EDMA enable and padding enable
+	 */
+	data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN;
+	edma_reg_write(EDMA_REG_PORT_CTRL, data);
+
+	/*
+	 * Enable Rx rings
+	 */
+	for (i = ehw->rxdesc_ring_start; i < ehw->rxdesc_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_RXDESC_CTRL(i));
+		data |= EDMA_RXDESC_RX_EN;
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), data);
+	}
+
+	for (i = ehw->rxfill_ring_start; i < ehw->rxfill_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_RXFILL_RING_EN(i));
+		data |= EDMA_RXFILL_RING_EN;
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), data);
+	}
+
+	/*
+	 * Enable Tx rings
+	 */
+	for (i = ehw->txdesc_ring_start; i < ehw->txdesc_ring_end; i++) {
+		data = edma_reg_read(EDMA_REG_TXDESC_CTRL(i));
+		data |= EDMA_TXDESC_TX_EN;
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(i), data);
+	}
+
+	ehw->edma_initialized = true;
+
+	return 0;
+}

feeds/ipq807x/qca-nss-dp/src/hal/edma/edma_data_plane.c

@@ -0,0 +1,962 @@
+/*
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <fal/fal_vsi.h>
+
+#include "nss_dp_dev.h"
+#include "edma_regs.h"
+#include "edma_data_plane.h"
+
+/*
+ * EDMA hardware instance
+ */
+struct edma_hw edma_hw;
+
+/*
+ * edma_get_port_num_from_netdev()
+ *	Get port number from net device
+ */
+static int edma_get_port_num_from_netdev(struct net_device *netdev)
+{
+	int i;
+
+	for (i = 0; i < EDMA_MAX_GMACS; i++) {
+		/* In the port-id to netdev mapping table, port-id
+		 * starts from 1 and table index starts from 0.
+		 * So we return index + 1 for port-id
+		 */
+		if (edma_hw.netdev_arr[i] == netdev)
+			return i+1;
+	}
+
+	return -1;
+}
+
+/*
+ * edma_reg_read()
+ *	Read EDMA register
+ */
+uint32_t edma_reg_read(uint32_t reg_off)
+{
+	return (uint32_t)readl(edma_hw.reg_base + reg_off);
+}
+
+/*
+ * edma_reg_write()
+ *	Write EDMA register
+ */
+void edma_reg_write(uint32_t reg_off, uint32_t val)
+{
+	writel(val, edma_hw.reg_base + reg_off);
+}
+
+/*
+ * edma_disable_interrupts()
+ *	Disable EDMA RX/TX interrupt masks.
+ */
+static void edma_disable_interrupts(void)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	int i;
+
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		rxfill_ring = &edma_hw.rxfill_ring[i];
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	/*
+	 * Clear MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_CLEAR);
+}
+
+/*
+ * edma_enable_interrupts()
+ *	Enable RX/TX EDMA interrupt masks.
+ */
+static void edma_enable_interrupts(void)
+{
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	int i;
+
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		rxfill_ring = &edma_hw.rxfill_ring[i];
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+				edma_hw.rxfill_intr_mask);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				edma_hw.txcmpl_intr_mask);
+	}
+
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+				edma_hw.rxdesc_intr_mask);
+	}
+
+	/*
+	 * Enable MISC interrupt mask.
+	 */
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, edma_hw.misc_intr_mask);
+}
+
+/*
+ * nss_dp_edma_if_open()
+ *	Do slow path data plane open
+ */
+static int edma_if_open(struct nss_dp_data_plane_ctx *dpc,
+			uint32_t tx_desc_ring, uint32_t rx_desc_ring,
+			uint32_t mode)
+{
+	if (!dpc->dev)
+		return NSS_DP_FAILURE;
+
+	/*
+	 * Enable NAPI
+	 */
+	if (edma_hw.active++ != 0)
+		return NSS_DP_SUCCESS;
+
+	napi_enable(&edma_hw.napi);
+
+	/*
+	 * Enable the interrupt masks.
+	 */
+	edma_enable_interrupts();
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_close()
+ *	Do slow path data plane close
+ */
+static int edma_if_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	if (--edma_hw.active != 0)
+		return NSS_DP_SUCCESS;
+
+	/*
+	 * Disable the interrupt masks.
+	 */
+	edma_disable_interrupts();
+
+	/*
+	 * Disable NAPI
+	 */
+	napi_disable(&edma_hw.napi);
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_link_state()
+ */
+static int edma_if_link_state(struct nss_dp_data_plane_ctx *dpc,
+			      uint32_t link_state)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_mac_addr()
+ */
+static int edma_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_change_mtu()
+ */
+static int edma_if_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_xmit()
+ *	Transmit a packet using EDMA
+ */
+static netdev_tx_t edma_if_xmit(struct nss_dp_data_plane_ctx *dpc,
+				struct sk_buff *skb)
+{
+	struct net_device *netdev = dpc->dev;
+	int ret;
+	uint32_t tx_ring, skbq, nhead, ntail;
+	bool expand_skb = false;
+
+	if (skb->len < ETH_HLEN) {
+		netdev_dbg(netdev, "skb->len < ETH_HLEN\n");
+		goto drop;
+	}
+
+	/*
+	 * Select a Tx ring
+	 */
+	skbq = skb_get_queue_mapping(skb);
+	tx_ring = 0;
+	if ((edma_hw.txdesc_rings > 1) && (skbq > 0))
+		tx_ring = edma_hw.txdesc_rings % skbq;
+
+	/*
+	 * Check for non-linear skb
+	 */
+	if (skb_is_nonlinear(skb)) {
+		netdev_dbg(netdev, "cannot Tx non-linear skb:%px\n", skb);
+		goto drop;
+	}
+
+	/*
+	 * Check for headroom/tailroom and clone
+	 */
+	nhead = netdev->needed_headroom;
+	ntail = netdev->needed_tailroom;
+
+	if (skb_cloned(skb) ||
+		(skb_headroom(skb) < nhead) ||
+		(skb_headroom(skb) < ntail)) {
+		expand_skb = true;
+	}
+
+	/*
+	 * Expand the skb. This also unclones a cloned skb.
+	 */
+	if (expand_skb && pskb_expand_head(skb, nhead, ntail, GFP_ATOMIC)) {
+		netdev_dbg(netdev, "cannot expand skb:%px\n", skb);
+		goto drop;
+	}
+
+	/*
+	 * Transmit the packet
+	 */
+	ret = edma_ring_xmit(&edma_hw, netdev, skb,
+			&edma_hw.txdesc_ring[tx_ring]);
+	if (ret == EDMA_TX_OK)
+		return NETDEV_TX_OK;
+
+	/*
+	 * Not enough descriptors. Stop netdev Tx queue.
+	 */
+	if (ret == EDMA_TX_DESC) {
+		netif_stop_queue(netdev);
+		return NETDEV_TX_BUSY;
+	}
+
+drop:
+	dev_kfree_skb_any(skb);
+	netdev->stats.tx_dropped++;
+
+	return NETDEV_TX_OK;
+}
+
+/*
+ * edma_if_set_features()
+ *	Set the supported net_device features
+ */
+static void edma_if_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	/*
+	 * TODO - add flags to support HIGHMEM/cksum offload VLAN
+	 * the features are enabled.
+	 */
+}
+
+/* TODO - check if this is needed */
+/*
+ * edma_if_pause_on_off()
+ *	Set pause frames on or off
+ *
+ * No need to send a message if we defaulted to slow path.
+ */
+static int edma_if_pause_on_off(struct nss_dp_data_plane_ctx *dpc,
+				uint32_t pause_on)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_vsi_assign()
+ *	assign vsi of the data plane
+ *
+ */
+static int edma_if_vsi_assign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct net_device *netdev = dpc->dev;
+	int32_t port_num;
+
+	port_num = edma_get_port_num_from_netdev(netdev);
+
+	if (port_num < 0)
+		return NSS_DP_FAILURE;
+
+	if (fal_port_vsi_set(0, port_num, vsi) < 0)
+		return NSS_DP_FAILURE;
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_if_vsi_unassign()
+ *	unassign vsi of the data plane
+ *
+ */
+static int edma_if_vsi_unassign(struct nss_dp_data_plane_ctx *dpc, uint32_t vsi)
+{
+	struct net_device *netdev = dpc->dev;
+	uint32_t port_num;
+
+	port_num = edma_get_port_num_from_netdev(netdev);
+
+	if (port_num < 0)
+		return NSS_DP_FAILURE;
+
+	if (fal_port_vsi_set(0, port_num, 0xffff) < 0)
+		return NSS_DP_FAILURE;
+
+	return NSS_DP_SUCCESS;
+}
+
+#ifdef CONFIG_RFS_ACCEL
+/*
+ * edma_if_rx_flow_steer()
+ *	Flow steer of the data plane
+ *
+ * Initial receive flow steering function for data plane operation.
+ */
+static int edma_if_rx_flow_steer(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb,
+					uint32_t cpu, bool is_add)
+{
+	return NSS_DP_SUCCESS;
+}
+#endif
+
+/*
+ * edma_if_deinit()
+ *	Free edma resources
+ */
+static int edma_if_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	/*
+	 * Free up resources used by EDMA if all the
+	 * interfaces have been overridden
+	 * */
+	if (edma_hw.dp_override_cnt == EDMA_MAX_GMACS - 1) {
+		edma_cleanup(true);
+	} else {
+		edma_hw.dp_override_cnt++;
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * edma_irq_init()
+ *	Initialize interrupt handlers for the driver
+ */
+static int edma_irq_init(void)
+{
+	int err;
+	uint32_t entry_num, i;
+
+	/*
+	 * Get TXCMPL rings IRQ numbers
+	 */
+	entry_num = 0;
+	for (i = 0; i < edma_hw.txcmpl_rings; i++, entry_num++) {
+		edma_hw.txcmpl_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.txcmpl_intr[i] < 0) {
+			pr_warn("%s: txcmpl_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: txcmpl_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.txcmpl_intr[i]);
+	}
+
+	/*
+	 * Get RXFILL rings IRQ numbers
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++, entry_num++) {
+		edma_hw.rxfill_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.rxfill_intr[i] < 0) {
+			pr_warn("%s: rxfill_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: rxfill_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.rxfill_intr[i]);
+	}
+
+	/*
+	 * Get RXDESC rings IRQ numbers
+	 *
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++, entry_num++) {
+		edma_hw.rxdesc_intr[i] =
+			platform_get_irq(edma_hw.pdev, entry_num);
+		if (edma_hw.rxdesc_intr[i] < 0) {
+			pr_warn("%s: rxdesc_intr[%u] irq get failed\n",
+					(edma_hw.device_node)->name, i);
+			return -1;
+		}
+
+		pr_debug("%s: rxdesc_intr[%u] = %u\n",
+				 (edma_hw.device_node)->name,
+				 i, edma_hw.rxdesc_intr[i]);
+	}
+
+	/*
+	 * Get misc IRQ number
+	 */
+	edma_hw.misc_intr = platform_get_irq(edma_hw.pdev, entry_num);
+	pr_debug("%s: misc IRQ:%u\n",
+			  (edma_hw.device_node)->name,
+			  edma_hw.misc_intr);
+
+	/*
+	 * Request IRQ for TXCMPL rings
+	 */
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		err = request_irq(edma_hw.txcmpl_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_txcmpl", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("TXCMPL ring IRQ:%d request failed\n",
+					edma_hw.txcmpl_intr[i]);
+			return -1;
+
+		}
+	}
+
+	/*
+	 * Request IRQ for RXFILL rings
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		err = request_irq(edma_hw.rxfill_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_rxfill", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("RXFILL ring IRQ:%d request failed\n",
+					edma_hw.rxfill_intr[i]);
+			goto rx_fill_ring_intr_req_fail;
+		}
+	}
+
+	/*
+	 * Request IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		err = request_irq(edma_hw.rxdesc_intr[i],
+				  edma_handle_irq, IRQF_SHARED,
+				  "edma_rxdesc", (void *)edma_hw.pdev);
+		if (err) {
+			pr_debug("RXDESC ring IRQ:%d request failed\n",
+					edma_hw.rxdesc_intr[i]);
+			goto rx_desc_ring_intr_req_fail;
+		}
+	}
+
+	/*
+	 * Request Misc IRQ
+	 */
+	err = request_irq(edma_hw.misc_intr, edma_handle_misc_irq,
+			  IRQF_SHARED, "edma_misc",
+			  (void *)edma_hw.pdev);
+	if (err) {
+		pr_debug("MISC IRQ:%d request failed\n",
+				edma_hw.misc_intr);
+		goto misc_intr_req_fail;
+	}
+
+	return 0;
+
+misc_intr_req_fail:
+
+	/*
+	 * Free IRQ for RXDESC rings
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		synchronize_irq(edma_hw.rxdesc_intr[i]);
+		free_irq(edma_hw.rxdesc_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+rx_desc_ring_intr_req_fail:
+
+	/*
+	 * Free IRQ for RXFILL rings
+	 */
+	for (i = 0; i < edma_hw.rxfill_rings; i++) {
+		synchronize_irq(edma_hw.rxfill_intr[i]);
+		free_irq(edma_hw.rxfill_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+rx_fill_ring_intr_req_fail:
+
+	/*
+	 * Free IRQ for TXCMPL rings
+	 */
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+
+		synchronize_irq(edma_hw.txcmpl_intr[i]);
+		free_irq(edma_hw.txcmpl_intr[i],
+				(void *)&(edma_hw.pdev)->dev);
+	}
+
+	return -1;
+}
+
+/*
+ * edma_register_netdevice()
+ *	Register netdevice with EDMA
+ */
+static int edma_register_netdevice(struct net_device *netdev, uint32_t macid)
+{
+	if (!netdev) {
+		pr_info("nss_dp_edma: Invalid netdev pointer %px\n", netdev);
+		return -EINVAL;
+	}
+
+	if ((macid < EDMA_START_GMACS) || (macid > EDMA_MAX_GMACS)) {
+		netdev_dbg(netdev, "nss_dp_edma: Invalid macid(%d) for %s\n",
+			macid, netdev->name);
+		return -EINVAL;
+	}
+
+	netdev_info(netdev, "nss_dp_edma: Registering netdev %s(qcom-id:%d) with EDMA\n",
+		netdev->name, macid);
+
+	/*
+	 * We expect 'macid' to correspond to ports numbers on
+	 * IPQ807x. These begin from '1' and hence we subtract
+	 * one when using it as an array index.
+	 */
+	edma_hw.netdev_arr[macid - 1] = netdev;
+
+	/*
+	 * NAPI add
+	 */
+	if (!edma_hw.napi_added) {
+		netif_napi_add(netdev, &edma_hw.napi, edma_napi,
+				EDMA_NAPI_WORK);
+		/*
+		 * Register the interrupt handlers and enable interrupts
+		 */
+		if (edma_irq_init() < 0)
+			return -EINVAL;
+
+		edma_hw.napi_added = 1;
+	}
+
+	return 0;
+}
+
+/*
+ * edma_if_init()
+ */
+
+static int edma_if_init(struct nss_dp_data_plane_ctx *dpc)
+{
+
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *dp_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	int ret = 0;
+
+	/*
+	 * Register the netdev
+	 */
+	ret = edma_register_netdevice(netdev, dp_dev->macid);
+	if (ret) {
+		netdev_dbg(netdev,
+				"Error registering netdevice with EDMA %s\n",
+				netdev->name);
+		return NSS_DP_FAILURE;
+	}
+
+	/*
+	 * Headroom needed for Tx preheader
+	 */
+	netdev->needed_headroom += EDMA_TX_PREHDR_SIZE;
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * nss_dp_edma_ops
+ */
+struct nss_dp_data_plane_ops nss_dp_edma_ops = {
+	.init		= edma_if_init,
+	.open		= edma_if_open,
+	.close		= edma_if_close,
+	.link_state	= edma_if_link_state,
+	.mac_addr	= edma_if_mac_addr,
+	.change_mtu	= edma_if_change_mtu,
+	.xmit		= edma_if_xmit,
+	.set_features	= edma_if_set_features,
+	.pause_on_off	= edma_if_pause_on_off,
+	.vsi_assign	= edma_if_vsi_assign,
+	.vsi_unassign	= edma_if_vsi_unassign,
+#ifdef CONFIG_RFS_ACCEL
+	.rx_flow_steer	= edma_if_rx_flow_steer,
+#endif
+	.deinit		= edma_if_deinit,
+};
+
+/*
+ * edma_of_get_pdata()
+ *	Read the device tree details for EDMA
+ */
+static int edma_of_get_pdata(struct resource *edma_res)
+{
+	/*
+	 * Find EDMA node in device tree
+	 */
+	edma_hw.device_node = of_find_node_by_name(NULL,
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_hw.device_node) {
+		pr_warn("EDMA device tree node (%s) not found\n",
+				EDMA_DEVICE_NODE_NAME);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA device node
+	 */
+	edma_hw.pdev = of_find_device_by_node(edma_hw.device_node);
+	if (!edma_hw.pdev) {
+		pr_warn("Platform device for node %px(%s) not found\n",
+				edma_hw.device_node,
+				(edma_hw.device_node)->name);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get EDMA register resource
+	 */
+	if (of_address_to_resource(edma_hw.device_node, 0, edma_res) != 0) {
+		pr_warn("Unable to get register address for edma device: "
+			  EDMA_DEVICE_NODE_NAME"\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get id of first TXDESC ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txdesc-ring-start",
+				      &edma_hw.txdesc_ring_start) != 0) {
+		pr_warn("Read error 1st TXDESC ring (txdesc_ring_start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of TXDESC rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txdesc-rings",
+				 &edma_hw.txdesc_rings) != 0) {
+		pr_warn("Unable to read number of txdesc rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.txdesc_ring_end = edma_hw.txdesc_ring_start +
+					edma_hw.txdesc_rings;
+
+	/*
+	 * Get id of first TXCMPL ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txcmpl-ring-start",
+				&edma_hw.txcmpl_ring_start) != 0) {
+		pr_warn("Read error 1st TXCMPL ring (txcmpl_ring_start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of TXCMPL rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,txcmpl-rings",
+				&edma_hw.txcmpl_rings) != 0) {
+		pr_warn("Unable to read number of txcmpl rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.txcmpl_ring_end = edma_hw.txcmpl_ring_start +
+					edma_hw.txcmpl_rings;
+
+	/*
+	 * Get id of first RXFILL ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxfill-ring-start",
+				      &edma_hw.rxfill_ring_start) != 0) {
+		pr_warn("Read error 1st RXFILL ring (rxfill-ring-start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of RXFILL rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxfill-rings",
+					&edma_hw.rxfill_rings) != 0) {
+		pr_warn("Unable to read number of rxfill rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.rxfill_ring_end = edma_hw.rxfill_ring_start +
+					edma_hw.rxfill_rings;
+
+	/*
+	 * Get id of first RXDESC ring
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxdesc-ring-start",
+				      &edma_hw.rxdesc_ring_start) != 0) {
+		pr_warn("Read error 1st RXDESC ring (rxdesc-ring-start)\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Get number of RXDESC rings
+	 */
+	if (of_property_read_u32(edma_hw.device_node, "qcom,rxdesc-rings",
+					&edma_hw.rxdesc_rings) != 0) {
+		pr_warn("Unable to read number of rxdesc rings.\n");
+		return -EINVAL;
+	}
+	edma_hw.rxdesc_ring_end = edma_hw.rxdesc_ring_start +
+					edma_hw.rxdesc_rings;
+
+	return 0;
+}
+
+/*
+ * edma_init()
+ *	EDMA init
+ */
+int edma_init(void)
+{
+	int ret = 0;
+	struct resource res_edma;
+
+	/*
+	 * Get all the DTS data needed
+	 */
+	if (edma_of_get_pdata(&res_edma) < 0) {
+		pr_warn("Unable to get EDMA DTS data.\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Request memory region for EDMA registers
+	 */
+	edma_hw.reg_resource = request_mem_region(res_edma.start,
+				resource_size(&res_edma),
+				EDMA_DEVICE_NODE_NAME);
+	if (!edma_hw.reg_resource) {
+		pr_warn("Unable to request EDMA register memory.\n");
+		return -EFAULT;
+	}
+
+	/*
+	 * Remap register resource
+	 */
+	edma_hw.reg_base = ioremap_nocache((edma_hw.reg_resource)->start,
+				resource_size(edma_hw.reg_resource));
+	if (!edma_hw.reg_base) {
+		pr_warn("Unable to remap EDMA register memory.\n");
+		ret = -EFAULT;
+		goto edma_init_remap_fail;
+	}
+
+	if (edma_hw_init(&edma_hw) != 0) {
+		ret = -EFAULT;
+		goto edma_init_hw_init_fail;
+	}
+
+	platform_set_drvdata(edma_hw.pdev, (void *)&edma_hw);
+
+	edma_hw.napi_added = 0;
+
+	return 0;
+
+edma_init_hw_init_fail:
+	iounmap(edma_hw.reg_base);
+
+edma_init_remap_fail:
+	release_mem_region((edma_hw.reg_resource)->start,
+			   resource_size(edma_hw.reg_resource));
+	return ret;
+}
+
+/*
+ * edma_disable_port()
+ * 	EDMA disable port
+ */
+static void edma_disable_port(void)
+{
+	edma_reg_write(EDMA_REG_PORT_CTRL, EDMA_DISABLE);
+}
+
+/*
+ * edma_cleanup()
+ *	EDMA cleanup
+ */
+void edma_cleanup(bool is_dp_override)
+{
+	int i;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+
+	/*
+	 * The cleanup can happen from data plane override
+	 * or from module_exit, we want to cleanup only once
+	 */
+	if (!edma_hw.edma_initialized) {
+		/*
+		 * Disable EDMA only at module exit time, since NSS firmware
+		 * depends on this setting.
+		 */
+		if (!is_dp_override) {
+			edma_disable_port();
+		}
+		return;
+	}
+
+	/*
+	 * Disable Rx rings used by this driver
+	 */
+	for (i = edma_hw.rxdesc_ring_start; i < edma_hw.rxdesc_ring_end; i++)
+		edma_reg_write(EDMA_REG_RXDESC_CTRL(i), EDMA_RING_DISABLE);
+
+	/*
+	 * Disable Tx rings used by this driver
+	 */
+	for (i = edma_hw.txdesc_ring_start; i < edma_hw.txdesc_ring_end; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TXDESC_CTRL(i),
+				EDMA_RING_DISABLE);
+	}
+
+	/*
+	 * Disable RxFill Rings used by this driver
+	 */
+	for (i = edma_hw.rxfill_ring_start; i < edma_hw.rxfill_ring_end; i++)
+		edma_reg_write(EDMA_REG_RXFILL_RING_EN(i), EDMA_RING_DISABLE);
+
+	/*
+	 * Clear interrupt mask
+	 */
+	for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+		rxdesc_ring = &edma_hw.rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+		txcmpl_ring = &edma_hw.txcmpl_ring[i];
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+			       EDMA_MASK_INT_CLEAR);
+	}
+
+	edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_CLEAR);
+	/*
+	 * Remove interrupt handlers and NAPI
+	 */
+	if (edma_hw.napi_added) {
+
+		/*
+		 * Free IRQ for TXCMPL rings
+		 */
+		for (i = 0; i < edma_hw.txcmpl_rings; i++) {
+			synchronize_irq(edma_hw.txcmpl_intr[i]);
+			free_irq(edma_hw.txcmpl_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free IRQ for RXFILL rings
+		 */
+		for (i = 0; i < edma_hw.rxfill_rings; i++) {
+			synchronize_irq(edma_hw.rxfill_intr[i]);
+			free_irq(edma_hw.rxfill_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free IRQ for RXDESC rings
+		 */
+		for (i = 0; i < edma_hw.rxdesc_rings; i++) {
+			synchronize_irq(edma_hw.rxdesc_intr[i]);
+			free_irq(edma_hw.rxdesc_intr[i],
+					(void *)(edma_hw.pdev));
+		}
+
+		/*
+		 * Free Misc IRQ
+		 */
+		synchronize_irq(edma_hw.misc_intr);
+		free_irq(edma_hw.misc_intr, (void *)(edma_hw.pdev));
+
+		netif_napi_del(&edma_hw.napi);
+		edma_hw.napi_added = 0;
+	}
+
+	/*
+	 * Disable EDMA only at module exit time, since NSS firmware
+	 * depends on this setting.
+	 */
+	if (!is_dp_override) {
+		edma_disable_port();
+	}
+
+	/*
+	 * cleanup rings and free
+	 */
+	edma_cleanup_rings(&edma_hw);
+	iounmap(edma_hw.reg_base);
+	release_mem_region((edma_hw.reg_resource)->start,
+			   resource_size(edma_hw.reg_resource));
+
+	/*
+	 * Mark initialize false, so that we do not
+	 * try to cleanup again
+	 */
+	edma_hw.edma_initialized = false;
+}

feeds/ipq807x/qca-nss-dp/src/hal/edma/edma_data_plane.h

@@ -0,0 +1,287 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2018-2021, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+#include "nss_dp_dev.h"
+
+#ifndef __NSS_DP_EDMA_DATAPLANE__
+#define __NSS_DP_EDMA_DATAPLANE__
+
+#define EDMA_BUF_SIZE			2000
+#define EDMA_DEVICE_NODE_NAME		"edma"
+#define EDMA_RX_BUFF_SIZE		(EDMA_BUF_SIZE + EDMA_RX_PREHDR_SIZE)
+#define EDMA_RX_PREHDR_SIZE		(sizeof(struct edma_rx_preheader))
+#define EDMA_TX_PREHDR_SIZE		(sizeof(struct edma_tx_preheader))
+#define EDMA_RING_SIZE			128
+#define EDMA_NAPI_WORK			100
+#define EDMA_START_GMACS		NSS_DP_START_IFNUM
+#define EDMA_MAX_GMACS			NSS_DP_HAL_MAX_PORTS
+#define EDMA_TX_PKT_MIN_SIZE		33	/* IPQ807x EDMA needs a minimum packet size of 33 bytes */
+#if defined(NSS_DP_IPQ60XX)
+#define EDMA_MAX_TXCMPL_RINGS		24	/* Max TxCmpl rings */
+#else
+#define EDMA_MAX_TXCMPL_RINGS		8	/* Max TxCmpl rings */
+#endif
+#define EDMA_MAX_RXDESC_RINGS		16	/* Max RxDesc rings */
+#define EDMA_MAX_RXFILL_RINGS		8	/* Max RxFill rings */
+#define EDMA_MAX_TXDESC_RINGS		24	/* Max TxDesc rings */
+#define EDMA_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
+#define EDMA_RXFILL_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxfill_desc)
+#define EDMA_RXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_rxdesc_desc)
+#define EDMA_TXDESC_DESC(R, i) EDMA_GET_DESC(R, i, struct edma_txdesc_desc)
+#define EDMA_RXPH_SRC_INFO_TYPE_GET(rxph)	(((rxph)->src_info >> 8) & 0xf0)
+#define EDMA_RXPH_SERVICE_CODE_GET(rxph)	(((rxph)->rx_pre4) & 0xff)
+
+/*
+ * Tx descriptor
+ */
+struct edma_txdesc_desc {
+	uint32_t buffer_addr;
+		/* buffer address */
+	uint32_t word1;
+		/* more bit, TSO, preheader, pool, offset and length */
+};
+
+/*
+ * TxCmpl descriptor
+ */
+struct edma_txcmpl_desc {
+	uint32_t buffer_addr;	/* buffer address/opaque */
+	uint32_t status;	/* status */
+};
+
+/*
+ * Rx descriptor
+ */
+struct edma_rxdesc_desc {
+	uint32_t buffer_addr;	/* buffer address */
+	uint32_t status;	/* status */
+};
+
+/*
+ * RxFill descriptor
+ */
+struct edma_rxfill_desc {
+	uint32_t buffer_addr;	/* Buffer address */
+	uint32_t word1;		/* opaque_ind and buffer size */
+};
+
+/*
+ * Tx descriptor ring
+ */
+struct edma_txdesc_ring {
+	uint32_t id;			/* TXDESC ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	spinlock_t tx_lock;		/* Tx ring lock */
+	uint16_t count;			/* number of descriptors */
+};
+
+/*
+ * TxCmpl ring
+ */
+struct edma_txcmpl_ring {
+	uint32_t id;			/* TXCMPL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxFill ring
+ */
+struct edma_rxfill_ring {
+	uint32_t id;			/* RXFILL ring number */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	spinlock_t lock;		/* Rx ring lock */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * RxDesc ring
+ */
+struct edma_rxdesc_ring {
+	uint32_t id;			/* RXDESC ring number */
+	struct edma_rxfill_ring *rxfill;	/* RXFILL ring used */
+	void *desc;			/* descriptor ring virtual address */
+	dma_addr_t dma;			/* descriptor ring physical address */
+	uint16_t count;			/* number of descriptors in the ring */
+};
+
+/*
+ * EDMA Tx Preheader
+ */
+struct edma_tx_preheader {
+	uint32_t opaque;   /* Opaque, contains skb pointer */
+	uint16_t src_info; /* Src information */
+	uint16_t dst_info; /* Dest information */
+	uint32_t tx_pre2;  /* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t tx_pre3;  /* STAG, CTAG */
+	uint32_t tx_pre4;  /* CPU code, L3 & L4 offset, service code */
+	uint32_t tx_pre5;  /* IP addr index, ACL index */
+	uint32_t tx_pre6;  /* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t tx_pre7;  /* Timestamp, QoS TAG */
+};
+
+/*
+ * EDMA Rx Preheader
+ */
+struct edma_rx_preheader {
+	uint32_t opaque;
+		/* Opaque, contains skb pointer*/
+	uint16_t src_info;
+		/* Src information */
+	uint16_t dst_info;
+		/* Dest information */
+	uint32_t rx_pre2;
+		/* SVLAN & CVLAN flag, drop prec, hash value */
+	uint32_t rx_pre3;
+		/* STAG, CTAG */
+	uint32_t rx_pre4;
+		/* CPU code, L3 & L4 offset, service code */
+	uint32_t rx_pre5;
+		/* IP addr index, ACL index */
+	uint32_t rx_pre6;
+		/* IP payload checksum, copy2cpu, timestamp, dscp */
+	uint32_t rx_pre7;
+		/* Timestamp, QoS TAG */
+};
+
+enum edma_tx {
+	EDMA_TX_OK = 0,		/* Tx success */
+	EDMA_TX_DESC = 1,	/* Not enough descriptors */
+	EDMA_TX_FAIL = 2,	/* Tx failure */
+};
+
+/*
+ * EDMA private data structure
+ */
+struct edma_hw {
+	struct napi_struct napi;
+			/* napi structure */
+	struct net_device *netdev_arr[EDMA_MAX_GMACS];
+			/* netdev for each gmac port */
+	struct device_node *device_node;
+			/* Device tree node */
+	struct platform_device *pdev;
+			/* Platform device */
+	void __iomem *reg_base;
+			/* Base register address */
+	struct resource *reg_resource;
+			/* Memory resource */
+	uint16_t rx_payload_offset;
+			/* start of the payload offset */
+	uint32_t flags;
+			/* internal flags */
+	int active;
+			/* status */
+	int napi_added;
+			/* flag to indicate napi add status */
+
+	/*
+	 * Debugfs entries
+	 */
+	struct dentry *edma_dentry;
+	struct dentry *txdesc_dentry;
+	struct dentry *txcmpl_dentry;
+	struct dentry *rxdesc_dentry;
+
+	/*
+	 * Store for tx and rx skbs
+	 */
+	struct sk_buff *rx_skb_store[EDMA_RING_SIZE];
+	struct sk_buff *tx_skb_store[EDMA_RING_SIZE];
+
+	struct edma_rxfill_ring *rxfill_ring;
+			/* Rx Fill Ring, SW is producer */
+	struct edma_rxdesc_ring *rxdesc_ring;
+			/* Rx Descriptor Ring, SW is consumer */
+	struct edma_txdesc_ring *txdesc_ring;
+			/* Tx Descriptor Ring, SW is producer */
+	struct edma_txcmpl_ring *txcmpl_ring;
+			/* Tx Completion Ring, SW is consumer */
+
+	uint32_t txdesc_rings;
+			/* Number of TxDesc rings */
+	uint32_t txdesc_ring_start;
+			/* Id of first TXDESC ring */
+	uint32_t txdesc_ring_end;
+			/* Id of the last TXDESC ring */
+	uint32_t txcmpl_rings;
+			/* Number of TxCmpl rings */
+	uint32_t txcmpl_ring_start;
+			/* Id of first TXCMPL ring */
+	uint32_t txcmpl_ring_end;
+			/* Id of last TXCMPL ring */
+	uint32_t rxfill_rings;
+			/* Number of RxFill rings */
+	uint32_t rxfill_ring_start;
+			/* Id of first RxFill ring */
+	uint32_t rxfill_ring_end;
+			/* Id of last RxFill ring */
+	uint32_t rxdesc_rings;
+			/* Number of RxDesc rings */
+	uint32_t rxdesc_ring_start;
+			/* Id of first RxDesc ring */
+	uint32_t rxdesc_ring_end;
+			/* Id of last RxDesc ring */
+	uint32_t txcmpl_intr[EDMA_MAX_TXCMPL_RINGS];
+			/* TxCmpl ring IRQ numbers */
+	uint32_t rxfill_intr[EDMA_MAX_RXFILL_RINGS];
+			/* Rx fill ring IRQ numbers */
+	uint32_t rxdesc_intr[EDMA_MAX_RXDESC_RINGS];
+			/* Rx desc ring IRQ numbers */
+	uint32_t misc_intr;
+			/* Misc IRQ number */
+
+	uint32_t tx_intr_mask;
+			/* Tx interrupt mask */
+	uint32_t rxfill_intr_mask;
+			/* Rx fill ring interrupt mask */
+	uint32_t rxdesc_intr_mask;
+			/* Rx Desc ring interrupt mask */
+	uint32_t txcmpl_intr_mask;
+			/* Tx Cmpl ring interrupt mask */
+	uint32_t misc_intr_mask;
+			/* misc interrupt interrupt mask */
+	uint32_t dp_override_cnt;
+			/* number of interfaces overriden */
+	bool edma_initialized;
+			/* flag to check initialization status */
+};
+
+extern struct edma_hw edma_hw;
+
+uint32_t edma_reg_read(uint32_t reg_off);
+void edma_reg_write(uint32_t reg_off, uint32_t val);
+
+int edma_alloc_rx_buffer(struct edma_hw *ehw,
+		struct edma_rxfill_ring *rxfill_ring);
+enum edma_tx edma_ring_xmit(struct edma_hw *ehw,
+			    struct net_device *netdev,
+			    struct sk_buff *skb,
+			    struct edma_txdesc_ring *txdesc_ring);
+uint32_t edma_clean_tx(struct edma_hw *ehw,
+			struct edma_txcmpl_ring *txcmpl_ring);
+irqreturn_t edma_handle_irq(int irq, void *ctx);
+irqreturn_t edma_handle_misc_irq(int irq, void *ctx);
+int edma_napi(struct napi_struct *napi, int budget);
+void edma_cleanup_rings(struct edma_hw *ehw);
+void edma_cleanup(bool is_dp_override);
+int edma_hw_init(struct edma_hw *ehw);
+#endif /* __NSS_DP_EDMA_DATAPLANE__ */

feeds/ipq807x/qca-nss-dp/src/hal/edma/edma_regs.h

@@ -0,0 +1,454 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+#ifndef __EDMA_REGS__
+#define __EDMA_REGS__
+
+/*
+ * IPQ807x EDMA register offsets
+ */
+#define EDMA_REG_MAS_CTRL		0x0
+#define EDMA_REG_PORT_CTRL		0x4
+#define EDMA_REG_VLAN_CTRL		0x8
+#define EDMA_REG_RXDESC2FILL_MAP_0	0x18
+#define EDMA_REG_RXDESC2FILL_MAP_1	0x1c
+#define EDMA_REG_TXQ_CTRL		0x20
+#define EDMA_REG_TXQ_CTRL_2		0x24
+#define EDMA_REG_TXQ_FC_0		0x28
+#define EDMA_REG_TXQ_FC_1		0x30
+#define EDMA_REG_TXQ_FC_2		0x34
+#define EDMA_REG_TXQ_FC_3		0x38
+#define EDMA_REG_RXQ_CTRL		0x3c
+#define EDMA_REG_RX_TX_FULL_QID		0x40
+#define EDMA_REG_RXQ_FC_THRE		0x44
+#define EDMA_REG_DMAR_CTRL		0x48
+#define EDMA_REG_AXIR_CTRL		0x4c
+#define EDMA_REG_AXIW_CTRL		0x50
+#define EDMA_REG_MIN_MSS		0x54
+#define EDMA_REG_LOOPBACK_CTRL		0x58
+#define EDMA_REG_MISC_INT_STAT		0x5c
+#define EDMA_REG_MISC_INT_MASK		0x60
+#define EDMA_REG_DBG_CTRL		0x64
+#define EDMA_REG_DBG_DATA		0x68
+#define EDMA_REG_TXDESC_BA(n)		(0x1000 + (0x1000 * n))
+#define EDMA_REG_TXDESC_PROD_IDX(n)	(0x1004 + (0x1000 * n))
+#define EDMA_REG_TXDESC_CONS_IDX(n)	(0x1008 + (0x1000 * n))
+#define EDMA_REG_TXDESC_RING_SIZE(n)	(0x100c + (0x1000 * n))
+#define EDMA_REG_TXDESC_CTRL(n)		(0x1010 + (0x1000 * n))
+#if defined(NSS_DP_IPQ807X)
+#define EDMA_REG_TXDESC2CMPL_MAP_0	0xc
+#define EDMA_REG_TXDESC2CMPL_MAP_1	0x10
+#define EDMA_REG_TXDESC2CMPL_MAP_2	0x14
+#define EDMA_REG_TXCMPL_BASE		0x19000
+#define EDMA_REG_TX_BASE		0x21000
+#else
+#define EDMA_REG_TXCMPL_BASE		0x79000
+#define EDMA_REG_TX_BASE		0x91000
+#endif
+#define EDMA_REG_TXCMPL_BA_OFFSET		0x00000
+#define EDMA_REG_TXCMPL_PROD_IDX_OFFSET		0x00004
+#define EDMA_REG_TXCMPL_CONS_IDX_OFFSET		0x00008
+#define EDMA_REG_TXCMPL_RING_SIZE_OFFSET	0x0000c
+#define EDMA_REG_TXCMPL_UGT_THRE_OFFSET		0x00010
+#define EDMA_REG_TXCMPL_CTRL_OFFSET		0x00014
+#define EDMA_REG_TXCMPL_BPC_OFFSET		0x00018
+#define EDMA_REG_TX_INT_STAT_OFFSET		0x00000
+#define EDMA_REG_TX_INT_MASK_OFFSET		0x00004
+#define EDMA_REG_TX_MOD_TIMER_OFFSET		0x00008
+#define EDMA_REG_TX_INT_CTRL_OFFSET		0x0000c
+#define EDMA_REG_TXCMPL_BA(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_BA_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_PROD_IDX(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_PROD_IDX_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_CONS_IDX(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_CONS_IDX_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_RING_SIZE(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_RING_SIZE_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_UGT_THRE(n)	(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_UGT_THRE_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_CTRL(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_CTRL_OFFSET + (0x1000 * n))
+#define EDMA_REG_TXCMPL_BPC(n)		(EDMA_REG_TXCMPL_BASE + EDMA_REG_TXCMPL_BPC_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_STAT(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_STAT_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_MASK(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_MASK_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_MOD_TIMER(n)	(EDMA_REG_TX_BASE + EDMA_REG_TX_MOD_TIMER_OFFSET + (0x1000 * n))
+#define EDMA_REG_TX_INT_CTRL(n)		(EDMA_REG_TX_BASE + EDMA_REG_TX_INT_CTRL_OFFSET + (0x1000 * n))
+#define EDMA_REG_RXFILL_BA(n)		(0x29000 + (0x1000 * n))
+#define EDMA_REG_RXFILL_PROD_IDX(n)	(0x29004 + (0x1000 * n))
+#define EDMA_REG_RXFILL_CONS_IDX(n)	(0x29008 + (0x1000 * n))
+#define EDMA_REG_RXFILL_RING_SIZE(n)	(0x2900c + (0x1000 * n))
+#define EDMA_REG_RXFILL_BUFFER1_SIZE(n)	(0x29010 + (0x1000 * n))
+#define EDMA_REG_RXFILL_FC_THRE(n)	(0x29014 + (0x1000 * n))
+#define EDMA_REG_RXFILL_UGT_THRE(n)	(0x29018 + (0x1000 * n))
+#define EDMA_REG_RXFILL_RING_EN(n)	(0x2901c + (0x1000 * n))
+#define EDMA_REG_RXFILL_DISABLE(n)	(0x29020 + (0x1000 * n))
+#define EDMA_REG_RXFILL_DISABLE_DONE(n)	(0x29024 + (0x1000 * n))
+#define EDMA_REG_RXFILL_INT_STAT(n)	(0x31000 + (0x1000 * n))
+#define EDMA_REG_RXFILL_INT_MASK(n)	(0x31004 + (0x1000 * n))
+#define EDMA_REG_RXDESC_BA(n)		(0x39000 + (0x1000 * n))
+#define EDMA_REG_RXDESC_PROD_IDX(n)	(0x39004 + (0x1000 * n))
+#define EDMA_REG_RXDESC_CONS_IDX(n)	(0x39008 + (0x1000 * n))
+#define EDMA_REG_RXDESC_RING_SIZE(n)	(0x3900c + (0x1000 * n))
+#define EDMA_REG_RXDESC_FC_THRE(n)	(0x39010 + (0x1000 * n))
+#define EDMA_REG_RXDESC_UGT_THRE(n)	(0x39014 + (0x1000 * n))
+#define EDMA_REG_RXDESC_CTRL(n)		(0x39018 + (0x1000 * n))
+#define EDMA_REG_RXDESC_BPC(n)		(0x3901c + (0x1000 * n))
+#define EDMA_REG_RXDESC_INT_STAT(n)	(0x49000 + (0x1000 * n))
+#define EDMA_REG_RXDESC_INT_MASK(n)	(0x49004 + (0x1000 * n))
+#define EDMA_REG_RX_MOD_TIMER(n)	(0x49008 + (0x1000 * n))
+#define EDMA_REG_RX_INT_CTRL(n)		(0x4900c + (0x1000 * n))
+#define EDMA_QID2RID_TABLE_MEM(q)	(0x5a000 + (0x4 * q))
+#define EDMA_REG_RXRING_PC(n)		(0x5A200 + (0x10 * n))
+#define EDMA_REG_RXRING_BC_0(n)		(0x5A204 + (0x10 * n))
+#define EDMA_REG_RXRING_BC_1(n)		(0x5A208 + (0x10 * n))
+#define EDMA_REG_TXRING_PC(n)		(0x74000 + (0x10 * n))
+#define EDMA_REG_TXRING_BC_0(n)		(0x74004 + (0x10 * n))
+#define EDMA_REG_TXRING_BC_1(n)		(0x74008 + (0x10 * n))
+
+/*
+ * EDMA_REG_PORT_CTRL register
+ */
+#define EDMA_PORT_PAD_EN		0x1
+#define EDMA_PORT_EDMA_EN		0x2
+
+/*
+ * EDMA_REG_TXQ_CTRL register
+ */
+#define EDMA_TXDESC_PF_THRE_MASK		0xf
+#define EDMA_TXDESC_PF_THRE_SHIFT		0
+#define EDMA_TXCMPL_WB_THRE_MASK		0xf
+#define EDMA_TXCMPL_WB_THRE_SHIFT		4
+#define EDMA_TXDESC_PKT_SRAM_THRE_MASK		0xff
+#define EDMA_TXDESC_PKT_SRAM_THRE_SHIFT		8
+#define EDMA_TXCMPL_WB_TIMER_MASK		0xffff
+#define EDMA_TXCMPL_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_CTRL register
+ */
+#define EDMA_RXFILL_PF_THRE_MASK		0xf
+#define EDMA_RXFILL_PF_THRE_SHIFT		0
+#define EDMA_RXDESC_WB_THRE_MASK		0xf
+#define EDMA_RXDESC_WB_THRE_SHIFT		4
+#define EDMA_RXDESC_WB_TIMER_MASK		0xffff
+#define EDMA_RXDESC_WB_TIMER_SHIFT		16
+
+/*
+ * EDMA_REG_RX_TX_FULL_QID register
+ */
+#define EDMA_RX_DESC_FULL_QID_MASK		0xff
+#define EDMA_RX_DESC_FULL_QID_SHIFT		0
+#define EDMA_TX_CMPL_BUF_FULL_QID_MASK		0xff
+#define EDMA_TX_CMPL_BUF_FULL_QID_SHIFT		8
+#define EDMA_TX_SRAM_FULL_QID_MASK		0x1f
+#define EDMA_TX_SRAM_FULL_QID_SHIFT		16
+
+/*
+ * EDMA_REG_RXQ_FC_THRE reister
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE_MASK		0x1f
+#define EDMA_RXFILL_FIFO_XOFF_THRE_SHIFT	0
+#define EDMA_DESC_FIFO_XOFF_THRE_MASK		0x3f
+#define EDMA_DESC_FIFO_XOFF_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_DMAR_CTRL register
+ */
+#define EDMA_DMAR_REQ_PRI_MASK			0x7
+#define EDMA_DMAR_REQ_PRI_SHIFT			0
+#define EDMA_DMAR_BURST_LEN_MASK		0x1
+#define EDMA_DMAR_BURST_LEN_SHIFT		3
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK	0x1f
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT	4
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT	9
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK	0x7
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT	12
+
+#define EDMA_DMAR_REQ_PRI_SET(x)        	(((x) & EDMA_DMAR_REQ_PRI_MASK) << EDMA_DMAR_REQ_PRI_SHIFT)
+#define EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_TXDATA_OUTSTANDING_NUM_MASK) << EDMA_DMAR_TXDATA_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_TXDESC_OUTSTANDING_NUM_MASK) << EDMA_DMAR_TXDESC_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SET(x) (((x) & EDMA_DMAR_RXFILL_OUTSTANDING_NUM_MASK) << EDMA_DMAR_RXFILL_OUTSTANDING_NUM_SHIFT)
+#define EDMA_DMAR_BURST_LEN_SET(x)		(((x) & EDMA_DMAR_BURST_LEN_MASK) << EDMA_DMAR_BURST_LEN_SHIFT)
+
+/*
+ * Enable 128 byte EDMA burts for IPQ60xx
+ */
+#if defined(NSS_DP_IPQ60XX)
+#define EDMA_BURST_LEN_ENABLE		1
+#else
+#define EDMA_BURST_LEN_ENABLE		0
+#endif
+
+/*
+ * EDMA_REG_AXIW_CTRL_REG
+ */
+#define EDMA_AXIW_MAX_WR_SIZE_EN		0x400
+
+/*
+ * EDMA DISABLE
+ */
+#define EDMA_DISABLE				0
+
+/*
+ * EDMA_REG_TXDESC_PROD_IDX register
+ */
+#define EDMA_TXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CONS_IDX register
+ */
+#define EDMA_TXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_RING_SIZE register
+ */
+#define EDMA_TXDESC_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXDESC_CTRL register
+ */
+#define EDMA_TXDESC_ARB_GRP_ID_MASK		0x3
+#define EDMA_TXDESC_ARB_GRP_ID_SHIFT		4
+#define EDMA_TXDESC_FC_GRP_ID_MASK		0x7
+#define EDMA_TXDESC_FC_GRP_ID_SHIFT		1
+#define EDMA_TXDESC_TX_EN			0x1
+
+/*
+ * EDMA_REG_TXCMPL_PROD_IDX register
+ */
+#define EDMA_TXCMPL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_CONS_IDX register
+ */
+#define EDMA_TXCMPL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_RING_SIZE register
+ */
+#define EDMA_TXCMPL_RING_SIZE_MASK		0xffff
+
+/*
+ * EDMA_REG_TXCMPL_UGT_THRE register
+ */
+#define EDMA_TXCMPL_LOW_THRE_MASK		0xffff
+#define EDMA_TXCMPL_LOW_THRE_SHIFT		0
+#define EDMA_TXCMPL_FC_THRE_MASK		0x3f
+#define EDMA_TXCMPL_FC_THRE_SHIFT		16
+
+/*
+ * EDMA_REG_TXCMPL_CTRL register
+ */
+#define EDMA_TXCMPL_RET_MODE_BUFF_ADDR		0x0
+#define EDMA_TXCMPL_RET_MODE_OPAQUE		0x1
+
+/*
+ * EDMA_REG_TX_MOD_TIMER register
+ */
+#define EDMA_TX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_TX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA_REG_TX_INT_CTRL register
+ */
+#define EDMA_TX_INT_MASK			0x3
+
+/*
+ * EDMA_REG_RXFILL_PROD_IDX register
+ */
+#define EDMA_RXFILL_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_CONS_IDX register
+ */
+#define EDMA_RXFILL_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXFILL_RING_SIZE register
+ */
+#define EDMA_RXFILL_RING_SIZE_MASK		0xffff
+#define EDMA_RXFILL_BUF_SIZE_MASK		0x3fff
+#define EDMA_RXFILL_BUF_SIZE_SHIFT		16
+
+/*
+ * EDMA_REG_RXFILL_FC_THRE register
+ */
+#define EDMA_RXFILL_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XON_THRE_SHIFT		12
+#define EDMA_RXFILL_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXFILL_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_UGT_THRE register
+ */
+#define EDMA_RXFILL_LOW_THRE_MASK		0xffff
+#define EDMA_RXFILL_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXFILL_RING_EN register
+ */
+#define EDMA_RXFILL_RING_EN			0x1
+
+/*
+ * EDMA_REG_RXFILL_INT_MASK register
+ */
+#define EDMA_RXFILL_INT_MASK			0x1
+
+/*
+ * EDMA_REG_RXDESC_PROD_IDX register
+ */
+#define EDMA_RXDESC_PROD_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_CONS_IDX register
+ */
+#define EDMA_RXDESC_CONS_IDX_MASK		0xffff
+
+/*
+ * EDMA_REG_RXDESC_RING_SIZE register
+ */
+#define EDMA_RXDESC_RING_SIZE_MASK		0xffff
+#define EDMA_RXDESC_PL_OFFSET_MASK		0x1ff
+#define EDMA_RXDESC_PL_OFFSET_SHIFT		16
+
+/*
+ * EDMA_REG_RXDESC_FC_THRE register
+ */
+#define EDMA_RXDESC_FC_XON_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XON_THRE_SHIFT		12
+#define EDMA_RXDESC_FC_XOFF_THRE_MASK		0x7ff
+#define EDMA_RXDESC_FC_XOFF_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_UGT_THRE register
+ */
+#define EDMA_RXDESC_LOW_THRE_MASK		0xffff
+#define EDMA_RXDESC_LOW_THRE_SHIFT		0
+
+/*
+ * EDMA_REG_RXDESC_CTRL register
+ */
+#define EDMA_RXDESC_STAG_REMOVE_EN		0x8
+#define EDMA_RXDESC_CTAG_REMOVE_EN		0x4
+#define EDMA_RXDESC_QDISC_EN			0x2
+#define EDMA_RXDESC_RX_EN			0x1
+
+/*
+ * EDMA_REG_TX_INT_MASK register
+ */
+#define EDMA_TX_INT_MASK_PKT_INT		0x1
+#define EDMA_TX_INT_MASK_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_STAT register
+ */
+#define EDMA_RXDESC_INT_STAT_PKT_INT		0x1
+#define EDMA_RXDESC_INT_STAT_UGT_INT		0x2
+
+/*
+ * EDMA_REG_RXDESC_INT_MASK register
+ */
+#define EDMA_RXDESC_INT_MASK_PKT_INT		0x1
+#define EDMA_RXDESC_INT_MASK_TIMER_INT_DIS	0x2
+
+#define EDMA_MASK_INT_DISABLE			0x0
+#define EDMA_MASK_INT_CLEAR			0x0
+
+/*
+ * EDMA_REG_RX_MOD_TIMER register
+ */
+#define EDMA_RX_MOD_TIMER_INIT_MASK		0xffff
+#define EDMA_RX_MOD_TIMER_INIT_SHIFT		0
+
+/*
+ * EDMA QID2RID register sizes
+ */
+#define EDMA_QID2RID_DEPTH			0x40
+#define EDMA_QID2RID_QUEUES_PER_ENTRY		8
+
+/*
+ * TXDESC shift values
+ */
+#define EDMA_TXDESC_MORE_SHIFT			31
+#define EDMA_TXDESC_TSO_EN_SHIFT		30
+#define EDMA_TXDESC_PREHEADER_SHIFT		29
+#define EDMA_TXDESC_POOL_ID_SHIFT		24
+#define EDMA_TXDESC_POOL_ID_MASK		0x1f
+#define EDMA_TXDESC_DATA_OFFSET_SHIFT		16
+#define EDMA_TXDESC_DATA_OFFSET_MASK		0xff
+#define EDMA_TXDESC_DATA_LENGTH_SHIFT		0
+#define EDMA_TXDESC_DATA_LENGTH_MASK		0xffff
+
+#define EDMA_PREHDR_DSTINFO_PORTID_IND		0x20
+#define EDMA_PREHDR_PORTNUM_BITS		0x0fff
+#define EDMA_RING_DMA_MASK			0xffffffff
+/*
+ * RXDESC shift values
+ */
+#define EDMA_RXDESC_RX_RXFILL_CNT_MASK		0x000f
+#define EDMA_RXDESC_RX_RXFILL_CNT_SHIFT		16
+
+#define EDMA_RXDESC_PKT_SIZE_MASK		0x3fff
+#define EDMA_RXDESC_PKT_SIZE_SHIFT		0
+
+#define EDMA_RXDESC_RXD_VALID_MASK		0x1
+#define EDMA_RXDESC_RXD_VALID_SHIFT		31
+
+#define EDMA_RXDESC_PACKET_LEN_MASK		0x3fff
+#define EDMA_RXDESC_RING_INT_STATUS_MASK	0x3
+
+#define EDMA_RING_DISABLE			0
+#define EDMA_TXCMPL_RING_INT_STATUS_MASK	0x3
+#define EDMA_TXCMPL_RETMODE_OPAQUE		0x0
+#define EDMA_RXFILL_RING_INT_STATUS_MASK	0x1
+
+/*
+ * TODO tune the timer and threshold values
+ */
+#define EDMA_RXFILL_FIFO_XOFF_THRE		0x3
+#define EDMA_RXFILL_PF_THRE			0x3
+#define EDMA_RXDESC_WB_THRE			0x0
+#define EDMA_RXDESC_WB_TIMER			0x2
+
+#define EDMA_RXDESC_XON_THRE			50
+#define EDMA_RXDESC_XOFF_THRE			30
+#define EDMA_RXDESC_LOW_THRE			0
+#define EDMA_RX_MOD_TIMER_INIT			1000
+
+#define EDMA_TXDESC_PF_THRE			0x3
+#define EDMA_TXCMPL_WB_THRE			0X0
+#define EDMA_TXDESC_PKT_SRAM_THRE		0x20
+#define EDMA_TXCMPL_WB_TIMER			0x2
+
+#define EDMA_TX_MOD_TIMER			150
+
+/*
+ * EDMA misc error mask
+ */
+#define EDMA_MISC_AXI_RD_ERR_MASK_EN		0x1
+#define EDMA_MISC_AXI_WR_ERR_MASK_EN		0x2
+#define EDMA_MISC_RX_DESC_FIFO_FULL_MASK_EN	0x4
+#define EDMA_MISC_RX_ERR_BUF_SIZE_MASK_EN	0x8
+#define EDMA_MISC_TX_SRAM_FULL_MASK_EN		0x10
+#define EDMA_MISC_TX_CMPL_BUF_FULL_MASK_EN	0x20
+
+#if defined(NSS_DP_IPQ807X)
+#define EDMA_MISC_PKT_LEN_LA_64K_MASK_EN	0x40
+#define EDMA_MISC_PKT_LEN_LE_40_MASK_EN		0x80
+#define EDMA_MISC_DATA_LEN_ERR_MASK_EN		0x100
+#else
+#define EDMA_MISC_DATA_LEN_ERR_MASK_EN		0x40
+#define EDMA_MISC_TX_TIMEOUT_MASK_EN		0x80
+#endif
+
+#endif /*  __EDMA_REGS__ */

feeds/ipq807x/qca-nss-dp/src/hal/edma/edma_tx_rx.c

@@ -0,0 +1,795 @@
+/*
+ * Copyright (c) 2016-2018, 2020-21, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+ * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT
+ * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+ * USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/version.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+#include <linux/debugfs.h>
+
+#include "nss_dp_dev.h"
+#include "edma_regs.h"
+#include "edma_data_plane.h"
+
+/*
+ * edma_alloc_rx_buffer()
+ *	Alloc Rx buffers for one RxFill ring
+ */
+int edma_alloc_rx_buffer(struct edma_hw *ehw,
+		struct edma_rxfill_ring *rxfill_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct sk_buff *skb;
+	uint16_t num_alloc = 0;
+	uint16_t cons, next, counter;
+	struct edma_rxfill_desc *rxfill_desc;
+	uint32_t reg_data = 0;
+	uint32_t store_index = 0;
+	struct edma_rx_preheader *rxph = NULL;
+
+	/*
+	 * Read RXFILL ring producer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id));
+	next = reg_data & EDMA_RXFILL_PROD_IDX_MASK & (rxfill_ring->count - 1);
+
+	/*
+	 * Read RXFILL ring consumer index
+	 */
+	reg_data = edma_reg_read(EDMA_REG_RXFILL_CONS_IDX(rxfill_ring->id));
+	cons = reg_data & EDMA_RXFILL_CONS_IDX_MASK;
+
+	while (1) {
+		counter = next;
+		if (++counter == rxfill_ring->count)
+			counter = 0;
+
+		if (counter == cons)
+			break;
+
+		/*
+		 * Allocate buffer
+		 */
+		skb = dev_alloc_skb(EDMA_RX_BUFF_SIZE);
+		if (unlikely(!skb))
+			break;
+
+		/*
+		 * Get RXFILL descriptor
+		 */
+		rxfill_desc = EDMA_RXFILL_DESC(rxfill_ring, next);
+
+		/*
+		 * Make room for Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			skb_push(skb, EDMA_RX_PREHDR_SIZE);
+
+		/*
+		 * Store the skb in the rx store
+		 */
+		store_index = next;
+		if (ehw->rx_skb_store[store_index] != NULL) {
+			dev_kfree_skb_any(skb);
+			break;
+		}
+		ehw->rx_skb_store[store_index] = skb;
+		memcpy((uint8_t *)&rxph->opaque, (uint8_t *)&store_index, 4);
+		/*
+		 * Save buffer size in RXFILL descriptor
+		 */
+		rxfill_desc->word1 = cpu_to_le32(EDMA_RX_BUFF_SIZE
+					& EDMA_RXFILL_BUF_SIZE_MASK);
+
+		/*
+		 * Map Rx buffer for DMA
+		 */
+		rxfill_desc->buffer_addr = cpu_to_le32(dma_map_single(
+						&pdev->dev,
+						skb->data,
+						EDMA_RX_BUFF_SIZE,
+						DMA_FROM_DEVICE));
+
+		if (!rxfill_desc->buffer_addr) {
+			dev_kfree_skb_any(skb);
+			ehw->rx_skb_store[store_index] = NULL;
+			break;
+		}
+
+		num_alloc++;
+		next = counter;
+	}
+
+	if (num_alloc) {
+		/*
+		 * Update RXFILL ring producer index
+		 */
+		reg_data = next & EDMA_RXFILL_PROD_IDX_MASK;
+
+		/*
+		 * make sure the producer index updated before
+		 * updating the hardware
+		 */
+		wmb();
+
+		edma_reg_write(EDMA_REG_RXFILL_PROD_IDX(rxfill_ring->id),
+				reg_data);
+	}
+
+	return num_alloc;
+}
+
+/*
+ * edma_clean_tx()
+ *	Reap Tx descriptors
+ */
+uint32_t edma_clean_tx(struct edma_hw *ehw,
+			struct edma_txcmpl_ring *txcmpl_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct edma_txcmpl_desc *txcmpl = NULL;
+	uint16_t prod_idx = 0;
+	uint16_t cons_idx = 0;
+	uint32_t data = 0;
+	uint32_t txcmpl_consumed = 0;
+	struct sk_buff *skb;
+	uint32_t len;
+	int store_index;
+	dma_addr_t daddr;
+
+	/*
+	 * Get TXCMPL ring producer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXCMPL_PROD_IDX(txcmpl_ring->id));
+	prod_idx = data & EDMA_TXCMPL_PROD_IDX_MASK;
+
+	/*
+	 * Get TXCMPL ring consumer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id));
+	cons_idx = data & EDMA_TXCMPL_CONS_IDX_MASK;
+
+	while (cons_idx != prod_idx) {
+		txcmpl = &(((struct edma_txcmpl_desc *)
+					(txcmpl_ring->desc))[cons_idx]);
+
+		/*
+		 * skb for this is stored in tx store and
+		 * tx header contains the index in the field
+		 * buffer address (opaque) of txcmpl
+		 */
+		store_index = txcmpl->buffer_addr;
+		skb = ehw->tx_skb_store[store_index];
+		ehw->tx_skb_store[store_index] = NULL;
+
+		if (unlikely(!skb)) {
+			pr_warn("Invalid skb: cons_idx:%u prod_idx:%u status %x\n",
+				  cons_idx, prod_idx, txcmpl->status);
+			goto next_txcmpl_desc;
+		}
+
+		len = skb_headlen(skb);
+		daddr = (dma_addr_t)virt_to_phys(skb->data);
+
+		pr_debug("skb:%px cons_idx:%d prod_idx:%d word1:0x%x\n",
+			   skb, cons_idx, prod_idx, txcmpl->status);
+
+		dma_unmap_single(&pdev->dev, daddr,
+				 len, DMA_TO_DEVICE);
+		dev_kfree_skb_any(skb);
+
+next_txcmpl_desc:
+		if (++cons_idx == txcmpl_ring->count)
+			cons_idx = 0;
+
+		txcmpl_consumed++;
+	}
+
+	if (txcmpl_consumed == 0)
+		return 0;
+
+	pr_debug("TXCMPL:%u txcmpl_consumed:%u prod_idx:%u cons_idx:%u\n",
+			txcmpl_ring->id, txcmpl_consumed, prod_idx, cons_idx);
+
+	/*
+	 * Update TXCMPL ring consumer index
+	 */
+	wmb();
+	edma_reg_write(EDMA_REG_TXCMPL_CONS_IDX(txcmpl_ring->id), cons_idx);
+
+	return txcmpl_consumed;
+}
+
+/*
+ * nss_phy_tstamp_rx_buf()
+ *	Receive timestamp packet
+ */
+void nss_phy_tstamp_rx_buf(__attribute__((unused))void *app_data, struct sk_buff *skb)
+{
+	struct net_device *ndev = skb->dev;
+
+	/*
+	 * The PTP_CLASS_ value 0 is passed to phy driver, which will be
+	 * set to the correct PTP class value by calling ptp_classify_raw
+	 * in drv->rxtstamp function.
+	 */
+	if (ndev && ndev->phydev && ndev->phydev->drv &&
+			ndev->phydev->drv->rxtstamp)
+		if(ndev->phydev->drv->rxtstamp(ndev->phydev, skb, 0))
+			return;
+
+	netif_receive_skb(skb);
+}
+EXPORT_SYMBOL(nss_phy_tstamp_rx_buf);
+
+/*
+ * nss_phy_tstamp_tx_buf()
+ *	Transmit timestamp packet
+ */
+void nss_phy_tstamp_tx_buf(struct net_device *ndev, struct sk_buff *skb)
+{
+	/*
+	 * Function drv->txtstamp will create a clone of skb if necessary,
+	 * the PTP_CLASS_ value 0 is passed to phy driver, which will be
+	 * set to the correct PTP class value by calling ptp_classify_raw
+	 * in the drv->txtstamp function.
+	 */
+	if (ndev && ndev->phydev && ndev->phydev->drv &&
+			ndev->phydev->drv->txtstamp)
+		ndev->phydev->drv->txtstamp(ndev->phydev, skb, 0);
+}
+EXPORT_SYMBOL(nss_phy_tstamp_tx_buf);
+
+/*
+ * edma_clean_rx()
+ *	Reap Rx descriptors
+ */
+static uint32_t edma_clean_rx(struct edma_hw *ehw,
+				int work_to_do,
+				struct edma_rxdesc_ring *rxdesc_ring)
+{
+	struct platform_device *pdev = ehw->pdev;
+	struct net_device *ndev;
+	struct sk_buff *skb = NULL;
+	struct edma_rxdesc_desc *rxdesc_desc;
+	struct edma_rx_preheader *rxph = NULL;
+	uint16_t prod_idx = 0;
+	int src_port_num = 0;
+	int pkt_length = 0;
+	uint16_t cons_idx = 0;
+	uint32_t work_done = 0;
+	int store_index;
+
+	/*
+	 * Read Rx ring consumer index
+	 */
+	cons_idx = edma_reg_read(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id))
+				& EDMA_RXDESC_CONS_IDX_MASK;
+
+	while (1) {
+		/*
+		 * Read Rx ring producer index
+		 */
+		prod_idx = edma_reg_read(
+			EDMA_REG_RXDESC_PROD_IDX(rxdesc_ring->id))
+			& EDMA_RXDESC_PROD_IDX_MASK;
+
+		if (cons_idx == prod_idx)
+			break;
+
+		if (work_done >= work_to_do)
+			break;
+
+		rxdesc_desc = EDMA_RXDESC_DESC(rxdesc_ring, cons_idx);
+
+		/*
+		 * Get Rx preheader
+		 */
+		rxph = (struct edma_rx_preheader *)
+			phys_to_virt(rxdesc_desc->buffer_addr);
+
+		/*
+		 * DMA unmap Rx buffer
+		 */
+		dma_unmap_single(&pdev->dev,
+				 rxdesc_desc->buffer_addr,
+				 EDMA_RX_BUFF_SIZE,
+				 DMA_FROM_DEVICE);
+
+		store_index = rxph->opaque;
+		skb = ehw->rx_skb_store[store_index];
+		ehw->rx_skb_store[store_index] = NULL;
+		if (unlikely(!skb)) {
+			pr_warn("WARN: empty skb reference in rx_store:%d\n",
+					cons_idx);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Check src_info from Rx preheader
+		 */
+		if (EDMA_RXPH_SRC_INFO_TYPE_GET(rxph) ==
+				EDMA_PREHDR_DSTINFO_PORTID_IND) {
+			src_port_num = rxph->src_info &
+				EDMA_PREHDR_PORTNUM_BITS;
+		} else {
+			pr_warn("WARN: src_info_type:0x%x. Drop skb:%px\n",
+				  EDMA_RXPH_SRC_INFO_TYPE_GET(rxph), skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Get packet length
+		 */
+		pkt_length = rxdesc_desc->status & EDMA_RXDESC_PACKET_LEN_MASK;
+
+		if (unlikely((src_port_num < NSS_DP_START_IFNUM)  ||
+			(src_port_num > NSS_DP_HAL_MAX_PORTS))) {
+			pr_warn("WARN: Port number error :%d. Drop skb:%px\n",
+					src_port_num, skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Get netdev for this port using the source port
+		 * number as index into the netdev array. We need to
+		 * subtract one since the indices start form '0' and
+		 * port numbers start from '1'.
+		 */
+		ndev = ehw->netdev_arr[src_port_num - 1];
+		if (unlikely(!ndev)) {
+			pr_warn("WARN: netdev Null src_info_type:0x%x. Drop skb:%px\n",
+					src_port_num, skb);
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		if (unlikely(!netif_running(ndev))) {
+			dev_kfree_skb_any(skb);
+			goto next_rx_desc;
+		}
+
+		/*
+		 * Remove Rx preheader
+		 */
+		skb_pull(skb, EDMA_RX_PREHDR_SIZE);
+
+		/*
+		 * Update skb fields and indicate packet to stack
+		 */
+		skb->dev = ndev;
+		skb->skb_iif = ndev->ifindex;
+		skb_put(skb, pkt_length);
+		skb->protocol = eth_type_trans(skb, skb->dev);
+#ifdef CONFIG_NET_SWITCHDEV
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0))
+		skb->offload_fwd_mark = ndev->offload_fwd_mark;
+#else
+		/*
+		 * TODO: Implement ndo_get_devlink_port()
+		 */
+		 skb->offload_fwd_mark = 0;
+#endif
+		pr_debug("skb:%px ring_idx:%u pktlen:%d proto:0x%x mark:%u\n",
+			   skb, cons_idx, pkt_length, skb->protocol,
+			   skb->offload_fwd_mark);
+#else
+		pr_debug("skb:%px ring_idx:%u pktlen:%d proto:0x%x\n",
+			   skb, cons_idx, pkt_length, skb->protocol);
+#endif
+		/*
+		 * Deliver the ptp packet to phy driver for RX timestamping
+		 */
+		if (unlikely(EDMA_RXPH_SERVICE_CODE_GET(rxph) ==
+					NSS_PTP_EVENT_SERVICE_CODE))
+			nss_phy_tstamp_rx_buf(ndev, skb);
+		else
+			netif_receive_skb(skb);
+
+next_rx_desc:
+		/*
+		 * Update consumer index
+		 */
+		if (++cons_idx == rxdesc_ring->count)
+			cons_idx = 0;
+
+		/*
+		 * Update work done
+		 */
+		work_done++;
+	}
+
+	edma_alloc_rx_buffer(ehw, rxdesc_ring->rxfill);
+
+	/*
+	 * make sure the consumer index is updated
+	 * before updating the hardware
+	 */
+	wmb();
+	edma_reg_write(EDMA_REG_RXDESC_CONS_IDX(rxdesc_ring->id), cons_idx);
+	return work_done;
+}
+
+/*
+ * edma_napi()
+ *	EDMA NAPI handler
+ */
+int edma_napi(struct napi_struct *napi, int budget)
+{
+	struct edma_hw *ehw = container_of(napi, struct edma_hw, napi);
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+
+	struct net_device *ndev;
+	int work_done = 0;
+	int i;
+
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		work_done += edma_clean_rx(ehw, budget, rxdesc_ring);
+	}
+
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		work_done += edma_clean_tx(ehw, txcmpl_ring);
+	}
+
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		work_done += edma_alloc_rx_buffer(ehw, rxfill_ring);
+	}
+
+	/*
+	 * Resume netdev Tx queue
+	 */
+	/*
+	 * TODO works currently since we have a single queue.
+	 * Need to make sure we have support in place when there is
+	 * support for multiple queues
+	 */
+	for (i = 0; i < EDMA_MAX_GMACS; i++) {
+		ndev = ehw->netdev_arr[i];
+		if (!ndev)
+			continue;
+
+		if (netif_queue_stopped(ndev) && netif_carrier_ok(ndev))
+			netif_start_queue(ndev);
+	}
+
+	/*
+	 * TODO - rework and fix the budget control
+	 */
+	if (work_done < budget) {
+		/*
+		 * TODO per core NAPI
+		 */
+		napi_complete(napi);
+
+		/*
+		 * Set RXDESC ring interrupt mask
+		 */
+		for (i = 0; i < ehw->rxdesc_rings; i++) {
+			rxdesc_ring = &ehw->rxdesc_ring[i];
+			edma_reg_write(
+				EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+				ehw->rxdesc_intr_mask);
+		}
+
+		/*
+		 * Set TXCMPL ring interrupt mask
+		 */
+		for (i = 0; i < ehw->txcmpl_rings; i++) {
+			txcmpl_ring = &ehw->txcmpl_ring[i];
+			edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+					ehw->txcmpl_intr_mask);
+		}
+
+		/*
+		 * Set RXFILL ring interrupt mask
+		 */
+		for (i = 0; i < ehw->rxfill_rings; i++) {
+			rxfill_ring = &ehw->rxfill_ring[i];
+			edma_reg_write(EDMA_REG_RXFILL_INT_MASK(
+						rxfill_ring->id),
+						edma_hw.rxfill_intr_mask);
+		}
+	}
+	return work_done;
+}
+
+/*
+ * edma_ring_xmit()
+ *	Transmit a packet using an EDMA ring
+ */
+enum edma_tx edma_ring_xmit(struct edma_hw *ehw,
+			    struct net_device *netdev,
+			    struct sk_buff *skb,
+			    struct edma_txdesc_ring *txdesc_ring)
+{
+	struct nss_dp_dev *dp_dev = netdev_priv(netdev);
+	struct edma_txdesc_desc *txdesc = NULL;
+	uint16_t buf_len;
+	uint16_t hw_next_to_use, hw_next_to_clean, chk_idx;
+	uint32_t data;
+	uint32_t store_index = 0;
+	struct edma_tx_preheader *txph = NULL;
+
+	/*
+	 * TODO - revisit locking
+	 */
+	spin_lock_bh(&txdesc_ring->tx_lock);
+
+	/*
+	 * Read TXDESC ring producer index
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id));
+	hw_next_to_use = data & EDMA_TXDESC_PROD_IDX_MASK;
+
+	/*
+	 * Read TXDESC ring consumer index
+	 */
+	/*
+	 * TODO - read to local variable to optimize uncached access
+	 */
+	data = edma_reg_read(EDMA_REG_TXDESC_CONS_IDX(txdesc_ring->id));
+	hw_next_to_clean = data & EDMA_TXDESC_CONS_IDX_MASK;
+
+	/*
+	 * Check for available Tx descriptor
+	 */
+	chk_idx = (hw_next_to_use + 1) & (txdesc_ring->count-1);
+
+	if (chk_idx == hw_next_to_clean) {
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_DESC;
+	}
+
+#if defined(NSS_DP_EDMA_TX_SMALL_PKT_WAR)
+	/*
+	 * IPQ807x EDMA hardware can't process the packet if the packet size is
+	 * less than EDMA_TX_PKT_MIN_SIZE (33 Byte). So, if the packet size
+	 * is indeed less than EDMA_TX_PKT_MIN_SIZE, perform padding
+	 * (if possible), otherwise drop the packet.
+	 * Using skb_padto() API for padding the packet. This API will drop
+	 * the packet if the padding is not possible.
+	 */
+	if (unlikely(skb->len < EDMA_TX_PKT_MIN_SIZE)) {
+		if (skb_padto(skb, EDMA_TX_PKT_MIN_SIZE)) {
+			netdev_dbg(netdev, "padding couldn't happen, skb is freed.\n");
+			netdev->stats.tx_dropped++;
+			spin_unlock_bh(&txdesc_ring->tx_lock);
+			return EDMA_TX_OK;
+		}
+		skb->len = EDMA_TX_PKT_MIN_SIZE;
+	}
+#endif
+
+	buf_len = skb_headlen(skb);
+
+	/*
+	 * Deliver the ptp packet to phy driver for TX timestamping
+	 */
+	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
+		nss_phy_tstamp_tx_buf(netdev, skb);
+
+	/*
+	 * Make room for Tx preheader
+	 */
+	txph = (struct edma_tx_preheader *)skb_push(skb,
+			EDMA_TX_PREHDR_SIZE);
+	memset((void *)txph, 0, EDMA_TX_PREHDR_SIZE);
+
+	/*
+	 * Populate Tx preheader dst info, port id is macid in dp_dev
+	 */
+	txph->dst_info = (EDMA_PREHDR_DSTINFO_PORTID_IND << 8) |
+			(dp_dev->macid & 0x0fff);
+
+	/*
+	 * Store the skb in tx_store
+	 */
+	store_index = hw_next_to_use & (txdesc_ring->count - 1);
+	if (unlikely(ehw->tx_skb_store[store_index] != NULL)) {
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_DESC;
+	}
+
+	ehw->tx_skb_store[store_index] = skb;
+	memcpy(skb->data, &store_index, 4);
+
+	/*
+	 * Get Tx descriptor
+	 */
+	txdesc = EDMA_TXDESC_DESC(txdesc_ring, hw_next_to_use);
+	memset(txdesc, 0, sizeof(struct edma_txdesc_desc));
+
+	/*
+	 * Map buffer to DMA address
+	 */
+	txdesc->buffer_addr = cpu_to_le32(dma_map_single(&(ehw->pdev)->dev,
+				       skb->data,
+				       buf_len + EDMA_TX_PREHDR_SIZE,
+				       DMA_TO_DEVICE));
+	if (!txdesc->buffer_addr) {
+		/*
+		 * DMA map failed for this address. Drop it
+		 * and make sure does not got to stack again
+		 */
+		dev_kfree_skb_any(skb);
+
+		ehw->tx_skb_store[store_index] = NULL;
+		spin_unlock_bh(&txdesc_ring->tx_lock);
+		return EDMA_TX_OK;
+	}
+
+	/*
+	 * Populate Tx descriptor
+	 */
+	txdesc->word1 |= (1 << EDMA_TXDESC_PREHEADER_SHIFT)
+			| ((EDMA_TX_PREHDR_SIZE & EDMA_TXDESC_DATA_OFFSET_MASK)
+			   << EDMA_TXDESC_DATA_OFFSET_SHIFT);
+	txdesc->word1 |= ((buf_len & EDMA_TXDESC_DATA_LENGTH_MASK)
+			<< EDMA_TXDESC_DATA_LENGTH_SHIFT);
+
+	netdev_dbg(netdev, "skb:%px tx_ring:%u proto:0x%x\n",
+			skb, txdesc_ring->id, ntohs(skb->protocol));
+	netdev_dbg(netdev, "port:%u prod_idx:%u cons_idx:%u\n",
+			dp_dev->macid, hw_next_to_use, hw_next_to_clean);
+
+	/*
+	 * Update producer index
+	 */
+	hw_next_to_use = (hw_next_to_use + 1) & (txdesc_ring->count - 1);
+
+	/*
+	 * make sure the hw_next_to_use is updated before the
+	 * write to hardware
+	 */
+	wmb();
+
+	edma_reg_write(EDMA_REG_TXDESC_PROD_IDX(txdesc_ring->id),
+		       hw_next_to_use & EDMA_TXDESC_PROD_IDX_MASK);
+	spin_unlock_bh(&txdesc_ring->tx_lock);
+	return EDMA_TX_OK;
+}
+
+/*
+ * edma_handle_misc_irq()
+ *	Process IRQ
+ */
+irqreturn_t edma_handle_misc_irq(int irq, void *ctx)
+{
+	uint32_t misc_intr_status = 0;
+	uint32_t reg_data = 0;
+	struct edma_hw *ehw = NULL;
+	struct platform_device *pdev = (struct platform_device *)ctx;
+
+	ehw = platform_get_drvdata(pdev);
+
+	/*
+	 * Read Misc intr status
+	 */
+	reg_data = edma_reg_read(EDMA_REG_MISC_INT_STAT);
+	misc_intr_status = reg_data & ehw->misc_intr_mask;
+
+	/*
+	 * TODO - error logging
+	 */
+	if (misc_intr_status == 0)
+		return IRQ_NONE;
+	else
+		edma_reg_write(EDMA_REG_MISC_INT_MASK, EDMA_MASK_INT_DISABLE);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * edma_handle_irq()
+ *	Process IRQ and schedule napi
+ */
+irqreturn_t edma_handle_irq(int irq, void *ctx)
+{
+	uint32_t reg_data = 0;
+	uint32_t rxdesc_intr_status = 0;
+	uint32_t txcmpl_intr_status = 0;
+	uint32_t rxfill_intr_status = 0;
+	int i;
+	struct edma_txcmpl_ring *txcmpl_ring = NULL;
+	struct edma_rxdesc_ring *rxdesc_ring = NULL;
+	struct edma_rxfill_ring *rxfill_ring = NULL;
+	struct edma_hw *ehw = NULL;
+	struct platform_device *pdev = (struct platform_device *)ctx;
+
+	ehw = platform_get_drvdata(pdev);
+	if (!ehw) {
+		pr_info("Unable to retrieve platrofm data");
+		return IRQ_HANDLED;
+	}
+
+	/*
+	 * Read RxDesc intr status
+	 */
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_RXDESC_INT_STAT(rxdesc_ring->id));
+		rxdesc_intr_status |= reg_data &
+				EDMA_RXDESC_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable RxDesc intr
+		 */
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 * Read TxCmpl intr status
+	 */
+	for (i = 0; i < ehw->txcmpl_rings; i++) {
+		txcmpl_ring = &ehw->txcmpl_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_TX_INT_STAT(txcmpl_ring->id));
+		txcmpl_intr_status |= reg_data &
+				EDMA_TXCMPL_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable TxCmpl intr
+		 */
+		edma_reg_write(EDMA_REG_TX_INT_MASK(txcmpl_ring->id),
+				EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 * Read RxFill intr status
+	 */
+	for (i = 0; i < ehw->rxfill_rings; i++) {
+		rxfill_ring = &ehw->rxfill_ring[i];
+		reg_data = edma_reg_read(
+				EDMA_REG_RXFILL_INT_STAT(rxfill_ring->id));
+		rxfill_intr_status |= reg_data &
+				EDMA_RXFILL_RING_INT_STATUS_MASK;
+
+		/*
+		 * Disable RxFill intr
+		 */
+		edma_reg_write(EDMA_REG_RXFILL_INT_MASK(rxfill_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+
+	}
+
+	if ((rxdesc_intr_status == 0) && (txcmpl_intr_status == 0) &&
+			(rxfill_intr_status == 0))
+		return IRQ_NONE;
+
+	for (i = 0; i < ehw->rxdesc_rings; i++) {
+		rxdesc_ring = &ehw->rxdesc_ring[i];
+		edma_reg_write(EDMA_REG_RXDESC_INT_MASK(rxdesc_ring->id),
+			       EDMA_MASK_INT_DISABLE);
+	}
+
+	/*
+	 *TODO - per core NAPI
+	 */
+	if (rxdesc_intr_status || txcmpl_intr_status || rxfill_intr_status)
+		if (likely(napi_schedule_prep(&ehw->napi)))
+			__napi_schedule(&ehw->napi);
+
+	return IRQ_HANDLED;
+}

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/qcom/qcom_dev.h

@@ -0,0 +1,697 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __QCOM_DEV_H__
+#define __QCOM_DEV_H__
+
+#include <nss_dp_hal_if.h>
+#include "qcom_reg.h"
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+
+/*
+ * Subclass for base nss_gmac_haldev
+ */
+struct qcom_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+	fal_mib_counter_t stats;	/* Stats structure */
+};
+/*
+ * qcom_set_rx_flow_ctrl()
+ */
+static inline void qcom_set_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_RX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_rx_flow_ctrl()
+ */
+static inline void qcom_clear_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_RX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_set_tx_flow_ctrl()
+ */
+static inline void qcom_set_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_TX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_tx_flow_ctrl()
+ */
+static inline void qcom_clear_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_TX_FLOW_ENABLE);
+}
+
+/*
+ * qcom_clear_mac_ctrl0()
+ */
+static inline void qcom_clear_mac_ctrl0(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL0, 0);
+}
+
+/*
+ * qcom_rx_enable()
+ */
+static inline void qcom_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_RX_MAC_ENABLE);
+}
+
+/*
+ * qcom_rx_disable()
+ *	Disable the reception of frames on GMII/MII.
+ *	GMAC receive state machine is disabled after completion of reception of
+ *	current frame.
+ */
+static inline void qcom_rx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_RX_MAC_ENABLE);
+}
+
+/*
+ * qcom_tx_enable()
+ */
+static inline void qcom_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_TX_MAC_ENABLE);
+}
+
+/*
+ * qcom_tx_disable()
+ *	Disable the transmission of frames on GMII/MII.
+ *	GMAC transmit state machine is disabled after completion of
+ *	transmission of current frame.
+ */
+static inline void qcom_tx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_TX_MAC_ENABLE);
+}
+
+/*
+ * qcom_set_full_duplex()
+ */
+static inline void qcom_set_full_duplex(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_DUPLEX);
+}
+
+/*
+ * qcom_set_half_duplex()
+ */
+static inline void qcom_set_half_duplex(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_ENABLE, QCOM_DUPLEX);
+}
+
+/*
+ * qcom_set_ipgt()
+ */
+static inline void qcom_set_ipgt(struct nss_gmac_hal_dev *nghd, uint32_t ipgt)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL0);
+	data &= ~QCOM_IPGT_POS;
+	ipgt = ipgt << QCOM_IPGT_LSB;
+	data |= ipgt;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL0, data);
+}
+
+/*
+ * qcom_set_ipgr()
+ */
+static inline void qcom_set_ipgr(struct nss_gmac_hal_dev *nghd, uint32_t ipgr)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL0);
+	data &= ~QCOM_IPGR2_POS;
+	ipgr = ipgr << QCOM_IPGR2_LSB;
+	data |= ipgr;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL0, data);
+}
+
+/*
+ * qcom_set_half_thdf_ctrl()
+ */
+static inline void qcom_set_half_thdf_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_HALF_THDF_CTRL);
+}
+
+/*
+ * qcom_reset_half_thdf_ctrl()
+ */
+static inline void qcom_reset_half_thdf_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_HALF_THDF_CTRL);
+}
+
+/*
+ * qcom_set_frame_len_chk()
+ */
+static inline void qcom_set_frame_len_chk(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_FLCHK);
+}
+
+/*
+ * qcom_reset_frame_len_chk()
+ */
+static inline void qcom_reset_frame_len_chk(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_FLCHK);
+}
+
+/*
+ * qcom_set_abebe()
+ */
+static inline void qcom_set_abebe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_ABEBE);
+}
+
+/*
+ * qcom_reset_abebe()
+ */
+static inline void qcom_reset_abebe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_ABEBE);
+}
+
+/*
+ * qcom_set_amaxe()
+ */
+static inline void qcom_set_amaxe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_AMAXE);
+}
+
+/*
+ * qcom_reset_amaxe()
+ */
+static inline void qcom_reset_amaxe(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_AMAXE);
+}
+
+/*
+ * qcom_set_bpnb()
+ */
+static inline void qcom_set_bpnb(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_BPNB);
+}
+
+/*
+ * qcom_reset_bpnb()
+ */
+static inline void qcom_reset_bpnb(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_BPNB);
+}
+
+/*
+ * qcom_set_nobo()
+ */
+static inline void qcom_set_nobo(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_NOBO);
+}
+
+/*
+ * qcom_reset_nobo()
+ */
+static inline void qcom_reset_nobo(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_NOBO);
+}
+
+/*
+ * qcom_set_drbnib_rxok()
+ */
+static inline void qcom_set_drbnib_rxok(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_DRBNIB_RXOK);
+}
+
+/*
+ * qcom_reset_drbnib_rxok()
+ */
+static inline void qcom_reset_drbnib_rxok(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL0, QCOM_DRBNIB_RXOK);
+}
+
+/*
+ * qcom_set_jam_ipg()
+ */
+static inline void qcom_set_jam_ipg(struct nss_gmac_hal_dev *nghd,
+							uint32_t jam_ipg)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_JAM_IPG_POS;
+	jam_ipg = jam_ipg << QCOM_JAM_IPG_LSB;
+	data |= jam_ipg;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_ctrl1_test_pause()
+ */
+static inline void qcom_set_ctrl1_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_TPAUSE);
+}
+
+/*
+ * qcom_reset_ctrl1_test_pause()
+ */
+static inline void qcom_reset_ctrl1_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_TPAUSE);
+}
+
+/*
+ * qcom_reset_ctrl1_test_pause()
+ */
+static inline void qcom_set_tctl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_TCTL);
+}
+
+/*
+ * qcom_reset_tctl()
+ */
+static inline void qcom_reset_tctl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_TCTL);
+}
+
+/*
+ * qcom_set_sstct()
+ */
+static inline void qcom_set_sstct(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_SSTCT);
+}
+
+/*
+ * qcom_reset_sstct()
+ */
+static inline void qcom_reset_sstct(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_SSTCT);
+}
+
+/*
+ * qcom_set_simr()
+ */
+static inline void qcom_set_simr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_SIMR);
+}
+
+/*
+ * qcom_reset_simr()
+ */
+static inline void qcom_reset_simr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_SIMR);
+}
+
+/*
+ * qcom_set_retry()
+ */
+static inline void qcom_set_retry(struct nss_gmac_hal_dev *nghd, uint32_t retry)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_RETRY_POS;
+	retry = retry << QCOM_RETRY_LSB;
+	data |= retry;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_prlen()
+ */
+static inline void qcom_set_prlen(struct nss_gmac_hal_dev *nghd, uint32_t prlen)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_PRLEN_POS;
+	prlen = prlen << QCOM_PRLEN_LSB;
+	data |= prlen;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_ppad()
+ */
+static inline void qcom_set_ppad(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_PPAD);
+}
+
+/*
+ * qcom_reset_ppad()
+ */
+static inline void qcom_reset_ppad(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_PPAD);
+}
+
+/*
+ * qcom_set_povr()
+ */
+static inline void qcom_set_povr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_POVR);
+}
+
+/*
+ * qcom_reset_povr()
+ */
+static inline void qcom_reset_povr(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_POVR);
+}
+
+/*
+ * qcom_set_phug()
+ */
+static inline void qcom_set_phug(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_PHUG);
+}
+
+/*
+ * qcom_reset_phug()
+ */
+static inline void qcom_reset_phug(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_PHUG);
+}
+
+/*
+ * qcom_set_mbof()
+ */
+static inline void qcom_set_mbof(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_MBOF);
+}
+
+/*
+ * qcom_reset_mbof()
+ */
+static inline void qcom_reset_mbof(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_MBOF);
+}
+
+/*
+ * qcom_set_lcol()
+ */
+static inline void qcom_set_lcol(struct nss_gmac_hal_dev *nghd, uint32_t lcol)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_CTRL1);
+	data &= ~QCOM_LCOL_POS;
+	lcol = lcol << QCOM_LCOL_LSB;
+	data |= lcol;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_CTRL1, data);
+}
+
+/*
+ * qcom_set_long_jam()
+ */
+static inline void qcom_set_long_jam(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_LONG_JAM);
+}
+
+/*
+ * qcom_reset_long_jam()
+ */
+static inline void qcom_reset_long_jam(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL1, QCOM_LONG_JAM);
+}
+
+/*
+ * qcom_set_ipg_dec_len()
+ */
+static inline void qcom_set_ipg_dec_len(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_IPG_DEC_LEN);
+}
+
+/*
+ * qcom_reset_ipg_dec_len()
+ */
+static inline void qcom_reset_ipg_dec_len(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_IPG_DEC_LEN);
+}
+
+/*
+ * qcom_set_ctrl2_test_pause()
+ */
+static inline void qcom_set_ctrl2_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_TEST_PAUSE);
+}
+
+/*
+ * qcom_reset_ctrl2_test_pause()
+ */
+static inline void qcom_reset_ctrl2_test_pause(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_TEST_PAUSE);
+}
+
+/*
+ * qcom_set_mac_loopback()
+ */
+static inline void qcom_set_mac_loopback(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_MAC_LOOPBACK);
+}
+
+/*
+ * qcom_reset_mac_loopback()
+ */
+static inline void qcom_reset_mac_loopback(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_MAC_LOOPBACK);
+}
+
+/*
+ * qcom_set_ipg_dec()
+ */
+static inline void qcom_set_ipg_dec(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_IPG_DEC);
+}
+
+/*
+ * qcom_reset_ipg_dec()
+ */
+static inline void qcom_reset_ipg_dec(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_IPG_DEC);
+}
+
+/*
+ * qcom_set_crs_sel()
+ */
+static inline void qcom_set_crs_sel(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_SRS_SEL);
+}
+
+/*
+ * qcom_reset_crs_sel()
+ */
+static inline void qcom_reset_crs_sel(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_SRS_SEL);
+}
+
+/*
+ * qcom_set_crc_rsv()
+ */
+static inline void qcom_set_crc_rsv(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_CRC_RSV);
+}
+
+/*
+ * qcom_reset_crc_rsv()
+ */
+static inline void qcom_reset_crc_rsv(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_CTRL2, QCOM_CRC_RSV);
+}
+
+/*
+ * qcom_set_ipgr1()
+ */
+static inline void qcom_set_ipgr1(struct nss_gmac_hal_dev *nghd, uint32_t ipgr1)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_IPGR1_POS;
+	ipgr1 = ipgr1 << QCOM_DBG_IPGR1_LSB;
+	data |= ipgr1;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_hihg_ipg()
+ */
+static inline void qcom_set_hihg_ipg(struct nss_gmac_hal_dev *nghd,
+			uint32_t hihg_ipg)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_HIHG_IPG_POS;
+	data |= hihg_ipg << QCOM_DBG_HIHG_IPG_LSB;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_mac_ipg_ctrl()
+ */
+static inline void qcom_set_mac_ipg_ctrl(struct nss_gmac_hal_dev *nghd,
+			uint32_t mac_ipg_ctrl)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL);
+	data &= ~QCOM_DBG_MAC_IPG_CTRL_POS;
+	data |= mac_ipg_ctrl << QCOM_DBG_MAC_IPG_CTRL_LSB;
+	hal_write_reg(nghd->mac_base, QCOM_MAC_DBG_CTRL, data);
+}
+
+/*
+ * qcom_set_mac_len_ctrl()
+ */
+static inline void qcom_set_mac_len_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_DBG_CTRL, QCOM_DBG_MAC_LEN_CTRL);
+}
+
+/*
+ * qcom_reset_mac_len_ctrl()
+ */
+static inline void qcom_reset_mac_len_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_DBG_CTRL, QCOM_DBG_MAC_LEN_CTRL);
+}
+
+/*
+ * qcom_set_edxsdfr_transmit()
+ */
+static inline void qcom_set_edxsdfr_transmit(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_DBG_CTRL, QCOM_DBG_EDxSDFR_TRANS);
+}
+
+/*
+ * qcom_reset_edxsdfr_transmit()
+ */
+static inline void qcom_reset_edxsdfr_transmit(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, QCOM_MAC_DBG_CTRL, QCOM_DBG_EDxSDFR_TRANS);
+}
+
+/*
+ * qcom_set_mac_dbg_addr()
+ */
+static inline void qcom_set_mac_dbg_addr(struct nss_gmac_hal_dev *nghd,
+						uint8_t mac_dbg_addr)
+{
+	hal_write_reg(nghd->mac_base, QCOM_MAC_DBG_ADDR, mac_dbg_addr);
+}
+
+/*
+ * qcom_set_mac_dbg_data()
+ */
+static inline void qcom_set_mac_dbg_data(struct nss_gmac_hal_dev *nghd,
+						uint32_t mac_dbg_data)
+{
+	hal_write_reg(nghd->mac_base, QCOM_MAC_DBG_DATA, mac_dbg_data);
+}
+
+/*
+ * qcom_set_mac_jumbosize()
+ */
+static inline void qcom_set_mac_jumbosize(struct nss_gmac_hal_dev *nghd,
+						uint16_t mac_jumbo_size)
+{
+	hal_write_reg(nghd->mac_base, QCOM_MAC_JMB_SIZE, mac_jumbo_size);
+}
+
+/*
+ * qcom_clear_mib_ctrl()
+ */
+static inline void qcom_clear_mib_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, QCOM_MAC_MIB_CTRL, 0);
+}
+
+/*
+ * qcom_set_mib_ctrl()
+ */
+static inline void qcom_set_mib_ctrl(struct nss_gmac_hal_dev *nghd,
+						int mib_settings)
+{
+	hal_set_reg_bits(nghd, QCOM_MAC_MIB_CTRL,
+			mib_settings);
+}
+
+/*
+ * qcom_get_stats()
+ */
+static int qcom_get_stats(struct nss_gmac_hal_dev *nghd)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *stats = &(qhd->stats);
+
+	if (fal_mib_counter_get(0, nghd->mac_id, stats) < 0)
+		return -1;
+
+	return 0;
+}
+#endif /* __QCOM_DEV_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/qcom/qcom_if.c

@@ -0,0 +1,479 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_hal_if.h>
+#include <nss_dp_dev.h>
+#include "qcom_dev.h"
+
+#define QCOM_STAT(m) offsetof(fal_mib_counter_t, m)
+
+/*
+ * Ethtool stats pointer structure
+ */
+struct qcom_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint32_t stat_offset;
+};
+
+/*
+ * Array of strings describing statistics
+ */
+static const struct qcom_ethtool_stats qcom_gstrings_stats[] = {
+	{"rx_broadcast", QCOM_STAT(RxBroad)},
+	{"rx_pause", QCOM_STAT(RxPause)},
+	{"rx_unicast", QCOM_STAT(RxUniCast)},
+	{"rx_multicast", QCOM_STAT(RxMulti)},
+	{"rx_fcserr", QCOM_STAT(RxFcsErr)},
+	{"rx_alignerr", QCOM_STAT(RxAllignErr)},
+	{"rx_runt", QCOM_STAT(RxRunt)},
+	{"rx_frag", QCOM_STAT(RxFragment)},
+	{"rx_jmbfcserr", QCOM_STAT(RxJumboFcsErr)},
+	{"rx_jmbalignerr", QCOM_STAT(RxJumboAligenErr)},
+	{"rx_pkt64", QCOM_STAT(Rx64Byte)},
+	{"rx_pkt65to127", QCOM_STAT(Rx128Byte)},
+	{"rx_pkt128to255", QCOM_STAT(Rx256Byte)},
+	{"rx_pkt256to511", QCOM_STAT(Rx512Byte)},
+	{"rx_pkt512to1023", QCOM_STAT(Rx1024Byte)},
+	{"rx_pkt1024to1518", QCOM_STAT(Rx1518Byte)},
+	{"rx_pkt1519tox", QCOM_STAT(RxMaxByte)},
+	{"rx_toolong", QCOM_STAT(RxTooLong)},
+	{"rx_pktgoodbyte", QCOM_STAT(RxGoodByte)},
+	{"rx_pktbadbyte", QCOM_STAT(RxBadByte)},
+	{"rx_overflow", QCOM_STAT(RxOverFlow)},
+	{"tx_broadcast", QCOM_STAT(TxBroad)},
+	{"tx_pause", QCOM_STAT(TxPause)},
+	{"tx_multicast", QCOM_STAT(TxMulti)},
+	{"tx_underrun", QCOM_STAT(TxUnderRun)},
+	{"tx_pkt64", QCOM_STAT(Tx64Byte)},
+	{"tx_pkt65to127", QCOM_STAT(Tx128Byte)},
+	{"tx_pkt128to255", QCOM_STAT(Tx256Byte)},
+	{"tx_pkt256to511", QCOM_STAT(Tx512Byte)},
+	{"tx_pkt512to1023", QCOM_STAT(Tx1024Byte)},
+	{"tx_pkt1024to1518", QCOM_STAT(Tx1518Byte)},
+	{"tx_pkt1519tox", QCOM_STAT(TxMaxByte)},
+	{"tx_oversize", QCOM_STAT(TxOverSize)},
+	{"tx_pktbyte_h", QCOM_STAT(TxByte)},
+	{"tx_collisions", QCOM_STAT(TxCollision)},
+	{"tx_abortcol", QCOM_STAT(TxAbortCol)},
+	{"tx_multicol", QCOM_STAT(TxMultiCol)},
+	{"tx_singlecol", QCOM_STAT(TxSingalCol)},
+	{"tx_exesdeffer", QCOM_STAT(TxExcDefer)},
+	{"tx_deffer", QCOM_STAT(TxDefer)},
+	{"tx_latecol", QCOM_STAT(TxLateCol)},
+	{"tx_unicast", QCOM_STAT(TxUniCast)},
+};
+
+/*
+ * Array of strings describing private flag names
+ */
+static const char * const qcom_strings_priv_flags[] = {
+	"linkpoll",
+	"tstamp",
+	"tsmode",
+};
+
+#define QCOM_STATS_LEN ARRAY_SIZE(qcom_gstrings_stats)
+#define QCOM_PRIV_FLAGS_LEN ARRAY_SIZE(qcom_strings_priv_flags)
+
+/*
+ * qcom_set_mac_speed()
+ */
+static int32_t qcom_set_mac_speed(struct nss_gmac_hal_dev *nghd,
+				uint32_t mac_speed)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * qcom_get_mac_speed()
+ */
+static uint32_t qcom_get_mac_speed(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * qcom_set_duplex_mode()
+ */
+static void qcom_set_duplex_mode(struct nss_gmac_hal_dev *nghd,
+				uint8_t duplex_mode)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "This API deprecated\n");
+}
+
+/*
+ * qcom_get_duplex_mode()
+ */
+static uint8_t qcom_get_duplex_mode(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * qcom_rx_flow_control()
+ */
+static void qcom_rx_flow_control(struct nss_gmac_hal_dev *nghd, bool enabled)
+{
+	if (enabled)
+		qcom_set_rx_flow_ctrl(nghd);
+	else
+		qcom_clear_rx_flow_ctrl(nghd);
+}
+
+/*
+ * qcom_tx_flow_control()
+ */
+static void qcom_tx_flow_control(struct nss_gmac_hal_dev *nghd, bool enabled)
+{
+	if (enabled)
+		qcom_set_tx_flow_ctrl(nghd);
+	else
+		qcom_clear_tx_flow_ctrl(nghd);
+}
+
+/*
+ * qcom_get_mib_stats()
+ */
+static int32_t qcom_get_mib_stats(struct nss_gmac_hal_dev *nghd)
+{
+	if (qcom_get_stats(nghd))
+		return -1;
+
+	return 0;
+}
+
+/*
+ * qcom_set_maxframe()
+ */
+static int32_t qcom_set_maxframe(struct nss_gmac_hal_dev *nghd,
+				 uint32_t maxframe)
+{
+	return fal_port_max_frame_size_set(0, nghd->mac_id, maxframe);
+}
+
+/*
+ * qcom_get_maxframe()
+ */
+static int32_t qcom_get_maxframe(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret)
+		return mtu;
+
+	return ret;
+}
+
+/*
+ * qcom_get_netdev_stats()
+ */
+static int32_t qcom_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+		struct rtnl_link_stats64 *stats)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *hal_stats = &(qhd->stats);
+
+	if (qcom_get_mib_stats(nghd))
+		return -1;
+
+	stats->rx_packets = hal_stats->RxUniCast + hal_stats->RxBroad
+				+ hal_stats->RxMulti;
+	stats->tx_packets = hal_stats->TxUniCast + hal_stats->TxBroad
+				+ hal_stats->TxMulti;
+	stats->rx_bytes = hal_stats->RxGoodByte;
+	stats->tx_bytes = hal_stats->TxByte;
+
+	/* RX errors */
+	stats->rx_crc_errors = hal_stats->RxFcsErr + hal_stats->RxJumboFcsErr;
+	stats->rx_frame_errors = hal_stats->RxAllignErr +
+				 hal_stats->RxJumboAligenErr;
+	stats->rx_fifo_errors = hal_stats->RxRunt;
+	stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors +
+			   stats->rx_fifo_errors;
+
+	stats->rx_dropped = hal_stats->RxTooLong + stats->rx_errors;
+
+	/* TX errors */
+	stats->tx_fifo_errors = hal_stats->TxUnderRun;
+	stats->tx_aborted_errors = hal_stats->TxAbortCol;
+	stats->tx_errors = stats->tx_fifo_errors + stats->tx_aborted_errors;
+
+	stats->collisions = hal_stats->TxCollision;
+	stats->multicast = hal_stats->RxMulti;
+
+	return 0;
+}
+
+/*
+ * qcom_get_strset_count()
+ *	Get string set count for ethtool operations
+ */
+int32_t qcom_get_strset_count(struct nss_gmac_hal_dev *nghd, int32_t sset)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return QCOM_STATS_LEN;
+	case ETH_SS_PRIV_FLAGS:
+		return QCOM_PRIV_FLAGS_LEN;
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * qcom_get_strings()
+ *	Get strings
+ */
+int32_t qcom_get_strings(struct nss_gmac_hal_dev *nghd, int32_t sset,
+						uint8_t *data)
+{
+	struct net_device *netdev = nghd->netdev;
+	int i;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < QCOM_STATS_LEN; i++) {
+			memcpy(data, qcom_gstrings_stats[i].stat_string,
+				strlen(qcom_gstrings_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+	case ETH_SS_PRIV_FLAGS:
+		for (i = 0; i < QCOM_PRIV_FLAGS_LEN; i++) {
+			memcpy(data, qcom_strings_priv_flags[i],
+				strlen(qcom_strings_priv_flags[i]));
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * qcom_get_eth_stats()
+ */
+static int32_t qcom_get_eth_stats(struct nss_gmac_hal_dev *nghd, uint64_t *data)
+{
+	struct qcom_hal_dev *qhd = (struct qcom_hal_dev *)nghd;
+	fal_mib_counter_t *stats = &(qhd->stats);
+	uint8_t *p;
+	int i;
+
+	if (qcom_get_mib_stats(nghd))
+		return -1;
+
+	for (i = 0; i < QCOM_STATS_LEN; i++) {
+		p = (uint8_t *)stats + qcom_gstrings_stats[i].stat_offset;
+		data[i] = *(uint32_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * qcom_send_pause_frame()
+ */
+static void qcom_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_set_ctrl2_test_pause(nghd);
+}
+
+/*
+ * qcom_stop_pause_frame()
+ */
+static void qcom_stop_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_reset_ctrl2_test_pause(nghd);
+}
+
+/*
+ * qcom_start()
+ */
+static int32_t qcom_start(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_set_full_duplex(nghd);
+
+	/* TODO: Read speed from dts */
+
+	if (qcom_set_mac_speed(nghd, SPEED_1000))
+		return -1;
+
+	qcom_tx_enable(nghd);
+	qcom_rx_enable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px mac_enable:0x%x\n",
+			__func__, nghd->mac_base,
+			hal_read_reg(nghd->mac_base, QCOM_MAC_ENABLE));
+
+	return 0;
+}
+
+/*
+ * qcom_stop()
+ */
+static int32_t qcom_stop(struct nss_gmac_hal_dev *nghd)
+{
+	qcom_tx_disable(nghd);
+	qcom_rx_disable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: mac_base:0x%px mac_enable:0x%x\n",
+			__func__, nghd->mac_base,
+			hal_read_reg(nghd->mac_base, QCOM_MAC_ENABLE));
+	return 0;
+}
+
+/*
+ * qcom_init()
+ */
+static void *qcom_init(struct gmac_hal_platform_data *gmacpdata)
+{
+	struct qcom_hal_dev *qhd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	if (!devm_request_mem_region(&dp_priv->pdev->dev, res->start,
+				     resource_size(res), ndev->name)) {
+		netdev_dbg(ndev, "Request mem region failed. Returning...\n");
+		return NULL;
+	}
+
+	qhd = (struct qcom_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+				sizeof(struct qcom_hal_dev), GFP_KERNEL);
+	if (!qhd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	/* Save netdev context in QCOM HAL context */
+	qhd->nghd.netdev = gmacpdata->netdev;
+	qhd->nghd.mac_id = gmacpdata->macid;
+
+	/* Populate the mac base addresses */
+	qhd->nghd.mac_base = devm_ioremap_nocache(&dp_priv->pdev->dev,
+						res->start, resource_size(res));
+	if (!qhd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		return NULL;
+	}
+
+	spin_lock_init(&qhd->nghd.slock);
+
+	netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			qhd->nghd.mac_base);
+
+	/* Reset MIB Stats */
+	if (fal_mib_port_flush_counters(0, qhd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)qhd;
+}
+
+/*
+ * qcom_get_mac_address()
+ */
+static void qcom_get_mac_address(struct nss_gmac_hal_dev *nghd,
+				 uint8_t *macaddr)
+{
+	uint32_t data = hal_read_reg(nghd->mac_base, QCOM_MAC_ADDR0);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_reg(nghd->mac_base, QCOM_MAC_ADDR1);
+	macaddr[0] = (data >> 24) & 0xff;
+	macaddr[1] = (data >> 16) & 0xff;
+	macaddr[2] = (data >> 8) & 0xff;
+	macaddr[3] = (data) & 0xff;
+}
+
+/*
+ * qcom_set_mac_address()
+ */
+static void qcom_set_mac_address(struct nss_gmac_hal_dev *nghd,
+				uint8_t *macaddr)
+{
+	uint32_t data = (macaddr[5] << 8) | macaddr[4];
+	hal_write_reg(nghd->mac_base, QCOM_MAC_ADDR0, data);
+	data = (macaddr[0] << 24) | (macaddr[1] << 16)
+		| (macaddr[2] << 8) | macaddr[3];
+	hal_write_reg(nghd->mac_base, QCOM_MAC_ADDR1, data);
+}
+
+/*
+ * MAC hal_ops base structure
+ */
+struct nss_gmac_hal_ops qcom_hal_ops = {
+	.init = &qcom_init,
+	.start = &qcom_start,
+	.stop = &qcom_stop,
+	.setmacaddr = &qcom_set_mac_address,
+	.getmacaddr = &qcom_get_mac_address,
+	.rxflowcontrol = &qcom_rx_flow_control,
+	.txflowcontrol = &qcom_tx_flow_control,
+	.setspeed = &qcom_set_mac_speed,
+	.getspeed = &qcom_get_mac_speed,
+	.setduplex = &qcom_set_duplex_mode,
+	.getduplex = &qcom_get_duplex_mode,
+	.getstats = &qcom_get_mib_stats,
+	.setmaxframe = &qcom_set_maxframe,
+	.getmaxframe = &qcom_get_maxframe,
+	.getndostats = &qcom_get_netdev_stats,
+	.getssetcount = &qcom_get_strset_count,
+	.getstrings = &qcom_get_strings,
+	.getethtoolstats = &qcom_get_eth_stats,
+	.sendpause = &qcom_send_pause_frame,
+	.stoppause = &qcom_stop_pause_frame,
+};

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/qcom/qcom_reg.h

@@ -0,0 +1,156 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __QCOM_REG_H__
+#define __QCOM_REG_H__
+
+/* Register Offsets */
+/* Offsets of GMAC config and status registers within NSS_GMAC_QCOM_MAC_BASE */
+#define QCOM_MAC_ENABLE		0x0000
+#define QCOM_MAC_SPEED		0x0004
+#define QCOM_MAC_ADDR0		0x0008
+#define QCOM_MAC_ADDR1		0x000c
+#define QCOM_MAC_CTRL0		0x0010
+#define QCOM_MAC_CTRL1		0x0014
+#define QCOM_MAC_CTRL2		0x0018
+#define QCOM_MAC_DBG_CTRL	0x001c
+#define QCOM_MAC_DBG_ADDR	0x0020
+#define QCOM_MAC_DBG_DATA	0x0024
+#define QCOM_MAC_JMB_SIZE	0x0030
+#define QCOM_MAC_MIB_CTRL	0x0034
+
+/* RX stats */
+#define QCOM_RXBROAD		0x0040
+#define QCOM_RXPAUSE		0x0044
+#define QCOM_RXMULTI		0x0048
+#define QCOM_RXFCSERR		0x004c
+#define QCOM_RXALIGNERR		0x0050
+#define QCOM_RXRUNT		0x0054
+#define QCOM_RXFRAG		0x0058
+#define QCOM_RXJMBFCSERR	0x005c
+#define QCOM_RXJMBALIGNERR	0x0060
+#define QCOM_RXPKT64		0x0064
+#define QCOM_RXPKT65TO127	0x0068
+#define QCOM_RXPKT128TO255	0x006c
+#define QCOM_RXPKT256TO511	0x0070
+#define QCOM_RXPKT512TO1023	0x0074
+#define QCOM_RXPKT1024TO1518	0x0078
+#define QCOM_RXPKT1519TOX	0x007c
+#define QCOM_RXPKTTOOLONG	0x0080
+#define QCOM_RXPKTGOODBYTE_L	0x0084
+#define QCOM_RXPKTGOODBYTE_H	0x0088
+#define QCOM_RXPKTBADBYTE_L	0x008c
+#define QCOM_RXPKTBADBYTE_H	0x0090
+#define QCOM_RXUNI		0x0094
+
+/* TX stats */
+#define QCOM_TXBROAD		0x00a0
+#define QCOM_TXPAUSE		0x00a4
+#define QCOM_TXMULTI		0x00a8
+#define QCOM_TXUNDERUN		0x00aC
+#define QCOM_TXPKT64		0x00b0
+#define QCOM_TXPKT65TO127	0x00b4
+#define QCOM_TXPKT128TO255	0x00b8
+#define QCOM_TXPKT256TO511	0x00bc
+#define QCOM_TXPKT512TO1023	0x00c0
+#define QCOM_TXPKT1024TO1518	0x00c4
+#define QCOM_TXPKT1519TOX	0x00c8
+#define QCOM_TXPKTBYTE_L	0x00cc
+#define QCOM_TXPKTBYTE_H	0x00d0
+#define QCOM_TXCOLLISIONS	0x00d4
+#define QCOM_TXABORTCOL		0x00d8
+#define QCOM_TXMULTICOL		0x00dc
+#define QCOM_TXSINGLECOL	0x00e0
+#define QCOM_TXEXCESSIVEDEFER	0x00e4
+#define QCOM_TXDEFER		0x00e8
+#define QCOM_TXLATECOL		0x00ec
+#define QCOM_TXUNI		0x00f0
+
+/* Bit Masks */
+/* GMAC BITs */
+#define QCOM_RX_MAC_ENABLE	1
+#define QCOM_TX_MAC_ENABLE	0x2
+#define QCOM_DUPLEX		0x10
+#define QCOM_RX_FLOW_ENABLE	0x20
+#define QCOM_TX_FLOW_ENABLE	0x40
+
+#define QCOM_MAC_SPEED_10	0
+#define QCOM_MAC_SPEED_100	1
+#define QCOM_MAC_SPEED_1000	2
+
+/* MAC CTRL0 */
+#define QCOM_IPGT_POS		0x0000007f
+#define QCOM_IPGT_LSB		0
+#define QCOM_IPGR2_POS		0x00007f00
+#define QCOM_IPGR2_LSB		8
+#define QCOM_HALF_THDF_CTRL	0x8000
+#define QCOM_HUGE_RECV		0x10000
+#define QCOM_HUGE_TRANS		0x20000
+#define QCOM_FLCHK		0x40000
+#define QCOM_ABEBE		0x80000
+#define QCOM_AMAXE		0x10000000
+#define QCOM_BPNB		0x20000000
+#define QCOM_NOBO		0x40000000
+#define QCOM_DRBNIB_RXOK	0x80000000
+
+/* MAC CTRL1 */
+#define QCOM_JAM_IPG_POS	0x0000000f
+#define QCOM_JAM_IPG_LSB	0
+#define QCOM_TPAUSE		0x10
+#define QCOM_TCTL		0x20
+#define QCOM_SSTCT		0x40
+#define QCOM_SIMR		0x80
+#define QCOM_RETRY_POS		0x00000f00
+#define QCOM_RETRY_LSB		8
+#define QCOM_PRLEN_POS		0x0000f000
+#define QCOM_PRLEN_LSB		8
+#define QCOM_PPAD		0x10000
+#define QCOM_POVR		0x20000
+#define QCOM_PHUG		0x40000
+#define QCOM_MBOF		0x80000
+#define QCOM_LCOL_POS		0x0ff00000
+#define QCOM_LCOL_LSB		20
+#define QCOM_LONG_JAM		0x10000000
+
+/* MAC CTRL2 */
+#define QCOM_IPG_DEC_LEN	0x2
+#define QCOM_TEST_PAUSE		0x4
+#define QCOM_MAC_LPI_TX_IDLE	0x8
+#define QCOM_MAC_LOOPBACK	0x10
+#define QCOM_IPG_DEC		0x20
+#define QCOM_SRS_SEL		0x40
+#define QCOM_CRC_RSV		0x80
+#define QCOM_MAXFR_POS		0x003fff00
+#define QCOM_MAXFR_LSB		8
+
+/* MAC DEBUG_CTRL */
+#define QCOM_DBG_IPGR1_POS	0x0000007f
+#define QCOM_DBG_IPGR1_LSB	0
+#define QCOM_DBG_HIHG_IPG_POS	0x0000ff00
+#define QCOM_DBG_HIHG_IPG_LSB	8
+#define QCOM_DBG_MAC_IPG_CTRL_POS	0x0000ff00
+#define QCOM_DBG_MAC_IPG_CTRL_LSB	20
+#define QCOM_DBG_MAC_LEN_CTRL	0x40000000
+#define QCOM_DBG_EDxSDFR_TRANS	0x80000000
+
+/* MAC MIB-CTRL*/
+#define QCOM_MIB_ENABLE		1
+#define QCOM_MIB_RESET		0x2
+#define QCOM_MIB_RD_CLR		0x4
+
+#endif /*__QCOM_REG_H__*/

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/gmac/syn_dev.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_DEV_H__
+#define __SYN_DEV_H__
+
+#include <nss_dp_dev.h>
+
+/*
+ * Subclass for base nss_gmac_hal_dev
+ */
+struct syn_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+	struct nss_dp_gmac_stats stats;	/* Stats structure */
+};
+
+#endif /*__SYN_DEV_H__*/

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/gmac/syn_if.c

@@ -0,0 +1,959 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_hal.h>
+#include "syn_dev.h"
+#include "syn_reg.h"
+
+#define SYN_STAT(m)	offsetof(struct nss_dp_hal_gmac_stats, m)
+#define HW_ERR_SIZE	sizeof(uint64_t)
+
+/*
+ * Array to store ethtool statistics
+ */
+struct syn_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint64_t stat_offset;
+};
+
+/*
+ * Array of strings describing statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_stats[] = {
+	{"rx_bytes", SYN_STAT(rx_bytes)},
+	{"rx_packets", SYN_STAT(rx_packets)},
+	{"rx_errors", SYN_STAT(rx_errors)},
+	{"rx_receive_errors", SYN_STAT(rx_receive_errors)},
+	{"rx_descriptor_errors", SYN_STAT(rx_descriptor_errors)},
+	{"rx_late_collision_errors", SYN_STAT(rx_late_collision_errors)},
+	{"rx_dribble_bit_errors", SYN_STAT(rx_dribble_bit_errors)},
+	{"rx_length_errors", SYN_STAT(rx_length_errors)},
+	{"rx_ip_header_errors", SYN_STAT(rx_ip_header_errors)},
+	{"rx_ip_payload_errors", SYN_STAT(rx_ip_payload_errors)},
+	{"rx_no_buffer_errors", SYN_STAT(rx_no_buffer_errors)},
+	{"rx_transport_csum_bypassed", SYN_STAT(rx_transport_csum_bypassed)},
+	{"tx_bytes", SYN_STAT(tx_bytes)},
+	{"tx_packets", SYN_STAT(tx_packets)},
+	{"tx_collisions", SYN_STAT(tx_collisions)},
+	{"tx_errors", SYN_STAT(tx_errors)},
+	{"tx_jabber_timeout_errors", SYN_STAT(tx_jabber_timeout_errors)},
+	{"tx_frame_flushed_errors", SYN_STAT(tx_frame_flushed_errors)},
+	{"tx_loss_of_carrier_errors", SYN_STAT(tx_loss_of_carrier_errors)},
+	{"tx_no_carrier_errors", SYN_STAT(tx_no_carrier_errors)},
+	{"tx_late_collision_errors", SYN_STAT(tx_late_collision_errors)},
+	{"tx_excessive_collision_errors", SYN_STAT(tx_excessive_collision_errors)},
+	{"tx_excessive_deferral_errors", SYN_STAT(tx_excessive_deferral_errors)},
+	{"tx_underflow_errors", SYN_STAT(tx_underflow_errors)},
+	{"tx_ip_header_errors", SYN_STAT(tx_ip_header_errors)},
+	{"tx_ip_payload_errors", SYN_STAT(tx_ip_payload_errors)},
+	{"tx_dropped", SYN_STAT(tx_dropped)},
+	{"rx_missed", SYN_STAT(rx_missed)},
+	{"fifo_overflows", SYN_STAT(fifo_overflows)},
+	{"rx_scatter_errors", SYN_STAT(rx_scatter_errors)},
+	{"tx_ts_create_errors", SYN_STAT(tx_ts_create_errors)},
+	{"pmt_interrupts", SYN_STAT(hw_errs[0])},
+	{"mmc_interrupts", SYN_STAT(hw_errs[0]) + (1 * HW_ERR_SIZE)},
+	{"line_interface_interrupts", SYN_STAT(hw_errs[0]) + (2 * HW_ERR_SIZE)},
+	{"fatal_bus_error_interrupts", SYN_STAT(hw_errs[0]) + (3 * HW_ERR_SIZE)},
+	{"rx_buffer_unavailable_interrupts", SYN_STAT(hw_errs[0]) + (4 * HW_ERR_SIZE)},
+	{"rx_process_stopped_interrupts", SYN_STAT(hw_errs[0]) + (5 * HW_ERR_SIZE)},
+	{"tx_underflow_interrupts", SYN_STAT(hw_errs[0]) + (6 * HW_ERR_SIZE)},
+	{"rx_overflow_interrupts", SYN_STAT(hw_errs[0]) + (7 * HW_ERR_SIZE)},
+	{"tx_jabber_timeout_interrutps", SYN_STAT(hw_errs[0]) + (8 * HW_ERR_SIZE)},
+	{"tx_process_stopped_interrutps", SYN_STAT(hw_errs[0]) + (9 * HW_ERR_SIZE)},
+	{"gmac_total_ticks", SYN_STAT(gmac_total_ticks)},
+	{"gmac_worst_case_ticks", SYN_STAT(gmac_worst_case_ticks)},
+	{"gmac_iterations", SYN_STAT(gmac_iterations)},
+	{"tx_pause_frames", SYN_STAT(tx_pause_frames)},
+	{"mmc_rx_overflow_errors", SYN_STAT(mmc_rx_overflow_errors)},
+	{"mmc_rx_watchdog_timeout_errors", SYN_STAT(mmc_rx_watchdog_timeout_errors)},
+	{"mmc_rx_crc_errors", SYN_STAT(mmc_rx_crc_errors)},
+	{"mmc_rx_ip_header_errors", SYN_STAT(mmc_rx_ip_header_errors)},
+	{"mmc_rx_octets_g", SYN_STAT(mmc_rx_octets_g)},
+	{"mmc_rx_ucast_frames", SYN_STAT(mmc_rx_ucast_frames)},
+	{"mmc_rx_bcast_frames", SYN_STAT(mmc_rx_bcast_frames)},
+	{"mmc_rx_mcast_frames", SYN_STAT(mmc_rx_mcast_frames)},
+	{"mmc_rx_undersize", SYN_STAT(mmc_rx_undersize)},
+	{"mmc_rx_oversize", SYN_STAT(mmc_rx_oversize)},
+	{"mmc_rx_jabber", SYN_STAT(mmc_rx_jabber)},
+	{"mmc_rx_octets_gb", SYN_STAT(mmc_rx_octets_gb)},
+	{"mmc_rx_frag_frames_g", SYN_STAT(mmc_rx_frag_frames_g)},
+	{"mmc_tx_octets_g", SYN_STAT(mmc_tx_octets_g)},
+	{"mmc_tx_ucast_frames", SYN_STAT(mmc_tx_ucast_frames)},
+	{"mmc_tx_bcast_frames", SYN_STAT(mmc_tx_bcast_frames)},
+	{"mmc_tx_mcast_frames", SYN_STAT(mmc_tx_mcast_frames)},
+	{"mmc_tx_deferred", SYN_STAT(mmc_tx_deferred)},
+	{"mmc_tx_single_col", SYN_STAT(mmc_tx_single_col)},
+	{"mmc_tx_multiple_col", SYN_STAT(mmc_tx_multiple_col)},
+	{"mmc_tx_octets_gb", SYN_STAT(mmc_tx_octets_gb)},
+};
+
+#define SYN_STATS_LEN		ARRAY_SIZE(syn_gstrings_stats)
+
+/*
+ * syn_set_rx_flow_ctrl()
+ */
+static inline void syn_set_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_RX_FLOW_CONTROL);
+}
+
+/*
+ * syn_clear_rx_flow_ctrl()
+ */
+static inline void syn_clear_rx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_RX_FLOW_CONTROL);
+
+}
+
+/*
+ * syn_set_tx_flow_ctrl()
+ */
+static inline void syn_set_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_TX_FLOW_CONTROL);
+}
+
+/*
+ * syn_send_tx_pause_frame()
+ */
+static inline void syn_send_tx_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	syn_set_tx_flow_ctrl(nghd);
+	hal_set_reg_bits(nghd, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_SEND_PAUSE_FRAME);
+}
+
+/*
+ * syn_clear_tx_flow_ctrl()
+ */
+static inline void syn_clear_tx_flow_ctrl(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_FLOW_CONTROL,
+			SYN_MAC_FC_TX_FLOW_CONTROL);
+}
+
+/*
+ * syn_rx_enable()
+ */
+static inline void syn_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_CONFIGURATION, SYN_MAC_RX);
+	hal_set_reg_bits(nghd, SYN_MAC_FRAME_FILTER, SYN_MAC_FILTER_OFF);
+}
+
+/*
+ * syn_tx_enable()
+ */
+static inline void syn_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_CONFIGURATION, SYN_MAC_TX);
+}
+
+/************Ip checksum offloading APIs*************/
+
+/*
+ * syn_enable_rx_chksum_offload()
+ *	Enable IPv4 header and IPv4/IPv6 TCP/UDP checksum calculation by GMAC.
+ */
+static inline void syn_enable_rx_chksum_offload(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd,
+			      SYN_MAC_CONFIGURATION, SYN_MAC_RX_IPC_OFFLOAD);
+}
+
+/*
+ * syn_disable_rx_chksum_offload()
+ *	Disable the IP checksum offloading in receive path.
+ */
+static inline void syn_disable_rx_chksum_offload(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd,
+				SYN_MAC_CONFIGURATION, SYN_MAC_RX_IPC_OFFLOAD);
+}
+
+/*
+ * syn_rx_tcpip_chksum_drop_enable()
+ *	Instruct the DMA to drop the packets that fail TCP/IP checksum.
+ *
+ * This is to instruct the receive DMA engine to drop the recevied
+ * packet if they fails the tcp/ip checksum in hardware. Valid only when
+ * full checksum offloading is enabled(type-2).
+ */
+static inline void syn_rx_tcpip_chksum_drop_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd,
+				SYN_DMA_OPERATION_MODE, SYN_DMA_DISABLE_DROP_TCP_CS);
+}
+
+/*******************Ip checksum offloading APIs**********************/
+
+/*
+ * syn_ipc_offload_init()
+ *	Initialize IPC Checksum offloading.
+ */
+static inline void syn_ipc_offload_init(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv;
+	dp_priv = netdev_priv(nghd->netdev);
+
+	if (test_bit(__NSS_DP_RXCSUM, &dp_priv->flags)) {
+		/*
+		 * Enable the offload engine in the receive path
+		 */
+		syn_enable_rx_chksum_offload(nghd);
+
+		/*
+		 * DMA drops the packets if error in encapsulated ethernet
+		 * payload.
+		 */
+		syn_rx_tcpip_chksum_drop_enable(nghd);
+		netdev_dbg(nghd->netdev, "%s: enable Rx checksum\n", __func__);
+	} else {
+		syn_disable_rx_chksum_offload(nghd);
+		netdev_dbg(nghd->netdev, "%s: disable Rx checksum\n", __func__);
+	}
+}
+
+/*
+ * syn_disable_mac_interrupt()
+ *	Disable all the interrupts.
+ */
+static inline void syn_disable_mac_interrupt(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_INTERRUPT_MASK, 0xffffffff);
+}
+
+/*
+ * syn_disable_mmc_tx_interrupt()
+ *	Disable the MMC Tx interrupt.
+ *
+ * The MMC tx interrupts are masked out as per the mask specified.
+ */
+static inline void syn_disable_mmc_tx_interrupt(struct nss_gmac_hal_dev *nghd,
+						uint32_t mask)
+{
+	hal_set_reg_bits(nghd, SYN_MMC_TX_INTERRUPT_MASK, mask);
+}
+
+/*
+ * syn_disable_mmc_rx_interrupt()
+ *	Disable the MMC Rx interrupt.
+ *
+ * The MMC rx interrupts are masked out as per the mask specified.
+ */
+static inline void syn_disable_mmc_rx_interrupt(struct nss_gmac_hal_dev *nghd,
+						uint32_t mask)
+{
+	hal_set_reg_bits(nghd, SYN_MMC_RX_INTERRUPT_MASK, mask);
+}
+
+/*
+ * syn_disable_mmc_ipc_rx_interrupt()
+ *	Disable the MMC ipc rx checksum offload interrupt.
+ *
+ * The MMC ipc rx checksum offload interrupts are masked out as
+ * per the mask specified.
+ */
+static inline void syn_disable_mmc_ipc_rx_interrupt(struct nss_gmac_hal_dev *nghd,
+					   uint32_t mask)
+{
+	hal_set_reg_bits(nghd, SYN_MMC_IPC_RX_INTR_MASK, mask);
+}
+
+/*
+ * syn_disable_dma_interrupt()
+ *	Disables all DMA interrupts.
+ */
+void syn_disable_dma_interrupt(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_INT_ENABLE, SYN_DMA_INT_DISABLE);
+}
+
+/*
+ * syn_enable_dma_interrupt()
+ *	Enables all DMA interrupts.
+ */
+void syn_enable_dma_interrupt(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_INT_ENABLE, SYN_DMA_INT_EN);
+}
+
+/*
+ * syn_disable_interrupt_all()
+ *	Disable all the interrupts.
+ */
+static inline void syn_disable_interrupt_all(struct nss_gmac_hal_dev *nghd)
+{
+	syn_disable_mac_interrupt(nghd);
+	syn_disable_dma_interrupt(nghd);
+	syn_disable_mmc_tx_interrupt(nghd, 0xFFFFFFFF);
+	syn_disable_mmc_rx_interrupt(nghd, 0xFFFFFFFF);
+	syn_disable_mmc_ipc_rx_interrupt(nghd, 0xFFFFFFFF);
+}
+
+/*
+ * syn_dma_bus_mode_init()
+ *	Function to program DMA bus mode register.
+ */
+static inline void syn_dma_bus_mode_init(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_BUS_MODE, SYN_DMA_BUS_MODE_VAL);
+}
+
+/*
+ * syn_clear_dma_status()
+ *	Clear all the pending dma interrupts.
+ */
+void syn_clear_dma_status(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, SYN_DMA_STATUS);
+	hal_write_reg(nghd->mac_base, SYN_DMA_STATUS, data);
+}
+
+/*
+ * syn_enable_dma_rx()
+ *	Enable Rx GMAC operation
+ */
+void syn_enable_dma_rx(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE);
+	data |= SYN_DMA_RX_START;
+	hal_write_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_disable_dma_rx()
+ *	Disable Rx GMAC operation
+ */
+void syn_disable_dma_rx(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE);
+	data &= ~SYN_DMA_RX_START;
+	hal_write_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_enable_dma_tx()
+ *	Enable Rx GMAC operation
+ */
+void syn_enable_dma_tx(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE);
+	data |= SYN_DMA_TX_START;
+	hal_write_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_disable_dma_tx()
+ *	Disable Rx GMAC operation
+ */
+void syn_disable_dma_tx(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t data;
+
+	data = hal_read_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE);
+	data &= ~SYN_DMA_TX_START;
+	hal_write_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE, data);
+}
+
+/*
+ * syn_resume_dma_tx
+ *	Resumes the DMA Transmission.
+ */
+void syn_resume_dma_tx(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_TX_POLL_DEMAND, 0);
+}
+
+/*
+ * syn_get_rx_missed
+ *	Get Rx missed errors
+ */
+uint32_t syn_get_rx_missed(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t missed_frame_buff_overflow;
+	missed_frame_buff_overflow = hal_read_reg(nghd->mac_base, SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER);
+	return missed_frame_buff_overflow & 0xFFFF;
+}
+
+/*
+ * syn_get_fifo_overflows
+ *	Get FIFO overflows
+ */
+uint32_t syn_get_fifo_overflows(struct nss_gmac_hal_dev *nghd)
+{
+	uint32_t missed_frame_buff_overflow;
+	missed_frame_buff_overflow = hal_read_reg(nghd->mac_base, SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER);
+	return (missed_frame_buff_overflow >> 17) & 0x7ff;
+}
+
+/*
+ * syn_init_tx_desc_base()
+ *	Programs the Dma Tx Base address with the starting address of the descriptor ring or chain.
+ */
+void syn_init_tx_desc_base(struct nss_gmac_hal_dev *nghd, uint32_t tx_desc_dma)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_TX_DESCRIPTOR_LIST_ADDRESS, tx_desc_dma);
+}
+
+/*
+ * syn_init_rx_desc_base()
+ *	Programs the Dma Rx Base address with the starting address of the descriptor ring or chain.
+ */
+void syn_init_rx_desc_base(struct nss_gmac_hal_dev *nghd, uint32_t rx_desc_dma)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_RX_DESCRIPTOR_LIST_ADDRESS, rx_desc_dma);
+}
+
+/*
+ * syn_dma_axi_bus_mode_init()
+ *	Function to program DMA AXI bus mode register.
+ */
+static inline void syn_dma_axi_bus_mode_init(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_AXI_BUS_MODE,
+					SYN_DMA_AXI_BUS_MODE_VAL);
+}
+
+/*
+ * syn_dma_operation_mode_init()
+ *	Function to program DMA Operation Mode register.
+ */
+static inline void syn_dma_operation_mode_init(struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_DMA_OPERATION_MODE, SYN_DMA_OMR);
+}
+
+/*
+ * syn_broadcast_enable()
+ *	Enables Broadcast frames.
+ *
+ * When enabled Address filtering module passes all incoming broadcast frames.
+ */
+static inline void syn_broadcast_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_FRAME_FILTER, SYN_MAC_BROADCAST);
+}
+
+/*
+ * syn_multicast_enable()
+ *	Enables Multicast frames.
+ *
+ * When enabled all multicast frames are passed.
+ */
+static inline void syn_multicast_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_FRAME_FILTER, SYN_MAC_MULTICAST_FILTER);
+}
+
+/*
+ * syn_promisc_enable()
+ *	Enables promiscous mode.
+ *
+ * When enabled Address filter modules pass all incoming frames
+ * regardless of their Destination and source addresses.
+ */
+static inline void syn_promisc_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_FRAME_FILTER, SYN_MAC_FILTER_OFF);
+	hal_set_reg_bits(nghd, SYN_MAC_FRAME_FILTER,
+				SYN_MAC_PROMISCUOUS_MODE_ON);
+}
+
+/*
+ * syn_get_stats()
+ */
+static int syn_get_stats(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv;
+	struct syn_hal_dev *shd;
+	struct nss_dp_gmac_stats *stats;
+
+	BUG_ON(nghd == NULL);
+
+	shd = (struct syn_hal_dev *)nghd;
+	stats = &(shd->stats);
+
+	dp_priv = netdev_priv(nghd->netdev);
+	if (!dp_priv->data_plane_ops)
+		return -1;
+
+	dp_priv->data_plane_ops->get_stats(dp_priv->dpc, stats);
+
+	return 0;
+}
+
+/*
+ * syn_rx_flow_control()
+ */
+static void syn_rx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_rx_flow_ctrl(nghd);
+	else
+		syn_clear_rx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_tx_flow_control()
+ */
+static void syn_tx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_tx_flow_ctrl(nghd);
+	else
+		syn_clear_tx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_get_max_frame_size()
+ */
+static int32_t syn_get_max_frame_size(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	BUG_ON(nghd == NULL);
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret)
+		return mtu;
+
+	return ret;
+}
+
+/*
+ * syn_set_max_frame_size()
+ */
+static int32_t syn_set_max_frame_size(struct nss_gmac_hal_dev *nghd,
+					uint32_t val)
+{
+	BUG_ON(nghd == NULL);
+
+	return fal_port_max_frame_size_set(0, nghd->mac_id, val);
+}
+
+/*
+ * syn_set_mac_speed()
+ */
+static int32_t syn_set_mac_speed(struct nss_gmac_hal_dev *nghd,
+				   uint32_t mac_speed)
+{
+	struct net_device *netdev;
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_get_mac_speed()
+ */
+static uint32_t syn_get_mac_speed(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev;
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_set_duplex_mode()
+ */
+static void syn_set_duplex_mode(struct nss_gmac_hal_dev *nghd,
+				uint8_t duplex_mode)
+{
+	struct net_device *netdev;
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+}
+
+/*
+ * syn_get_duplex_mode()
+ */
+static uint8_t syn_get_duplex_mode(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev;
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_get_netdev_stats()
+ */
+static int syn_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+				struct rtnl_link_stats64 *stats)
+{
+	struct syn_hal_dev *shd;
+	struct nss_dp_hal_gmac_stats *ndo_stats;
+
+	BUG_ON(nghd == NULL);
+
+	shd = (struct syn_hal_dev *)nghd;
+	ndo_stats = &(shd->stats.stats);
+
+	/*
+	 * Read stats from the registered dataplane.
+	 */
+	if (syn_get_stats(nghd))
+		return -1;
+
+	stats->rx_packets = ndo_stats->rx_packets;
+	stats->rx_bytes = ndo_stats->rx_bytes;
+	stats->rx_errors = ndo_stats->rx_errors;
+	stats->rx_dropped = ndo_stats->rx_errors;
+	stats->rx_length_errors = ndo_stats->rx_length_errors;
+	stats->rx_over_errors = ndo_stats->mmc_rx_overflow_errors;
+	stats->rx_crc_errors = ndo_stats->mmc_rx_crc_errors;
+	stats->rx_frame_errors = ndo_stats->rx_dribble_bit_errors;
+	stats->rx_fifo_errors = ndo_stats->fifo_overflows;
+	stats->rx_missed_errors = ndo_stats->rx_missed;
+	stats->collisions = ndo_stats->tx_collisions + ndo_stats->rx_late_collision_errors;
+	stats->tx_packets = ndo_stats->tx_packets;
+	stats->tx_bytes = ndo_stats->tx_bytes;
+	stats->tx_errors = ndo_stats->tx_errors;
+	stats->tx_dropped = ndo_stats->tx_dropped;
+	stats->tx_carrier_errors = ndo_stats->tx_loss_of_carrier_errors + ndo_stats->tx_no_carrier_errors;
+	stats->tx_fifo_errors = ndo_stats->tx_underflow_errors;
+	stats->tx_window_errors = ndo_stats->tx_late_collision_errors;
+
+	return 0;
+}
+
+/*
+ * syn_get_eth_stats()
+ */
+static int32_t syn_get_eth_stats(struct nss_gmac_hal_dev *nghd,
+						uint64_t *data)
+{
+	struct syn_hal_dev *shd;
+	struct nss_dp_gmac_stats *stats;
+	uint8_t *p = NULL;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	shd = (struct syn_hal_dev *)nghd;
+	stats = &(shd->stats);
+
+	/*
+	 * Read stats from the registered dataplane.
+	 */
+	if (syn_get_stats(nghd))
+		return -1;
+
+	for (i = 0; i < SYN_STATS_LEN; i++) {
+		p = ((uint8_t *)(stats) +
+				syn_gstrings_stats[i].stat_offset);
+		data[i] = *(uint32_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_get_strset_count()
+ */
+static int32_t syn_get_strset_count(struct nss_gmac_hal_dev *nghd,
+							int32_t sset)
+{
+	struct net_device *netdev;
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return SYN_STATS_LEN;
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * syn_get_strings()
+ */
+static int32_t syn_get_strings(struct nss_gmac_hal_dev *nghd,
+					int32_t stringset, uint8_t *data)
+{
+	struct net_device *netdev;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < SYN_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_stats[i].stat_string,
+				ETH_GSTRING_LEN);
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_send_pause_frame()
+ */
+static void syn_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_send_tx_pause_frame(nghd);
+}
+
+/*
+ * syn_set_mac_address()
+ */
+static void syn_set_mac_address(struct nss_gmac_hal_dev *nghd,
+							uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	if (!macaddr) {
+		netdev_warn(nghd->netdev, "macaddr is not valid.\n");
+		return;
+	}
+
+	data = (macaddr[5] << 8) | macaddr[4] | SYN_MAC_ADDR_HIGH_AE;
+	hal_write_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH, data);
+	data = (macaddr[3] << 24) | (macaddr[2] << 16) | (macaddr[1] << 8)
+		| macaddr[0];
+	hal_write_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW, data);
+}
+
+/*
+ * syn_get_mac_address()
+ */
+static void syn_get_mac_address(struct nss_gmac_hal_dev *nghd,
+							uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	if (!macaddr) {
+		netdev_warn(nghd->netdev, "macaddr is not valid.\n");
+		return;
+	}
+
+	data = hal_read_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW);
+	macaddr[3] = (data >> 24) & 0xff;
+	macaddr[2] = (data >> 16) & 0xff;
+	macaddr[1] = (data >> 8) & 0xff;
+	macaddr[0] = (data) & 0xff;
+}
+
+/*
+ * syn_dma_init()
+ *	Initialize settings for GMAC DMA and AXI bus.
+ */
+static void syn_dma_init(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *ndev = nghd->netdev;
+	struct nss_dp_dev *dp_priv = netdev_priv(ndev);
+
+	/*
+	 * Enable SoC specific GMAC clocks.
+	 */
+	nss_dp_hal_clk_enable(dp_priv);
+
+	/*
+	 * Configure DMA registers.
+	 */
+	syn_dma_bus_mode_init(nghd);
+	syn_dma_axi_bus_mode_init(nghd);
+	syn_dma_operation_mode_init(nghd);
+}
+
+/*
+ * syn_init()
+ */
+static void *syn_init(struct gmac_hal_platform_data *gmacpdata)
+{
+	struct syn_hal_dev *shd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	shd = (struct syn_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+					sizeof(struct syn_hal_dev),
+					GFP_KERNEL);
+	if (!shd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	shd->nghd.mac_reg_len = resource_size(res);
+	shd->nghd.memres = devm_request_mem_region(&dp_priv->pdev->dev,
+								res->start,
+								resource_size(res),
+								ndev->name);
+	if (!shd->nghd.memres) {
+		netdev_dbg(ndev, "Request mem region failed. Returning...\n");
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	/*
+	 * Save netdev context in syn HAL context
+	 */
+	shd->nghd.netdev = gmacpdata->netdev;
+	shd->nghd.mac_id = gmacpdata->macid;
+	shd->nghd.duplex_mode = DUPLEX_FULL;
+
+	set_bit(__NSS_DP_RXCSUM, &dp_priv->flags);
+
+	/*
+	 * Populate the mac base addresses
+	 */
+	shd->nghd.mac_base =
+		devm_ioremap_nocache(&dp_priv->pdev->dev, res->start,
+				     resource_size(res));
+	if (!shd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		devm_kfree(&dp_priv->pdev->dev, shd);
+		return NULL;
+	}
+
+	spin_lock_init(&shd->nghd.slock);
+
+	netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			shd->nghd.mac_base);
+
+	syn_disable_interrupt_all(&shd->nghd);
+	syn_dma_init(&shd->nghd);
+	syn_ipc_offload_init(&shd->nghd);
+	syn_promisc_enable(&shd->nghd);
+	syn_broadcast_enable(&shd->nghd);
+	syn_multicast_enable(&shd->nghd);
+	syn_rx_enable(&shd->nghd);
+	syn_tx_enable(&shd->nghd);
+
+	/*
+	 * Reset MIB Stats
+	 */
+	if (fal_mib_port_flush_counters(0, shd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)shd;
+}
+
+/*
+ * syn_exit()
+ */
+static void syn_exit(struct nss_gmac_hal_dev *nghd)
+{
+	struct nss_dp_dev *dp_priv = NULL;
+
+	dp_priv = netdev_priv(nghd->netdev);
+	devm_iounmap(&dp_priv->pdev->dev,
+			(void *)nghd->mac_base);
+	devm_release_mem_region(&dp_priv->pdev->dev,
+			(nghd->memres)->start,
+			nghd->mac_reg_len);
+
+	nghd->memres = NULL;
+	nghd->mac_base = NULL;
+}
+
+struct nss_gmac_hal_ops syn_hal_ops = {
+	.init = &syn_init,
+	.start =  NULL,
+	.stop = NULL,
+	.exit = &syn_exit,
+	.setmacaddr = &syn_set_mac_address,
+	.getmacaddr = &syn_get_mac_address,
+	.rxflowcontrol = &syn_rx_flow_control,
+	.txflowcontrol = &syn_tx_flow_control,
+	.setspeed = &syn_set_mac_speed,
+	.getspeed = &syn_get_mac_speed,
+	.setduplex = &syn_set_duplex_mode,
+	.getduplex = &syn_get_duplex_mode,
+	.setmaxframe = &syn_set_max_frame_size,
+	.getmaxframe = &syn_get_max_frame_size,
+	.getndostats = &syn_get_netdev_stats,
+	.getssetcount = &syn_get_strset_count,
+	.getstrings = &syn_get_strings,
+	.getethtoolstats = &syn_get_eth_stats,
+	.sendpause = &syn_send_pause_frame,
+};

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/gmac/syn_reg.h

@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __SYN_REG_H__
+#define __SYN_REG_H__
+
+/*
+ * MAC register offset
+ */
+#define SYN_MAC_CONFIGURATION				0x0000
+#define SYN_MAC_FRAME_FILTER				0x0004
+#define SYN_MAC_FLOW_CONTROL				0x0018
+#define SYN_VLAN_TAG					0x001C
+#define SYN_VERSION					0x0020
+#define SYN_DEBUG					0x0024
+#define SYN_REMOTE_WAKE_UP_FRAME_FILTER			0x0028
+#define SYN_PMT_CONTROL_STATUS				0x002C
+#define SYN_LPI_CONTROL_STATUS				0x0030
+#define SYN_LPI_TIMERS_CONTROL				0x0034
+#define SYN_INTERRUPT_STATUS				0x0038
+#define SYN_INTERRUPT_MASK				0x003C
+
+/*
+ * MAC address register offset
+ */
+#define SYN_MAC_ADDR0_HIGH				0x0040
+#define SYN_MAC_ADDR0_LOW				0x0044
+#define SYN_MAC_ADDR1_HIGH				0x0048
+#define SYN_MAC_ADDR1_LOW				0x004C
+#define SYN_MAC_ADDR2_HIGH				0x0050
+#define SYN_MAC_ADDR2_LOW				0x0054
+#define SYN_MAC_ADDR3_HIGH				0x0058
+#define SYN_MAC_ADDR3_LOW				0x005C
+#define SYN_MAC_ADDR4_HIGH				0x0060
+#define SYN_MAC_ADDR4_LOW				0x0064
+
+/*
+ * Watchdog timeout register
+ */
+#define SYN_WDOG_TIMEOUT				0x00DC
+
+/*
+ * Mac Management Counters (MMC) register offset
+ */
+#define SYN_MMC_CONTROL					0x0100
+#define SYN_MMC_RX_INTERRUPT				0x0104
+#define SYN_MMC_TX_INTERRUPT				0x0108
+#define SYN_MMC_RX_INTERRUPT_MASK			0x010C
+#define SYN_MMC_TX_INTERRUPT_MASK			0x0110
+#define SYN_MMC_IPC_RX_INTR_MASK			0x0200
+
+/*
+ * DMA Register offset
+ */
+#define SYN_DMA_BUS_MODE				0x1000
+#define SYN_DMA_TX_POLL_DEMAND				0x1004
+#define SYN_DMA_RX_POLL_DEMAND				0x1008
+#define SYN_DMA_RX_DESCRIPTOR_LIST_ADDRESS		0x100C
+#define SYN_DMA_TX_DESCRIPTOR_LIST_ADDRESS		0x1010
+#define SYN_DMA_STATUS					0x1014
+#define SYN_DMA_OPERATION_MODE				0x1018
+#define SYN_DMA_INT_ENABLE				0x101C
+#define SYN_DMA_MISSED_FRAME_AND_BUFF_OVERFLOW_COUNTER	0x1020
+#define SYN_DMA_RX_INTERRUPT_WATCHDOG_TIMER		0x1024
+#define SYN_DMA_AXI_BUS_MODE				0x1028
+#define SYN_DMA_AHB_OR_AXI_STATUS			0x102C
+#define SYN_DMA_CURRENT_HOST_TX_DESCRIPTOR		0x1048
+#define SYN_DMA_CURRENT_HOST_RX_DESCRIPTOR		0x104C
+#define SYN_DMA_CURRENT_HOST_TX_BUFFER_ADDRESS		0x1050
+#define SYN_DMA_CURRENT_HOST_RX_BUFFER_ADDRESS		0x1054
+
+/*
+ * Optional HW feature register
+ */
+#define SYN_HW_FEATURE					0x1058
+
+/*
+ * Register Bit Definitions
+ */
+
+/*
+ * SYN_MAC_CONFIGURATION = 0x0000,	MAC config Register Layout
+ */
+enum syn_mac_config_reg {
+	SYN_MAC_TWOKPE = 0x08000000,			/* Support for 2K packets */
+	SYN_MAC_TWOKPE_ENABLE = 0x08000000,
+	SYN_MAC_TWOKPE_DISABLE = 0x00000000,
+	SYN_MAC_CST = 0x02000000,			/* (CST) CRC Stripping for Type Frames */
+	SYN_MAC_CST_ENABLE = 0x02000000,
+	SYN_MAC_CST_DISABLE = 0x02000000,
+	SYN_MAC_TC = 0x01000000,			/* (TC) Transmit configuration */
+	SYN_MAC_WATCHDOG = 0x00800000,
+	SYN_MAC_WATCHDOG_ENABLE = 0x00000000,		/* Enable watchdog timer */
+	SYN_MAC_WATCHDOG_DISABLE = 0x00800000,		/* (WD)Disable watchdog timer on Rx */
+	SYN_MAC_JABBER = 0x00400000,
+	SYN_MAC_JABBER_ENABLE = 0x00000000,		/* Enable jabber timer */
+	SYN_MAC_JABBER_DISABLE = 0x00400000,		/* (JD)Disable jabber timer on Tx */
+	SYN_MAC_FRAME_BURST = 0x00200000,
+	SYN_MAC_FRAME_BURST_ENABLE = 0x00200000,	/* (BE)Enable frame bursting
+							   during Tx */
+	SYN_MAC_FRAME_BURST_DISABLE = 0x00000000,	/* Disable frame bursting */
+	SYN_MAC_JUMBO_FRAME = 0x00100000,
+	SYN_MAC_JUMBO_FRAME_ENABLE = 0x00100000,	/* (JE)Enable jumbo frame for Rx */
+	SYN_MAC_JUMBO_FRAME_DISABLE = 0x00000000,	/* Disable jumbo frame */
+	SYN_MAC_INTER_FRAME_GAP7 = 0x000E0000,		/* (IFG) Config7 - 40bit times */
+	SYN_MAC_INTER_FRAME_GAP6 = 0x000C0000,		/* (IFG) Config6 - 48bit times */
+	SYN_MAC_INTER_FRAME_GAP5 = 0x000A0000,		/* (IFG) Config5 - 56bit times */
+	SYN_MAC_INTER_FRAME_GAP4 = 0x00080000,		/* (IFG) Config4 - 64bit times */
+	SYN_MAC_INTER_FRAME_GAP3 = 0x00060000,		/* (IFG) Config3 - 72bit times */
+	SYN_MAC_INTER_FRAME_GAP2 = 0x00040000,		/* (IFG) Config2 - 80bit times */
+	SYN_MAC_INTER_FRAME_GAP1 = 0x00020000,		/* (IFG) Config1 - 88bit times */
+	SYN_MAC_INTER_FRAME_GAP0 = 0x00000000,		/* (IFG) Config0 - 96bit times */
+	SYN_MAC_DISABLE_CRS = 0x00010000,		/* (DCRS) Disable Carrier Sense During Transmission */
+	SYN_MAC_MII_GMII = 0x00008000,
+	SYN_MAC_SELECT_MII = 0x00008000,		/* (PS)Port Select-MII mode   */
+	SYN_MAC_SELECT_GMII = 0x00000000,		/* GMII mode                  */
+	SYN_MAC_FE_SPEED100 = 0x00004000,		/* (FES)Fast Ethernet speed 100Mbps */
+	SYN_MAC_FE_SPEED = 0x00004000,			/* (FES)Fast Ethernet speed 100Mbps */
+	SYN_MAC_FE_SPEED10 = 0x00000000,		/* (FES)Fast Ethernet speed 10Mbps */
+	SYN_MAC_RX_OWN = 0x00002000,
+	SYN_MAC_DISABLE_RX_OWN = 0x00002000,		/* (DO)Disable receive own packets */
+	SYN_MAC_ENABLE_RX_OWN = 0x00000000,		/* Enable receive own packets */
+	SYN_MAC_LOOPBACK = 0x00001000,
+	SYN_MAC_LOOPBACK_ON = 0x00001000,		/* (LM)Loopback mode for GMII/MII */
+	SYN_MAC_LOOPBACK_OFF = 0x00000000,		/* Normal mode                */
+	SYN_MAC_DUPLEX = 0x00000800,
+	SYN_MAC_FULL_DUPLEX = 0x00000800,		/* (DM)Full duplex mode       */
+	SYN_MAC_HALF_DUPLEX = 0x00000000,		/* Half duplex mode           */
+	SYN_MAC_RX_IPC_OFFLOAD = 0x00000400,		/* IPC checksum offload       */
+	SYN_MAC_RX_IPC_OFFLOAD_ENABLE = 0x00000400,
+	SYN_MAC_RX_IPC_OFFLOAD_DISABLE = 0x00000000,
+	SYN_MAC_RETRY = 0x00000200,
+	SYN_MAC_RETRY_DISABLE = 0x00000200,		/* (DR)Disable Retry          */
+	SYN_MAC_RETRY_ENABLE = 0x00000000,		/* Enable retransmission as per BL */
+	SYN_MAC_LINK_UP = 0x00000100,			/* (LUD)Link UP               */
+	SYN_MAC_LINK_DOWN = 0x00000100,			/* Link Down                  */
+	SYN_MAC_PAD_CRC_STRIP = 0x00000080,
+	SYN_MAC_PAD_CRC_STRIP_ENABLE = 0x00000080,	/* (ACS) Automatic Pad/Crc strip enable */
+	SYN_MAC_PAD_CRC_STRIP_DISABLE = 0x00000000,	/* Automatic Pad/Crc stripping disable */
+	SYN_MAC_BACKOFF_LIMIT = 0x00000060,
+	SYN_MAC_BACKOFF_LIMIT3 = 0x00000060,		/* (BL)Back-off limit in HD mode */
+	SYN_MAC_BACKOFF_LIMIT2 = 0x00000040,
+	SYN_MAC_BACKOFF_LIMIT1 = 0x00000020,
+	SYN_MAC_BACKOFF_LIMIT0 = 0x00000000,
+	SYN_MAC_DEFERRAL_CHECK = 0x00000010,
+	SYN_MAC_DEFERRAL_CHECK_ENABLE = 0x00000010,	/* (DC)Deferral check enable in HD mode */
+	SYN_MAC_DEFERRAL_CHECK_DISABLE = 0x00000000,	/* Deferral check disable    */
+	SYN_MAC_TX = 0x00000008,
+	SYN_MAC_TX_ENABLE = 0x00000008,			/* (TE)Transmitter enable */
+	SYN_MAC_TX_DISABLE = 0x00000000,		/* Transmitter disable */
+	SYN_MAC_RX = 0x00000004,
+	SYN_MAC_RX_ENABLE = 0x00000004,			/* (RE)Receiver enable */
+	SYN_MAC_RX_DISABLE = 0x00000000,		/* Receiver disable */
+	SYN_MAC_PRELEN_RESERVED = 0x00000003,		/* Preamble Length for Transmit Frames */
+	SYN_MAC_PRELEN_3B = 0x00000002,
+	SYN_MAC_PRELEN_5B = 0x00000001,
+	SYN_MAC_PRELEN_7B = 0x00000000,
+};
+
+/*
+ * SYN_MAC_FRAME_FILTER = 0x0004,	Mac frame filtering controls Register
+ */
+enum syn_mac_frame_filter_reg {
+	SYN_MAC_FILTER = 0x80000000,
+	SYN_MAC_FILTER_OFF = 0x80000000,		/* (RA)Receive all incoming packets */
+	SYN_MAC_FILTER_ON = 0x00000000,			/* Receive filtered pkts only */
+	SYN_MAC_HASH_PERFECT_FILTER = 0x00000400,	/* Hash or Perfect Filter enable */
+	SYN_MAC_SRC_ADDR_FILTER = 0x00000200,
+	SYN_MAC_SRC_ADDR_FILTER_ENABLE = 0x00000200,	/* (SAF)Source Address Filter enable */
+	SYN_MAC_SRC_ADDR_FILTER_DISABLE = 0x00000000,
+	SYN_MAC_SRC_INVA_ADDR_FILTER = 0x00000100,
+	SYN_MAC_SRC_INV_ADDR_FILTER_EN = 0x00000100,	/* (SAIF)Inv Src Addr Filter enable */
+	SYN_MAC_SRC_INV_ADDR_FILTER_DIS = 0x00000000,
+	SYN_MAC_PASS_CONTROL = 0x000000C0,
+	SYN_MAC_PASS_CONTROL3 = 0x000000C0,		/* (PCF)Forwards ctrl frames that pass AF */
+	SYN_MAC_PASS_CONTROL2 = 0x00000080,		/* Forwards all control frames
+							   even if they fail the AF */
+	SYN_MAC_PASS_CONTROL1 = 0x00000040,		/* Forwards all control frames except
+							   PAUSE control frames to application
+							   even if they fail the AF */
+	SYN_MAC_PASS_CONTROL0 = 0x00000000,		/* Don't pass control frames */
+	SYN_MAC_BROADCAST = 0x00000020,
+	SYN_MAC_BROADCAST_DISABLE = 0x00000020,		/* (DBF)Disable Rx of broadcast frames */
+	SYN_MAC_BROADCAST_ENABLE = 0x00000000,		/* Enable broadcast frames    */
+	SYN_MAC_MULTICAST_FILTER = 0x00000010,
+	SYN_MAC_MULTICAST_FILTER_OFF = 0x00000010,	/* (PM) Pass all multicast packets */
+	SYN_MAC_MULTICAST_FILTER_ON = 0x00000000,	/* Pass filtered multicast packets */
+	SYN_MAC_DEST_ADDR_FILTER = 0x00000008,
+	SYN_MAC_DEST_ADDR_FILTER_INV = 0x00000008,	/* (DAIF)Inverse filtering for DA */
+	SYN_MAC_DEST_ADDR_FILTER_NOR = 0x00000000,	/* Normal filtering for DA */
+	SYN_MAC_MCAST_HASH_FILTER = 0x00000004,
+	SYN_MAC_MCAST_HASH_FILTER_ON = 0x00000004,	/* (HMC)perfom multicast hash filtering */
+	SYN_MAC_MCAST_HASH_FILTER_OFF = 0x00000000,	/* perfect filtering only     */
+	SYN_MAC_UCAST_HASH_FILTER = 0x00000002,
+	SYN_MAC_UCAST_HASH_FILTER_ON = 0x00000002,	/* (HUC)Unicast Hash filtering only */
+	SYN_MAC_UCAST_HASH_FILTER_OFF = 0x00000000,	/* perfect filtering only     */
+	SYN_MAC_PROMISCUOUS_MODE = 0x00000001,
+	SYN_MAC_PROMISCUOUS_MODE_ON = 0x00000001,	/* Receive all frames         */
+	SYN_MAC_PROMISCUOUS_MODE_OFF = 0x00000000,	/* Receive filtered packets only */
+};
+
+/*
+ * SYN_MAC_FLOW_CONTROL = 0x0018,	Flow control Register Layout
+ */
+enum syn_mac_flow_control_reg {
+	SYN_MAC_FC_PAUSE_TIME_MASK = 0xFFFF0000,	/* (PT) PAUSE TIME field
+							   in the control frame */
+	SYN_MAC_FC_PAUSE_TIME_SHIFT = 16,
+	SYN_MAC_FC_PAUSE_LOW_THRESH = 0x00000030,
+	SYN_MAC_FC_PAUSE_LOW_THRESH3 = 0x00000030,	/* (PLT)thresh for pause
+							   tmr 256 slot time */
+	SYN_MAC_FC_PAUSE_LOW_THRESH2 = 0x00000020,	/* 144 slot time         */
+	SYN_MAC_FC_PAUSE_LOW_THRESH1 = 0x00000010,	/* 28 slot time          */
+	SYN_MAC_FC_PAUSE_LOW_THRESH0 = 0x00000000,	/* 4 slot time           */
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME = 0x00000008,
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME_ON = 0x00000008,	/* (UP)Detect pause frame
+							   with unicast addr. */
+	SYN_MAC_FC_UNICAST_PAUSE_FRAME_OFF = 0x00000000,/* Detect only pause frame
+							   with multicast addr. */
+	SYN_MAC_FC_RX_FLOW_CONTROL = 0x00000004,
+	SYN_MAC_FC_RX_FLOW_CONTROL_ENABLE = 0x00000004,	/* (RFE)Enable Rx flow control */
+	SYN_MAC_FC_RX_FLOW_CONTROL_DISABLE = 0x00000000,/* Disable Rx flow control */
+	SYN_MAC_FC_TX_FLOW_CONTROL = 0x00000002,
+	SYN_MAC_FC_TX_FLOW_CONTROL_ENABLE = 0x00000002,	/* (TFE)Enable Tx flow control */
+	SYN_MAC_FC_TX_FLOW_CONTROL_DISABLE = 0x00000000,/* Disable flow control */
+	SYN_MAC_FC_FLOW_CONTROL_BACK_PRESSURE = 0x00000001,
+	SYN_MAC_FC_SEND_PAUSE_FRAME = 0x00000001,	/* (FCB/PBA)send pause frm/Apply
+							   back pressure */
+};
+
+/*
+ * SYN_MAC_ADDR_HIGH Register
+ */
+enum syn_mac_addr_high {
+	SYN_MAC_ADDR_HIGH_AE = 0x80000000,
+};
+
+/*
+ * SYN_DMA_BUS_MODE = 0x0000,		CSR0 - Bus Mode
+ */
+enum syn_dma_bus_mode_reg {
+	SYN_DMA_FIXED_BURST_ENABLE = 0x00010000,	/* (FB)Fixed Burst SINGLE, INCR4,
+							   INCR8 or INCR16 */
+	SYN_DMA_FIXED_BURST_DISABLE = 0x00000000,	/* SINGLE, INCR */
+	SYN_DMA_TX_PRIORITY_RATIO11 = 0x00000000,	/* (PR)TX:RX DMA priority ratio 1:1 */
+	SYN_DMA_TX_PRIORITY_RATIO21 = 0x00004000,	/* (PR)TX:RX DMA priority ratio 2:1 */
+	SYN_DMA_TX_PRIORITY_RATIO31 = 0x00008000,	/* (PR)TX:RX DMA priority ratio 3:1 */
+	SYN_DMA_TX_PRIORITY_RATIO41 = 0x0000C000,	/* (PR)TX:RX DMA priority ratio 4:1 */
+	SYN_DMA_ADDRESS_ALIGNED_BEATS = 0x02000000,	/* Address Aligned beats */
+	SYN_DMA_BURST_LENGTHX8 = 0x01000000,		/* When set mutiplies the PBL by 8 */
+	SYN_DMA_BURST_LENGTH256 = 0x01002000,		/* (dma_burst_lengthx8 |
+							   dma_burst_length32) = 256 */
+	SYN_DMA_BURST_LENGTH128 = 0x01001000,		/* (dma_burst_lengthx8 |
+							   dma_burst_length16) = 128 */
+	SYN_DMA_BURST_LENGTH64 = 0x01000800,		/* (dma_burst_lengthx8 |
+							   dma_burst_length8) = 64 */
+	/* (PBL) programmable burst length */
+	SYN_DMA_BURST_LENGTH32 = 0x00002000,		/* Dma burst length = 32 */
+	SYN_DMA_BURST_LENGTH16 = 0x00001000,		/* Dma burst length = 16 */
+	SYN_DMA_BURST_LENGTH8 = 0x00000800,		/* Dma burst length = 8  */
+	SYN_DMA_BURST_LENGTH4 = 0x00000400,		/* Dma burst length = 4  */
+	SYN_DMA_BURST_LENGTH2 = 0x00000200,		/* Dma burst length = 2  */
+	SYN_DMA_BURST_LENGTH1 = 0x00000100,		/* Dma burst length = 1  */
+	SYN_DMA_BURST_LENGTH0 = 0x00000000,		/* Dma burst length = 0  */
+
+	SYN_DMA_DESCRIPTOR8_WORDS = 0x00000080,		/* Enh Descriptor works  1=>
+							   8 word descriptor          */
+	SYN_DMA_DESCRIPTOR4_WORDS = 0x00000000,		/* Enh Descriptor works  0=>
+							   4 word descriptor          */
+	SYN_DMA_DESCRIPTOR_SKIP16 = 0x00000040,		/* (DSL)Descriptor skip length (no.of dwords) */
+	SYN_DMA_DESCRIPTOR_SKIP8 = 0x00000020,		/* between two unchained descriptors */
+	SYN_DMA_DESCRIPTOR_SKIP4 = 0x00000010,
+	SYN_DMA_DESCRIPTOR_SKIP2 = 0x00000008,
+	SYN_DMA_DESCRIPTOR_SKIP1 = 0x00000004,
+	SYN_DMA_DESCRIPTOR_SKIP0 = 0x00000000,
+	SYN_DMA_ARBIT_RR = 0x00000000,			/* (DA) DMA RR arbitration    */
+	SYN_DMA_ARBIT_PR = 0x00000002,			/* Rx has priority over Tx    */
+	SYN_DMA_RESET_ON = 0x00000001,			/* (SWR)Software Reset DMA engine */
+	SYN_DMA_RESET_OFF = 0x00000000,
+};
+
+/*
+ * SYN_DMA_STATUS = 0x0014,		CSR5 - Dma status Register
+ */
+enum syn_dma_status_reg {
+	SYN_DMA_GMAC_PMT_INTR = 0x10000000,		/* (GPI)Gmac subsystem interrupt */
+	SYN_DMA_GMAC_MMC_INTR = 0x08000000,		/* (GMI)Gmac MMC subsystem interrupt */
+	SYN_DMA_GMAC_LINE_INTF_INTR = 0x04000000,	/* Line interface interrupt */
+	SYN_DMA_ERROR_BIT2 = 0x02000000,		/* (EB)Error bits 0-data buffer, 1-desc access */
+	SYN_DMA_ERROR_BIT1 = 0x01000000,		/* (EB)Error bits 0-write trnsf, 1-read transfer */
+	SYN_DMA_ERROR_BIT0 = 0x00800000,		/* (EB)Error bits 0-Rx DMA, 1-Tx DMA */
+	SYN_DMA_TX_STATE = 0x00700000,			/* (TS)Transmit process state */
+	SYN_DMA_TX_STOPPED = 0x00000000,		/* Stopped - Reset or Stop Tx Command issued */
+	SYN_DMA_TX_FETCHING = 0x00100000,		/* Running - fetching the Tx descriptor */
+	SYN_DMA_TX_WAITING = 0x00200000,		/* Running - waiting for status */
+	SYN_DMA_TX_READING = 0x00300000,		/* Running - reading the data from host memory */
+	SYN_DMA_TX_SUSPENDED = 0x00600000,		/* Suspended - Tx Descriptor unavailabe */
+	SYN_DMA_TX_CLOSING = 0x00700000,		/* Running - closing Rx descriptor */
+	SYN_DMA_RX_STATE = 0x000E0000,			/* (RS)Receive process state */
+	SYN_DMA_RX_STOPPED = 0x00000000,		/* Stopped - Reset or Stop Rx Command issued */
+	SYN_DMA_RX_FETCHING = 0x00020000,		/* Running - fetching the Rx descriptor */
+	SYN_DMA_RX_WAITING = 0x00060000,		/* Running - waiting for packet */
+	SYN_DMA_RX_SUSPENDED = 0x00080000,		/* Suspended - Rx Descriptor unavailable */
+	SYN_DMA_RX_CLOSING = 0x000A0000,		/* Running - closing descriptor */
+	SYN_DMA_RX_QUEUING = 0x000E0000,		/* Running - queuing the receive frame into host memory */
+	SYN_DMA_INT_NORMAL = 0x00010000,		/* (NIS)Normal interrupt summary */
+	SYN_DMA_INT_ABNORMAL = 0x00008000,		/* (AIS)Abnormal interrupt summary */
+	SYN_DMA_INT_EARLY_RX = 0x00004000,		/* Early receive interrupt (Normal) */
+	SYN_DMA_INT_BUS_ERROR = 0x00002000,		/* Fatal bus error (Abnormal) */
+	SYN_DMA_INT_EARLY_TX = 0x00000400,		/* Early transmit interrupt (Abnormal) */
+	SYN_DMA_INT_RX_WDOG_TO = 0x00000200,		/* Receive Watchdog Timeout (Abnormal) */
+	SYN_DMA_INT_RX_STOPPED = 0x00000100,		/* Receive process stopped (Abnormal) */
+	SYN_DMA_INT_RX_NO_BUFFER = 0x00000080,		/* RX buffer unavailable (Abnormal) */
+	SYN_DMA_INT_RX_COMPLETED = 0x00000040,		/* Completion of frame RX (Normal) */
+	SYN_DMA_INT_TX_UNDERFLOW = 0x00000020,		/* Transmit underflow (Abnormal) */
+	SYN_DMA_INT_RCV_OVERFLOW = 0x00000010,		/* RX Buffer overflow interrupt */
+	SYN_DMA_INT_TX_JABBER_TO = 0x00000008,		/* TX Jabber Timeout (Abnormal) */
+	SYN_DMA_INT_TX_NO_BUFFER = 0x00000004,		/* TX buffer unavailable (Normal) */
+	SYN_DMA_INT_TX_STOPPED = 0x00000002,		/* TX process stopped (Abnormal) */
+	SYN_DMA_INT_TX_COMPLETED = 0x00000001,		/* Transmit completed (Normal) */
+};
+
+/*
+ * SYN_DMA_OPERATION_MODE = 0x0018,		CSR6 - Dma Operation Mode Register
+ */
+enum syn_dma_operation_mode_reg {
+	SYN_DMA_DISABLE_DROP_TCP_CS = 0x04000000,	/* (DT) Dis. drop. of tcp/ip
+							   CS error frames            */
+	SYN_DMA_RX_STORE_AND_FORWARD = 0x02000000,	/* Rx (SF)Store and forward   */
+	SYN_DMA_RX_FRAME_FLUSH = 0x01000000,		/* Disable Receive Frame Flush*/
+	SYN_DMA_TX_STORE_AND_FORWARD = 0x00200000,	/* Tx (SF)Store and forward   */
+	SYN_DMA_FLUSH_TX_FIFO = 0x00100000,		/* (FTF)Tx FIFO controller
+							   is reset to default        */
+	SYN_DMA_TX_THRESH_CTRL = 0x0001C000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo                */
+	SYN_DMA_TX_THRESH_CTRL16 = 0x0001C000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 16             */
+	SYN_DMA_TX_THRESH_CTRL24 = 0x00018000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 24             */
+	SYN_DMA_TX_THRESH_CTRL32 = 0x00014000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 32             */
+	SYN_DMA_TX_THRESH_CTRL40 = 0x00010000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 40             */
+	SYN_DMA_TX_THRESH_CTRL256 = 0x0000c000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 256            */
+	SYN_DMA_TX_THRESH_CTRL192 = 0x00008000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 192            */
+	SYN_DMA_TX_THRESH_CTRL128 = 0x00004000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 128            */
+	SYN_DMA_TX_THRESH_CTRL64 = 0x00000000,		/* (TTC)Controls thre Thresh of
+							   MTL tx Fifo 64             */
+	SYN_DMA_TX_START = 0x00002000,			/* (ST)Start/Stop transmission*/
+	SYN_DMA_RX_FLOW_CTRL_DEACT = 0x00401800,	/* (RFD)Rx flow control
+							   deact. Threshold            */
+	SYN_DMA_RX_FLOW_CTRL_DEACT1K = 0x00000000,	/* (RFD)Rx flow control
+							   deact. Threshold (1kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT2K = 0x00000800,	/* (RFD)Rx flow control
+							   deact. Threshold (2kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT3K = 0x00001000,	/* (RFD)Rx flow control
+							   deact. Threshold (3kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT4K = 0x00001800,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT5K = 0x00400000,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT6K = 0x00400800,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_DEACT7K = 0x00401000,	/* (RFD)Rx flow control
+							   deact. Threshold (4kbytes)  */
+	SYN_DMA_RX_FLOW_CTRL_ACT = 0x00800600,		/* (RFA)Rx flow control
+							   Act. Threshold              */
+	SYN_DMA_RX_FLOW_CTRL_ACT1K = 0x00000000,	/* (RFA)Rx flow control
+							   Act. Threshold (1kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT2K = 0x00000200,	/* (RFA)Rx flow control
+							   Act. Threshold (2kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT3K = 0x00000400,	/* (RFA)Rx flow control
+							   Act. Threshold (3kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT4K = 0x00000600,	/* (RFA)Rx flow control
+							   Act. Threshold (4kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT5K = 0x00800000,	/* (RFA)Rx flow control
+							   Act. Threshold (5kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT6K = 0x00800200,	/* (RFA)Rx flow control
+							   Act. Threshold (6kbytes)    */
+	SYN_DMA_RX_FLOW_CTRL_ACT7K = 0x00800400,	/* (RFA)Rx flow control
+							   Act. Threshold (7kbytes)    */
+	SYN_DMA_RX_THRESH_CTRL = 0x00000018,		/* (RTC)Controls thre
+							   Thresh of MTL rx Fifo       */
+	SYN_DMA_RX_THRESH_CTRL64 = 0x00000000,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 64    */
+	SYN_DMA_RX_THRESH_CTRL32 = 0x00000008,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 32    */
+	SYN_DMA_RX_THRESH_CTRL96 = 0x00000010,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 96    */
+	SYN_DMA_RX_THRESH_CTRL128 = 0x00000018,		/* (RTC)Controls thre
+							   Thresh of MTL tx Fifo 128   */
+	SYN_DMA_EN_HW_FLOW_CTRL = 0x00000100,		/* (EFC)Enable HW flow control*/
+	SYN_DMA_DIS_HW_FLOW_CTRL = 0x00000000,		/* Disable HW flow control    */
+	SYN_DMA_FWD_ERROR_FRAMES = 0x00000080,		/* (FEF)Forward error frames  */
+	SYN_DMA_FWD_UNDER_SZ_FRAMES = 0x00000040,	/* (FUF)Forward undersize
+							   frames                     */
+	SYN_DMA_TX_SECOND_FRAME = 0x00000004,		/* (OSF)Operate on 2nd frame  */
+	SYN_DMA_RX_START = 0x00000002,			/* (SR)Start/Stop reception   */
+};
+
+/*
+ * SYN_DMA_INT_ENABLE = 0x101C,		CSR7 - Interrupt enable Register Layout
+ */
+enum syn_dma_interrupt_reg {
+	SYN_DMA_IE_NORMAL = SYN_DMA_INT_NORMAL,		/* Normal interrupt enable */
+	SYN_DMA_IE_ABNORMAL = SYN_DMA_INT_ABNORMAL,	/* Abnormal interrupt enable */
+	SYN_DMA_IE_EARLY_RX = SYN_DMA_INT_EARLY_RX,	/* Early RX interrupt enable */
+	SYN_DMA_IE_BUS_ERROR = SYN_DMA_INT_BUS_ERROR,	/* Fatal bus error enable */
+	SYN_DMA_IE_EARLY_TX = SYN_DMA_INT_EARLY_TX,	/* Early TX interrupt enable */
+	SYN_DMA_IE_RX_WDOG_TO = SYN_DMA_INT_RX_WDOG_TO,	/* RX Watchdog Timeout enable */
+	SYN_DMA_IE_RX_STOPPED = SYN_DMA_INT_RX_STOPPED,	/* RX process stopped enable */
+	SYN_DMA_IE_RX_NO_BUFFER = SYN_DMA_INT_RX_NO_BUFFER,
+							/* Receive buffer unavailable enable */
+	SYN_DMA_IE_RX_COMPLETED = SYN_DMA_INT_RX_COMPLETED,
+							/* Completion of frame reception enable */
+	SYN_DMA_IE_TX_UNDERFLOW = SYN_DMA_INT_TX_UNDERFLOW,
+							/* TX underflow enable */
+	SYN_DMA_IE_RX_OVERFLOW = SYN_DMA_INT_RCV_OVERFLOW,
+							/* RX Buffer overflow interrupt */
+	SYN_DMA_IE_TX_JABBER_TO = SYN_DMA_INT_TX_JABBER_TO,
+							/* TX Jabber Timeout enable */
+	SYN_DMA_IE_TX_NO_BUFFER = SYN_DMA_INT_TX_NO_BUFFER,
+							/* TX buffer unavailable enable */
+	SYN_DMA_IE_TX_STOPPED = SYN_DMA_INT_TX_STOPPED,
+							/* TX process stopped enable */
+	SYN_DMA_IE_TX_COMPLETED = SYN_DMA_INT_TX_COMPLETED,
+							/* TX completed enable */
+};
+
+/*
+ * SYN_DMA_AXI_BUS_MODE = 0x1028
+ */
+enum syn_dma_axi_bus_mode_reg {
+	SYN_DMA_EN_LPI = 0x80000000,
+	SYN_DMA_LPI_XIT_FRM = 0x40000000,
+	SYN_DMA_WR_OSR_NUM_REQS16 = 0x00F00000,
+	SYN_DMA_WR_OSR_NUM_REQS8 = 0x00700000,
+	SYN_DMA_WR_OSR_NUM_REQS4 = 0x00300000,
+	SYN_DMA_WR_OSR_NUM_REQS2 = 0x00100000,
+	SYN_DMA_WR_OSR_NUM_REQS1 = 0x00000000,
+	SYN_DMA_RD_OSR_NUM_REQS16 = 0x000F0000,
+	SYN_DMA_RD_OSR_NUM_REQS8 = 0x00070000,
+	SYN_DMA_RD_OSR_NUM_REQS4 = 0x00030000,
+	SYN_DMA_RD_OSR_NUM_REQS2 = 0x00010000,
+	SYN_DMA_RD_OSR_NUM_REQS1 = 0x00000000,
+	SYN_DMA_ONEKBBE = 0x00002000,
+	SYN_DMA_AXI_AAL = 0x00001000,
+	SYN_DMA_AXI_BLEN256 = 0x00000080,
+	SYN_DMA_AXI_BLEN128 = 0x00000040,
+	SYN_DMA_AXI_BLEN64 = 0x00000020,
+	SYN_DMA_AXI_BLEN32 = 0x00000010,
+	SYN_DMA_AXI_BLEN16 = 0x00000008,
+	SYN_DMA_AXI_BLEN8 = 0x00000004,
+	SYN_DMA_AXI_BLEN4 = 0x00000002,
+	SYN_DMA_UNDEFINED = 0x00000001,
+};
+
+/*
+ * Values to initialize DMA registers
+ */
+enum syn_dma_init_values {
+	/*
+	 * Interrupt groups
+	 */
+	SYN_DMA_INT_ERROR_MASK = SYN_DMA_INT_BUS_ERROR,		/* Error              */
+	SYN_DMA_INT_RX_ABN_MASK = SYN_DMA_INT_RX_NO_BUFFER,	/* RX abnormal intr   */
+	SYN_DMA_INT_RX_NORM_MASK = SYN_DMA_INT_RX_COMPLETED,	/* RXnormal intr      */
+	SYN_DMA_INT_RX_STOPPED_MASK = SYN_DMA_INT_RX_STOPPED,	/* RXstopped          */
+	SYN_DMA_INT_TX_ABN_MASK = SYN_DMA_INT_TX_UNDERFLOW,	/* TX abnormal intr   */
+	SYN_DMA_INT_TX_NORM_MASK = SYN_DMA_INT_TX_COMPLETED,	/* TX normal intr     */
+	SYN_DMA_INT_TX_STOPPED_MASK = SYN_DMA_INT_TX_STOPPED,	/* TX stopped         */
+
+	SYN_DMA_BUS_MODE_INIT = SYN_DMA_FIXED_BURST_ENABLE | SYN_DMA_BURST_LENGTH8
+		| SYN_DMA_DESCRIPTOR_SKIP2 | SYN_DMA_RESET_OFF,
+
+	SYN_DMA_BUS_MODE_VAL = SYN_DMA_BURST_LENGTH32
+		| SYN_DMA_BURST_LENGTHX8 | SYN_DMA_DESCRIPTOR_SKIP0
+		| SYN_DMA_DESCRIPTOR8_WORDS | SYN_DMA_ARBIT_PR | SYN_DMA_ADDRESS_ALIGNED_BEATS,
+
+	SYN_DMA_OMR = SYN_DMA_TX_STORE_AND_FORWARD | SYN_DMA_RX_STORE_AND_FORWARD
+		| SYN_DMA_RX_THRESH_CTRL128 | SYN_DMA_TX_SECOND_FRAME,
+
+	SYN_DMA_INT_EN = SYN_DMA_IE_NORMAL | SYN_DMA_IE_ABNORMAL | SYN_DMA_INT_ERROR_MASK
+		| SYN_DMA_INT_RX_ABN_MASK | SYN_DMA_INT_RX_NORM_MASK
+		| SYN_DMA_INT_RX_STOPPED_MASK | SYN_DMA_INT_TX_ABN_MASK
+		| SYN_DMA_INT_TX_NORM_MASK | SYN_DMA_INT_TX_STOPPED_MASK,
+	SYN_DMA_INT_DISABLE = 0,
+	SYN_DMA_AXI_BUS_MODE_VAL = SYN_DMA_AXI_BLEN16 | SYN_DMA_RD_OSR_NUM_REQS8
+		| SYN_DMA_WR_OSR_NUM_REQS8,
+};
+
+/*
+ * desc_mode
+ *	GMAC descriptors mode
+ */
+enum desc_mode {
+	RINGMODE = 0x00000001,
+	CHAINMODE = 0x00000002,
+};
+
+extern void syn_disable_dma_interrupt(struct nss_gmac_hal_dev *nghd);
+extern void syn_enable_dma_interrupt(struct nss_gmac_hal_dev *nghd);
+extern void syn_enable_dma_rx(struct nss_gmac_hal_dev *nghd);
+extern void syn_disable_dma_rx(struct nss_gmac_hal_dev *nghd);
+extern void syn_enable_dma_tx(struct nss_gmac_hal_dev *nghd);
+extern void syn_disable_dma_tx(struct nss_gmac_hal_dev *nghd);
+extern void syn_clear_dma_status(struct nss_gmac_hal_dev *nghd);
+extern void syn_resume_dma_tx(struct nss_gmac_hal_dev *nghd);
+extern uint32_t syn_get_rx_missed(struct nss_gmac_hal_dev *nghd);
+extern uint32_t syn_get_fifo_overflows(struct nss_gmac_hal_dev *nghd);
+
+extern void syn_init_tx_desc_base(struct nss_gmac_hal_dev *nghd, uint32_t tx_desc_dma);
+extern void syn_init_rx_desc_base(struct nss_gmac_hal_dev *nghd, uint32_t rx_desc_dma);
+
+#endif /*__SYN_REG_H__*/

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/xgmac/syn_dev.h

@@ -0,0 +1,189 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __SYN_DEV_H__
+#define __SYN_DEV_H__
+
+#include "syn_reg.h"
+#include <fal/fal_mib.h>
+#include <fal/fal_port_ctrl.h>
+
+/*
+ * Subclass for base nss_gmac_haldev
+ */
+struct syn_hal_dev {
+	struct nss_gmac_hal_dev nghd;	/* Base class */
+	fal_xgmib_info_t stats;		/* Stats structure */
+};
+
+/*
+ * syn_set_rx_flow_ctrl()
+ */
+static inline void syn_set_rx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_RX_FLOW_CTL,
+			SYN_MAC_RX_FLOW_ENABLE);
+}
+
+/*
+ * syn_clear_rx_flow_ctrl()
+ */
+static inline void syn_clear_rx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_RX_FLOW_CTL,
+			SYN_MAC_RX_FLOW_ENABLE);
+}
+
+/*
+ * syn_set_tx_flow_ctrl()
+ */
+static inline void syn_set_tx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+}
+
+/*
+ * syn_send_tx_pause_frame()
+ */
+static inline void syn_send_tx_pause_frame(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+	hal_set_reg_bits(nghd, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_PAUSE_SEND);
+}
+
+/*
+ * syn_clear_tx_flow_ctrl()
+ */
+static inline void syn_clear_tx_flow_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_Q0_TX_FLOW_CTL,
+			SYN_MAC_TX_FLOW_ENABLE);
+}
+
+/*
+ * syn_clear_mac_ctrl()
+ */
+static inline void syn_clear_mac_ctrl(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_write_reg(nghd->mac_base, SYN_MAC_TX_CONFIG, 0);
+	hal_write_reg(nghd->mac_base, SYN_MAC_RX_CONFIG, 0);
+}
+
+/*
+ * syn_rx_enable()
+ */
+static inline void syn_rx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_RX_CONFIG, SYN_MAC_RX_ENABLE);
+	hal_set_reg_bits(nghd, SYN_MAC_PACKET_FILTER, SYN_MAC_RX_ENABLE);
+}
+
+/*
+ * syn_rx_disable()
+ */
+static inline void syn_rx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_RX_CONFIG, SYN_MAC_RX_ENABLE);
+}
+
+/*
+ * syn_tx_enable()
+ */
+static inline void syn_tx_enable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_TX_CONFIG, SYN_MAC_TX_ENABLE);
+}
+
+/*
+ * syn_tx_disable()
+ */
+static inline void syn_tx_disable(struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_TX_CONFIG,
+			SYN_MAC_TX_ENABLE);
+}
+
+/*
+ * syn_set_mmc_stats()
+ */
+static inline void syn_set_mmc_stats(struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_MMC_CTL,
+			SYN_MAC_MMC_RSTONRD);
+}
+
+/*
+ * syn_rx_jumbo_frame_enable()
+ */
+static inline void syn_rx_jumbo_frame_enable(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_set_reg_bits(nghd, SYN_MAC_RX_CONFIG,
+			SYN_MAC_JUMBO_FRAME_ENABLE);
+}
+
+/*
+ * syn_rx_jumbo_frame_disable()
+ */
+static inline void syn_rx_jumbo_frame_disable(
+		struct nss_gmac_hal_dev *nghd)
+{
+	hal_clear_reg_bits(nghd, SYN_MAC_RX_CONFIG,
+			SYN_MAC_JUMBO_FRAME_ENABLE);
+}
+
+/*
+ * syn_set_full_duplex()
+ */
+static inline void syn_set_full_duplex(
+		struct nss_gmac_hal_dev *nghd)
+{
+	/* TBD */
+	return;
+}
+
+/*
+ * syn_set_half_duplex()
+ */
+static inline void syn_set_half_duplex(
+		struct nss_gmac_hal_dev *nghd)
+{
+	/* TBD */
+	return;
+}
+
+static int syn_get_stats(struct nss_gmac_hal_dev *nghd)
+{
+	struct syn_hal_dev *shd = (struct syn_hal_dev *)nghd;
+	fal_xgmib_info_t *stats = &(shd->stats);
+
+	if (fal_get_xgmib_info(0, nghd->mac_id, stats))
+		return -1;
+
+	return 0;
+}
+#endif /*__SYN_DEV_H__*/

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/xgmac/syn_if.c

@@ -0,0 +1,505 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+#include <linux/delay.h>
+#include <linux/ethtool.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <nss_dp_hal_if.h>
+#include <nss_dp_dev.h>
+#include "syn_dev.h"
+
+#define SYN_STAT(m)	offsetof(fal_xgmib_info_t, m)
+
+struct syn_ethtool_stats {
+	uint8_t stat_string[ETH_GSTRING_LEN];
+	uint64_t stat_offset;
+};
+
+/*
+ * Array of strings describing statistics
+ */
+static const struct syn_ethtool_stats syn_gstrings_stats[] = {
+	{"rx_frame", SYN_STAT(RxFrame)},
+	{"rx_bytes", SYN_STAT(RxByte)},
+	{"rx_bytes_g", SYN_STAT(RxByteGood)},
+	{"rx_broadcast", SYN_STAT(RxBroadGood)},
+	{"rx_multicast", SYN_STAT(RxMultiGood)},
+	{"rx_crc_err", SYN_STAT(RxFcsErr)},
+	{"rx_runt_err", SYN_STAT(RxRuntErr)},
+	{"rx_jabber_err", SYN_STAT(RxJabberError)},
+	{"rx_undersize", SYN_STAT(RxUndersizeGood)},
+	{"rx_oversize", SYN_STAT(RxOversizeGood)},
+	{"rx_pkt64", SYN_STAT(Rx64Byte)},
+	{"rx_pkt65to127", SYN_STAT(Rx128Byte)},
+	{"rx_pkt128to255", SYN_STAT(Rx256Byte)},
+	{"rx_pkt256to511", SYN_STAT(Rx512Byte)},
+	{"rx_pkt512to1023", SYN_STAT(Rx1024Byte)},
+	{"rx_pkt1024tomax", SYN_STAT(RxMaxByte)},
+	{"rx_unicast", SYN_STAT(RxUnicastGood)},
+	{"rx_len_err", SYN_STAT(RxLengthError)},
+	{"rx_outofrange_err_ctr", SYN_STAT(RxOutOfRangeError)},
+	{"rx_pause", SYN_STAT(RxPause)},
+	{"rx_fifo_overflow", SYN_STAT(RxOverFlow)},
+	{"rx_vlan", SYN_STAT(RxVLANFrameGoodBad)},
+	{"rx_wdog", SYN_STAT(RxWatchDogError)},
+	{"rx_lpi_usec_ctr", SYN_STAT(RxLPIUsec)},
+	{"rx_lpi_tran_ctr", SYN_STAT(RxLPITran)},
+	{"rx_drop_frame_ctr", SYN_STAT(RxDropFrameGoodBad)},
+	{"rx_drop_byte_ctr", SYN_STAT(RxDropByteGoodBad)},
+	{"tx_bytes", SYN_STAT(TxByte)},
+	{"tx_frame", SYN_STAT(TxFrame)},
+	{"tx_broadcast", SYN_STAT(TxBroadGood)},
+	{"tx_broadcast_gb", SYN_STAT(TxBroad)},
+	{"tx_multicast", SYN_STAT(TxMultiGood)},
+	{"tx_multicast_gb", SYN_STAT(TxMulti)},
+	{"tx_pkt64", SYN_STAT(Tx64Byte)},
+	{"tx_pkt65to127", SYN_STAT(Tx128Byte)},
+	{"tx_pkt128to255", SYN_STAT(Tx256Byte)},
+	{"tx_pkt256to511", SYN_STAT(Tx512Byte)},
+	{"tx_pkt512to1023", SYN_STAT(Tx1024Byte)},
+	{"tx_pkt1024tomax", SYN_STAT(TxMaxByte)},
+	{"tx_unicast", SYN_STAT(TxUnicast)},
+	{"tx_underflow_err", SYN_STAT(TxUnderFlowError)},
+	{"tx_bytes_g", SYN_STAT(TxByteGood)},
+	{"tx_frame_g", SYN_STAT(TxFrameGood)},
+	{"tx_pause", SYN_STAT(TxPause)},
+	{"tx_vlan", SYN_STAT(TxVLANFrameGood)},
+	{"tx_lpi_usec_ctr", SYN_STAT(TxLPIUsec)},
+	{"tx_lpi_tran_ctr", SYN_STAT(TxLPITran)},
+};
+
+/*
+ * Array of strings describing private flag names
+ */
+static const char *const syn_strings_priv_flags[] = {
+	"test",
+};
+
+#define SYN_STATS_LEN	ARRAY_SIZE(syn_gstrings_stats)
+#define SYN_PRIV_FLAGS_LEN	ARRAY_SIZE(syn_strings_priv_flags)
+
+/*
+ * syn_rx_flow_control()
+ */
+static void syn_rx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_rx_flow_ctrl(nghd);
+	else
+		syn_clear_rx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_tx_flow_control()
+ */
+static void syn_tx_flow_control(struct nss_gmac_hal_dev *nghd,
+				     bool enabled)
+{
+	BUG_ON(nghd == NULL);
+
+	if (enabled)
+		syn_set_tx_flow_ctrl(nghd);
+	else
+		syn_clear_tx_flow_ctrl(nghd);
+}
+
+/*
+ * syn_get_mmc_stats()
+ */
+static int32_t syn_get_mmc_stats(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	if (syn_get_stats(nghd))
+		return -1;
+
+	return 0;
+}
+
+/*
+ * syn_get_max_frame_size()
+ */
+static int32_t syn_get_max_frame_size(struct nss_gmac_hal_dev *nghd)
+{
+	int ret;
+	uint32_t mtu;
+
+	ret = fal_port_max_frame_size_get(0, nghd->mac_id, &mtu);
+
+	if (!ret)
+		return mtu;
+
+	return ret;
+}
+
+/*
+ * syn_set_max_frame_size()
+ */
+static int32_t syn_set_max_frame_size(struct nss_gmac_hal_dev *nghd,
+					uint32_t val)
+{
+	return fal_port_max_frame_size_set(0, nghd->mac_id, val);
+}
+
+/*
+ * syn_set_mac_speed()
+ */
+static int32_t syn_set_mac_speed(struct nss_gmac_hal_dev *nghd,
+				   uint32_t mac_speed)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_get_mac_speed()
+ */
+static uint32_t syn_get_mac_speed(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_set_duplex_mode()
+ */
+static void syn_set_duplex_mode(struct nss_gmac_hal_dev *nghd,
+				uint8_t duplex_mode)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+}
+
+/*
+ * syn_get_duplex_mode()
+ */
+static uint8_t syn_get_duplex_mode(struct nss_gmac_hal_dev *nghd)
+{
+	struct net_device *netdev = nghd->netdev;
+
+	netdev_warn(netdev, "API deprecated\n");
+	return 0;
+}
+
+/*
+ * syn_get_netdev_stats()
+ */
+static int syn_get_netdev_stats(struct nss_gmac_hal_dev *nghd,
+		struct rtnl_link_stats64 *stats)
+{
+	struct syn_hal_dev *shd;
+	fal_xgmib_info_t *hal_stats;
+
+	BUG_ON(nghd == NULL);
+
+	shd = (struct syn_hal_dev *)nghd;
+	hal_stats = &(shd->stats);
+
+	if (syn_get_stats(nghd))
+		return -1;
+
+	stats->rx_packets = hal_stats->RxUnicastGood
+		+ hal_stats->RxBroadGood + hal_stats->RxMultiGood;
+	stats->tx_packets = hal_stats->TxUnicast
+		+ hal_stats->TxBroadGood + hal_stats->TxMultiGood;
+	stats->rx_bytes = hal_stats->RxByte;
+	stats->tx_bytes = hal_stats->TxByte;
+	stats->multicast =
+		hal_stats->RxMultiGood;
+	stats->rx_dropped =
+		hal_stats->RxDropFrameGoodBad;
+	stats->rx_length_errors =
+		hal_stats->RxLengthError;
+	stats->rx_crc_errors =
+		hal_stats->RxFcsErr;
+	stats->rx_fifo_errors =
+		hal_stats->RxOverFlow;
+
+	return 0;
+}
+
+/*
+ * syn_get_eth_stats()
+ */
+static int32_t syn_get_eth_stats(struct nss_gmac_hal_dev *nghd,
+				   uint64_t *data)
+{
+	struct syn_hal_dev *shd;
+	fal_xgmib_info_t *stats;
+	uint8_t *p = NULL;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	shd = (struct syn_hal_dev *)nghd;
+	stats = &(shd->stats);
+
+	if (syn_get_stats(nghd))
+		return -1;
+
+	for (i = 0; i < SYN_STATS_LEN; i++) {
+		p = ((uint8_t *)(stats) +
+				syn_gstrings_stats[i].stat_offset);
+		data[i] = *(uint32_t *)p;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_get_strset_count()
+ */
+static int32_t syn_get_strset_count(struct nss_gmac_hal_dev *nghd,
+					 int32_t sset)
+{
+	struct net_device *netdev;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (sset) {
+	case ETH_SS_STATS:
+		return SYN_STATS_LEN;
+
+	case ETH_SS_PRIV_FLAGS:
+		return SYN_PRIV_FLAGS_LEN;
+	}
+
+	netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+	return -EPERM;
+}
+
+/*
+ * syn_get_strings()
+ */
+static int32_t syn_get_strings(struct nss_gmac_hal_dev *nghd,
+				    int32_t stringset, uint8_t *data)
+{
+	struct net_device *netdev;
+	int i;
+
+	BUG_ON(nghd == NULL);
+
+	netdev = nghd->netdev;
+
+	switch (stringset) {
+	case ETH_SS_STATS:
+		for (i = 0; i < SYN_STATS_LEN; i++) {
+			memcpy(data, syn_gstrings_stats[i].stat_string,
+				strlen(syn_gstrings_stats[i].stat_string));
+			data += ETH_GSTRING_LEN;
+		}
+		break;
+
+	case ETH_SS_PRIV_FLAGS:
+		for (i = 0; i < SYN_PRIV_FLAGS_LEN; i++) {
+			memcpy(data, syn_strings_priv_flags[i],
+				strlen(syn_strings_priv_flags[i]));
+			data += ETH_GSTRING_LEN;
+		}
+
+		break;
+	default:
+		netdev_dbg(netdev, "%s: Invalid string set\n", __func__);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * syn_send_pause_frame()
+ */
+static void syn_send_pause_frame(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_send_tx_pause_frame(nghd);
+}
+
+/*
+ * syn_start
+ */
+static int32_t syn_start(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_tx_enable(nghd);
+	syn_rx_enable(nghd);
+	syn_set_full_duplex(nghd);
+	if (syn_set_mac_speed(nghd, SPEED_10000))
+		return -1;
+
+	netdev_dbg(nghd->netdev,
+			"%s: mac_base:0x%px tx_enable:0x%x rx_enable:0x%x\n",
+			__func__,
+			nghd->mac_base,
+			hal_read_reg(nghd->mac_base,
+				SYN_MAC_TX_CONFIG),
+			hal_read_reg(nghd->mac_base,
+				SYN_MAC_RX_CONFIG));
+
+	return 0;
+}
+
+/*
+ * syn_stop
+ */
+static int32_t syn_stop(struct nss_gmac_hal_dev *nghd)
+{
+	BUG_ON(nghd == NULL);
+
+	syn_tx_disable(nghd);
+	syn_rx_disable(nghd);
+
+	netdev_dbg(nghd->netdev, "%s: Stopping mac_base:0x%px\n", __func__,
+		   nghd->mac_base);
+
+	return 0;
+}
+
+/*
+ * syn_init()
+ */
+static void *syn_init(struct gmac_hal_platform_data *gmacpdata)
+{
+	struct syn_hal_dev *shd = NULL;
+	struct net_device *ndev = NULL;
+	struct nss_dp_dev *dp_priv = NULL;
+	struct resource *res;
+
+	ndev = gmacpdata->netdev;
+	dp_priv = netdev_priv(ndev);
+
+	res = platform_get_resource(dp_priv->pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		netdev_dbg(ndev, "Resource get failed.\n");
+		return NULL;
+	}
+
+	if (!devm_request_mem_region(&dp_priv->pdev->dev, res->start,
+				     resource_size(res), ndev->name)) {
+		netdev_dbg(ndev, "Request mem region failed. Returning...\n");
+		return NULL;
+	}
+
+	shd = (struct syn_hal_dev *)devm_kzalloc(&dp_priv->pdev->dev,
+					sizeof(struct syn_hal_dev),
+					GFP_KERNEL);
+	if (!shd) {
+		netdev_dbg(ndev, "kzalloc failed. Returning...\n");
+		return NULL;
+	}
+
+	/* Save netdev context in syn HAL context */
+	shd->nghd.netdev = gmacpdata->netdev;
+	shd->nghd.mac_id = gmacpdata->macid;
+
+	/* Populate the mac base addresses */
+	shd->nghd.mac_base =
+		devm_ioremap_nocache(&dp_priv->pdev->dev, res->start,
+				     resource_size(res));
+	if (!shd->nghd.mac_base) {
+		netdev_dbg(ndev, "ioremap fail.\n");
+		return NULL;
+	}
+
+	spin_lock_init(&shd->nghd.slock);
+
+	netdev_dbg(ndev, "ioremap OK.Size 0x%x Ndev base 0x%lx macbase 0x%px\n",
+			gmacpdata->reg_len,
+			ndev->base_addr,
+			shd->nghd.mac_base);
+
+	/* Reset MIB Stats */
+	if (fal_mib_port_flush_counters(0, shd->nghd.mac_id)) {
+		netdev_dbg(ndev, "MIB stats Reset fail.\n");
+	}
+
+	return (struct nss_gmac_hal_dev *)shd;
+}
+
+/*
+ * syn_set_mac_address()
+ */
+static void syn_set_mac_address(struct nss_gmac_hal_dev *nghd,
+				     uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	data = (macaddr[5] << 8) | macaddr[4] | SYN_MAC_ADDR_RSVD_BIT;
+	hal_write_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH, data);
+	data = (macaddr[3] << 24) | (macaddr[2] << 16) | (macaddr[1] << 8)
+		| macaddr[0];
+	hal_write_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW, data);
+}
+
+/*
+ * syn_get_mac_address()
+ */
+static void syn_get_mac_address(struct nss_gmac_hal_dev *nghd,
+				     uint8_t *macaddr)
+{
+	uint32_t data;
+
+	BUG_ON(nghd == NULL);
+
+	data = hal_read_reg(nghd->mac_base, SYN_MAC_ADDR0_HIGH);
+	macaddr[5] = (data >> 8) & 0xff;
+	macaddr[4] = (data) & 0xff;
+
+	data = hal_read_reg(nghd->mac_base, SYN_MAC_ADDR0_LOW);
+	macaddr[3] = (data >> 24) & 0xff;
+	macaddr[2] = (data >> 16) & 0xff;
+	macaddr[1] = (data >> 8) & 0xff;
+	macaddr[0] = (data) & 0xff;
+}
+
+struct nss_gmac_hal_ops syn_hal_ops = {
+	.init = &syn_init,
+	.start = &syn_start,
+	.stop = &syn_stop,
+	.setmacaddr = &syn_set_mac_address,
+	.getmacaddr = &syn_get_mac_address,
+	.rxflowcontrol = &syn_rx_flow_control,
+	.txflowcontrol = &syn_tx_flow_control,
+	.setspeed = &syn_set_mac_speed,
+	.getspeed = &syn_get_mac_speed,
+	.setduplex = &syn_set_duplex_mode,
+	.getduplex = &syn_get_duplex_mode,
+	.getstats = &syn_get_mmc_stats,
+	.setmaxframe = &syn_set_max_frame_size,
+	.getmaxframe = &syn_get_max_frame_size,
+	.getndostats = &syn_get_netdev_stats,
+	.getssetcount = &syn_get_strset_count,
+	.getstrings = &syn_get_strings,
+	.getethtoolstats = &syn_get_eth_stats,
+	.sendpause = &syn_send_pause_frame,
+};

feeds/ipq807x/qca-nss-dp/src/hal/gmac_hal_ops/syn/xgmac/syn_reg.h

@@ -0,0 +1,255 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __SYN_REG_H__
+#define __SYN_REG_H__
+
+/*
+ *
+ MAC Register Offset
+ *
+ */
+#define SYN_MAC_TX_CONFIG		0x0000
+#define SYN_MAC_RX_CONFIG		0x0004
+#define SYN_MAC_PACKET_FILTER		0x0008
+#define SYN_MAC_WDOG_TIMEOUT		0x000c
+#define SYN_MAC_HASH_TBL_REG0		0x0010
+#define SYN_MAC_VLAN_TAG		0x0050
+#define SYN_MAC_VLAN_HASH_TBL		0x0058
+#define SYN_MAC_VLAN_INCL		0x0060
+#define SYN_MAC_INNER_VLAN_INCL		0x0064
+#define SYN_MAC_RX_ETH_TYP_MATCH	0x006c
+#define SYN_MAC_Q0_TX_FLOW_CTL		0x0070
+#define SYN_MAC_Q1_TX_FLOW_CTL		0x0074
+#define SYN_MAC_Q2_TX_FLOW_CTL		0x0078
+#define SYN_MAC_Q3_TX_FLOW_CTL		0x007c
+#define SYN_MAC_Q4_TX_FLOW_CTL		0x0080
+#define SYN_MAC_Q5_TX_FLOW_CTL		0x0084
+#define SYN_MAC_Q6_TX_FLOW_CTL		0x0088
+#define SYN_MAC_Q7_TX_FLOW_CTL		0x008c
+#define SYN_MAC_RX_FLOW_CTL		0x0090
+#define SYN_MAC_RXQ_CTL0		0x00a0
+#define SYN_MAC_RXQ_CTL1		0x00a4
+#define SYN_MAC_RXQ_CTL2		0x00a8
+#define SYN_MAC_RXQ_CTL3		0x00ac
+#define SYN_MAC_INT_STATUS		0x00b0
+#define SYN_MAC_INT_ENABLE		0x00b4
+#define SYN_MAC_TX_RX_STATUS		0x00b8
+#define SYN_MAC_PMT_CTL_STATUS		0x00c0
+#define SYN_MAC_RWK_PACKET_FILTER	0x00c4
+#define SYN_MAC_LPI_CTL_STATUS		0x00d0
+#define SYN_MAC_LPI_TIMER_STATUS	0x00d4
+#define SYN_MAC_VERSION			0x0110
+#define SYN_MAC_DEBUG			0x0114
+#define SYN_MAC_FW_FEATURE0		0x011c
+#define SYN_MAC_FW_FEATURE1		0x0120
+#define SYN_MAC_FW_FEATURE2		0x0124
+#define SYN_MAC_GPIO_CTL		0x0278
+#define SYN_MAC_GPIO_STATUS		0x027c
+#define SYN_MAC_ADDR0_HIGH		0x0300
+#define SYN_MAC_ADDR0_LOW		0x0304
+#define SYN_MAC_ADDR1_HIGH		0x0308
+#define SYN_MAC_ADDR1_LOW		0x030c
+#define SYN_MAC_TS_CTL			0x0d00
+#define SYN_MAC_SUB_SEC_INCR		0x0d04
+#define SYN_MAC_SYS_TIME_SECS		0x0d08
+#define SYN_MAC_SYS_TIME_NSECS		0x0d0c
+#define SYN_MAC_SYS_TIME_SECS_UPDATE	0x0d10
+#define SYN_MAC_SYS_TIME_NSECS_UPDATE	0x0d14
+#define SYN_MAC_TS_ADDEND		0x0d18
+#define SYN_MAC_TS_STATUS		0x0d20
+#define SYN_MAC_TX_TS_STATUS_NSECS	0x0d30
+#define SYN_MAC_TX_TS_STATUS_SECS	0x0d34
+#define SYN_MAC_PPS_CTL			0x0d70
+#define SYN_MAC_MMC_CTL			0x0800
+#define SYN_MAC_MMC_RX_INT		0x0804
+#define SYN_MAC_MMC_TX_INT		0x0808
+#define SYN_MAC_MMC_RX_INT_EN		0x080c
+#define SYN_MAC_MMC_TX_INT_EN		0x0810
+
+/* MAC TX MMC Counters */
+#define SYN_MAC_MMC_TX_BCAST_LO		0x0824
+#define SYN_MAC_MMC_TX_BCAST_HI		0x0828
+#define SYN_MAC_MMC_TX_FRAME_LO		0x0894
+#define SYN_MAC_MMC_TX_FRAME_HI		0x0898
+#define SYN_MAC_MMC_TX_MCAST_LO		0x082c
+#define SYN_MAC_MMC_TX_MCAST_HI		0x0830
+#define SYN_MAC_MMC_TX_PKT64_LO		0x0834
+#define SYN_MAC_MMC_TX_PKT64_HI		0x0838
+#define SYN_MAC_MMC_TX_PKT65TO127_LO	0x083c
+#define SYN_MAC_MMC_TX_PKT65TO127_HI	0x0840
+#define SYN_MAC_MMC_TX_PKT128TO255_LO	0x0844
+#define SYN_MAC_MMC_TX_PKT128TO255_HI	0x0848
+#define SYN_MAC_MMC_TX_PKT256TO511_LO	0x084c
+#define SYN_MAC_MMC_TX_PKT256TO511_HI	0x0850
+#define SYN_MAC_MMC_TX_PKT512TO1023_LO	0x0854
+#define SYN_MAC_MMC_TX_PKT512TO1023_HI	0x0858
+#define SYN_MAC_MMC_TX_PKT1024TOMAX_LO	0x085c
+#define SYN_MAC_MMC_TX_PKT1024TOMAX_HI	0x0860
+#define SYN_MAC_MMC_TX_UNICAST_LO	0x0864
+#define SYN_MAC_MMC_TX_UNICAST_HI	0x0868
+#define SYN_MAC_MMC_TX_MCAST_GB_LO	0x086c
+#define SYN_MAC_MMC_TX_MCAST_GB_HI	0x0870
+#define SYN_MAC_MMC_TX_BCAST_GB_LO	0x0874
+#define SYN_MAC_MMC_TX_BCAST_GB_HI	0x0878
+#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_LO	0x087c
+#define SYN_MAC_MMC_TX_UNDERFLOW_ERR_HI	0x0880
+#define SYN_MAC_MMC_TX_BYTES_LO		0x0884
+#define SYN_MAC_MMC_TX_BYTES_HI		0x0888
+#define SYN_MAC_MMC_TX_PAUSE_FRAME_LO	0x0894
+#define SYN_MAC_MMC_TX_PAUSE_FRAME_HI	0x0898
+#define SYN_MAC_MMC_TX_VLAN_LO		0x089c
+#define SYN_MAC_MMC_TX_VLAN_HI		0x08a0
+#define SYN_MAC_MMC_TX_LPI_USEC_CTR_LO	0x08a4
+#define SYN_MAC_MMC_TX_LPI_USEC_CTR_HI	0x08a8
+
+/* MAC RX MMC Counters */
+#define SYN_MAC_MMC_RX_FRAME_LO		0x0900
+#define SYN_MAC_MMC_RX_FRAME_HI		0x0904
+#define SYN_MAC_MMC_RX_BYTES_LO		0x0910
+#define SYN_MAC_MMC_RX_BYTES_HI		0x0914
+#define SYN_MAC_MMC_RX_BCAST_LO		0x0918
+#define SYN_MAC_MMC_RX_BCAST_HI		0x091c
+#define SYN_MAC_MMC_RX_MCAST_LO		0x0920
+#define SYN_MAC_MMC_RX_MCAST_HI		0x0924
+#define SYN_MAC_MMC_RX_CRC_ERR_LO	0x0928
+#define SYN_MAC_MMC_RX_CRC_ERR_HI	0x092c
+#define SYN_MAC_MMC_RX_RUNT_ERR		0x0930
+#define SYN_MAC_MMC_RX_JABBER_ERR	0x0934
+#define SYN_MAC_MMC_RX_UNDERSIZE	0x0938
+#define SYN_MAC_MMC_RX_OVERSIZE		0x093c
+#define SYN_MAC_MMC_RX_PKT64_LO		0x0940
+#define SYN_MAC_MMC_RX_PKT64_HI		0x0944
+#define SYN_MAC_MMC_RX_PKT65TO127_LO	0x0948
+#define SYN_MAC_MMC_RX_PKT65TO127_HI	0x094c
+#define SYN_MAC_MMC_RX_PKT128TO255_LO	0x0950
+#define SYN_MAC_MMC_RX_PKT128TO255_HI	0x0954
+#define SYN_MAC_MMC_RX_PKT256TO511_LO	0x0958
+#define SYN_MAC_MMC_RX_PKT256TO511_HI	0x095c
+#define SYN_MAC_MMC_RX_PKT512TO1023_LO	0x0960
+#define SYN_MAC_MMC_RX_PKT512TO1023_HI	0x0964
+#define SYN_MAC_MMC_RX_PKT1024TOMAX_LO	0x0968
+#define SYN_MAC_MMC_RX_PKT1024TOMAX_HI	0x096c
+#define SYN_MAC_MMC_RX_UNICAST_LO	0x0970
+#define SYN_MAC_MMC_RX_UNICAST_HI	0x0974
+#define SYN_MAC_MMC_RX_LEN_ERR_LO	0x0978
+#define SYN_MAC_MMC_RX_LEN_ERR_HI	0x097c
+#define SYN_MAC_MMC_RX_PAUSE_FRAME_LO	0x0988
+#define SYN_MAC_MMC_RX_PAUSE_FRAME_HI	0x098c
+#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_LO	0x0990
+#define SYN_MAC_MMC_RX_FIFO_OVERFLOW_HI	0x0994
+#define SYN_MAC_MMC_RX_VLAN_FRAME_LO	0x0998
+#define SYN_MAC_MMC_RX_VLAN_FRAME_HI	0x099c
+#define SYN_MAC_MMC_RX_LPI_USEC_CTR_LO	0x09a4
+#define SYN_MAC_MMC_RX_LPI_USEC_CTR_HI	0x09a8
+#define SYN_MAC_MMC_RX_DISCARD_FRAME_LO	0x09ac
+#define SYN_MAC_MMC_RX_DISCARD_FRAME_HI	0x09b0
+
+/* MAC Register Bit Definitions*/
+
+/* SYN_MAC_Q0_TX_FLOW_CTL Bit definitions */
+#define SYN_MAC_TX_PAUSE_SEND		0x00000001
+#define SYN_MAC_TX_FLOW_ENABLE		0x00000002
+#define SYN_MAC_TX_PAUSE_LOW_THRESHOLD	0x00000070
+#define SYN_MAC_ADDR_RSVD_BIT		0x80000000
+
+/* SYN_MAC_RX_FLOW_CTL Bit definitions */
+#define SYN_MAC_RX_FLOW_ENABLE		0x00000001
+
+/* SYN_MAC_TX_CONFIG Bit definitions */
+#define SYN_MAC_TX_ENABLE		0x00000001
+#define SYN_MAC_TX_SPEED_SELECT		0x60000000
+
+/* SYN_MAC_RX_CONFIG Bit definitions */
+#define SYN_MAC_RX_ENABLE		0x00000001
+#define SYN_MAC_JUMBO_FRAME_ENABLE	0x00000100
+
+#define SYN_MAC_SPEED_10G		0x0
+#define SYN_MAC_SPEED_2_5G		0x2
+#define SYN_MAC_SPEED_1G		0x3
+#define SYN_MAC_SPEED_BITPOS		29
+#define SYN_MAC_SPEED_BITMASK		0x3
+
+#define SYN_MAC_DEFAULT_MAX_FRAME_SIZE	1518
+#define SYN_MAC_MAX_FRAME_SIZE_BITPOS	16
+#define SYN_MAC_MAX_FRAME_SIZE_BITMASK	0x3fff
+
+/* SYN_MAC_MMC_CTL Bit definitions */
+#define  SYN_MAC_MMC_RSTONRD		0x00000004
+
+/*
+ *
+ MTL Register Offset
+ *
+ */
+#define SYN_MTL_OPER_MODE		0x1000
+#define SYN_MTL_DEBUG_CTL		0x1008
+#define SYN_MTL_DEBUG_STATUS		0x100c
+#define SYN_MTL_DEBUG_DATA		0x1010
+#define SYN_MTL_INT_STATUS		0x1020
+#define SYN_MTL_RXQ_DMA_MAP0		0x1030
+#define SYN_MTL_RXQ_DMA_MAP1		0x1034
+#define SYN_MTL_RXQ_DMA_MAP2		0x1038
+#define SYN_MTL_TC_PRIO_MAP0		0x1040
+#define SYN_MTL_TC_PRIO_MAP1		0x1044
+#define SYN_MTL_TXQ0_OPER_MODE		0x1100
+#define SYN_MTL_TXQ0_UNDERFLOW		0x1104
+#define SYN_MTL_TXQ0_DEBUG		0x1108
+#define SYN_MTL_TC0_ETS_CTL		0x1110
+#define SYN_MTL_TC0_ETS_STATUS		0x1114
+#define SYN_MTL_TC0_QUANTUM_WEIGHT	0x1118
+#define SYN_MTL_RXQ0_DEBUG		0x1148
+#define SYN_MTL_RXQ0_CTL		0x114c
+#define SYN_MTL_RXQ0_FLOW_CTL		0x1150
+#define SYN_MTL_Q0_INT_ENABLE		0x1170
+#define SYN_MTL_Q0_INT_STATUS		0x1174
+
+/* MTL Register Bit definitions */
+
+/*
+ *
+ DMA Register Offset
+ *
+ */
+#define SYN_DMA_MODE			0x3000
+#define SYN_DMA_SYSBUS_MODE		0x3004
+#define SYN_DMA_INT_STATUS		0x3008
+#define SYN_DMA_AXI_TX_AR_ACE_CTL	0x3010
+#define SYN_DMA_AXI_RX_AW_ACE_CTL	0x3018
+#define SYN_DMA_AXI_TXRX_AWAR_ACE_CTL	0x301c
+#define SYN_DMA_DEBUG_STATUS0		0x3020
+#define SYN_DMA_DEBUG_STATUS1		0x3024
+#define SYN_DMA_TX_EDMA_CTL		0x3040
+#define SYN_DMA_RX_EDMA_CTL		0x3044
+#define SYN_DMA_CH0_CTL			0x3100
+#define SYN_DMA_CH0_TX_CTL		0x3104
+#define SYN_DMA_CH0_RX_CTL		0x3108
+#define SYN_DMA_CH0_TXDESC_LIST_HADDR	0x3110
+#define SYN_DMA_CH0_TXDESC_LIST_LADDR	0x3114
+#define SYN_DMA_CH0_RXDESC_LIST_HADDR	0x3118
+#define SYN_DMA_CH0_RXDESC_LIST_LADDR	0x311c
+#define SYN_DMA_CH0_TXDESC_TAIL_LPTR	0x3124
+#define SYN_DMA_CH0_RXDESC_TAIL_LPTR	0x312c
+#define SYN_DMA_CH0_TXDESC_RING_LEN	0x3130
+#define SYN_DMA_CH0_RXDESC_RING_LEN	0x3134
+#define SYN_DMA_INT_ENABLE		0x3138
+#define SYN_DMA_RX_INT_WDOG_TIMER	0x313c
+
+/* DMA Register Bit definitions */
+
+#endif /*__SYN_REG_H__*/

feeds/ipq807x/qca-nss-dp/src/hal/include/edma.h

@@ -0,0 +1,31 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016, 2019-2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+*/
+
+/*
+ * This file includes declarations defined by the EDMA
+ * dataplane and used by other layers of this driver.
+ */
+
+#ifndef __NSS_DP_EDMA__
+#define __NSS_DP_EDMA__
+
+extern int edma_init(void);
+extern void edma_cleanup(bool is_dp_override);
+extern struct nss_dp_data_plane_ops nss_dp_edma_ops;
+
+#endif /*__NSS_DP_EDMA__ */

feeds/ipq807x/qca-nss-dp/src/hal/include/nss_dp_hal.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __NSS_DP_HAL_H__
+#define __NSS_DP_HAL_H__
+
+#include "nss_dp_dev.h"
+
+/*
+ * nss_dp_hal_get_gmac_ops()
+ *	Returns gmac hal ops based on the GMAC type.
+ */
+static inline struct nss_gmac_hal_ops *nss_dp_hal_get_gmac_ops(uint32_t gmac_type)
+{
+	return dp_global_ctx.gmac_hal_ops[gmac_type];
+}
+
+/*
+ * nss_dp_hal_set_gmac_ops()
+ *	Sets dp global gmac hal ops based on the GMAC type.
+ */
+static inline void nss_dp_hal_set_gmac_ops(struct nss_gmac_hal_ops *hal_ops, uint32_t gmac_type)
+{
+	dp_global_ctx.gmac_hal_ops[gmac_type] = hal_ops;
+}
+
+/*
+ * HAL functions implemented by SoC specific source files.
+ */
+extern bool nss_dp_hal_init(void);
+extern void nss_dp_hal_cleanup(void);
+extern void nss_dp_hal_clk_enable(struct nss_dp_dev *dp_priv);
+extern struct nss_dp_data_plane_ops *nss_dp_hal_get_data_plane_ops(void);
+
+#endif	/* __NSS_DP_HAL_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/include/nss_dp_hal_if.h

@@ -0,0 +1,162 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2016-2017,2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF0
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+#ifndef __NSS_DP_HAL_IF_H__
+#define __NSS_DP_HAL_IF_H__
+
+#include <linux/ioport.h>
+#include <linux/netdevice.h>
+#include <uapi/linux/if_link.h>
+
+enum gmac_device_type {
+	GMAC_HAL_TYPE_QCOM = 0,	/* 1G GMAC type */
+	GMAC_HAL_TYPE_SYN_XGMAC,/* Synopsys XGMAC type */
+	GMAC_HAL_TYPE_SYN_GMAC,	/* Synopsys 1G GMAC type */
+	GMAC_HAL_TYPE_MAX
+};
+
+/*
+ * gmac_hal_platform_data
+ */
+struct gmac_hal_platform_data {
+	struct net_device *netdev; /* Net device */
+	uint32_t reg_len;	/* Register space length */
+	uint32_t mactype;	/* MAC chip type */
+	uint32_t macid;		/* MAC sequence id on the Chip */
+};
+
+/*
+ * NSS GMAC HAL device data
+ */
+struct nss_gmac_hal_dev {
+	void __iomem *mac_base;	/* Base address of MAC registers	*/
+	uint32_t version;	/* GMAC Revision version		*/
+	uint32_t drv_flags;	/* Driver specific feature flags	*/
+
+	/*
+	 * Phy related stuff
+	 */
+	uint32_t link_state;	/* Link status as reported by the Phy	*/
+	uint32_t duplex_mode;	/* Duplex mode of the Phy		*/
+	uint32_t speed;		/* Speed of the Phy			*/
+	uint32_t loop_back_mode;/* Loopback status of the Phy		*/
+	uint32_t phy_mii_type;	/* RGMII/SGMII/XSGMII			*/
+
+	struct net_device *netdev;
+	struct resource *memres;
+	uint32_t mac_reg_len;	/* MAC Register block length		*/
+	uint32_t mac_id;	/* MAC sequence id on the Chip */
+	spinlock_t slock;	/* lock to protect concurrent reg access */
+};
+
+/*
+ * nss_gmac_hal_ops
+ */
+struct nss_gmac_hal_ops {
+	void* (*init)(struct gmac_hal_platform_data *);
+	void (*exit)(struct nss_gmac_hal_dev *);
+	int32_t (*start)(struct nss_gmac_hal_dev *);
+	int32_t (*stop)(struct nss_gmac_hal_dev *);
+	void (*setmacaddr)(struct nss_gmac_hal_dev *, uint8_t *);
+	void (*getmacaddr)(struct nss_gmac_hal_dev *, uint8_t *);
+	void (*promisc)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*multicast)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*broadcast)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*rxcsumoffload)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*txcsumoffload)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*rxflowcontrol)(struct nss_gmac_hal_dev *, bool enabled);
+	void (*txflowcontrol)(struct nss_gmac_hal_dev *, bool enabled);
+	int32_t (*setspeed)(struct nss_gmac_hal_dev *, uint32_t);
+	uint32_t (*getspeed)(struct nss_gmac_hal_dev *);
+	void (*setduplex)(struct nss_gmac_hal_dev *, uint8_t);
+	uint8_t (*getduplex)(struct nss_gmac_hal_dev *);
+	int32_t (*getstats)(struct nss_gmac_hal_dev *);
+	int32_t (*setmaxframe)(struct nss_gmac_hal_dev *, uint32_t);
+	int32_t (*getmaxframe)(struct nss_gmac_hal_dev *);
+	int32_t (*getndostats)(struct nss_gmac_hal_dev *,
+			    struct rtnl_link_stats64 *);
+	void (*sendpause)(struct nss_gmac_hal_dev *);
+	void (*stoppause)(struct nss_gmac_hal_dev *);
+	int32_t (*getssetcount)(struct nss_gmac_hal_dev *, int32_t);
+	int32_t (*getstrings)(struct nss_gmac_hal_dev *, int32_t, uint8_t *);
+	int32_t (*getethtoolstats)(struct nss_gmac_hal_dev *, uint64_t *);
+};
+
+extern struct nss_gmac_hal_ops qcom_hal_ops;
+extern struct nss_gmac_hal_ops syn_hal_ops;
+
+/**********************************************************
+ * Common functions
+ **********************************************************/
+/*
+ * hal_read_reg()
+ */
+static inline uint32_t hal_read_reg(void __iomem *regbase, uint32_t regoffset)
+{
+	return readl_relaxed(regbase + regoffset);
+}
+
+/*
+ * hal_write_reg()
+ */
+static inline void hal_write_reg(void __iomem *regbase, uint32_t regoffset,
+				 uint32_t regdata)
+{
+	writel_relaxed(regdata, regbase + regoffset);
+}
+
+/*
+ * hal_set_reg_bits()
+ */
+static inline void hal_set_reg_bits(struct nss_gmac_hal_dev *nghd,
+				    uint32_t regoffset,
+				    uint32_t bitpos)
+{
+	uint32_t data;
+
+	spin_lock(&nghd->slock);
+	data = bitpos | hal_read_reg(nghd->mac_base, regoffset);
+	hal_write_reg(nghd->mac_base, regoffset, data);
+	spin_unlock(&nghd->slock);
+}
+
+/*
+ * hal_clear_reg_bits()
+ */
+static inline void hal_clear_reg_bits(struct nss_gmac_hal_dev *nghd,
+				      uint32_t regoffset,
+				      uint32_t bitpos)
+{
+	uint32_t data;
+
+	spin_lock(&nghd->slock);
+	data = ~bitpos & hal_read_reg(nghd->mac_base, regoffset);
+	hal_write_reg(nghd->mac_base, regoffset, data);
+	spin_unlock(&nghd->slock);
+}
+
+/*
+ * hal_check_reg_bits()
+ */
+static inline bool hal_check_reg_bits(void __iomem *regbase,
+				      uint32_t regoffset,
+				      uint32_t bitpos)
+{
+	return (bitpos & hal_read_reg(regbase, regoffset)) != 0;
+}
+#endif /* __NSS_DP_HAL_IF_H__ */

feeds/ipq807x/qca-nss-dp/src/hal/syn_gmac_dp/syn_data_plane.c

@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include "syn_data_plane.h"
+#include "syn_reg.h"
+
+#define SYN_DP_NAPI_BUDGET	64
+
+/*
+ * GMAC Ring info
+ */
+struct syn_dp_info dp_info[NSS_DP_HAL_MAX_PORTS];
+
+/*
+ * syn_dp_napi_poll()
+ *	Scheduled by napi to process RX and TX complete
+ */
+static int syn_dp_napi_poll(struct napi_struct *napi, int budget)
+{
+	struct nss_dp_dev *gmac_dev = container_of(napi, struct nss_dp_dev, napi);
+	struct syn_dp_info *dev_info = &dp_info[gmac_dev->macid - 1];
+	int work_done;
+
+	/*
+	 * Update GMAC stats
+	 */
+	spin_lock_bh(&dp_info->stats_lock);
+	dp_info->stats.stats.rx_missed += syn_get_rx_missed(gmac_dev->gmac_hal_ctx);
+	dp_info->stats.stats.rx_missed += syn_get_fifo_overflows(gmac_dev->gmac_hal_ctx);
+	spin_unlock_bh(&dp_info->stats_lock);
+
+	syn_dp_process_tx_complete(gmac_dev, dev_info);
+	work_done = syn_dp_rx(gmac_dev, dev_info, budget);
+	syn_dp_rx_refill(gmac_dev, dev_info);
+
+	if (work_done < budget) {
+		napi_complete(napi);
+		syn_enable_dma_interrupt(gmac_dev->gmac_hal_ctx);
+	}
+
+	return work_done;
+}
+
+/*
+ * syn_dp_handle_irq()
+ *	Process IRQ and schedule napi
+ */
+static irqreturn_t syn_dp_handle_irq(int irq, void *ctx)
+{
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)ctx;
+	struct nss_gmac_hal_dev *nghd = gmac_dev->gmac_hal_ctx;
+
+	syn_clear_dma_status(nghd);
+	syn_disable_dma_interrupt(nghd);
+
+	/*
+	 * Schedule NAPI
+	 */
+	napi_schedule(&gmac_dev->napi);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * syn_dp_if_init()
+ *	Initialize the GMAC data plane operations
+ */
+static int syn_dp_if_init(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	uint32_t macid = gmac_dev->macid;
+	struct syn_dp_info *dev_info = &dp_info[macid - 1];
+	struct device *dev = &gmac_dev->pdev->dev;
+	int err;
+
+	if (!netdev) {
+		netdev_dbg(netdev, "nss_dp_gmac: Invalid netdev pointer %px\n", netdev);
+		return NSS_DP_FAILURE;
+	}
+
+	netdev_info(netdev, "nss_dp_gmac: Registering netdev %s(qcom-id:%d) with GMAC\n", netdev->name, macid);
+
+	if (!dev_info->napi_added) {
+		netif_napi_add(netdev, &gmac_dev->napi, syn_dp_napi_poll, SYN_DP_NAPI_BUDGET);
+
+		/*
+		 * Requesting irq
+		 */
+		netdev->irq = platform_get_irq(gmac_dev->pdev, 0);
+		err = request_irq(netdev->irq, syn_dp_handle_irq, 0, "nss-dp-gmac", gmac_dev);
+		if (err) {
+			netdev_dbg(netdev, "err_code:%d, Mac %d IRQ %d request failed\n", err,
+					gmac_dev->macid, netdev->irq);
+			return NSS_DP_FAILURE;
+		}
+
+		gmac_dev->drv_flags |= NSS_DP_PRIV_FLAG(IRQ_REQUESTED);
+		dev_info->napi_added = 1;
+	}
+
+	/*
+	 * Forcing the kernel to use 32-bit DMA addressing
+	 */
+	dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+
+	/*
+	 * Initialize the Tx/Rx ring
+	 */
+	if (syn_dp_setup_rings(gmac_dev, netdev, dev, dev_info)) {
+		netdev_dbg(netdev, "nss_dp_gmac: Error initializing GMAC rings %px\n", netdev);
+		return NSS_DP_FAILURE;
+	}
+
+	spin_lock_init(&dev_info->data_lock);
+	spin_lock_init(&dev_info->stats_lock);
+
+	netdev_dbg(netdev,"Synopsys GMAC dataplane initialized\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_open()
+ *	Open the GMAC data plane operations
+ */
+static int syn_dp_if_open(struct nss_dp_data_plane_ctx *dpc, uint32_t tx_desc_ring,
+					uint32_t rx_desc_ring, uint32_t mode)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct nss_gmac_hal_dev *nghd = gmac_dev->gmac_hal_ctx;
+
+	syn_enable_dma_rx(nghd);
+	syn_enable_dma_tx(nghd);
+
+	napi_enable(&gmac_dev->napi);
+	syn_enable_dma_interrupt(nghd);
+
+	netdev_dbg(netdev, "Synopsys GMAC dataplane opened\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_close()
+ *	Close the GMAC data plane operations
+ */
+static int syn_dp_if_close(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct nss_gmac_hal_dev *nghd = gmac_dev->gmac_hal_ctx;
+
+	syn_disable_dma_rx(nghd);
+	syn_disable_dma_tx(nghd);
+
+	syn_disable_dma_interrupt(nghd);
+	napi_disable(&gmac_dev->napi);
+
+	netdev_dbg(netdev, "Synopsys GMAC dataplane closed\n");
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_link_state()
+ *	Change of link for the dataplane
+ */
+static int syn_dp_if_link_state(struct nss_dp_data_plane_ctx *dpc, uint32_t link_state)
+{
+	struct net_device *netdev = dpc->dev;
+
+	/*
+	 * Switch interrupt based on the link state
+	 */
+	if (link_state) {
+		netdev_dbg(netdev, "Data plane link up\n");
+	} else {
+		netdev_dbg(netdev, "Data plane link down\n");
+	}
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_mac_addr()
+ */
+static int syn_dp_if_mac_addr(struct nss_dp_data_plane_ctx *dpc, uint8_t *addr)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_change_mtu()
+ */
+static int syn_dp_if_change_mtu(struct nss_dp_data_plane_ctx *dpc, uint32_t mtu)
+{
+	/*
+	 * TODO: Work on MTU fix along with register update for frame length
+	 */
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_set_features()
+ *	Set the supported net_device features
+ */
+static void syn_dp_if_set_features(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+
+	netdev->features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
+	netdev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
+	netdev->vlan_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
+	netdev->wanted_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
+}
+
+/*
+ * syn_dp_if_xmit()
+ *	Dataplane method to transmit the packet
+ */
+static netdev_tx_t syn_dp_if_xmit(struct nss_dp_data_plane_ctx *dpc, struct sk_buff *skb)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct syn_dp_info *dev_info = &dp_info[gmac_dev->macid - 1];
+	int nfrags = skb_shinfo(skb)->nr_frags;
+
+	/*
+	 * Most likely, it is not a fragmented pkt, optimize for that
+	 */
+	if (likely(nfrags == 0)) {
+		if (syn_dp_tx(gmac_dev, dev_info, skb)) {
+			goto drop;
+		}
+
+		return NETDEV_TX_OK;
+	}
+
+drop:
+	dev_kfree_skb_any(skb);
+	dev_info->stats.stats.tx_dropped++;
+
+	return NETDEV_TX_BUSY;
+}
+
+/*
+ * syn_dp_if_pause_on_off()
+ */
+static int syn_dp_if_pause_on_off(struct nss_dp_data_plane_ctx *dpc, uint32_t pause_on)
+{
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * syn_dp_if_get_stats
+ *	Get Synopsys GMAC data plane stats
+ */
+static void syn_dp_if_get_stats(struct nss_dp_data_plane_ctx *dpc, struct nss_dp_gmac_stats *stats)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct syn_dp_info *dev_info = &dp_info[gmac_dev->macid - 1];
+
+	spin_lock_bh(&dev_info->stats_lock);
+	netdev_dbg(netdev, "GETTING stats: rx_packets:%llu rx_bytes:%llu mmc_rx_crc_errors:%llu", dev_info->stats.stats.rx_packets,
+			dev_info->stats.stats.rx_bytes, dev_info->stats.stats.mmc_rx_crc_errors);
+	memcpy(stats, &dev_info->stats, sizeof(*stats));
+	spin_unlock_bh(&dev_info->stats_lock);
+}
+
+/*
+ * syn_dp_if_deinit()
+ *	Free all the Synopsys GMAC resources
+ */
+static int syn_dp_if_deinit(struct nss_dp_data_plane_ctx *dpc)
+{
+	struct net_device *netdev = dpc->dev;
+	struct nss_dp_dev *gmac_dev = (struct nss_dp_dev *)netdev_priv(netdev);
+	struct syn_dp_info *dev_info = &dp_info[gmac_dev->macid - 1];
+
+	if (dev_info->napi_added) {
+		/*
+		 * Remove interrupt handlers and NAPI
+		 */
+		if (gmac_dev->drv_flags & NSS_DP_PRIV_FLAG(IRQ_REQUESTED)) {
+			netdev_dbg(netdev, "Freeing IRQ %d for Mac %d\n", netdev->irq, gmac_dev->macid);
+			synchronize_irq(netdev->irq);
+			free_irq(netdev->irq, gmac_dev);
+			gmac_dev->drv_flags &= ~NSS_DP_PRIV_FLAG(IRQ_REQUESTED);
+		}
+
+		netif_napi_del(&gmac_dev->napi);
+		dev_info->napi_added = 0;
+	}
+
+	/*
+	 * Cleanup and free the rings
+	 */
+	syn_dp_cleanup_rings(gmac_dev, netdev, dev_info);
+
+	return NSS_DP_SUCCESS;
+}
+
+/*
+ * nss_dp_gmac_ops
+ *	Data plane operations for Synopsys GMAC
+ */
+struct nss_dp_data_plane_ops nss_dp_gmac_ops = {
+	.init		= syn_dp_if_init,
+	.open		= syn_dp_if_open,
+	.close		= syn_dp_if_close,
+	.link_state	= syn_dp_if_link_state,
+	.mac_addr	= syn_dp_if_mac_addr,
+	.change_mtu	= syn_dp_if_change_mtu,
+	.xmit		= syn_dp_if_xmit,
+	.set_features	= syn_dp_if_set_features,
+	.pause_on_off	= syn_dp_if_pause_on_off,
+	.get_stats	= syn_dp_if_get_stats,
+	.deinit		= syn_dp_if_deinit,
+};