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zoombini: Add support for S0iX.

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Additionally, add the PMIC_INT_L GPIO.

BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash modified image on npcx7_evb, verify that no
panics or asserts are hit.

Change-Id: I1b1c4c0f09b78adc9b45b828f318b537fcbcb58b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585574
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Aseda Aboagye
2017-07-25 12:40:12 -07:00
committed by chrome-bot
parent 61a80d620a
commit fdbce2bcf4
2 changed files with 3 additions and 0 deletions
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2
board/zoombini/board.h
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@@ -53,6 +53,8 @@
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_S0IX
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
#define CONFIG_UART_HOST 0
#define CONFIG_I2C_MASTER

1
board/zoombini/gpio.inc
View File

@@ -27,6 +27,7 @@ GPIO_INT(PCH_SLP_SUS_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt)
/* TODO(aaboagye): Internal PU may be needed later on... */
GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_DPWROK, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_INT_L, PIN(D, 5), GPIO_INT_FALLING | GPIO_PULL_UP, power_signal_interrupt)
/* Power Enables. */
GPIO(EN_PP3300_DSW, PIN(6, 0), GPIO_OUT_HIGH)