TPM NVMEM commits are reenabled as soon as the system boots into
Chrome OS. However, sometimes the device does not boot into Chrome OS,
in which case it is necessary to be able to reinstate NVMEM commits
explicitly.
The new vendor command will provide this functionality.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=added code to depthcharge to issue the new vendor command if the
system falls into recovery mode, verify that commits are
re-instated once the command is issued.
Change-Id: I3c06b27175751dc2c095911441935eee62ed9c50
Reviewed-on: https://chromium-review.googlesource.com/424064
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch eliminates NVMEM commits at system startup, namely between
the moment the TPM is reset and the moment the AP is trying to read a
PCR (which is an indication of the AP having booted into OS).
To avoid losing NVMEM changes in case TPM is reset before PCR Read
command is issued, pending changes (if any) are saved before TPM reset
is processed.
For the same reason TPM reset invocation is being added to the hard
reboot path; this will kick in when there is a restart after cr50
firmware update.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=with instrumented coreboot/depthcharge observed the following
execution times for various TPM command issued at startup
command 0x144, 15203 us
command 0x14e, 11814 us
command 0x182, 12461 us
command 0x182, 12456 us
command 0x138, 11503 us
command 0x138, 11512 us
command 0x14e, 14648 us
command 0x14e, 12597 us
command 0x121, 11353 us
which totals 113 ms and shaves more than 200 ms off the boot time.
Change-Id: Ic52309291fdb9c3ede96e0ad015ad9fc076bddc5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424063
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
In preparation to adding new features, switch cr50 to using shared
memory allocator allowing concurrently allocated buffers.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=verified that cr50 works fine and could be updated on a reef.
Change-Id: I87656cbd1f6d4928f25396dbcc59cc3f43984d85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424850
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new code allows to replace the existing one buffer at a time
shared memory facility with a malloc/free implementation. A new
configuration option is being provided (CONFIG_MALLOC).
The names of functions allocating and freeing memory are not being
changed to allow to switch between the two implementations seamlessly.
A double linked list of buffers is used to keep track of free and
allocated memory. During initialization the entire free memory block
is considered a single free buffer. No allocations/frees are allowed
from within interrupts. The control structures are protected by a
semaphore, so allocate and free invocation could be blocking.
A test is added which randomly allocates and frees memory, continuing
until all branches in the allocate and free functions are taken.
BUG=chrome-os-partner:
TEST=make buildall -j succeeds, which includes testing the new
malloc/free implementation.
Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to reduce build times during development, this change allows an
engineer to build a subset of all boards, writing the results for each
board into the ".failedboards" directory.
The expectation is that, while working on code that affects multiple
boards, the engineer will invoke "make build_boards BOARDS=<board-list>"
periodically to confirm that all affected boards still build.
Before pushing any code for review, however, the engineer is still expected
to run "make buildall" to ensure all boards still build and tests pass.
* Define a new make variable, BOARDS, whose default value is $(boards).
This variable can be overridden on the make command line or via the
environment. Its value must be non-empty.
* Use the BOARDS make variable to control which boards will be built by the
new "build_boards" and "try_build_boards" targets.
* Refactor the "buildall" target so that it depends on "build_boards". This
indirectly allows the boards built to be controlled via the BOARDS make
variable.
* Here are some make command lines that were used to test the behavior of
the change:
make -j buildall # Builds all boards, runs tests.
make -j build_boards # Builds all boards, doesn't run tests.
make -j build_boards BOARDS="cr50 reef" # Builds cr50 and reef boards
make -j build_boards BOARDS= # Fails due to empty BOARDS.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I833277842e5e20d86eaa90df6457264a2f86a3fa
Reviewed-on: https://chromium-review.googlesource.com/420110
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
ISL9237 and ISL9238 are almost identical, with few register changes,
let's make the driver generic, to support both chargers.
BRANCH=none
BUG=chrome-os-partner:61166
TEST=make buildall -j
Change-Id: I029894dd62ab7e45897d877289707ee8c1ff1d09
Reviewed-on: https://chromium-review.googlesource.com/422197
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This error code is used to indicates the data has not changed.
Motion sense task will therefore not add any entry in the sensor FIFO.
BUG=chrome-os-partner:59423
TEST=make -j buildall
BRANCH=reef
Change-Id: I58b9be5675d8949bd682d8c89dadea1dfff9bf2e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424856
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If there's a task switching occurred between loading waiter and
unlocking the lock, the task with higher priority won't wake up since
the local variable, waiter, doesn't contain its ID bit before task
switching. In this situation, the higher priority task only can be
awakened when the other tasks execute mutex_unlock() again.
But consider the following conditions: (For example, the driver of
charger bd9995x.)
1. There are more than one mutex for the usage path of i2c port.
2. There are more than one task access this usage path of i2c port and
one of these tasks, task A, met the situation above.
3. The other tasks have no chance to execute mutex_unlock() of i2c since
the task A still occupied the mutex of charger.
All the tasks used the same i2c port or the other hardware will sleep
forever. This CL makes loading waiter and unlocking the lock as atomic
to solve this issue.
BRANCH=none
BUG=chrome-os-partner:60617
TEST=make BOARD=snappy; make BOARD=oak; Executed charger factory test on
4 units of snappy for 3 days and no symptom occurred.
Change-Id: Id976fc47955b33ca83bb2182b197d9f2781c341b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/423285
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We need 2 accelerometer for tablet mode. If one of them is not working,
disable tablet mode. We will stay in clamshell mode, lid angle will be
always unreliable.
BUG=chrome-os-partner:61141
TEST=On kevin with a single sensor. Check we are in clamshell mode
when rebooting the EC.
BRANCH=kevin
Change-Id: I7bf6cdc9d85370fce20e5183622b4bc18f4f5f99
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix issue where the block is calculated wrong since the offset that gets
added is wrongly EEPROM_BLOCK_COUNT_PSTORE which is the number of
total blocks rather than the starting block given by
EEPROM_BLOCK_START_PSTORE.
TEST=Build test, ran on board with stubbed out functions.
BUG=none
BRANCH=none
Change-Id: Ide4839845353c2b9f95a37eb689c8d800169bb22
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/424182
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF flags but it
does not deassert IRQ1 when already asserted. To make sure IRQ1 will
also be deasserted need to emulate a host read.
Modified drivers:
1. lpc.c: emulate a host read to clear OBF and deasserted IRQ1.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; Run FAFT items related to Power on/off, reboot,
and keyboard on Wheatley.
Change-Id: Ibf0ff3b8a4eeece853916e4e19d67fcc7ae2e989
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419909
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow reef setting.
discharges on AC till the charger is detected and settled but
when booting from the cut-off mode this will kill the power hence
do not discharge on AC when battery is still waking up and settled.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I09d8f5a363d20bb3d0df80694de52ae3a37a0ed9
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/422621
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added common code for charger profile override for fast charging.
Fast charging configs can be defined in the respective board battery
file and use the common code for imposing the custom data.
BUG=chrome-os-partner:59393
BRANCH=none
TEST=Enabled the config on Reef. Manually overrode the temperature
and voltage. Observed correct charge profile config is selected
for each tests.
Change-Id: I075d271258470b98d38e4d5395d749469d3fd469
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407928
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code that referenced these structure definitions was removed
months ago. GCC 6.2 warns about the structures being definte but
not used.
BRANCH=none
BUG=none
TEST=Build tested only
Change-Id: I68de7cc351667b3fb51aa9004dfc86d936f4a9cc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424432
Reviewed-by: Shawn N <shawnn@chromium.org>
- Enable keyboard backlight configuration option so the keyboard backlight
interface is present.
- Enable interrupt on both directions for volume buttons, otherwise we
see the press but not the release.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=manual testing on P1 board
Change-Id: If0b6a913bb63f31051ab5a30ffe9f0682550e058
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/424493
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add support for the Texas Instruments TMP112 I2C temperature
sensor. The sensor provides a single temperature value.
BUG=none
BRANCH=none
TEST=Ran 'temp' console command over and over. Verified values with
digital thermometer.
Change-Id: Ida4c082309d245c3f7c6282ecea74ce5af746e43
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/418488
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The EC attempts to limit USB ports to 1.5A if a device is plugged
into both ports, but this ends up with no power to the ports instead.
Until this can be debugged with the right equipment just pretend we
can do 3A to both ports so factory tests can pass.
BUG=chrome-os-partner:61431
BRANCH=none
TEST=plug device into both ports on P1 board and see that they work
Change-Id: Icd4430d0026dc323e56b7ce88b9d8e79e6e825c5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/424453
This is a purely cosmetic patch making it easier to maintain the list
of test in the ec tree.
BRANCH=none
BUG=none
TEST=make buildall -j succeeds
Change-Id: I2f0407c99776ad9d66445ea177a707bdfaa9b815
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424175
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The common/system.c:system_usable_ram_end() function is used to
determine how much room there is available for shared memory. This
assumes that the jdata container is located at the top of SRAM right
below the panic data buffer.
This correct for embedded mode, but when building for host, panic
structure is allocated in a different memory block, not necessarily
adjacent to the __shared_mem_buf array. This leads to incorrect
calculations of the available shared memory amount.
Let's make sure the two memory blocks are adjacent, this way the
available memory calculations are accurate.
BRANCH=none
BUG=none
TEST=verified that
make runtests -j
succeeds, including the new test for malloc/free from shared memory
(coming up in the next patch).
Change-Id: I1fdba0512ac5a85b113a8284216c8b00f1564a94
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424176
Reviewed-by: Randall Spangler <rspangler@chromium.org>
last_collection is used for sensor in forced mode to be sure we are not
calling the read routine too often. We should update last_collection even
when the reading fails, and not on the interrupt path.
For sensors that support interrupt, the new timing diagram is:
/-------- data rate period ---------\
--------------+------------------------------------+-----------------> t
| /\
read (sample request) |
| Interrupt (sample available)
\/ |
sensor
BUG=chrome-os-partner:59423
BRANCH=reef
TEST=Check the ALS read is not called too often even when the sensor
reports an error because the read value is not changed.
Change-Id: I2def7bbd5227cf373c1f613c9b70bc6215861008
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424222
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CL/385081 was incorrect, MAX should be used instead of MIN when calculating
the oversampling factor, to be sure it can't be 0.
BUG=b:27849483,chrome-os-partner:59423
BRANCH=reef
TEST=Using a special firmware on Reef reporting the ALS in motionsense,
check that oversampling is 1 when requested frequency is 5Hz while the
maximal frequency supported is 1Hz.
Check the ALS sensor reports information to ARC++.
Change-Id: I3c2d447bbc3a9ca0a5963aa86d5a24ee87ca6ab6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424221
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For oak, set a different list of task (no als, no accel) for compiling
revision 4 or less. Fix GPIO include issue.
BUG=chrome-os-partner:59423,chrome-os-partner:59084
TEST=compile for oak with board 4 and 5, tested on Reef.
BRANCH=kevin,reef
Change-Id: I09051a69cbad6d477a7b3bf9907f4c5c144b5136
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424220
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some board (kevin), use BOARD_KEVIN variable to specify the task list.
We need this variable to be provided to CPP when generating _tsk_lst.
BUG=chrome-os-partner:59423
TEST=Check with
echo "CONFIG_TASK_LIST" | arm-none-eabi-cpp -P -Iboard/kevin \
-D"TASK_NOTEST(n, r, d, s)=n" -D"TASK_ALWAYS(n, r, d, s)=n" \
-DBOARD_KEVIN=y -imacros ec.tasklist
That the proper task list is generated.
BRANCH=kevin,reef
Change-Id: I40fbe3040c98c2698221b52aaadaf5519da13312
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424219
Reviewed-by: Randall Spangler <rspangler@chromium.org>
sensor private structure for bmi160 and bmp280 were defined
in the drivers themselves. It worked because there was only one
instance of each sensors on a board. However, this is an error it
should be in board files, as it was done for other sensors like the kionix.
BUG=none
TEST=buildall.
BRANCH=kevin,reef
Change-Id: Ica3aba358d141a7df9a3e97251d4c1e520cbf2c8
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424218
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The function usb_power_map_error() is only called from a single
location, with a fixed value passed in, and the return value, which
is the only reason for the function, is ignored.
The whole thing is useless, so remove the function and call. Since the
sizes of all platforms are unchanged before and after removing this, I
suspect it was getting optimized out anyway.
Fixes coverity warning 157563: Useless call
BUG=None
BRANCH=None
TEST=build tested only.
Change-Id: Ie6572d2f5579819f06a53a567e1a93aabca217db
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418070
Reviewed-by: Shawn N <shawnn@chromium.org>
With expanding USB interface to processing vendor commands and to
query current version running on the chip, there are now occurrences
of fw_upgrade_complete() invoked at the device startup without actual
data transfer.
This causes clearing rollback counter before it is actually examined.
Let's not invoke fw_upgrade_complete() unless there was actual data
transferred for flash programming.
BRANCH=none
BUG=none
TEST=verified on chromebook reboots that the counter value is not
changed until the rollback condition is checked.
Change-Id: I50bf450882b001ba1c2f38657d27f87f8596b3e2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422454
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Perform PKCS1-padding-only signing for RSASSA if hashing algorithm is
TPM_ALG_NULL.
This feature is guarded by SUPPORT_PADDING_ONLY_RSASSA macro in
tpm2/Implementation.h.
BUG=chrome-os-partner:60967
BRANCH=none
TEST=On a unowned machine with TPM2: corp enroll, login, install
a network certificate (gECC or GMC), then:
a) retrieve the public key from the installed certificate
LIBCHAPS=`ls /usr/lib**/libchaps.so`
CERTID=`pkcs11-tool --module=$LIBCHAPS --slot=1 --type=cert \
-O | grep "ID:" | awk '{print $2}'`
pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID \
--type=cert -r > /tmp/cert
openssl x509 -inform der -pubkey -noout -in /tmp/cert > /tmp/pub.key
b) sign a sample text using the private key for the certificate and
MD5-RSA-PKCS mechanism, not supported by TPM2_Sign command:
echo "ABCDEF" > /tmp/1.txt
pkcs11-tool --module=$LIBCHAPS --slot=1 --id=$CERTID --sign \
-i /tmp/1.txt -o /tmp/1.sig -m MD5-RSA-PKCS
c) verify signature:
openssl dgst -md5 -verify /tmp/pub.key \
-signature /tmp/1.sig /tmp/1.txt
Step (b) should succeed and step (c) should return "Verified OK".
Change-Id: I0d7a11c48cdb04e37748f7255b98e9e023481a96
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420854
Reviewed-by: Darren Krahn <dkrahn@chromium.org>
This change takes away control of trackpad from EC entirely. This will
prevent EC from interfering with the OS's interaction with the trackpad
for firmware update, device detection at boot, or entering S3.
Disadvantages are the trackpad will stay on (thus can wake up the system
unintentionally) when the system enters S3 in laptop mode then
transitions to tablet mode, or vice versa: the trackpad will stay off
(thus cannot wake up the system) when the system enters S3 in tablet mode
then transitions to laptop mode.
However, these corner cases can be handled by waking up the system upon
mode transition. The OS can then disable or enable the trackpad depending
on the transition direction (laptop <-> tablet) and re-enters S3. Or the
OS can leave the system running because mode transition implies a user's
intention to start interacting with the device.
The keyboard will continue to be managed by EC and disabled or enabled
upon mode transition.
BUG=chrome-os-partner:61058
BRANCH=reef
TEST=Put device into S3 in tablet mode. Wake it up.
Change-Id: I2f4aa72d704c6562dd861b105225b1995226a09a
Reviewed-on: https://chromium-review.googlesource.com/421275
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables accels in S3. Accels are required to calculate a
lid angle. EC enables/disables keyboard based on lid angles. EC
needs to be able to control it because the kernel is in sleep state
in S3.
BUG=chrome-os-partner:58792
BRANCH=reef
TEST=lid angles are calculated correctly in S0 and S3.
Change-Id: I13c69a47da2c6521cd0c03c66cf061deb3f4fabd
Reviewed-on: https://chromium-review.googlesource.com/421276
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The CONFIG_FLASH_NVMEM option implements persistent, reliable storage
regions in flash. This adds CONFIG_FLASH_NVMEM_VARS, which uses one of
those storage regions for free-form variables.
Refer to the comments in include/nvmem_vars.h and common/nvmem_vars.c
for usage and implementation details.
BUG=chrome-os-partner:61107
BRANCH=none
TEST=make runtests
This CL includes a number of new tests, specifically for this feature.
No target boards use this feature yet so there's nothing to test on
actual hardware, but the test/nvmem_vars executable includes console
commands ("get", "set", "print") to try it out.
Change-Id: I8597415dc3b00a1462f5b164eeb5073129030525
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414194
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Provide the calling stubs for p256 sign, verify, point mul, etc.
This also drops third_party/cryptoc/p256_ec and p256_ecdsa from the
image. And fewer routines from cryptoc/p256.c remain as well.
BRANCH=none
BUG=none
TEST=tcg_tests pass, test/tpm_test/tpmtest.py pass
Change-Id: Ib6c35f5d34a2c8434e78b44cbef8b69802734c50
Signed-off-by: Marius Schilder <mschilder@google.com>
Reviewed-on: https://chromium-review.googlesource.com/422942
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Trybot-Ready: Marius Schilder <mschilder@chromium.org>
After every reboot, we were resetting the write protect and console
lock states back to default. With this change the wp and lock states
will be preserved through deep sleep. They will still be reset on any
other type of reboot (like Power On reset or panic).
The states are also cleared if the system detects a rollback even when
booting from the deep sleep.
With this patch it is going to be impossible to remove hardware write
protection guarding writes into AP and EC firmware flash, unless the
cr50 console is unlocked.
Locking the console would reinstate hardware write protection
automatically even if it was disabled when the console was unlocked.
Two long life scratch register 1 bits are used to keep the console and
write protect states over resets. To make code cleaner bitmap
assignments of the long life scratch register is put in its own
include file.
BUG=chrome-os-partner:58961
BRANCH=none
TEST=manual
On prod/dev images verify that the default wp and console lock
states are still correct.
change the lock and write protect states from the default and
verify they are preserved through deep sleep.
reboot cr50 and make sure that they are reset.
unlock the console and enable flash writes, then set fallback
counter on cr50 to the value of 6 (rw 0x40000128 1; rw
0x4000012c 6) and put the AP into deep sleep by hitting
Alt-H-VolUp.
In five minutes press the power button on the device to bring
it back from s5. Observe cr50 fall back to an older image and
console lock and wp disabled.
Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- CHG port can connect as SNK at different voltage levels
- DUT port presents as SNK only
- DUT port uses fixed polarity since it has a fixed cable
- Not supporting ALT or ALT_DP modes in terms of svdm messages at
this point.
- No support yet for USB mux.
BUG=chromium:571476
BRANCH=None
TEST=Manual
CHG port: Tested with Zinger and Plankton and 5/12/20V VBUS levels.
DUT port: Tested against Reef and verified that port reached SNK_READY.
Change-Id: Idbdc963ba077a14efad9eea3b047f35a5a605bd6
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/419117
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When including USB PD support, the image won't fit in the default RO
size of 0xf000, but does fit in the 0x10000 RW. This change removes
PSTATE and increases the RO to 0x10000.
BRANCH=none
BUG=chrome-os-partner:61170
TEST=manual
Verfied the image still builds and can run after updating via
util/flash_ec and via /usb_updater/fw_update.py -b servo_v4.json
Change-Id: I8f60bb1f107060e26390e6c8292a3add58703c0d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422450
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Auto-role toggle on the anx74xx does not function correctly with
e-marked cables and cannot be used.
Also check for TCPC support for auto-toggle at runtime, to allow
auto-toggle supported TCPC to be used alongside an unsupported part.
(from CL:420405)
BUG=chrome-os-partner:60890
BRANCH=reef
TEST=Manual on reef, boot to S0:
`pd 0 state`: Toggling between SRC_DISCONNECTED / SNK_DISCONNECTED
`pd 1 state`: DRP_AUTO_TOGGLE
Also verify port 0 can become sink + source correctly in S0.
Change-Id: Iafdedf31773feef23923cefe1f4fb02fcffda120
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420866
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are plans to extend use of the LONG_LIFE_SCRATCH1 register for
other purposes than keeping board properties. Just as the board
properties, the new use is also very board specific. This patch moves
the board properties code from chip/g to board/cr50, where it belongs.
Instead of reading board properties bitmap and checking if various
bits are set, api functions are now provided to allow determining
various properties settings without actually looking at the properties
bitmap.
CQ-DEPEND=CL:*313057
BRANCH=none
BUG=chrome-os-partner:58961
TEST=verified that both Gru and Reef boot with the new image,
additionally, on Reef confirmed that it is possible to
communicate with the H1 over USB, and that plt_reset signal is
handled properly.
Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547
Reviewed-on: https://chromium-review.googlesource.com/422081
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Since ec doesn't support old-style host command, this CL removes
unsupported parts in npcx's lpc driver and lets the hand-shaking
mechanism between host and ec as easy as possible. It makes sure only
following conditions that ec can clear processing bit of host command.
1. Received LRESET signal.
2. In lpc_init() initialization function caused by sysjump.
3. If command is valid, it will be cleared in lpc_send_response_packet()
called by host command task.
4. If command is invalid, it will be cleared in lpc_send_response()
after the response package is ready.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; do stress test on wheatley.
Change-Id: I53d17fd9e09b7fb080e4bf71437392bf43db6258
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/422707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We use the latest nde32 official toolchain to verify the bug of
GP-related instruction was fixed (we can remove "-mno-gp-direct" flag to
save code space), and code optimization.
We got some error on official toolchain, so we fix them as well:
- "break" instead of "trap".
N8 CPU does not support "trap" instruction to generate an unconditional
trap exception, but no error occurred while compiling by using current
GCC toolchain (this will trigger a reserved instruction exception,
so "ASSERT()" still work).
We use "break" to generate a exception in this change.
- "li" instead of "la".
To fix the error: "Error: la must use with symbol".
Also fix:
- The "_bss_start" has to be word-aligned because we use "lwi" instruction
to load a word from the memory into the general register.
BRANCH=none
BUG=none
TEST=1. console command "crash assert".
2. check registers settings: f02030h, f0203eh, and f02044h.
Change-Id: I33404a1d60eeebfa135bf43d3a7d5e73ab35c678
Reviewed-on: https://chromium-review.googlesource.com/422608
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The earlier change introduced the uninitialized variable bug, which
was not caught by the compiler.
Let's make sure the variable is always initialized, and also let's add
a message informing the user that the binary image is ignored when -f
or -c command line options are given.
BRANCH=none
BUG=chrome-os-partner:55667
TEST=there is no accidental attempts to erase the inactive firmware
any more. The message is printed when the binary image is ignored.
Change-Id: If67841fa3933e7c2df772348ed5308ff722a6e3a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421498
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The idle task on g devices seems to be very close to its stack
capacity. Adding debug code, print statements, etc., causes occasional
stack overflow panics.
Let's increase the stack size to avoid these problems.
BRANCH=none
BUG=none
TEST=the stack overflow panics do not happen anymore when debug
processing on the idle task context is added.
Change-Id: Id259719c1b644e2743f3bb3dbf0d99d667662901
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422078
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Battery need some time to provide power when releases
shipping mode or plug in battery at first time.
BUG=chrome-os-partner:60921, 59904
BRANCH=master
TEST=remove battery & AC, then insert battery & AC,
system can boot up.
Change-Id: I33ca4df54e0b02e68ade9426864561dae8c57851
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/419881
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If VBUS is lost and then quickly recovers, we may detect the re-presence
of the charger before charge_ramp has been informed about the loss. In
this case, charge manager's supplier registration time will precede our
ACTIVE_OC_INFO timestamp. Fix our timestamp comparison to correctly
detect OC in this case.
In addition, correctly mark all OC events stale once we have encountered
a disconnect / reconnect that we determine not to be related to OC.
BUG=chrome-os-partner:56367
TEST=Manual on reef, verify Motorola 800mA DCP charger settles at ~800mA
after OC.
BRANCH=reef
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3fdfd3929d07c60b82655999dd5aa731c1c7bc9b
Reviewed-on: https://chromium-review.googlesource.com/419775
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 19ba4a053027486ca415c4d703944b38e3c5e652)
Reviewed-on: https://chromium-review.googlesource.com/421208
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
