Commit Graph

26 Commits

Author SHA1 Message Date
Vijay Hiremath
f543a8e798 glkrvp: Switch from NPCX5 EC to NPCX7 EC
BUG=b:68987606, b:72483287
BRANCH=glkrvp
TEST=GLKRVP can boot to OS

Change-Id: If4b99ca60005b97c59a1d8dc16c4065af63d34d8
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/750365
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30 09:02:13 -08:00
Shamile Khan
0348eb1059 glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMI
BUG=None
BRANCH=None
TEST=GLKRVP can boot to OS when a coreboot image with eSPI
     enabled is flashed.

Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/818196
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2018-01-16 21:26:27 -08:00
Divya Sasidharan
bc8fda9e0f glkrvp: Enable discharge on AC config
This CONFIG DISCHARGE_ON_AC enables discharging
battery even when AC is connected.

BUG=b:71364739
BRANCH=glkrvp
TEST=On glkrvp EC console, execute command
     "chgstate discharge on" and verify if battery
     is discharging with "battery" command.

Change-Id: I709c7b5ccfea9058961d387a1575db9aebe70707
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
2017-12-28 14:50:30 -08:00
Divya Sasidharan
d41766df11 glkrvp: Fix hibernate <sec> to allow wakeup from hibernation
Issue was found when EC would not wake up from hibernate after
specified time period.

The infinite while loop blocks further hibernate functions
that needs to be executed after the board specific
hibernate method.
Remove this while loop to complete hibernation logic.

Also in hibernate function we should not be cutting down power
to EC (SMC_SHUTDOWN) as this will limit supporting wake sources
feature. Removing it in this patch.

BRANCH=master
BUG=b:70690772
TEST=On glkrvp EC console, check if "hibernate 30" wakes up EC
     after 30 sec, with only battery, only AC, with AC+battery.

Change-Id: Iae735cc26eeef8e205771d2f3c6e5260918e093e
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
2017-12-28 14:50:29 -08:00
Daisuke Nojiri
26b4617c43 charge_manager: Add EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT
Usually, the max current and supply voltage of dedicated chargers
are not known to the EC.

This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
allows the host to change the max current and supply voltage of the
dedicated charge port.

BUG=b:64442692
BRANCH=none
TEST=make runtests && buildall. Boot Fizz and let coreboot set
the adapter current and voltage.

Change-Id: I29b3f5762f8b316ca363c23e230530cdf4ca207a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/769152
2017-11-28 10:22:27 -08:00
Aseda Aboagye
34a97f50d5 buttons: Make buttons[] common.
Nearly every board had a buttons array defined in which its contents had
the standard volume buttons.  This commit creates a single common
buttons array that can contain the standard volume buttons and recovery
buttons.  If a board has volume up and down buttons, they can simply
define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with
the standard definition.  The buttons are active low and have a 30 ms
debounce period.  Similiarly, if a board has a dedicated recovery
button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the
buttons array with a recovery button.

BUG=chromium:783371
BRANCH=None
TEST=make -j buildall.
TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume
buttons still work.

Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/773794
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-11-17 20:18:38 -08:00
Vijay Hiremath
cab93b613b glkrvp: Allow system to boot using DC Jack
There are two Type-C ports and a DC Jack on GLKRVP. Added code
to allow system to boot from DC Jack also. This helps to boot
the device without Type-C connector during early stage of
software development.

BUG=b:69005234
BRANCH=glkrvp
TEST=GLKRVP can boot to OS without battery and DC Jack attached.
     Also VBATA is set to battery voltage max.
     When DC-Jack is present Type-C port is not enabled and
     vice-versa.

Change-Id: I0fe5631c40490c56fba6ed5f3ad7ba7f5248460a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/757874
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-11-10 09:16:35 -08:00
Vijay Hiremath
ee7716b544 GLKRVP: Enable low power idle mode
BUG=b:67782644
BRANCH=glkrvp
TEST=Make buildall -j

Change-Id: I89eae439c7adebf9abdec7620f5b126aab48b9a4
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/719975
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-17 00:33:12 -07:00
Vijay Hiremath
08210d0a34 GLKRVP: Enable verified boot support
BUG=b:67780603
BRANCH=glkrvp
TEST=EC console command 'hash' can print the vboot hash
     calculated values.

Change-Id: I3d9efa7b6c57f8a862676929a1af9ae21b5c9b2d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/719881
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-17 00:33:11 -07:00
Vijay Hiremath
b2d6bf0ada GLKRVP: Correct GPIO assignment for PCH_WAKE_L
BUG=b:67797598
BRANCH=glkrvp
TEST=In S3, toggling PCH_WAKE_L wakes system to S0.

Change-Id: If4d6786d8b24488c11f7894499c7e19f43a9b7f8
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/719486
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-10-16 14:14:04 -07:00
Shawn Nematbakhsh
286b800f14 pd: Move *_set_input_current() to common code
Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.

BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2017-10-05 21:24:46 -07:00
Furquan Shaikh
04db902fee intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exit
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.

BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.

Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-10-03 17:28:28 -07:00
Furquan Shaikh
a27f1049b6 power: Add flags parameter to power_signal_info
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.

Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.

BUG=b:65421825
BRANCH=None
TEST=make -j buildall

Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2017-10-03 14:26:09 -07:00
Shawn Nematbakhsh
c781609bfd charge_manager: Support no-BC1.2 configuration
If BC1.2 isn't supported, don't waste space + time checking for inputs
that don't exist.

BUG=chromium:759880
BRANCH=None
TEST=`make buildall -j`

Change-Id: I47e81451abd79a67a666d1859faf2610ee5c941a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/663838
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-09-28 11:18:54 -07:00
Shawn Nematbakhsh
dde1a514de pd: Remove support for debug accessories that provide VBUS + Rd
Reworked suzy-q and suzy-qable all provide Rp, so there is no need for
special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS
is no longer relevant, since we no longer take special action when VBUS
is seen without Rp.

BUG=chromium:737755
BRANCH=None
TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5.
Also, verify zinger works in S5 on reef.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec
Reviewed-on: https://chromium-review.googlesource.com/656067
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2017-09-11 11:14:23 -07:00
Vijay Hiremath
1623f192e8 GLKRVP: Enable Volume buttons
BUG=b:65461918
BRANCH=glkrvp
TEST=Volume button notification can scroll in the UI.

Change-Id: I9229e0fd0613bd672eff22e4cc087ad447d8d795
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/656530
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 15:05:14 -07:00
Scott Collyer
6d286d157c battery: Check physical battery presence before inhibiting power
In order to satisfy factory testing requirements we need to
boot a bare board with just an AC adapter without requiring
a power button.

However we also don't want to always allow booting of the
battery is present but cut-off (which will indicate BP_NO so
we can't use the existing battery_is_present function) or has
critically low level as it may not immediately boot.

To accomplish this add a function that allows the board to
specify a custom "hardware presence" for the battery that is
separate from the battery presence check.

This CL is taking a change done for Eve and pulling into TOT so it can
be used for other projects that have the same
requirements. https://chromium-review.googlesource.com/c/582544

BUG=b:63957122
BRANCH=none
TEST=manual

Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627113
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 21:17:22 -07:00
Divya Sasidharan
577a741855 glkrvp: Enable USB MUX PS8743 driver
Add Parade PS8743 USB Type-C Redriving Switch for USB Host /
DisplayPort.

BUG=b:64598680
BRANCH=glkrvp
TEST=On glkrvp,
     Connect Apple dongle and verify mux setting with i2c read.
     1. i2cxfer r 1 0x20 0 -> 0x50 (DP/USB enabled)
     2. flip i2cxfer r 1 0x20 0 -> 0x54 (Flip bit enabled)
     Connect pluggable and verify the same.
     Similar testing was successful on second type-c port.

Change-Id: I96ec380024eb659e071b019dd58b3c640fa1cc03
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/616075
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-21 22:03:53 -07:00
Vijay Hiremath
309289df45 glkrvp: Enable TCPC using NXP PTN5110 AIC
BUG=b:64531818
BRANCH=glkrvp
TEST=TCPC can negotiate to 20V & 2.25A

Change-Id: I16510a510133bbb1827634303a6b9d02dec4bbc6
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/614311
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-21 22:03:53 -07:00
Vijay Hiremath
97fe22e8d5 glkrvp: Enable switches
BUG=b:64491401
BRANCH=glkrvp
TEST=mmapinfo is updated when lidopen & lidclose are performed
     SCI/SMI gpios toggle

Change-Id: I93f1ae2cc8dbc389b3e870b49d5ee2bfff503451
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/606892
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-11 14:36:18 -07:00
Vijay Hiremath
76a64e7c82 glkrvp: Enable S0iX support
BUG=b:64559696
BRANCH=glkrvp
TEST=EC console command powerindebug shows correct GPIO info

Change-Id: Iee346f61bc0a0b26d612d2966350d308be596592
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/610304
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-10 15:39:51 -07:00
Vijay Hiremath
5dc101be09 glkrvp: Enable board version identification
BUG=b:64491133
BRANCH=glkrvp
TEST='version' works on EC console.

Change-Id: I7ed56870ec8fa817d55ab8acb362761c99f5bb29
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/606893
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-10 12:26:42 -07:00
Vijay Hiremath
8bfde69fdd GLKRVP: Enable fast charging and battery cut-off
BUG=b:64452259
BRANCH=glkrvp
TEST=Fast charging & battery cut-off works

Change-Id: Ica19ed11891ef5ac8b37140a5fcbb311333d5b5a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/604732
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-08 17:34:10 -07:00
Vijay Hiremath
045e3340d9 glkrvp: Enable charger & smart battery
GLKRVP uses ISL9238 Charger & SMP-CA-445 Smart Battery.

BUG=b:64452259
BRANCH=glkrvp
TEST=EC command 'charger' & 'battery' work.

Change-Id: I41adf9bc3264a64850a3f609e7529c2d51df88d0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/604731
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-08 17:34:09 -07:00
Vijay Hiremath
fc3beea4e9 GLKRVP: Control PMIC enable & disable from EC
By default PMIC is always on GLKRVP. Added code to enable & disable
the PMIC according to GLK power sequencing steps.

BUG=b:64394037
BRANCH=glkrvp
TEST=Reboot & Cold reset work

Change-Id: I3d7692f1ca8cb5e92e68eaf5bb37a826119300fd
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/603988
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
2017-08-07 22:18:49 -07:00
Vijay Hiremath
3bd19634bb Intel GLK-RVP: Add initial board bringup code
Added bare minimum code to bringup the Intel GLK-RVP using
Nuvoton AIC.

BUG=b:64394037
BRANCH=glkrvp
TEST=Intel GLK-RVP2.0 boots to Chrome OS using Nuvoton AIC.

Change-Id: I86816d09fe428091438a16f014e23b2e0c0025b7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/602515
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
2017-08-07 22:18:49 -07:00