This allows the acpi_light sysfs entry to be populated with the actual
ALS data.
BUG=b:70290036
BRANCH=None
TEST=Flash meowth; read both illuminance values for the ALS devices
under iio and verify that they are both operational.
Change-Id: Ia22633629195d5bdeedc70a908ceca1411110b7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/888218
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is used by the keyboard backlight driver. Add support so we can
start talking to this chip.
BUG=b:69379749
BRANCH=none
TEST=i2cscan shows a device at 0x6c on bus 4 now
Change-Id: I951ecd0fa3030f9f408ed0a4504b54950b7ca174
Signed-off-by: Benjamin Gordon <bmgordon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879081
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit enables support for reviving a battery from disconnect while
also providing the code to detect if the batteries are disconnected or
not. The disconnection code behaves similarly to some other battery
packs used in Chromebooks.
BUG=b:71515229
BRANCH=None
TEST=Flash zoombini; cut off battery; apply AC and verify that we do not
leave safe mode until the battery is no longer "disconnected".
TEST=Repeat above test for meowth.
TEST=Cutoff the battery and apply AC and verify that board wakes up from
cutoff.
Change-Id: I52fe91bd6522901671ad5a302bfa0ca27e5f5aa0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/864830
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
These boards are using the OPT3001 ALS. Enable the drivers for them as
well as the motionsense stack.
BUG=b:70290036, b:69140267
BRANCH=None
TEST=Flash meowth and zoombini; verify that they still boot okay.
Change-Id: Iddbf0af5cc01973999703de4a75ad461bc6a025f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/833168
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The boards need to have 5V masked off from the power good tree.
Additionially, Meowth needs to have the COMP_C fault masked from the
fault mask because its enable is connected and not grounded like on
Zoombini.
BUG=b:69935563
BRANCH=None
TEST=flash zoombini; Verify that we can boot to S0.
Change-Id: Ia51004a131e7c31d0e5ee59d87ab13455b822779
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807632
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added code to support port 1 and 2 power path controller
since we didn't have the parts on rev 0.
BUG=None
BRANCH=None
TEST=make board=zoombini, make board=meowth
TEST=Make sure Zoombini can charge in on all ports.
TEST=Make sure Zoombini can charge out on all ports.
Change-Id: Idf174125cc5a617ad77378ce65d5c0f6cbb9fce4
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/823211
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In gpio.inc, fixed EN_PP3300_WLAN so it's always high
since CNVi requires PP3300_WLAN power up at the same
time as PP3300_A.
Also, fixed USB_PD_RST_L to be an OD output.
BUG=b:69139536
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: I3c2a4e7ca7b1ab5f9122d17324822dc5e61e70a8
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/778120
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BUG=None
BRANCH=None
TEST=Flash zoombini; Plug in a PD sink, verify that 5V 3A source caps
are sent. Plug in a second device, verify that 5V 1.5A source caps are
sent. Unplug the first device and verify that 5V 3A source caps are
sent.
TEST=Repeat above tests for meowth.
Change-Id: I0c2b6ce1d2793230f3855856c58633d8cae4b375
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/818336
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Having seen how bright the LEDs are without a diffuser, let's turn the
brightness way down for the time being.
BUG=None
BRANCH=None
TEST=Flash a meowth, notice it's much less bright, listen to the praises
of my retinas.
TEST=Flash zoombini, verify that LEDs still work as before, just dimmer.
Change-Id: I7762ba9f0a7ce930b7b177c6d11ed664a87019e0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/823281
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The cannonlake power state chipset code would fail to keep an accurate
record of the chipset's power state. For example, the EC could claim
that the AP was in G3, whereas the SLP_SUS_L signal was deasserted.
This commit fixes a few issues with the chipset code.
- First, don't have PP3300_DSW_EN enabled by default coming out of
reset.
The default chipset power state when the EC comes out of reset is G3,
therefore we should not enable the PP33000 DSW rail until we decide to
leave G3. This is usually triggered by a power button press.
- Similarly, when we wish to enter G3, we should turn off the PP3300 DSW
rail instead of the noop that was done before.
- Lastly, turn on the 5V rail when entering S5 instead of S3 and turn it
off when leaving S5 to G3.
BUG=b:70184397,b:70244199
BRANCH=None
TEST=Flash zoombini; Verify that AP boots to S0 and can shutdown to S5
and the EC tracks it. Verify that after the S5 inactivity timer, we
fall to G3. Verify that SLP_SUS_L is asserted and DSWPWROK is low.
Verify that we can still perform BC1.2 detection in G3. `reboot ap-off`
and verify that the AP does indeed remain off and no port 80 codes are
seen.
TEST=Verify that 5V is off in G3, but can be turned on if needed.
TEST=Verify that 5V is on in S5.
TEST=With the exception of BC1.2, repeat the above tests for meowth.
Change-Id: I444a8f29969ef6a68a83d1734912d239bad429a5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/813501
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit enables the interrupt handlers for the SN5S330 for both
meowth and zoombini. Additionally, on meowth the interrupt line is
shared between the TCPC and the PPC, therefore we have to check both
parts when an interrupt occurs. The TCPC will be serviced first,
however when reporting the alert status, we need to actually read the
alert registers since we cannot simply use the level of the interrupt
line as the PPC may be asserting an interrupt as well.
The PPC is currently setup to interrupt on PP1 overcurrent situations.
The EC will then notify the AP of the overcurrent status by simply
setting the overcurrent GPIOs.
BUG=b:69139844
BRANCH=None
TEST=Flash meowth; Verify EC boots up okay.
TEST=Flash zoombini; Verify EC boots up okay. Verify can still perform
PD negotiation.
CQ-DEPEND=CL:797936
Change-Id: I43445799088711de9d5ed488abc945e6f1084918
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/797937
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit just adds the GPIO for controlling the display backlight for
meowth and zoombini. The backlight should be enabled from the EC side
on transitions to S0 and turned off when suspending. Additionally, if
the lid is opened or closed the display backlight will be enabled or
disabled respectively.
BUG=b:69972660
BRANCH=None
TEST=`make -j buildall`
TEST=Flash meowth; Boot to S0, verify that the ENABLE_BACKLIGHT GPIO is
set high; Shut down; Verify that ENABLE_BACKLIGHT is 0.
TEST=Repeat above test on zoombini. Also, boot to S0, use a magnet to
simulate the lid closing, verify that ENABLE_BACKLIGHT is 0 when lid is
"closed". Verify it is 1 when lid is "open".
Change-Id: Iffc5db89a0378d354b1fe9e9e5347d57e7caf69b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/811752
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit introduces a driver framework for power path controllers.
It provides some common PPC APIs as well as allowing a board to use
multiple different PPCs drivers/parts. This should make it easier to
add PPC drivers in the future.
BUG=None
BRANCH=None
TEST=`make -j buildall`
TEST=Flash zoombini; verify PPC works as expected.
TEST=Flash meowth; verify PPC works as expected.
Change-Id: Icfb99f384610590b431456cfd28d4aff18442cb2
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807630
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are two different types of suspend states that are supported on
x86 platforms -- S3 and S0ix. When AP enters S3, the chipset state is
identified as CHIPSET_STATE_SUSPEND. On the other hand, when AP enters
S0ix, the chipset state is identified as CHIPSET_STATE_STANDBY. There
are several components within the EC e.g. charger state machine, usb
pd task, motion sense task that take actions based on the chipset
suspend state (and checked only for CHIPSET_STATE_SUSPEND until
now). In order to ensure that different EC components do not have to
worry about checking for all the different types of suspend states
that are supported, introduce a new combination
CHIPSET_STATE_ANY_SUSPEND which is a combination of
CHIPSET_STATE_SUSPEND(S3) and CHIPSET_STATE_STANDBY(S0ix).
BUG=b:69690699
BRANCH=None
TEST=make -j buildall. Ruben verified that with this change, EC power
consumption in S0ix drops from 7.85mW to 6.59mW on Soraka.
Change-Id: I599a0ea2fe2f39132764a6068fa77c3aea02affa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/786919
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not needed since we're using the SN5S330.
BUG=b:69140019
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Id8fa17e1e20ac805405fc6e48e481ceade1a1981
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/777823
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Created Meowth symbolic link to Zoombini.
Modified Zoombini gpio.inc and board, etc. files to
compile a Meowth EC image with the correct gpios.
BUG=b:69133424
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/762039
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Charge port / current selection often needs to be significantly altered
when a battery cannot provide sufficient charge, so have charge_manager
initially enter safe mode. After a battery with sufficient capacity has
been identified, charge manager will leave safe mode, and port / current
selection will return to standard rules.
BUG=chromium:777596
BRANCH=None
TEST=Pass charge_manager unit tests. On kevin, remove battery, attach
Apple PD charger, verify safe mode is not exited and device does not
brown out. Hot-plug battery and verify safe mode is exited. Next,
remove battery, attach to Samus, verify safe mode is not exited and
device doesn't brown out. Hot-plug battery, verify that safe mode is
exited and no active charge port, due to dual-role exclusion.
Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/733954
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To protect zoombini's charge inductor, the input current limit needs to
be limited to 2.7A at voltages over 18V.
BUG=b:67020411
BRANCH=None
TEST=Flash zoombini; Verify that when charger voltage is over 18V, input
current limit is limited to 2.7A.
Change-Id: Ic0a790d3b5aa6bda52ba9c5f41e28a2c6fa9417c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/738920
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, the only we init we need to do is mask VCCIO and 5VA from the
power good tree. Additionally, we deassert PMIC_EN for 30ms during
boot.
BUG=b:66000679, b:66975317, b:66952064
BRANCH=None
TEST=Flash zoombini; Verify that PMIC initializes okay.
Change-Id: I29a300247e4a2359b98d3546de7a024fd111958e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736313
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The 5V power good signal is being removed from the PMIC power good tree,
however, if the 5V power good is not asserted, we should not try booting
to S0. This is because the 1050_STG rail load switch is powered off of
the 5V rail.
Since wireless power control is being moved to the AP, these pins are now
repurposed to control the PMIC enable and for the 5V power good signal.
This commit adds the 5V power good pin to the EC and makes it a required
power signal for S0.
BUG=b:66000679
BRANCH=None
TEST=make -j buildall
TEST=flash zoombini; Verify EC boots up okay.
Change-Id: I8924320030a00b8808aea27fb668451e6e41d590
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736312
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=b:67663166, b:67663124
BRANCH=None
TEST=Find a reworked zoombini with the SN5S330; Flash; verify that we
can charge at up to 20V on that port.
TEST=Plug in a USB-A to USB-C cable, verify that PD state machine still
transitions out of SNK_DISCONNECTED.
TEST=Plug in a weak power source to p0, plug in a stronger power source
to p1, verify that PP2 FET is turned off when stronger source is plugged
in. Verify that PP2 FET is turned on when strong power source is
removed.
Change-Id: I669494194f42d4fcc2b3d63ef1725132b6b8d9a8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/722105
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In the event where we don't have a battery, or the battery is criticial,
we should reject the charge port of "none" such that we don't stop
charging.
BUG=b:66516888
BRANCH=None
TEST=Flash zoombini; Unplug battery, plug in a Type-C charger, verify
that board doesn't enter a reboot loop.
TEST=Repeat the above test with all Type-C ports.
Change-Id: I794e370d5ba578adb76b3fb6edddb82ab72578bb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/678836
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is needed to prevent some of the power rails from turning on. They
should be weak enough for the AP to still drive them.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that PP3000 is not turned on.
Change-Id: I7aca716dc2497aaa0984a1cd033c1f45f2564bbb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/677875
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order for charge manager to be fully seeded, we need to initialize
all the Vbus suppliers.
Additionally, remove the hack for C0 since the TCPCs can detect Vbus
now.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that charge manager is seeded.
Change-Id: I086f70ea26a3f804815017a5f492bd624b85ffd0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/677874
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The GPIO that turns on Vbus for the BQ24392 is active low. This commit
changes the driver to make it clear that the enable is active low.
Additionally, the 5V rail is turned on prior to performing detection and
will be turned off if the AP is off.
For zoombini, since the chipset task can also control the 5V rail,
CONFIG_POWER_PP5000_CONTROL is enabled to do so in a task-safe way.
BUG=b:65992382, b:65991615
BRANCH=None
TEST=Verify that Vbus is turned on and the BQ24392 can output high on
charge detect pin.
Change-Id: Ib96ef9736ccc7fa285a3642ec6f3824a1df8f931
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/676762
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The decision on whether to ramp (and how high) depends on the quirks of
charger identification, so move the decision out of board, into the
drivers that implement usb_charger.
Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better
contrast with the existing CONFIG_CHARGE_RAMP_HW.
BUG=None
TEST=Manual on kevin, verify ramp occurs when port plugged into Z840
workstation.
BRANCH=None
Change-Id: I5b395274133837a18a4f4ac34b59b623287be175
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/702681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The TCPC interrupts were setup, but they weren't enabled yet. This
commit enables the interrupts.
Additionally, a "tcpcdump" debug command is added. This can be removed
later or expanded upon to be more generic.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that we respond to TCPC alerts.
Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670063
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The Vbus adc channel was defined as 0 in the enum, however, we don't
actually have a Vbus ADC channel, therefore it should be defined as -1.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that when charge manager tries to read the
Vbus voltage, the EC doesn't panic due to a non-existing channel.
Change-Id: I53dd3259afc7ae76f587e5b7925ce2f9daa06402
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670123
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
