Each pair of protect bits locks 4K, so for parts with 64K flash, don't
bother checking STM32_OPTB_WRP23.
BUG=chrome-os-partner:49354
TEST=Run flashrom to protect PD MCU (see repro steps on linked crbug),
reboot and verify system boots into dev mode with all_at_boot and
all_now protect flags set on PD MCU.
BRANCH=glados
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic375d97c30bfd68940350641c44d5535b0402a2f
Reviewed-on: https://chromium-review.googlesource.com/322823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We found the deviation of 115200 UART baud-rate is too large when core
clock is 16 or 12MHz. It causes failure during FAFT since sometime EC
could not receive correct commands to proceed test. We adjusted core
clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of
them have run FAFT and stress tests for weeks and no UART issues were
found.
Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH
and hold time directly for better i2c timing when freq is 400K. And if
freq is 100K, we introduced normal mode to handle it.
Modified sources:
1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz.
2. clock_chip.h: Set target core clock as 15 MHz.
3. uart.c: Add baud-rate support for 15/13 MHz.
4. register.h: Add new register definitions of SMBus.
5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c
timing.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322320
Reviewed-by: Shawn N <shawnn@chromium.org>
When a sysjump host command is received, there is a (usually) small
period of time when the EC has sent a reply packet back to the host, but
interrupts are still enabled. If the host sends a new host command,
STATUS_PROCESSING will be set by the EC ISR, but the host command will
never be handled due to pending sysjump. In this case, STATUS_PROCESSING
will still be set, so we need to clear it on LPC post-sysjump re-init.
BUG=chrome-os-partner:49318
TEST=Add 200ms msleep before call to interrupt_disable() in
jump_to_image(), boot to software sync, and verify host commands are
handled successfully post-sysjump and system continues to boot.
BRANCH=glados, cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759
Reviewed-on: https://chromium-review.googlesource.com/322431
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Includes support for encrypt / decrypt,
and sign / verify; padding schemes OAEP /
PKCS1; supporting bignum library.
RSA key sizes must be a multiple of 32-bits
(with the top bit set). Keying material,
input and output buffers are required to be
word-aligned.
BRANCH=none
TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316942
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L
and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs
simultaneously since EC's power rail is turned off by PMIC for a while.
VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery
mode detection.
The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset.
Use BOARD_WHEATLEY to distinguish them.
Modified drivers:
1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I96198ffb6901f0539755046ca303e94381ae7541
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320641
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support rpm mode, we use a TICK function (fan_tick_func) to
monitor tacho value and adjust PWM duty. In this version, fan driver always
enables clock source of MFT to make sure it can present real-time tacho value.
For better performance, the feedback value to adjust PWM duty is various.
We also change fan & pwm settings for SUNUN 4-pins pwm-type fan.
Modified drivers:
1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
3. fan_chip.h: Remove unnecessary default_count field of mft_t structure
4. fan.c: Add support for rpm mode
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320510
Reviewed-by: Randall Spangler <rspangler@chromium.org>
[task]
1. Copy task_wait_event_mask() function of cortex-m0.
[system]
2. Include host_command.h for host_command_pd_request_hibernate().
[i2c]
3. Update i2c handler to use task_wait_event_mask.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chromium:435611,chromium:435612
TEST=1. console commands: i2cscan, i2cxfer, and battery.
Change-Id: If5bb4407460d28c0b021ab133ca4b635ff7bc3c9
Reviewed-on: https://chromium-review.googlesource.com/320440
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We should consider the interval between the calling __hw_clock_event_set and
entering deep idle. In order to get more accurate value of deep idle time, FW
should record the time-stamp before entering deep idle and calculate the deep
idle time based on it.
Modified drivers:
1. hwtimer_chip.h: Add new function declarations for deep idle time caculation.
2. hwtimer.c: Add new functionsfor deep idle time caculation.
3. clock.c: Modified for calculating more accurate deep idle time.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Id037c4dc3564659e4ad493f2fc3ffc5d06c18b06
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320071
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Support lower core CLK frequency and configure the baudrate parameter of console
UART for current core CLK.
Modified drivers:
1. clock.c: Support lower core CLK frequency.
2. uart.c: Add baudrate setting for differenct core CLK.
3. clock_chip.h: Set default core CLK to 16MHz.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Id83ecf92c19bec508ec84e2d271d7e1fa278774f
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/319030
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add support for continuously writing ADC samples to a circular buffer.
CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an
appropriate sized buffer must be passed to adc_read_all_channels().
BUG=chromium:569994
TEST=Manual on snoball. Verify 'adc' continues to function (single
mode). With pending commit, verify that continuous conversion interrupt
is called at appropriate frequency and values look consistent.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e
Reviewed-on: https://chromium-review.googlesource.com/318505
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Adds the SPI master driver with support for both SPI masters with
support for using GPIOs as chip selects or using the hardware's
dedicated chip selects.
Note this has not been enabled in the cr50 board.
BRANCH=none
BUG=none
TEST=verified through use of the SPI_FLASH module on cr51
Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5
Signed-off-by: Ewout van Bekkum <ewout@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317329
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is a rewrite of the Cr50 USB Device Control Endpoint
implementation, using the instructions in the DWC USB 2.0 OTG
Programmer's Guide (such as they are). Some of the major
differences:
* Not every USB interrupt indicates the receipt of an incoming
packet. Many merely provide updates on packet transfer status,
transaction stages, or other activity. We handle those
cases correctly.
* We may need to start a new Control transaction at any point,
even in the middle of an existing transaction.
* Large IN data transfers can be handled with one interrupt by
chaining multiple together.
* Logical separation of the phases of each transaction (Setup,
Data, Status).
That said, while this CL matches the Programmer's Guide fairly
closely, that Guide is pretty crappy and this is just the first
commit. There is still a fair amount to do (marked with comments
and bug reports). However, it works at least as well as the
previous version and is much closer to what the supplier claims
is the correct implementation.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
We also connected this device to Windows, and Mac laptops (and a
Chromebook) and used a USB bus analyzer to monitor the behavior.
It works on machines those, too.
Change-Id: Ic515ea83e217a8d0552d61ac5eb19693661fcd15
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/318864
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
This allocates more space for FIFO buffers, according to the
instructions in the Programmer's Guide. Many more comments and
some slight refactoring was added to explain the configuration
more clearly.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I1a870a4b1dc628729f7cd1b80bab7ec6dfd11f37
Reviewed-on: https://chromium-review.googlesource.com/318262
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for
keyboard scan function.
2. Critical section for gpio_set_level().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: gpioset, gpioget, and version.
Change-Id: I8edae122525e6dcebaa3489116642d8e48520569
Reviewed-on: https://chromium-review.googlesource.com/318112
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The double-mapping modules(CIR, BRAM, SSPI, PECI, and UART) won't work
if GPD2 pin's status is low and GCR register's setting is at default.
We move 'IT83XX_GPIO_GCR = 0x06;' to 'gpio_pre_init()'
to prevent this case.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Register 'GCR'=0x6 after init.
2. GPD2 is low and UART works.
Change-Id: I71b4436ab6c2a8f9e77e0d6f5116e5327a3167e7
Reviewed-on: https://chromium-review.googlesource.com/318131
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
No new functionality, just a little refactoring and general
cleanup of the USB initialization steps.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317376
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: Ia6922acf82a793759870a61217562f4e63608a80
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317319
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
No new functionality, just adding stub handlers for some
additional USB interupts that we'll eventually need to deal with.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317354
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I805ac00432c31735d2904227c5d19ad53cfa7ccb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317376
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
The control endpoint (EP0) can receive some Setup packets that
are specific to individual Interfaces. The USB_DECLARE_IFACE
macro is used to register the callbacks that an interface
implementation provides to handle those Setup packets.
This change cleans up the callback API a bit, so that we don't
have to export the internal workings of the Cr50's EP0 interrupt
handler.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I9ac22f6a74f360f201c58e9ef39e3576834578a8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317269
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
No functional changes, just making the code prettier.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I1301c035eafc054567c1f317a80539197fcdeef4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317354
No functional changes, just some additional debug stuff that's
not normally compiled.
BUG=none
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I32b4944c01006f2e9c8cdb2e732a4b1710a60e19
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317560
The startup message includes the type of the image it is running (RO
vs RW currently). cr50 reports RW as RO, which this patch fixes. This
issue requires a bit more attention though: first, the RO type can be
deduced at compile time. Second, RW and RW_B should be accommodated.
RW_B should also be accounted in other places in the code where now
only two options are considered: RO vs RW.
BRANCH=none
BUG=chromium:567938
TEST=the startup message now reads:
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: RW, cr50_v1.1.4162-f1e71a6-dirty 2015-12-08 16:39:00 vbendeb@eskimo.mtv.corp.google.com]
Change-Id: I0db2db4413a13ebe915e1081b47cd4a6f85cbdd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316922
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If we haven't sent a stop condition, make note of that, and send a
repeated start next time.
BUG=chrome-os-partner:48294
BRANCH=None
TEST=Verify "ectool i2cxfer 1 0x25 1 2" succeeds on glados. Also verify
`i2cscan` on EC console succeeds.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id45bfc6540dc1cc3a3d1e9f6916a238bce5ae33f
Reviewed-on: https://chromium-review.googlesource.com/316022
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Allow boards to customize both the PWM frequency / period and the
enabling of complementary output signals.
BUG=chrome-os-partner:48044
TEST=Manual with snoball w/ subsequent commit. Run `pwm <ch> 50` for
each channel, verify with `adc` that each PD output voltage is
approximately VBUCK / 2.
BRANCH=None
Change-Id: I61cbb4a5b656f41ec7cec59339f5247902256295
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315141
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Stack space is pretty tight on cr50, and since there is no need to
support SHA digest sizes in excess of 256 bits, the digest buffer size
should be reduced.
This patch makes the maximum expected digest size dependent on the set
of configured hash algorithms, moves hash size related asserts from
run time to compile time, and passes compile time definition to the
TPM2 library to increase its hash state container (it became too small
when SHA384 was disabled).
The sw context requirements should be reduced, but this is a task for
another day. We also do not have to store a local digest copy if the
API allowed reading a partial digest.
CQ-DEPEND=CL:314883
BRANCH=none
BUG=chrome-os-partner:43025, chromium:564862
TEST=all tests pass:
$ ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
SUCCESS: AES:CTR256I 1
SUCCESS: sha1:single 0
SUCCESS: sha256:single 0
/New max timeout: 1 s
SUCCESS: sha256:finish 1
SUCCESS: sha1:finish 3
SUCCESS: sha256:finish 2
Change-Id: Iaef3a230469de129e72418814e1d113b447c0137
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314695
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Set alternative pin from GPIO to CLKRUN if SERIRQ is under quiet mode
Once we need LCLK, CLKRUN will pull low automatically.
Modified drivers:
1. lpc.c.: enable CLKRUN functionality for SERIRQ no matter continuous or
quiet mode.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I58b11340833b26bc64bfe499272fd3b319b33202
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/314971
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This just replaces a few manually created macros in
chip/g/registers.h with a more programmatic version based on
names in chip/g/hw_regdefs.h.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: I73ee2ee1ee3f53a0939000822c552deace46f154
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314937
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Use some meaningful macro names instead of just raw numbers when
selecting the correct USB phy port. Also we only need to do this
once, since it should be sticky through anything short of a
complete power down.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: If6ea2b9d9a62bf6ce4adaed1c5aac1f66013ebeb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314938
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
When Link Time Optimization is turned on, functions that set
task_waiting multiple times have one of the sets removed
by the linker leading to undesired results.
Marking task_waiting volatile alleviates this issue.
BUG=chrome-os-partner:46063
TEST=Manually tested on Kunimitsu.
Console command adc shows correct value of approx
20000 mV for VBUS.
BRANCH=none
Change-Id: I85a6e5c9688ae72c45d90fb58296f94b74a301aa
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314233
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add i2cscan and kbpress commands for FAFT.
Remove unnecessary i2c reading since there is no race condition.
Bugs fixed:
Fixed i2c_read_string bug since we shouldn't enable NACK if flag doesn't
contain I2C_XFER_STOP.
Fixed i2c_unwedge bug since the parameter should be port not controller.
Fixed state machine bug since we should restore bus state back to idle
if bus encountered timeout.
Modified drivers:
1. board.h: Add i2cscan and kbpress commands for FAFT.
2. i2c.c: Remove unnecessary reading since there is no race condition.
3. i2c.c: Fixed i2c_read_string and i2c_unwedge bugs.
4. i2c.c: Restore to idle state if bus encountered timeout.
5. board.h: Add CONFIG_LOW_POWER_IDLE for better power consumption.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I98974f852cbbaec270c697feb8016b52550005bc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/313393
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We support two FPGA images with the same firmware. To meet
timing, one image has support for USB but at the cost of reducing
the crypto multiplier to 8x8. The other image has full crypto but
no USB support.
This change displays the FPGA configuration at boot, in addition
to the FPGA image version.
BUG=b:25350751
BRANCH=none
TEST=make buildall, manual
Boot it and watch the console. You should see something like
this:
cr50 bootloader, 20151118_73026@80895, +USB, 8x8 crypto
Valid image found at 0x00044000, jumping
Change-Id: I0e5de453fcd1714fcbb170bf4364747b1e7ba894
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314824
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
If we're doing a read transaction without a write and asked to send a
start condition, assume that the slave has already been addressed and
make a repeated start.
BUG=chromium:561143
TEST=Verify "ectool i2cxfer 1 0x25 1 2" succeeds on glados
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic60a5c0f0fa32d5541b3cc6dce48cac28f26cd06
Reviewed-on: https://chromium-review.googlesource.com/314313
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add a hard timeout to wait_for_interrupt() so that we won't wait
forever, even if we get into a state where interrupts fire yet our
status is not as expected.
BUG=chromium:561143
TEST=Verify "ectool i2cxfer 1 0x25 1 2" doesn't watchdog on glados
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I39773370bb7e45a8f0c0cdb4a463904643f72587
Reviewed-on: https://chromium-review.googlesource.com/314253
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This change includes hardware and software support for SHA1/256 on
CR50. When running in the RO image, only hardware sha256 support is
included. When running in the RW image, the code auto-selects between
the software and hardware implementation. Software implementation path
is taken if the hardware is currently in use by some other context.
Refactor the CR50 loader to use this abstraction.
The existing software implementation for SHA1 and SHA256 is used for
the software path.
CQ-DEPEND=CL:*239385
BRANCH=none
TEST=EC shell boots fine (implies that SHA256 works)
BUG=chrome-os-partner:43025
Change-Id: I7bcefc12fcef869dac2e48793bd0cb5ce8e80d5b
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313011
Dcrypto support is a hardware property, it belongs with the chip
sub-tree, not with the board.
This patch just moves the files and modifies the makefiles to pick up
the files at the right spot.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=the image still builds, the devices still boots, the
test/tmp_test/tpmtest.py still succeeds.
Change-Id: Ie321ac738c11a9f403a7943524c56ec4366db297
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313655
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This is required to be able to consolidate hardware and software hash
implementations.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=the device still boots up.
Change-Id: If420541427bb316b97bc20a21fd3fd8a57708244
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313654
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This common for all g based boards file should not be associated with
a single board.
BRANCH=none
BUG=none
TEST=the device still builds and boots.
Change-Id: I34c49a095abd8e49b492c318823dd8f56609fdc8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313631
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A few minor changes, this is still a USB image, no dcrypto support.
BRANCH=none
BUG=none
TEST=built an image using the new description and signer files, booted
it on an fpga board:
> vers
Chip: g cr50 B1 20151118_11218
Board: 0
RO: cr50_v1.1.4081-c06cf49-dirty
RW:
Build: cr50_v1.1.4081-c06cf49-dirty 2015-11-20 09:56:03 vbendeb@eskimo.mtv.corp.google.com
>
Change-Id: I29bbaaa512ff604beb209a606acf19282331c96f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313630
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Our system timer uses capture compare mode, so the TIM1_CC interrupt
should be used.
BUG=chrome-os-partner:47851
TEST=Set TIM_CLOCK_LSB to 1 on snoball (TIM1), verify that timer
interrupts function, HOOK_SECOND hooks are called and watchdog doesn't
fire.
BRANCH=None
Change-Id: Id5cc18d0cd216b5b448e11cf0bae9696db74eb02
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313188
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In handle_interrupt(), "|= 1 << 29" will clears all status bits, not
just bit 29. Fix this to make it only clear specified status bit and
keep R/W bits intact.
BUG=None
BRANCH=None
TEST=Verified on Kunimitus system
1. In configure_controller() write R/W bits in completion register
2. In handle_interrupt() print the value of completion register and
status bits is cleared, R/W bits are kept.
Change-Id: I6a9cc17b3dfc1e163af5e56a80600afb8ac23247
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/312701
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
