Also tracks the distribution of IRQs, so we can see what's triggering
interrupts.
Task profiling is optional, enabled via CONFIG_TASK_PROFILING.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7464
TEST=taskinfo
Change-Id: I266f2b49bff9648cda446210d5a302b460fec244
This patch moves all I2C port initialization into configure_board
to ensure the alternate function gets set properly.
I2C ports should come up in their high-impedance state (Output,
open-drain, output set) and then get set as alternate function.
However, configure_board() runs before gpio_pre_init(), so the
mode register was getting set set back to general purpose output
instead of alt. function.
TODO: Fix gpio_pre_init() so we do not need to explicitly handle port
configuration in configure_board().
BUG=none
TEST=tested on daisy using keyboard
Change-Id: If837acd4f4204e467e7ed276f048b5b70ecbdb25
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Adding trickle charging mode to precharge batteries with
voltage lower than minimal design value. This CL adds
control to charger voltage to track battery input current
change.
To prevent battery from deeply discharging, this CL preserves
3% of the design capacity.
Minor bug fixes include error state check and charger control
logic.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8660,8661
TEST=manual
Plug AC power, the power adapter led should be
'yellow'. On the EC serial console, type 'battery'
and 'charger' commands.
Battery input current should staid close to its
desired current.
A deeply discharged battery (5.5V) should be revived to
a healthy state after 30 minutes ~ 4 hours.
Change-Id: Ibaa2396c6b751639d98db32f5919b1e8ec700e40
This adds I2C2 support for Daisy:
- Initializes I2C2 GPIO lines
- Adds CONFIG_I2C so main() will call init function
- Adds work task for I2C2
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: I147e3781b8bcac87ff248fb45c9978b614a24b89
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Set up signal to audio codec as open-drain output. This should
be benign on older revisions of Daisy.
The signal CODEC_INT is driven low whenever a keypress has been
processed. For Daisy, a delay of about ~1ms from the time a key
is pressed until the time the codec is signaled is okay. This
gives us time to scan the columns to see if a key was actually
pressed so that we don't cause spurious codec interrupts.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Tested on Daisy using oscilloscope
Change-Id: Id3564f4aacbf7294b7151b082075f3c3ec8b1eb2
Mainly add a typematic task that counts down the delay. Set the initial delay
in the keyboard_state_changed() when key pressed and clean it when released.
BUS=chrome-os-partner:8463
TEST=press on a particular key and screen shows that key is repeating.
Change-Id: Ic8432f8b38b514476588e0b7ad8fdc8a0b0c0b51
This eliminates the GPIO init code from stm32l's version of
keyboard_scan.c. It moves all initialization to board.c, and
also eliminates the input/output arrays that were used to represent
keyboard GPIOs earlier on. The keyboard code no longer needs
board-specific GPIO knowledge.
There were some minor nomenclature clean-ups along the way, but
but there is still more clean-up to do in future CLs.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=tested on Daisy
Change-Id: I27e92b10262e686111f20d8e3ed9e416db245355
This sets the EC_INT GPIO as an open-drain output and initializes
it in high-impedence state.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=tested on daisy (applied keyboard patch and tested that AP gets
interrupted and requests keyboard state upon keypress)
Change-Id: Id4b043dd0066db823cd1502bd738f69bb656eada
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=power system on; should still boot
Change-Id: I2e6c1f1cb4ffabf37d3113faca900da17c1353e9
This adds support for setting up the SPI pins and driver, as well as the
required SPI work task.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: Ie73560356fc8e4fcec0773c4692ecd6a7ba7affa
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7832
TEST=manual
1. Power on system
2. From ec console: kblight 100
3. Use a magnet next to the left shift key to trigger the lid switch. Screen and keyboard should go dark.
4. Remove the magnet and they should light up again.
Change-Id: I298ea94930976153d8dcd102316b010ee28cd747
I need to clean up the console commands and provide the same functionality
via ectool, but this is a good starting point.
BUG=chrome-os-partner:7839
TEST=manual
Power up the CPU. The lights should blink.
Change-Id: Ic05a171d2b647551f1cfc7d6b2fd101088cac137
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Provide a function which is called when keyboard scan data is ready,
and make it do the right thing.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I0089a7ff78ba035ba6648220ae2e03a958d444d8
We want to use this for drivers, so start it up on boot.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: Ie69fb9d6df75150dd3903fe37a9b72c0a663f045
Signed-off-by: Simon Glass <sjg@chromium.org>
Add nopll command to turn off the PLL, reducing the system clock to 16Mhz.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8798
TEST=manual
boot system
press power button to boot x86
temps // should print all temperatures
timerinfo
timerinfo
timerinfo // convince yourself this is counting up at about 1MHz
nopll // this drops the system clock to 16MHz
temps // should still print all temperatures
timerinfo
timerinfo
timerinfo // should still be counting up at about 1MHz
Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
De-assert the lightbar reset GPIO to be able to access its registers.
According to the HW guys, it will consume less power in standby than in
reset due the pull-up on the reset line.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
BUG=None
TEST=manual
On Link proto-1, type "lightbar test" in the EC console and see it blink.
On BDS, just build it. Nothing actually changes for BDS.
Change-Id: I9ec612c80f48d41ccf779f0962fc047966d4b7ba
Servo2 can set the write protect signal
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8580
TEST=manual
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:on
Then from EC console:
gpioget WRITE_PROTECTn
0 WRITE_PROTECTn
From chroot:
dut-control fw_wp_en:on
dut-control mfg_mode:off
Then from EC console:
gpioget WRITE_PROTECTn
1* WRITE_PROTECTn
Change-Id: I9976cd6f114c8dae75434adf99d9409107b6ada0
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
We moved a while ago to a table of ADC channels, so having a
meaningless constant defined in board.h is more harmful than helpful.
BUG=none
TEST=build link, bds
Change-Id: I651a609c9ed13f879bb943c90731275407d77e50
Signed-off-by: Randall Spangler <rspangler@chromium.org>
The kernel no longer uses port 80 as a delay mechanism, so we don't
need to detect the no-longer-present spammy writes.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7972
TEST=port80 scroll, then boot the system. see a few repeated bytes,
but not piles of 00 and ff's.
Change-Id: Id14dc43ab4e1b15c6bab99a17c062f295a59e7e6
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
This CL adds a charge state machine for SMB compliant battery pack.
Vendor specific charge constraints can be applied through function
call, defined in battery_pack.h .
BUG=chrome-os-partner:7526
TEST=Attach EC serial console
Unplug AC adapter: state ==> "discharge"
Plug AC adapter: state ==> "charge"
Battery full: state ==> "idle"
Unplug battery: state ==> "error"
Change-Id: Iabff0988a6067d37c17c11b060bbb7e66505c118
The thermal engine monitors the temperature readings from all sensors.
For each sensor, five threshold temperatures can be set:
1. Low fan speed.
2. High fan speed.
3. SMI warning.
4. Shutdown CPU.
5. Shutdown everything we can.
Each of these thresholds can be set to either a fixed value or disabled.
Currently the real implementation of SMI warning and shutting down is
left as TODO, as indicated in the comment.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manually change threshold value to test all actions can be triggered.
Change-Id: If168dcff78ef2d7a3203cb227e1739a08eca961e
Add a task to update fan speed in LPC mapped memory once per second.
Also added read_mapped_mem16 and read_mapped_mem32.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8183
TEST="ectool pwmgetfanrpm" shows same result as "faninfo" from ec
console.
Change-Id: Ibc536acd39f836ffcad0bfa7c9c14e730220bd49
On bds, always send the keyboard scan code for the power button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I56ad8c9dd67edfd54190d64f16742896a86b9ac1
