The testlab will be running rma open on a bunch of devices. This change
adds a script for them to use.
The script handles things like finding the cr50 console and converting
the rma_auth output into a full challenge url. The user can click on the
url and generate the authcode. They can input the generated authcode
back into the script. The script will check 'ccd' output to make sure
rma open succeeds.
BUG=none
BRANCH=none
TEST=on a reef and bob running 3.4, run the entire cr50_rma_open
process. Verify RMA open succeeds
Change-Id: I2c9aef565351b65848f29083cd1e2c1f6e77e2a4
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/994417
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.
Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.
BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
handler), check that panicinfo contains a sensible PC in r5
after reset.
Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When flash_ec script is run from /usr/bin it could not find
the ec source directory to calculate the basebord. Handle flash_ec
running from /usr/bin by using the default chroot source layout to
find ec platform dir. If dir is not present, then skip baseboard
check
BRANCH=none
BUG=b:77128456
TEST=sudo emerge ec-devutils && flash_ec --board=yorp
Change-Id: Ib7766e5c7ca701f0a209c6e6e6c1a192284b9d0b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/992993
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds execution-in-ram, opposite of XIP: execution-in-place
(a.k.a. XIP) to the EC features. It can be currently implied by
CONFIG_EXTERNAL_STORAGE.
BUG=b:77306460
BRANCH=none
TEST=Verify ectool prints EXEC_IN_RAM on Fizz.
Change-Id: I4a7fb3b267864debe59fd211956371eceac57613
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995968
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch clarifies the logic which determines whether we perform EFS
or not and print different messages for each case.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I5588018a3594be2bcad84a2f74f805b76a195f85
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/996398
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Use RMA public key definition generated based on the binary blob
containing the key and key ID.
Key generation is controlled by the make file in common/, but actual
key blob comes from the board directory.
The structure holding the key and key ID is being modified to allow
initialization using a flat array.
No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and
CONFIG_RMA_AUTH_SERVER_KEY_ID.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST='make buildall' still succeeds.
test RMA server generated authentication codes are accepted when
unlocking RMA.
Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The semantics in the EC code base are that CONFIG_INTERNAL_STORAGE
implies eXecute-In-Place semantics (XIP). Add a comment to make that
abundantly clear.
BUG=none
BRANCH=none
TEST=none
Change-Id: I80152eeb41dd35716f4c09ffd1753ae128aa7d2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/995956
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Driver implements TCPC for ANX7447 chip. Enable Type C
port for USB and DP alt mode.
BUG=b:73793947
BRANCH=NONE
TEST=tested compiled binary for pdeval-stm32f072 board with this patch.
Power contract establishment, port role swap, DP alt mode works fine.
Change-Id: Ic11e499fc5fb4aba7732c75e4cb2fee54828c616
Reviewed-on: https://chromium-review.googlesource.com/956790
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
On yorp, the PS8751 TCPC resets its event mask when it goes into low
power mode which turns off the VBUS detection event mask. Since the
first interrupts after lower power mode should contain the vbus
changed interrupt we miss it.
We have tried many different permutations of resetting the event mask
on reset without achieving 100% detection success.
The PPC Vbus detection code calls out to the PPC over i2c every time
vbus level is checked; applying that strategy for TPCPs make the
detection much more robust.
BRANCH=none
BUG=b:77458917
TEST=yorp detect vbus on insertion every time with PS8751
Change-Id: I15b5f2ee016f68bac9e4bf4d5d89bbaef323f131
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/993394
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This patch brings in both prod and test RMA server public keys as two
binary files.
A bash script for converting binary blob into C definition is also
provided.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST=none yet
Change-Id: I2edd78164b8c912408ac7eda2e0a3a0262a8e81f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990782
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a specific option for it83xx chip and is used to
include EC2I module.
And we won't need it without LPC module enabled, so just
depend on CONFIG_LPC.
BUG=none
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/987674
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the wrong battery profile is loaded into max17055, we need
to be able to recover it after EC POR by reloading the correct profile.
BUG=b:77491650
BRANCH=scarlet
TEST=First, unplug/replug battery many times until I see
the battery profile loaded is wrong (1/20).
Second, make sure after a hard reset the correct battery profile
is loaded.
Change-Id: Iabb24fc75d31b9ce87bfb835e03549f4726903ed
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/991192
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
__builtin_ffs takes an int as argument, and, therefore, does not
find bits >= 32. Fix this up when CONFIG_HOST_EVENT64.
BUG=b:69329196
BRANCH=fizz,poppy
TEST=Patch coreboot to add bit 33 in SCI mask, add EC code to send
such events, EC does not watchdog anymore
Change-Id: If868095f19fe1940b4f5924cf669a719f9535991
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/989514
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We want to be able to replace RMA public key and its key ID in the elf
module before signing. Let's make sure they are packed together for
ease of find and replace operation.
BRANCH=cr50, cr50-mp
BUG=b:73296144
TEST=built an image, verified that RMA unlock still works.
Change-Id: I1a8e155391421f32b7422f11ab2a5f53d1ddd0ac
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990781
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no point in allowing the environment to override board name
when building gsctool, it requires BOARD to be set to cr50 to build
properly.
And usb_updater2 does not really care about the board at all.
BRANCH=none
BUG=none
TEST='make -C extra/usb_updater now succeeds even if BOARD is set in
the environment.
Change-Id: I1ed16b8049f4d5936bb29585bb65718ed865d6b5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/972365
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done()
and lpc_sib_wait_host_write_done() routines, in rare case, ec might have
a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD
bits are high forever. (Normally, CSWR/CSRD bits won't be always high.
These bits are high forever also means something wrong on LPC/eSPI
bus.)
In order to prevent this situation, the CL checks TO_STS bit of ITCTS
in these routines. If this bit is set, restoring ITIM32 preload counter
value to maximum value and processing overflow will be done by
force_time().
BRANCH=eve,fizz,poppy
BUG=b:76182199
TEST=No build errors for npcx series. Passed test command of CL 979389
on npcx_evb. No symptom occurred during warm reset stress test on
soraka.
Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/979874
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable trackpad power when chipset is in S0 state. Keep
it disabled in other states.
BUG=b:73137125
BRANCH=master
TEST=On Octopus, kernel logs show ELAN enumerated
Change-Id: Ie1fd8ab777e82d900418127b4efee29fe65d1423
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/984405
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If we enable charge termination when booting w/o battery,
charge termination would trigger and cut the power for max17055.
BUG=b:72697658
BRANCH=scarlet
TEST=Read rt946x reg 0x02, confirm charge termination is
disabled when booting w/o battery, and enabled otherwise.
Change-Id: I5780196ad993299ddfb37621bee5e941aa9b0d14
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/989314
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
After a POR, max17055 takes ~2.5 seconds to finish the detection
for battery absence.
Let's report BP_NOT_SURE instead of the default BP_YES when the battery
detection result is not settled yet.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet w/o battery and confirm battery_is_present()
never return BP_YES before reporting BP_NO
Change-Id: Ia549b4b78a7403ce2c82802841b78bdd514c6200
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/989313
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
If a baseboard exists in the build.mk for a board, use that
as the unibuild path.
BRANCH=none
BUG=b:77128456
TEST=tested the following command with correct results:
flash_ec --board=yorp (baseboard)
flash_ec --board=bip (baseboard)
flash_ec --board=grunt (non-baseboard)
Change-Id: Ic4573cb01849275d1333ff9e715f69a4c95444b0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986753
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Use the reset count to determine if there was a rollback in
system_rollback_detected. Before system.c was checking if the inactive
header was newer than active one to determine if the system rolled back.
This wasn't accurate. Cr50 rollback isn't the only reason why a newer
image may be rejected. The image may have been rejected because it
wasn't signed correctly or it's corrupted, so we shouldn't be using the
newer header as a sign that there was a rollback.
The reset count is cleared when the AP boots. This means the rollback
state will be lost the first deep sleep resume after the AP has booted.
BUG=none
BRANCH=cr50
TEST=manual
flash a dbg image with version 4.0 that has two infomap bits
erased.
Check sysinfo to see that it doesn't think cr50 rolledback
flash a dbg image with version 4.4 that has one infomap bit
erased.
Make sure that 4.4 image is rejected and cr50 is still running
4.0
Check sysinfo to see that it doesn't think cr50 rolledback
flash a dbg image with version 4.4 that has two infomap bits
erased.
Make sure cr50 jumps to that image
rollback to the 4.0 image
Make sure sysinfo shows there was a rollback.
Boot the system
Make sure sysinfo shows there was a rollback.
Change-Id: I85f2e001ffed9e2185a276dfa916e9b0a05ff7bf
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/985029
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When building the `tests` target for a specific board that uses the
ite EC chip, it will fail to find the lpc_kbc_obe_interrupt function.
Adding #define around code similar to npcx set up.
This is needed because the unibuild system uses the tests target when
compiling chromeos-ec.
BRANCH=none
BUG=b:77274422
TEST=Can now successfully `make BOARD=bip tests`
Change-Id: I971aebe1667eb90e8ccccbe6047c5aa959c76c4b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986634
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This CL adds required code to the tcpc_alert_event() and
tcpc_get_alert_status() functions. In addition, it adds
board_tcpc_init().
The ANX7447 does not have an EC controlled reset line. Other than that
modification the actions taken in tcpc_alert_event and
tcpc_get_alert_status are the same as what's been done of previous
projects using these TCPCs.
board_reset_pd_mcu still needs to be implemented, but is not related
to the tcpc_alert_event() and tcpc_get_alert_status() functions. Also,
at this point ANX7447 is not supported as that depends on the driver
landing.
BUG=b:74127309
BRANCH=none
TEST=Verifed that with external charger that USB PD state machine
advances to SNK_READY state. Note that port 0 does not work at all in
this version.
Change-Id: Ib887b4dba6bacb4b3fb6e03f634362e1c3aa4da2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982518
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When reporting state, current code was only using the lid battery
level to determine if we are "near full" (different LED color).
Fix this to include both lid and base batteries in the logic.
BRANCH=none
BUG=b:75982704
TEST=Lid at 100%, base at 50%, LED is amber when charging.
Disconnect base => LED turns white (lid is near full)
Change-Id: I6fd44a16832cbd6d440f1bbb8c696e41c3f4699b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/983202
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
system_rollback_detected is used to determine if the system rolledback
in the rest of the system code base and it's state is saved longer. This
change switches board.c to use that to determine the sysinfo output
instead of using the reset count.
The reset count is cleared when the system boots. Depending on how fast
the system boots it may be difficult to read sysinfo before the reset
counter is cleared. In these cases it is difficult to tell whether an
image has been rejected entirely or the image caused a rollback.
BUG=b:71804463
BRANCH=cr50
TEST=boot the device. Make sure sysinfo shows there's no rollback.
Rollback and make sure sysinfo shows the system has rolledback
Change-Id: Ic29b105c758d0984e47482b9384cf00fe202b716
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/984393
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tell the base to hibernate when we are in S5, and no AC is connected.
Also, wake the base when AC status changes (S5), and when the system
transistions out of S5.
BRANCH=none
BUG=b:71874971
TEST=1. Lid EC console: apshutdown => Check that Base EC hibernates
2.a. Lid EC console: powerb; => Check that base reconnects
2.b. Connect/disconnect adapter: check that base disconnects
and reconnects
Change-Id: I5e9a4afc64a07ad92f37d171a78a914d26f07c8e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958814
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Allows the lid to hibernate the base.
BRANCH=none
BUG=b:71874971
TEST=With following change, lid hibernates the base when in S5,
and no AC is connected.
Change-Id: I8c8017d638442ba8b17c8117d0b1b31f3538925f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/981914
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, charge state changes (i.e. enum charge_state_v2) are not
announced. Because of this, a charge LED is controlled by HOOK_TICK
(and polling charge status by charge_get_state).
Instead of checking charge status every 200 msec (or 500 msec), we
should change a charge LED only when charge status changes.
This patch makes HOOK_BATTERY_SOC_CHANGE get notified when charge
state transitions.
BUG=chromium:824942
BRANCH=none
TEST=On Nami, try AC plug/unplug, battery connect/disconnect.
Change-Id: I47a9542035666636d55f414e857d55ec36d69638
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/981397
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This adds a config to specify whether sweetberry
should measure power, current, voltage per powerlog entry.
The json format is slightly revised to allow data type
per channel. powerlog and sweetberry fw are updated
to handle the new functionality.
BUG=b:72973433
BRANCH=None
TEST=./powerlog.py -b marlin.board -c marlin_a.scenario -s .5
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I231fc6600495146fad30583872bf14c660d5a50b
Reviewed-on: https://chromium-review.googlesource.com/905427
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Mengqi Guo <mqg@chromium.org>
MODULE_UART should be used for console UART, and MODULE_USART for
all secondary ones (like EC-EC side channel).
BRANCH=none
BUG=b:66575472
TEST=Flash wand, EC-EC communication works
Change-Id: I241bad7902c2e7228783ae1aa9cc33ad5da2c8a2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958813
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
chgdualdebug allows to force the dual-battery charging algorithm
to take certain decisions.
On AC, `chgdualdebug c <current>` allocates up to `<current>` to
the base, capped at the total current available from the adapter
(`chgdualdebug c auto` re-enables the algorithm).
When no AC is connected, `chgdualdebug d <current>` set the
current to transfer from lid to base (negative to transfer from
base to lid).
BRANCH=none
BUG=b:71881017
TEST=Try the commands above, see that they do what they advertise.
Change-Id: I98ee60eadd8f9202c1d489d9fca63267c32e8178
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958811
Reviewed-by: Randall Spangler <rspangler@chromium.org>
