Enable the RSA verification of the RW partition,
so we are using the RW partition by default and
the USB PD flashing VDMs are able to update
the firmware over the Control Channel.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:47823
TEST=run the following sequence on a Samus connected to Honeybuns :
ectool --name=cros_pd infopddev 1
ectool --name=cros_pd flashpd 5 1 ec.RW.bin
ectool --name=cros_pd version
and see the honeybuns properly updated and running the new version.
Change-Id: I8f1612ee153a412620bae5822d1b354ad8072916
Reviewed-on: https://chromium-review.googlesource.com/312998
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
No functional changes, just some additional debug stuff that's
not normally compiled.
BUG=none
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I32b4944c01006f2e9c8cdb2e732a4b1710a60e19
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317560
The startup message includes the type of the image it is running (RO
vs RW currently). cr50 reports RW as RO, which this patch fixes. This
issue requires a bit more attention though: first, the RO type can be
deduced at compile time. Second, RW and RW_B should be accommodated.
RW_B should also be accounted in other places in the code where now
only two options are considered: RO vs RW.
BRANCH=none
BUG=chromium:567938
TEST=the startup message now reads:
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: RW, cr50_v1.1.4162-f1e71a6-dirty 2015-12-08 16:39:00 vbendeb@eskimo.mtv.corp.google.com]
Change-Id: I0db2db4413a13ebe915e1081b47cd4a6f85cbdd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316922
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds a setup script for the ec3po package. This is
necessary such that ec3po can be included as a part of ec-devutils.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=Update the ec-devutils ebuild to install the ec3po package.
sudo emerge ec-devutils; `python -c 'import ec3po'; print ec3po`
in the chroot. Verify that ec3po is installed in the site-packages.
TEST=Verify that interpreter and console modules are exported in the
package.
CQ-DEPEND=CL:316479
Change-Id: I5c8856b530936dc4ce3b09e38802f1e015c4576b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316701
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
It was brought to my attention that there were some issues with the
ec3po code. This commit addresses those issues raised.
- executable bits dropped from __init__.py and interpreter.py.
- sys.argv[1:] is now passed into console.py:main().
- Added blank lines at top of header.
- Removed dummy exception class (MoveCursorError).
- Added name of modules in the logger, so that it's not just 'root'
when included in other modules.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=./util/ec3po/console_unittest.py -b
TEST=./util/ec3po/interpreter_unittest.py -b
TEST=cros lint --debug ./util/ec3po/console.py
TEST=cros lint --debug ./util/ec3po/console_unittest.py
TEST=cros lint --debug ./util/ec3po/interpreter.py
TEST=cros lint --debug ./util/ec3po/interpreter_unittest.py
Change-Id: I00db368906958d1089c3662eb253be23f81cc70c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Newer versions of glibc have moved to _DEFAULT_SOURCE and away from
_BSD_SOURCE. Trying to use the BSD define by itself leads to warnings
which causes build failures.
BRANCH=none
BUG=None
TEST=precq still works
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Change-Id: Ice24b84dc6a540695fc7b76e8f22a4c85c301976
Reviewed-on: https://chromium-review.googlesource.com/316730
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we haven't sent a stop condition, make note of that, and send a
repeated start next time.
BUG=chrome-os-partner:48294
BRANCH=None
TEST=Verify "ectool i2cxfer 1 0x25 1 2" succeeds on glados. Also verify
`i2cscan` on EC console succeeds.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id45bfc6540dc1cc3a3d1e9f6916a238bce5ae33f
Reviewed-on: https://chromium-review.googlesource.com/316022
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When AP is suspended, only predefined events could wakeup AP.
Check EC_MKBP_EVENT_KEY_MATRIX event when we use embedded keyboard to make AP
wakeup from S3 power state.
BRANCH=none
BUG=chrome-os-partner:47554
TEST=Enter "powerd_dbus_suspend" in AP console to make system
suspend and then press embedded keyboard to wakeup AP.
Change-Id: I79f91776c39554a4e488e50841d3537fe85fea13
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/312156
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
two port PD will keep interrupt low, and cause
EC.PDCMD task stuck with exchange status loop before
entering task-while-loop
BUG=chrome-os-partner:48232
BRANCH=lars
TEST=`make BOARD=lars -j`, OS can boot up normally
Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/315362
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add 2 bytes into the TX byte count register used in
TCPC interface.
BUG=chrome-os-partner:48256
BRANCH=none
TEST=load on glados and attach zinger, make sure
PD negotiation successful.
Change-Id: Ie57d79f20def861c22f6e2e023545a65825ab3b4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315879
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previous HW didn't correctly support 20V charging. The HW has been
corrected and now there is no need to keep 20V mode disabled in FW.
BUG=chrome-os-partner:48217
BRANCH=none
TEST=Tested in the lab by jguerin@ against Samus
Change-Id: I952872affb302c7aa2ddb97466cd5ce459d2ac54
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315219
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow boards to customize both the PWM frequency / period and the
enabling of complementary output signals.
BUG=chrome-os-partner:48044
TEST=Manual with snoball w/ subsequent commit. Run `pwm <ch> 50` for
each channel, verify with `adc` that each PD output voltage is
approximately VBUCK / 2.
BRANCH=None
Change-Id: I61cbb4a5b656f41ec7cec59339f5247902256295
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315141
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If we're still in DISCONNECTED or DISCONNECTED_DEBOUNCE state, don't check
CC lines to detect a disconnect since CC polarity has not yet been
established.
BUG=chrome-os-partner:48220
BRANCH=None
TEST=Verify PD contact can be negotiated on Snoball with either polarity.
Change-Id: Iacde14446c0ff5d2170936b650f56668038f613e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315780
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
A new extended subcommand code (1) is being added to handle hash
testing.
The new subcommand handler keeps track of multiple sha1 and sha256
contexts the host might want to exercise. The number of available
contexts is limited by the amount of available free memory.
One of four hash operations could be requested by the host: 'Start',
'Continue', 'Finish' - when hashing a single stream over multiple
extended command messages, and 'Single' when the entire message to be
hashed is included in one extended command payload.
The command payload had the following format:
* field | size | note
* ===================================================================
* mode | 1 | 0 - start, 1 - cont., 2 - finish, 3 - single
* hash_mode | 1 | 0 - sha1, 1 - sha256
* handle | 1 | seassion handle, ignored in 'single' mode
* text_len | 2 | size of the text to process, big endian
* text | text_len | text to hash
As soon as the first 'Start' message is encountered, the handler tries
to allocate shared memory to keep track of the test contexts, the
amount of available memory determines how many contexts the handler
can support concurrently.
As soon as the last 'Finish' command is encountered, the handler
returns the shared memory to the 'heap'.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=after adding the host side implementation and fixing a couple of
bugs, hash tests pass (see upcoming patches).
Change-Id: Iae18552d6220d670d1c6f32294f0af1a8d0d5c90
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314692
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Currently the EC waits until it reads a battery status with the flag
STATUS_INITIALIZED set, but the EC does not use this flag for charging
or any other battery operation. If this flag is not set, it does not
mean that the battery is unusable, it just means that its values may not
be trustworthy.
This change will remove the check for STATUS_INITIALIZED and just check
that the battery responds. The battery response shows that the battery
is connected and can be used by the EC.
BRANCH=none
BUG=chromium:564893
TEST=see that device without STATUS_INITIALIZED set will exit
battery_wait_for_stable() without timing out.
Change-Id: I07778e8570b6d9400b61beec6b2e222984a40692
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315200
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When none of temp sensors' temp/fan speed profile is not set(zero),
thermal control will set 0% duty over initial fan speed setting.
This patch allows fan under EC control at inital max speed
till host's DPTF sets proper fan speed.
BRANCH=master
BUG=none
TEST=1. check if fan is running at max speed until ChromeOS UI comes up.
2. check if fan is running when system is in recovery mode.
Change-Id: I1b3e69b003ba1045779e263b25ac35b103fe457e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314363
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Stack space is pretty tight on cr50, and since there is no need to
support SHA digest sizes in excess of 256 bits, the digest buffer size
should be reduced.
This patch makes the maximum expected digest size dependent on the set
of configured hash algorithms, moves hash size related asserts from
run time to compile time, and passes compile time definition to the
TPM2 library to increase its hash state container (it became too small
when SHA384 was disabled).
The sw context requirements should be reduced, but this is a task for
another day. We also do not have to store a local digest copy if the
API allowed reading a partial digest.
CQ-DEPEND=CL:314883
BRANCH=none
BUG=chrome-os-partner:43025, chromium:564862
TEST=all tests pass:
$ ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
SUCCESS: AES:CTR256I 1
SUCCESS: sha1:single 0
SUCCESS: sha256:single 0
/New max timeout: 1 s
SUCCESS: sha256:finish 1
SUCCESS: sha1:finish 3
SUCCESS: sha256:finish 2
Change-Id: Iaef3a230469de129e72418814e1d113b447c0137
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314695
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Set alternative pin from GPIO to CLKRUN if SERIRQ is under quiet mode
Once we need LCLK, CLKRUN will pull low automatically.
Modified drivers:
1. lpc.c.: enable CLKRUN functionality for SERIRQ no matter continuous or
quiet mode.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I58b11340833b26bc64bfe499272fd3b319b33202
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/314971
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new module generates hash test extension subcommands, driven by
the 'test_inputs' table.
Each table entry is a tuple, including the test name and the data to
be hashed. The test name determines the hash type (sha1 or sha256) and
the test mode (single or spread over several messages). The last
element of the name is the context number (ignored in single message
mode).
The hash extended command payload looks as follows:
field | size | note
===================================================================
hash_cmd | 1 | 0 - start, 1 - cont., 2 - finish, 4 - single
hash_mode | 1 | 0 - sha1, 1 - sha256
handle | 1 | session handle, ignored in 'single' mode
text_len | 2 | size of the text to process, big endian
text | text_len | text to hash
BRANCH=none
BUG=chrome-os-partner:43025
TEST=currently failing, a couple of hash code tweaks needed, see
upcoming patches.
Change-Id: Ie992bf01cae3c5278110357b482370b2fc11c70f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314693
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is a no-op change moving some common code out of tpmtest.py,
preparing it to support different testing modes.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=the AES test still succeeds:
$ test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
SUCCESS: AES:CTR256I 1
Change-Id: Ia6e0e3e89f99875297da0a4f6137de5901c8ca08
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314691
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If pulled up the backlight will be at 100% brightness instead of off.
BUG=chrome-os-partner:48130
BRANCH=none
TEST=hibernate on chell, see keyboard backlight stay off
Change-Id: I30cd289b9492356407aa54e6a84b04add647bd9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314936
Reviewed-by: Shawn N <shawnn@chromium.org>
The extended command code is fixed, there is no need to pass it as a
parameter when calling functions wrapping and unwrapping extended
commands.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=AES tests still pass:
$ ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
-New max timeout: 1 s
SUCCESS: AES:CTR256I 1
Change-Id: Ic0c9d7983755de8380b57e841891fd638ef2c62a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314690
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Stack of PDCMD task may be overflow during plug/unplug stree test
with Apple's AV Multiport Adapter. Enlarge the stack size to avoid
system reboot.
BUG=chrome-os-partner:47728
BRANCH=none
TEST=Manual
1.Connect DUT to sink monitor via HDMI dongle.
2.Unplug HDMI USB from DUT side.
3.Plug HDMI USB cable to DUT USB socket.
4.Repeat (Plug and unplug) USB from DUT for 10 times.
Change-Id: Ib6a1fbd0a552b2c6d4656c12554e1306c21adb8a
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/315020
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This just replaces a few manually created macros in
chip/g/registers.h with a more programmatic version based on
names in chip/g/hw_regdefs.h.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: I73ee2ee1ee3f53a0939000822c552deace46f154
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314937
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Use some meaningful macro names instead of just raw numbers when
selecting the correct USB phy port. Also we only need to do this
once, since it should be sticky through anything short of a
complete power down.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall; run it
No new functionality, just refactoring.
Change-Id: If6ea2b9d9a62bf6ce4adaed1c5aac1f66013ebeb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314938
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
When Link Time Optimization is turned on, functions that set
task_waiting multiple times have one of the sets removed
by the linker leading to undesired results.
Marking task_waiting volatile alleviates this issue.
BUG=chrome-os-partner:46063
TEST=Manually tested on Kunimitsu.
Console command adc shows correct value of approx
20000 mV for VBUS.
BRANCH=none
Change-Id: I85a6e5c9688ae72c45d90fb58296f94b74a301aa
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314233
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
From the "Device Class Definition for Human Interface Devices" spec:
When a Get_Descriptor(Configuration) request is issued, it
returns the Configuration descriptor, all Interface
descriptors, all Endpoint descriptors, and the HID descriptor
for each interface. It shall not return the String descriptor,
HID Report descriptor or any of the optional HID class
descriptors. The HID descriptor shall be interleaved between
the Interface and Endpoint descriptors for HID Interfaces. That
is, the order shall be:
Configuration descriptor
Interface descriptor (specifying HID Class)
HID descriptor (associated with above Interface)
Endpoint descriptor (for HID Interrupt In Endpoint)
Optional Endpoint descriptor (for HID Interrupt Out Endpoint)
This makes that happen.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=manual
"make buildall" works, this image seems to work on the Cr50.
Also, before this CL, I see this:
0x00060f5c 0x00000000 .rodata g NOTYPE __usb_desc
0x00060f5c 0x00000009 .rodata g OBJECT usb_desc_conf
0x00060f65 0x00000009 .rodata g OBJECT usb_desc_iface0_0iface
0x00060f6e 0x00000007 .rodata g OBJECT usb_desc_iface0_1ep0
0x00060f75 0x00000007 .rodata g OBJECT usb_desc_iface0_1ep1
0x00060f7c 0x00000009 .rodata g OBJECT usb_desc_iface1_0iface
0x00060f85 0x00000007 .rodata g OBJECT usb_desc_iface1_1ep81
0x00060f8c 0x00000009 .rodata g OBJECT usb_desc_iface1_2hid
0x00060f95 0x00000000 .rodata g NOTYPE __usb_desc_end
and after, this:
0x00060f5c 0x00000000 .rodata g NOTYPE __usb_desc
0x00060f5c 0x00000009 .rodata g OBJECT usb_desc_conf
0x00060f65 0x00000009 .rodata g OBJECT usb_desc_iface0_0iface
0x00060f6e 0x00000007 .rodata g OBJECT usb_desc_iface0_2ep0
0x00060f75 0x00000007 .rodata g OBJECT usb_desc_iface0_2ep1
0x00060f7c 0x00000009 .rodata g OBJECT usb_desc_iface1_0iface
0x00060f85 0x00000009 .rodata g OBJECT usb_desc_iface1_1hid
0x00060f8e 0x00000007 .rodata g OBJECT usb_desc_iface1_2ep81
0x00060f95 0x00000000 .rodata g NOTYPE __usb_desc_end
The HID descriptor comes before the endpoint.
Change-Id: I8035a4cc884d8bb900bc1eb25fd3e4e9aba05bf8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314832
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
refer to commit 75f740fa, enabling the option on oak too.
BUG=none
BRANCH=none
TEST=plug in CDP, SDP, DCP, type-C, and PD charger. Make sure
we ramp to a reasonable value for the correct suppliers.
Make sure we don't ramp for type-C and PD chargers.
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Change-Id: I9c6a0726e9cb23af59d5841c63a81897ae624998
Reviewed-on: https://chromium-review.googlesource.com/314436
Reviewed-by: Alec Berg <alecaberg@chromium.org>
It is possible for the ALS state machine and the chip to not
agree: The EC thinks the device is busy making a measurement,
while the chip is waiting for the IRQ status register to be written.
It is not clear how it happened, an IRQ must have been lost.
Reinitiliazed the chip is stuck for 10s.
BRANCH=smaug
BUG=chrome-os-partner:45627
TEST=With an extra patch that force the IRQ handler to not do anything
every 100th, check the device recovers.
Use andro sensor to monitor light/proximity outputs.
Change-Id: I80d50bf92af127f85f82dc5c0ae318d4cfe06812
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313668
Add i2cscan and kbpress commands for FAFT.
Remove unnecessary i2c reading since there is no race condition.
Bugs fixed:
Fixed i2c_read_string bug since we shouldn't enable NACK if flag doesn't
contain I2C_XFER_STOP.
Fixed i2c_unwedge bug since the parameter should be port not controller.
Fixed state machine bug since we should restore bus state back to idle
if bus encountered timeout.
Modified drivers:
1. board.h: Add i2cscan and kbpress commands for FAFT.
2. i2c.c: Remove unnecessary reading since there is no race condition.
3. i2c.c: Fixed i2c_read_string and i2c_unwedge bugs.
4. i2c.c: Restore to idle state if bus encountered timeout.
5. board.h: Add CONFIG_LOW_POWER_IDLE for better power consumption.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I98974f852cbbaec270c697feb8016b52550005bc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/313393
Reviewed-by: Randall Spangler <rspangler@chromium.org>
cl/301134 has a bug. If the AP wants a forced sensor (i.e. light) at
100Hz but a sampling frequency at 1s, we would still wake it up every
.1s instead of 1s.
Take in account force mode only when calculating the sampling frequency
not the interrupt interval.
BRANCH=smaug
BUG=b:25425420
TEST=Check the device goes to suspend even with 40Hz light sampling
rate:
echo 0 > /sys/bus/iio/devices/iio:device0/frequency
echo 40000 > /sys/bus/iio/devices/iio:device3/frequency
echo mem >/sys/power/state
Before it would resume just after suspend/while suspending.
Change-Id: Ie4fe36268cb1b04bc8f01ec885af84fad9e8b282
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314315
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If proximity overflow (daylight), we would still assume the data was valid
and consider there is an object very very close.
That would prevent the light to be measured. (cl/312982)
Leave the value as max range for the HAL to handle.
BRANCH=smaug
BUG=b:25573958
TEST=Check in daylight that light is still measured
Change-Id: I684e6f4a9aecd3fd6b338a9939f7ede26752ecb8
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314921
Reviewed-by: Alec Berg <alecaberg@chromium.org>
We support two FPGA images with the same firmware. To meet
timing, one image has support for USB but at the cost of reducing
the crypto multiplier to 8x8. The other image has full crypto but
no USB support.
This change displays the FPGA configuration at boot, in addition
to the FPGA image version.
BUG=b:25350751
BRANCH=none
TEST=make buildall, manual
Boot it and watch the console. You should see something like
this:
cr50 bootloader, 20151118_73026@80895, +USB, 8x8 crypto
Valid image found at 0x00044000, jumping
Change-Id: I0e5de453fcd1714fcbb170bf4364747b1e7ba894
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314824
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When sensor_shutdown() is called, the sensors may already been powered
off, or will be soon.
In that case, do not attempts to access them.
Check their state before setting range or disabling activities.
BRANCH=smaug
BUG=chromium:557966
TEST=compile
Change-Id: I60640b120a23f9aab393a93c4c67ef17222ced4e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314382
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since two port may cause some unexpected problem in a
one port board.
I've cloned this from glados_pd without any code changes
and I'll remove the second port settings at another CL.
BUG=None
BRANCH=lars
TEST=`make BOARD=lars_pd -j`
Change-Id: I84b3d2fa705ff089aabd52ab71d9fb59eecdd027
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/314637
Reviewed-by: Shawn N <shawnn@chromium.org>
Depending on timing, additional important messages may reside on our RX
FIFO at the time we process GoodCRC. Therefore, rather than flushing the
RX FIFO, simply read and discard the GoodCRC message.
BUG=chrome-os-partner:314492
BRANCH=None
TEST=Manual on Snoball with subsequent PWM changes. Verify PD contact
can be established with samus.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4f4fab1bc318d1bce1effffad9a792c5b4a43761
Reviewed-on: https://chromium-review.googlesource.com/314871
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
