Values should be as follows:
tTypeCSinkWaitCap: 310 to 620ms
tPSHardReset: 25 to 35ms
Current values are:
tTypeCSinkWaitCap (PD_T_SINK_WAIT_CAP): 240ms
tPSHardReset (PD_T_PS_HARD_RESET): 15ms
BUG=chromium:686122
TEST=manual testing on kevin along with make -j buildall
- used a kevin to send a hard reset to uut
> pd 0 hard
C0 st36
C0 st37
34725 ms <-- time it took hard reset to execute
C0 HARD RST TX
- used a kevin, operating as source, that does not send
source caps to test a uut operating as a sink.
C0 st6
C0 st36
613266 ms <-- time sink waited for source cap
- plugged in charger and logged pd negotiation
[1510.574091 event set 0x00200000]
C0 st15
C0 st3
[1510.845115 event set 0x08000000]
C0 st6
Req C0 [1] 5000mV 3000mA
[1510.945827 New chg p0]
C0 st7
[1510.949953 CL: pC0 st8
0 s0 i500 v15000]
[1510.954055 event set 0x00200000]
[C0 st9
1511.061285 event set 0x00400000]
[1511.064752 CL: p0 s0 i3000 v5000]
[Req C0 [3] 15000mV 3000mA
1511.067538 event set 0x00200000]
C0 st7
C0 st8
[1511.077896 CL: p0 s0 i500 v5000]
[1511.079048 event set 0x00200000]
C0 st9
[1511.275448 CL: p0 s0 i3000 v15000]
[1511.276913 event set 0x00200000]
Req C0 [3] 15000mV 3000mA
[1511.445719 CL: p0 s0 i500 v15000]
[1511.446117 event set 0x00200000]
C0 st7
C0 st8
C0 st9
[1511.565730 CL: p0 s0 i3000 v15000]
[1511.566566 event set 0x00200000]
[1511.812205 event set 0x00400000]
[1513.274941 event set 0x00200000]
[1529.324670 Battery 90% / 0h:29 to full]
BRANCH=none
Change-Id: I6e80637cfc50dcfc431feb0e473ec22f408d6f1a
Reviewed-on: https://chromium-review.googlesource.com/434103
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Defined the config option CONFIG_USB_PD_DTS to board.h.
- Added ccd_set_mode function in board.c
- Removed ccd attach/detach functions from board.c as that function is
- now integrated in the the usb_pd state machine.
- Removed the fixed polarity that was being used in usb_pd_config.h so
that the DUT port could connect as a SNK device.
- Defined PD_ROLE_DEFAULT to override the value in usb_Pd.h so that
CHG is SNK and DUT is SRC
This set of changes allows servo_v4 to act like a suzyq. Hoever, PD
messaging is still not supported. The CHG port can still connect as a
SNK device, but VBUS on the DUT is only being provided by the host and
not the CHG port.
BUG=chrome-os-partner:61878
BRANCH=None
TEST=Manual Connected zinger to CHG port and verifed via servo_v4
console that it reached SNK_READY. Connected DUT port to Reef and
verified that it reached SRC_ACCESSORY state and that the correct SBU
polarity was selected and that lsusb shows H1 as a USB device.
Bus 003 Device 042: ID 18d1:5014 Google Inc.
Change-Id: I4a0ab2468f383a3ba4db3a3236bb18df6a2c405a
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428309
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The cipher command implementation had to change to account for reduced
heap size and to improve coverage.
Note that the goal of this command is not to verify correctness of the
encryption services provided by the dcrypto, but to allow to exercise
the crypto engine on multiple passes, each time using the same clear
text but different initialization vector.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=ran cipher command on a few devices:
> cip
Will wait up to 4074 ms
running 1000 iterations
blob size 7111 at 1e020
original data 8f3d99fbfcbd26dd0c4d8dc444d106ee
hashed data 826a4e9b04d214fbbd5fbf4e0fba8068
Encryption results: min 1128 us, max 1456 us, average 1180 us
Decryption results: min 1124 us, max 7348 us, average 1193 us
>
Change-Id: Idf72b355dce0f288d4a3d8a065bc08eb9c4f6bc3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434167
Reviewed-by: Nagendra Modadugu <ngm@google.com>
All host commands must be 4-digit uppercase hex digits.
EC_CMD_HOST_EVENT_GET_WAKE_MASK is currently defined as 0x008d
BUG=chrome-os-partner:62518
TEST=make -j buildall
100bcffc R __host_cmd_0x00000x0087
100bd008 R __host_cmd_0x00000x008C
100bd014 R __host_cmd_0x00000x008D
100bd020 R __host_cmd_0x00000x008F
100bd02c R __host_cmd_0x00000x0092
BRANCH=none
Change-Id: If2460efa7453e8007514b10dd9a973120006c7e1
Reviewed-on: https://chromium-review.googlesource.com/435581
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This change explicitly sets the GPIO pin connected to the trackpad
IRQ gate low. The GPIO output registers are reset to zero.
So, this patch doesn't practically change anything.
BUG=chrome-os-partner:58792
BRANCH=none
TEST=Verified the value was 0 by gpioget command and the trackpad was
functional on a current Electro & a reworked Electro.
Change-Id: I52fec1efdd29453ee121cf1705242d877c0c4f1f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch locks the ec.
This also locks PD communication until sysjump to RW.
We don't want to allow communication to outside world until
we jump to RW. This can by overridden with the removal of
the write protect screw to allow for easier testing.
Electro doesn't operate on 15w power normally but 15w is enough for
recovery process.
BUG=chrome-os-partner:62487,chrome-os-partner:61801
BRANCH=none
TEST=flash -p ec --wp-enable.
Boot, shutdown, suspend, resume, & charge Electro. Run recovery
process with battery 2% charged and a charger on port 0.
Change-Id: I634291c00eb471e24ed2b06444302d9e2e42bbc8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/435005
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We wanted to reduce the number of interrupts that uart was producing so
we increased the number of characters needed in the fifos before it
would trigger an interrupt. Right now it needs 4 characters. If you
aren't printing a multiple of four characters, then not all text will be
printed.
This change changes the rxilvl back to 1. This will make using the
consoles and testing cr50 functionality more reliable.
BUG=chrome-os-partner:62158
BRANCH=none
TEST=login and boot still work fine. The AP and EC consoles print all
output correctly.
Change-Id: I2d48d02a275173d560c03e5363845a5afc94df7a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434891
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Eve has two 3 color PWM controlled LEDs. This CL adds basic support
for these LEDs so that they can be set to off, red, green, or blue. In
addition, the LED policy from Kevin is appropriated.
In S0 the LEDs will be blue.
In S3/S5 if no charger is connected, then the LEDs are off
If a charger is connected and the charge level is less than a
threshold, both LEDs are set to red. When the charge level gets above
a certain level or if the charge state is idle, then the LEDs are set
to green.
BRANCH=none
BUG=chrome-os-partner:60797
TEST=manual
Turn the system on so it's in S0, verify both LEDs are blue.
Close the lid with no external charger and verify that the LEDs are
both off. Connect the charger, and using battfake <> EC command verify
that when the charge level is less than the threshold the LEDs are
red, otherwise they are green. Set battfake to 0, and verified
flashing red.
Change-Id: I556ccdafde03cd5f5205e8948d5737dcbdc09d6d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434146
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
The current strap pin logic was checking for case of no pullup
resistors detected on either pair of strap pins, but did not check
explicitly for at least one pullup on each pair or strap pins. This
condition, which isn't expected, is an invalid configuration and
therefore can't be used to determine either SPI vs I2C or as a table
lookup entry.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Tested on Eve which has 4.7k pullup resistors to PP3300_A this rail is
not going down as expected. The result is that a pullup is read on
DIOA6 which is expected and strong pullups are read on
DIOA9|DIOA1. With this CL the strapping pin logic produces the
folloiwng output:
--- UART initialized after reboot ---
[Reset cause: hard]
[Image: RW_B, 0.0.14/DEV/cr50_v1.1.5933-18d527f
tpm2:v0.0.286-21er-linux.mtv.corp.go]
[0.004160 Inits done]
[0.005476 Invalid strap pins! default properties = 0x42]
Change-Id: Ibe85bc55d62b4c060b6c39629a225edc6d1dc341
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433146
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
For device that are using ceramic caps, when battery is full, discharge
to 97% and then charge again until the battery is full. This should also
help us meet CEC energy spec.
BUG=chrome-os-partner:56255
BRANCH=gru
TEST=Manual on kevin, insert charger with battery at 97%, verify battery
does charge until 100%, and then discharge down to 96% and verify battery
charges. Charge to 100% again.
Change-Id: I5099cbbb1228823cc611c456e7e3d8311f1c94d6
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/434220
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic8db5c706d82f7ca2ded2e90129747e7fbefdb38
Reviewed-on: https://chromium-review.googlesource.com/427959
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I49ea5fc27a7f11f66daba485a87d0dfe7d0c770f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427408
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The previous implementation of DCRYPTO_app_cipher
consumed roughly 16ms to cipher a 16kB buffer
(i.e. performance that is far worse than the
hardware is capable of).
This change speeds up the implementation by about
85%, to the tune of roughly 2.2ms for a 16kB buffer.
The gains originate from various sources: loop
unrolling, data-pipelining, eliminating local
variables (to reduce register pressure), eliminating
support for unaligned input/output data, compiling
hot code with -O (rather the default -Os), and
using the hidden key-ladder, which need only be
setup once per reset.
This change also switches from AES-128 to AES-256.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=make buildall succeeds;
cipher command succeeds;
TCG tests pass
Change-Id: I133741be6d9f1353d6ae732d0e863b4b18cc8c9e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433359
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This vendor command allows the host to retrieve the internal TPM
state. The first version of the command will return the failure
information collected during assert, if it ever happened, retry
counter value and the maximum retry counter value to be able to detect
if TPM is in lockout.
The structure is packed, it is serialized before being sent to the
host.
BRANCH=none
BUG=chrome-os-partner:60555
TEST=when running on a reef with a depthcharge image capable of
displaying TPM state on errors observed state information added
to the recovery screen text display.
Change-Id: I9d37f7a971013ce802f63218d43697fab68276c9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430952
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Add support for verifying messages signed
with 4096-bit RSA keys. Such messages may
be generated by host side applications.
Also update tpmtest.py to test 4k verification.
BRANCH=none
BUG=none
TEST=added new tests to tpmtest.py; TCG tests pass
Change-Id: I7450bd710c154c68c030ce176bfe7becbfbcb729
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/428220
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
tpm_reset just requests a tpm reset it doesn't reset the tpm. Rename the
function to reflect that.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I6f4763b5de578a8cf263b2fac98fad3af2c25d65
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434245
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The nvdc voltage has a kind of deep, so that rarely observed
NVDC down at this point because of back-boosting.
Our sequence to enable charger bit and setting vsysreg
is correct but rohm introduce charger may need some more time
to be stable when between chg_en and vsys_set to start charge
BUG=chrome-os-partner:60380
BRANCH=gru
TEST=Manual on kevin, trigger battery disconnect, re-attach AC, verify
system boots cleanly. and see voltage probing on c54@60380
Change-Id: Ic05091379322ffaac16fe827a47345c76c85f3e5
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/434252
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With introduction of encryption it is becoming impossible to read
NVMEM contents directly from flash. Decrypting the contents each time
there is a read request creates a significant performance hit. NVMEM
needs to be rearchitecture such that there is no need to run
decryption each time NVMEM read is performed.
This patch does just that, implementation details are described in the
header comment in common/nvmem.c.
To reduce memory impact the size of NVMEM is being decreased from 16K
to 12K. This is acceptable because eviction objects stored in NVMEM
serialized now, which dramatically reduces NVMEM size requirements.
The TPM2 NVMEM size definition must be kept in sync.
Another optimization this change introduces is bypassing writing into
the flash if NVMEM contents did not change, which is verified by
examining the hash of the cached storage.
A test is added to verify that the new commit scheme works as
expected, and the nvmem test is re-introduced to the list of test ran
on each 'make buildall'.
CQ-DEPEND=CL:433839
BRANCH=none
BUG=chrome-os-partner:62260,chrome-os-partner:62421
BUG=chrome-os-partner:62437
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I177daa3ceb4fd7aac299ca26b4506b863e31b946
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the chroot, we use ccache to speed up compilation. However, it's
possible for this cache to become corrupt which could lead to slower
builds. In order to keep things fresh, 'make clobber' should clean up
that ccache cache as well. This commit makes it so.
Note, this is NOT *clearing* the cache entirely.
BUG=chromium:681961
BRANCH=None
TEST=make clobber; verify that ccache is cleaned.
Change-Id: I8ccd7df4858c445485ed740843f3126af0abd33a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433108
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On ANX port connecting hoho and issuing hard reset
never recovered. From TCPCI spec R1.0.4.7.2 "TCPM
writes to the RECEIVE_DETECT register to enable PD
message passing". This was missing when the port sent
HARD RESET when it acts as SRC.
BRANCH=none
BUG=chrome-os-partner:61377
TEST= On Electro, on anx port, connect hoho and issuing
pd 0 hard successfully recovers from hard rst
Change-Id: Ia2cfcaf52b88fbc24ee702c6a089389400eb42d1
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/433387
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
- Modified src attach state to enable vbus when debug accessory is
detected.
- servo_v4 has two pd ports, but each port requires a different default
power role. Port 0 can only ever be a SNK, but port 1 which acts is
intended to be a DTS port should default to a SRC so it can be be a
source debug accessory. It may also act as a sink debug accessory, but
is not intended to toggle automatically but will swap roles if
necessary via pd role swap messaging.
- Add hook for ccd enable/disable for DTS mode
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual Verfied that can still build servo_v4 project. All changes
in this CL are contingent on config option CONFIG_USB_PD_DTS being enabled.
Change-Id: Iab968b6fbdfc8f2d155c4f8618921b32f313b9ec
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428308
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Update tpmtest.py to handle a success command code
(i.e. return value of 0) as per change
12da6c23fb
This change makes the test suite runnable (not all
tests pass though - sha and upgrade tests are broken).
Also rename local variable subcmd to avoid a name collision.
BUG=none
BRANCH=none
TEST=tpmtest.py passes, except for sha & upgrade
Change-Id: I927ead775a1e41b9abf9f905b9f191e8bd5e108b
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/411535
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Enable the Clock Recovery Subsystem to automatically adjust the internal
HSI48 clock for proper USB operation on the STM32F0.
BUG=chrome-os-partner:34160
TEST=Manual testing on STM32F072B-DISCOVERY
Plugged in board and verified that device was detected with dmesg.
[1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd
[1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f
[1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[1400698.720072] usb 3-10: Product: PDeval-stm32f072
[1400698.720075] usb 3-10: Manufacturer: Google Inc.
BRANCH=none
Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236
Reviewed-on: https://chromium-review.googlesource.com/433059
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In Sink mode, on the receipt of a GotoMin message,
reduce the current consumption to some minimum level.
BUG=chrome-os-partner:33688
TEST=Manual testing
Used a Kevin, with test routine, to test GotoMin feature
on another Kevin unit.
Test routine:
if (!strcasecmp(argv[2], "gm")) {
ccprintf("send goto min\n");
send_control(port, PD_CTRL_GOTO_MIN);
send_control(port, PD_CTRL_PS_RDY);
}
Kevin with GotoMin feature:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4277mV / 3000mA, max 5000mV / 3000mA / 15000mW
Port 1: Disconnected
After Test routine is executed:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4906mV / 500mA, max 5000mV / 500mA / 2500mW
Port 1: Disconnected
BRANCH=none
Change-Id: Iaac6e19706ceb10ccaff4d602d63fc086c808c8f
Reviewed-on: https://chromium-review.googlesource.com/425728
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds a separate CONFIG check for RO and RW.
Each section is built with the objects generated
based on it's own calculated CONFIGs, so that the
object list may be different for RO and RW.
The intent is to allow for differnt sized RO and
RW partitions to allow for a small RO and lager code
space for RW, for servo_v4 and hammer.
BRANCH=none
BUG=chrome-os-partner:61170
TEST=builds successfully
Change-Id: I5549cc7ac218e0c7681108074ecfd3b80d4af545
Reviewed-on: https://chromium-review.googlesource.com/433079
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Servo_v4 requires the ability to have a different default state per
port. In previous devices, the assumption was that each supported port
had the same default usb pd state and power role. This CL moves the
by the default power role which in turn is derived from
CONFIG_USB_PD_DUAL_ROLE. In addiiton to moving the location, it now
uses 'port' as argument so it can be port specific if required.
PD_DEFAULT_STATE was a board.h specific config, but in practice each
instance used to date was set to PD_STATE_SNK_DISCONNECTED if
CONFIG_USB_PD_DUAL_ROLE was defined and set to
PD_STATE_SRC_DISCONNECTED otherwise.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual run 'make -j buildall' to verify that all instances of
PD_DEFAULT_STATE were removed.
Change-Id: Iaf40718668732f525485ed7942ee7fc246d3f75d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431787
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If common layer called i2c_xfer() with only one byte read length and the
flag is I2C_XFER_STOP, the npcx's i2c driver will return error directly.
The reason is once ec read last byte of previous transaction, hardware
will release SCL and i2c slave start to send following byte. Ec might
not have chance to generate NACK in time. A additional dummy byte is
necessary to make sure ec generate NACK before STOP condition.
BRANCH=none
BUG=chrome-os-partner:60266
TEST=make BOARD=pyro; test battery command on pyro with CONFIG_CRC8 and
CONFIG_SMBUS.
Change-Id: I372ff494b49656cbfbd4044b99b00b13daf0b741
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/430569
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 66828807af.
I messed up this port, and only got half of the commit. Even with the
other half it still seems to break charging completely and needs more
investigation. Remove it all for now.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=ensure Eve P1 charges properly when charger attached after boot
Change-Id: I0219c397ae420738d85d8b437cf89c067f014c5e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431005
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(From CL 431233)
Limit battery charge voltage to prevent battery over-charge, due to
regulation inaccuracy. Since RO FW may charge > 8656 mV, ensure the
battery is not full before charging.
BUG=chrome-os-partner:61906
BRANCH=none
TEST=Manual on Electro, sysjump with battery @ 99%, verify battery
discharges, then re-charges to 100%, before discharging once again.
Change-Id: I28212c83057a442fd75e39f8ad51927a7a1f2817
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/432857
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes incompatible changes to the nvmem layout: the header
is increased to accommodate a 16 byte sha ans a 16 byte padding for
future extensions.
The layout version field is also introduced to make it easier to track
changes in the future. When calculating SHA the entire partition above
the SHA field is processed. Encryption covers everything above the
header.
Introducing encryption makes it impossible to use flash contents
directly for read and compare operations.
The nvmem_setup function is modified to use the nvnem_save() instead
of writing into the flash directly.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I50b148ac0dc6bc924f4d65c67bc6610100d9dfc0
Reviewed-on: https://chromium-review.googlesource.com/428691
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On boards based on the g chip cryptographic functions come from
hardware, they should be implemented in chip/g as opposed to a
particular board.
The common modules (like nvmem) should be using some generic API,
which hopefully will be implemented by other chips, or could be
replaced by a purely software implementation where crypto hardware
support is not available.
Crypto API definition is being added in include/ and the g chip
implementation (a wrapper around dcrypto functions) is being added in
chip/g.
test/nvmem_vars.h needed to be edited to avoid conflict with
<string.h>.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=make buildall -j still passes. Booting reef with the new image
works fine too.
Change-Id: Ifef281215f89239966882ecbe3e90c8351b9b91a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431313
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
ISL9238 is able to measure currents when battery is discharging
(like ISL9237), and charging (new feature).
Reverse AMON (OTG output current) is also supported by ISL9238,
but isn't very interesting on our boards.
BRANCH=none
BUG=chrome-os-partner:61166
TEST=Plug charger, "amon" in EC console, check that values match
current meter + "battery" information. Unplug charger,
values match "battery" information.
Change-Id: I9ecae6bec9e2049d17ef1a4596dbd4e3ff59919e
Reviewed-on: https://chromium-review.googlesource.com/430474
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously only 1 pin DI0A1 was being read to distinguish between
SPI/I2C configurations. This change adds code to support reading 4
strapping pins DIOA9|DIOA1 and DIOA12|DIOA6 and enabling the internal
pullup/pulldown reistors to differentiate between weak and strong
external pull up/dn restistors. An 8 bit strap config id is produced
and then a config table is searched to match the config id with known
configuraitons. The board properties to be used are read from the
config table.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Modified the Cr50 dev board with 1M and 5k pullup/pulldown resistors
and connected them to 4 GPIOs (defined as strapping pins). Tested the
12 possible external pullup/pulldown configurations and verified that
the correct 5 bit value was produced for each configuration.
Tested with both Reef and Gru. On Reef the strap config = 0x12 and on
Gru it reads 0x2 as expected. Verfifed TPM was functional on both systems.
Change-Id: I18c625a2b6b904bf4bcdaf2665ed9c3cbdafeb54
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421580
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change attaches all events related to changes in the AP state to
hooks. Different boards will be using different mechanisms to detect the
AP state, so we shouldn't have anything tied directly to the detection
mechanism.
BUG=none
BRANCH=none
TEST=device detection still works and AP uart is still enabled/disabled
based on the AP and Servo state.
Change-Id: I423bb8a21a1d4adf06809437f646c563551fdb12
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With upcoming versioning of NVMEM contents let's replace term
'version' with term 'generation' in the existing nvmem implementation.
Generation would allow to tell between two instances of NVMEM stored
in flash memory. The upcoming version field in the header will be used
to tell between different nvmem layouts.
This patch was created by invoking the following command:
sed -i 's/VERSION/GENERATION/g;s/version/generation/g' \
common/nvmem.c include/nvmem.h test/nvmem.c
and then editing a few remaining capitalized instances.
This also fixes nvmem test broken by an earlier patch.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=the following tests succeed:
make buildall -j
TEST_LIST_HOST=nvmem make runtests
booitng reef with cr50
Change-Id: I96e52dc93ca7c52c55794ba3e8c2774571212de0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431312
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Move GPIOs around so that VBUS detection is done via 2 GPIOs on
the EC side.
BRANCH=none
BUG=chrome-os-partner:61098
BUG=chrome-os-partner:61929
BUG=chrome-os-partner:61997
TEST=Rework board, VBUS detection works on both ports.
Change-Id: I5021b0877eff2e5710a42c7ba244faa557a361cb
Reviewed-on: https://chromium-review.googlesource.com/428485
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Base has 5.1K pull-down on detection pin, and there is a 100K
pull-up in the lid.
Accepts ADC values between 140 mV and 180 mV (4.4K to 5.8K) to
detect the base, and debounce for 5 ms. These values should be
verified later on with real hardware.
BRANCH=none
BUG=chrome-os-partner:61970
TEST=Manually with 5.1K resistor between BASE_DET_A and GND.
Change-Id: Ifded8475b06f8245e2636aa683beb0d2d0a9721d
Reviewed-on: https://chromium-review.googlesource.com/428733
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Each device keeps track of the last known state. If device_set_state
updates the device state to a new known state, then return true. Cr50
uses this returned value to check if the state has changed instead of
calculating it itself.
BUG=none
BRANCH=none
TEST=device detection still works
Change-Id: I8afac178c2c731def6f4f62ff7023fe169ec1479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also program EC_PLATFORM_RST as an out signal from the EC.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Compiles successfully for eve.
Change-Id: I41486e6050727ca822a27054244da3fed5ee3b7a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431194
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
