1. PD vender suggests to use chip default address setting (0x16).
2. Clean up board_print_tcpc_fw version function and related define.
BRANCH=None
BUG=None
TEST=Plug in type-c device and check behavior
Change-Id: I44b7156c914b8de67630696e4534147cc3b7f2c3
Reviewed-on: https://chromium-review.googlesource.com/469449
Commit-Ready: Lin Cloud <cloud_lin@compal.com>
Tested-by: Lin Cloud <cloud_lin@compal.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Before entering standby mode, bit 7 (cable_det) or analog_ctrl_0 is
cleared. This allows a new cable detect event to trigger the EC to
put the ANX4329 into normal mode. However, in some cases such as when
in S3/S5/G3 chipset power states a port will be in sink only mode and
therefore won't attach when a sink only adapter is connected to the
port. This results in the an indefinite toggle of standby<->normal
mode transitions. This constant toggle floods the EC console and more
importantly prevents the ANX4329 from remaining in standby mode and
the power consumption remains at ~9.5 mW instead of ~1.2 mW when no
adapter is connected.
This CL adds logic around clearing the cable_det bit so that it's only
cleared if both CC lines are open or if an Emark cable is
attached. Emark cable is determined from the presence of Ra on one CC
line and no Rd on the other CC line. The special consideration for an
Emark cable is reqiured because when an Emark cable is connected, the
USB PD auto toggle state may require some number of iterations until
the attach event is recognized.
In order to support handle cases where the drp mode is changed via
either the EC console command or host command, added a call to
tcpm_set_drp_toggle whenever the drp state is updated. Since the drp
mode is updated upon chipset resume events, the chipset resume hook in
board.c for anx74xx_cable_det_handler() became redundant and hence it
was removed.
BUG=b:35775019,b:35586188
BRANCH=reef
TEST=Tested the following cases:
- Sink, source adapters in chipset S0. Verified that adapters
connected as expected. Also, used Emark cable to connect to both USB
PD chargers (source) and Pixel phone (sink).
- Run 'lidclose' on EC console then connect Type C -> A adatper
[3490.370125 TCPC p0 reset!]
[3490.389588 TCPC p0 Low Power Mode]
It no longer toggles indefintely and after running 'lidopen' verified
that port 0 is now in SRC_DISCOVERY.
- In S3/G3 connected USB PD charger with regular and Emark typeC
cable. Verified that port 0 is in SNK_READY state.
- use 'pd dualrole sink' and test with Type C -> A adatper. Verified
that tcpc wakes up, but goes into standby mode until entering 'pd
dualrole on'.
- When sink only adapter is connected in S3/G3, measure power level
~1.2 mW as opposed to ~10 mW in S0.
- Repeated similar tests on port 1 (parade tcpc) to verify that
adapters connected as expected.
Change-Id: Ib8de666f72723934186fee7869f9dda01381c7a8
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/463991
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: S Wang <swang@analogix.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The cable_det signal is used to signal to the EC that the tcpc has
detected a cable being connected when low power mode is
configured. The driver then needs to take the tcpc out of suspend
state by setting PWR_EN and RESET_N high. Then bit 7 of analog_ctrl_0
needs to be set properly.
The code that is handling this transition was attempting to access the
tcpc via I2C before putting the chip in normal mode when
transitioning from suspend to normal. In addition there are issues
with calling the driver function directly from the hook task (in the
delayed ISR handler) and from the USB PD task.
This CL changes the delay ISR handler to only set the TCPC_RESET
indication so that the call to put the ANX3429 into normal from
standby to normal mode only happens in the USB PD task. The TCPC_RESET
event is only set if cable_det is high, but reset_n (to the ANX3429)
is low which indicates that the ANX3429 is currently in standby mode.
BUG=b:35775019
BRANCH=reef
TEST=Manual
Tested with various adapters in both S0 and S3/G3 chipset
states. Verified that adapters connected as expected. When in S3/G3
connecting a sink only adapter still causes an indefinite toggle, but
all calls into the driver are executed from within the USB PD 0 task
and all ANX3429 I2C accesses work as expected.
Change-Id: I6e4843e43f59afbf5ca3251feb68981b815c1c78
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457103
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Added a new static variable disable_dts_mode. By default, DUT port
will attempt to connect as a DTS source. However, if disable_dts_mode
is set via a console command, the DUT port will connect as a regular
source device. Charging behavior is identical between the two modes.
In DTS mode, Rp is presented on both CC lines. When it's disabled Rp
is presented only on CC1. Added tables to support the appropriate VNC
and RD voltage thresholds.
BUG=b:36908939
BRANCH=servo
TEST=Tested with new console command 'dts on|off'. If new mode equals
the current mode, no action is taken. If the mode is different, then
verified that DUT port connects as DTS following 'dts on' and regular
SRC following 'dts off'. Verifed this when the command is issued when
connected to the DUT or disconnected. Validated that the H1 console is
present for DTS mode and not present when DTS mode is disabled.
Change-Id: Ie649709d6b2bbe947708d05eac42fde61d2677a8
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/468447
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There's leakage through EC_INT when in S3 to the APs P3300_A rail.
Changing the GPIO config to be an input all EC_INT and all the SPI slave
pins during S3 removes the leakage.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, run int_test before & after suspend/resume successfully.
Change-Id: I68e286c4770831544bea0d58ffa98185fd7ba788
Reviewed-on: https://chromium-review.googlesource.com/469527
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Right now there is no way to verify cr50 is asleep just by looking at
the UART output. You can check by running taskinfo and seeing that the
GC_IRQNUM_PMU_INTR_WAKEUP_INT irq count has increased or by measuring
cr50 power.
In the past we have had Cr50 issues that we think are related to sleep.
Devices like poppy will have the Cr50 uart connected to servo, so we can
capture the Cr50 console output. It would be helpful if there was an
easy way to tell that cr50 is asleep from the UART output to more easily
confirm issues might be related to sleep. This change will print '.'
every time Cr50 resumes from sleep. Cr50 wakes up every half second for
HOOK_TICK, so with this change '.' prints every half second while cr50
is asleep.
BUG=none
BRANCH=none
TEST=boot a device, wait a while, and verify cr50 starts printing '.'
every half second. Turn off the device and verify the '.'s stop.
Change-Id: I94a82db00076062dbba2c3bc273cbe0731430520
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/463990
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The accelerometer sensors are not needed in S5, and having them get
enabled early in boot is causing issues on a subset of boards.
Similarly, the magnatometer is supposed to be disabled in S3/S5.
BUG=b:36919184
BRANCH=none
TEST=successfully boot on board that was previously failing
Change-Id: I3c079a83b21b2f1875330ac16ef8d3f9da267f9f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468686
Reviewed-by: Todd Broch <tbroch@chromium.org>
When a USB PD connection is made, servo_v4 senses the polarity of the
SBU signals and sets the SBU mux for the deteted polarity. If the DUT
is reset, the SBU mux needs to retain the same state so the H1 console
USB endpoint is not disrupted.
Modified the CCD_MODE_DISABLED case to no longer disable the SBU
mux. In addition, removed the static variable ccd_mode as it was being
set, but not ever being checked, so wasn't serving any purpose.
BUG=b:36561120
BRANCH=servo_v4
TEST=Connect servo_v4 to Electro. On Electro EC console enter 'reboot'
verify the H1 USB console remains connected.
Change-Id: I4f0f5167221c04314ca5be063411f200896bbdf6
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/464068
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This patch enables the entry/exit model for S0ix based on host
commands. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
BRANCH=none
BUG=b:36630881
TEST=Build/flash EC and check 'echo freeze > /sys/power/state'
command in OS shell. Verify EC goes to S0ix state, and on wake
it comes back to S0 state.
Change-Id: I22405021aead8488a5a1f166400cbde76faac59b
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/446219
Commit-Ready: Archana Patni <archana.patni@intel.corp-partner.google.com>
Tested-by: Archana Patni <archana.patni@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This will eventually be used for debug mode.
BRANCH=none
BUG=b:35775099
TEST=sysrq available in EC console
TEST=sysrq h => help message in AP console
TEST=sysrq b => AP reboots
Change-Id: I56b3a1f8f4b32d3ead91b83d474546356b65d221
Reviewed-on: https://chromium-review.googlesource.com/462757
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When Cr50 resumes from hibernate, it should use the WP state that was
stored in the long life scratch registers. All other boots should
simply follow the state of the BATT_PRES_L pin.
BUG=b:36659750
BRANCH=master,cr50
TEST=Power on Cr50 via battery, verify that WP_L remains asserted.
Change-Id: I516d43b6540d7c543e7629f8709ce63515bb7f76
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/464258
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The BIOS had the tablet mode device enabled in CL:439308, however
the corresponding change to the EC never was done. Therefore, powerd
was monitoring the tablet mode device which always reported tablet
mode because it wasn't reading the real state. As such the keyboard
and trackpad were never being unhibited by powerd. Ensure the EC
config matches the BIOS changes so that the correct state is properly
reported.
BUG=b:36788342
TEST=Booted device. keyboard and trackpad work as expected.
BRANCH=reef
Change-Id: Ie76007bc0e2ced046ebe1c241150f300efd3bb82
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/464026
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The derivatives development should be done in the firmware branch.
(here it is firmware-reef-9042.B)
They are way too many 'follow reef settings' CLs, either all derivatives
should be updated at the same time or we have to cut the rotten fruits.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36192920
TEST=make buildall
Change-Id: I20cbc4897c7e6e3355ca0a4ed0e856d6b1d17eff
Reviewed-on: https://chromium-review.googlesource.com/452459
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The default for servo_v4 DUT port is to be SRC to charge the DUT, but
a UFP data role so that the DUT's usb mux gets connected.
BUG=b:35586526
BRANCH=servo
TEST=Connect to Electro and verify that servo_v4 data role is that of
UFP and that electro is getting an IP address from the enet port on
servo_v4.
Change-Id: I8f2e4242777bf879598852004096f683d68c091c
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452725
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previous boards that implemented tcpc layer on chip didn't support
variable Rp values. However, servo_v4 can present any of the 3
possible Rp values and therefore the voltage thresholds that are used
to determine a no-connect or Ra attach status need a way to be set
based on the Rp value that's current attached to a given CC line.
- Added port and cc line selection to both the CC_NC and CC_RA macros
and now check if they are already defined before being defined in
usb_pd_tcpc.c.
- Defined each of these macros in board.h to use a function that's
able to select the threshold based on the current Rp configuration.
BUG=b:35586526
BRANCH=servo
TEST=Tested with servo_v4 against Electro and verified that it
connects when a charger is and is not connected to CHG port which
exercises the differnt Rp combinations that servo_v4 presents.
Change-Id: I1a31e430c0f290486f0fa8a50bdafdddf20d23ca
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451962
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This CL adds support for the DUT port to advertise different current
levels via the Rp resistor selection. The default setting is USB (500
mA).
The board_manage_chg_port function relies on the off->on transitions
only occurring when the CHG port is in a steady state condition. When
the charger being used supports PD messaging, the entry point
pd_set_input_current_limit() which is called after receiving a PS_RDY
message. For TypeC only chargers, the entry point is
typec_set_input_current_limit() which is called from SNK_DISOVERY
after only after the max number of hard reset attempts have been
attempted. This is intended to prevent this entry point from being
called when a USB PD charger is connected and the CHG port enters
SNK_DISCOVERY.
When the CHG port Vbus transitions from off->on, a src_pdo is updated
to reflect the current contract on the CHG port and this src_pdo can
then be used by the DUT port when either a new connection is done or
to update it's existing contract.
BUG=b:35586526
BRANCH=servo
TEST=Manual
Connected servo_v4 DUT port to Reef with no charger
connected. Verified that it connects, and CCD mode in Reef is enabled
(H1 console is available) and that only 500 mA charging current is
advertised. Then connected a 20V and 15V USB PD charger to the CHG
port. In each case verified that the DUT renegotiates to the 20 and
15V level respectively. Repated the test with Guppy and verifed that
VBUS is at 5V 3A. When Guppy is removed, then the DUT connection
reverts back to the host as the VBUS source.
Change-Id: I1a5eb346bbe1f0d586cb8b7bb24d77ff713fbf3c
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449954
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Setting PWM IO type in gpio driver seems not a proper way. This
CL moves this functionality to pwm driver and introduces a new
flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it
in board driver.
BRANCH=none
BUG=none
TEST=test pwm functionality on npcx_evb.
Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The cr50 code might need access to certain variables stored in the TPM
NVMEM. In particular the upcoming FWMP support will require reading
the NVMEM FWMP space.
This patch adds a generic function which allows to access TPM NVMEM
spaces. The implementation was borrowed from NV_REad.c in the tpm2
tree, the only difference being that the location, if present, is read
unconditionally, without checking access controls.
The API accepts the NVMEM index in Chrome OS scope and maps it into
TPM2 specification's NVMEM index space based at HR_NV_INDEX. The
definitions are included straight from the tpm2 tree.
BRANCH=none
BUG=chrome-os-partner:62489, chrome-os-partner:62205
TEST=this code is not yet even being compiled, tested with the next
patch.
Change-Id: I8bcfd8637c192249780634491f30e4a28229984f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457823
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
If we go to sleep with a lid close event, the trackpad is immediately
waking the system. Since we don't want to accidentally wake if the
trackpad got input while the lid is closed anyway this change will
disable trackpad wake when the lid is closed.
BUG=b:35587072
BRANCH=none
TEST=manual testing on Eve P1b:
1) enter suspend by closing lid and ensure it stays in suspend
2) enter suspend by idle, and then close the lid, and ensure
it stays suspended
Change-Id: Ied73dde61e99231f057504ca56c473432aa30e4b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457865
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
After running an update, we used to be dangerously close to
exhausting stack space, let's increase its size.
1 HOOKS 00000000 39.906350 476/488
BRANCH=none
BUG=b:35587171
TEST=Update FW using usb_updater2, 3 times in a row, without reboot,
no more panics.
Change-Id: Ia1559d7c4097b8d3179a6fa2f38bef126cb8055e
Reviewed-on: https://chromium-review.googlesource.com/458319
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With the rest of support in place, this patch adds code which would
corrupt the headers received during firmware updates.
The VENDOR_CC_TURN_UPDATE_ON vendor command will be required to enable
the new images.
Care should be taken that other commands operating on the inactive
image header do not do anything with it before it was enabled, some
code is being added for that.
The minor RW version is being bumped up to 19 to clearly indicate that
the device is expecting the vendor command to enable the new image
(this is used by usb_updater when downloading the image without the -p
or -u command line options).
BRANCH=cr50
BUG=b:35580805
TEST=verified that the new image can be installed and started by the
new usb_updater.
- the inactive header after uploading with the -p option (the
image_size field's offset is 0x32c):
> md 0x84320 4
00084320: 00000000 00000000 80033800 00084000
rebooting the device does not start the new image.
- the inactive header after uploading without the -p option:
> md 0x84320 4
00084320: 00000000 00000000 00033800 00084000
the device running a DBG image reports the following in the end of
the image update:
[64.176780 FW update: done]
turn_update_on: rebooting in 100 ms
Change-Id: I4d763eb89c8b1a43a13697033201066779826e85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The upcoming move of the Cr50 firmware update to the background
requires postponing the activation of the newly uploaded Cr50 image to
a later point in time, when the AP is ready to switch to start using
the new Cr50 image.
The suggested way of achieving it is as follows: when downloading the
new image, the current Cr50 code modifies the header's 'image_size'
field, setting its top bit to 1. This both makes the size invalid and
guarantees that the new image would not verify on the following Cr50
restarts.
When the AP is ready to switch to running the new Cr50 image, it will
send a vendor command, which would trigger the currently running Cr50
image to restore the other image's size field. This vendor command
would also communicate the timeout for the Cr50 to wait before
rebooting, if there has been at least one header (ro or rw) restored.
Rebooting the Cr50 would trigger rebooting the AP, resulting in the
entire system running the updated firmware.
Response sent to the AP will indicate if there has been a header
restored and the reboot is indeed upcoming, this would allow the AP to
quiesce the state of the device to handle the reboot gracefully.
BRANCH=cr50
BUG=b:35580805
TEST=with the rest of the patches applied observed the system properly
after the new header version was restored.
Change-Id: Ia1edee67b6aa8f458810d5dc2931477cfaab1566
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rowan uses BMI160 as g-sensor and gyro sensor.
This change removes KX022 settings and adds BMI160 settings.
The LID_ANGLE config is also removed.
BRANCH=none
BUG=chrome-os-partner:62673
TEST=check the values of the sensors are correct:
run ectool motionsense while the machine is flat on the table, raised on
its left side and raised on its front edge. With these 3 measurements
the accel data along the Z, X and Y axis are showing + 1G.
Change-Id: I03c84f143bbfc3037fd5232398d15e9c2a511291
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/427566
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
tigertail allows muxing a usb-c port onto two different
passthough targets. This allows for automated switching
between USB host and device without DUT or endpoint knowledge.
tigertail also routes SBU lines to stm32 UART, and has INAs on
VBUS and VCONN to measure power.
BUG=b:35849284
BRANCH=None
TEST=Muxing power, muxing USB, uart works, INAs work.
Change-Id: I5bf2ba038aa78e59352ad99cd71efb0f0d0fbec9
Reviewed-on: https://chromium-review.googlesource.com/438677
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In order to enable toggling on/off of LTE based on chipset power state
transitions, define WIRELESS_GPIO_WWAN that would allow the common
wireless component to take care of the gpio toggling.
BUG=b:36447195
BRANCH=None
TEST=Verified that PP3300_A drops down from 0.9V to 0.63V when
apshutdown is done on EC console and system transitions to fake G3.
Change-Id: Id46bcbdffde06e4929910b6ab87a6d9a96d18a23
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457402
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jerry Parson <jwp@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In order to support waking from Deep S3 the trackpad interrupt
is routed to the EC.
The EC needs to enable this interrupt when going into S3, and
disable it otherwise.
It also needs to filter events and only wake the system when it
is not in tablet mode.
This is accomplished with the following rules:
1) Enable trackpad wake in S0->S3 transition, if !tablet_mode
2) Disable trackpad wake in S3->S5 transition
3) Disable trackpad wake in S3->S0 transition
4) Disable trackpad wake when entering tablet mode in S3
5) Enable trackpad wake when lid angle is <180 degrees and in S3
And finally a check in the trackpad interrupt itself to ensure that
it only sends the wake event if not in tablet mode.
The function to enable or disable trackpad wake uses a static variable
to keep track of the enable state because when enabling the GPIO for
wake it first clears pending events and if multiple transitions are
happening (suspending, plus lid angle rotation) this can get called
multiple times in quick succession.
Currently a placeholder KEY_PRESSED event is used to wake the AP
since we do not have device specific events. Fixing this behavior
is tracked in b/36024430.
BUG=b:35587072
BRANCH=none
TEST=manual testing on eve P1b:
1) ensure that trackpad wake in clamshell mode works
2) ensure that trackpad wake in tablet mode does not waork
3) ensure that if in S3 during transition to or from tablet
mode the wake event is enabled appropriately
Change-Id: Ib2020b5010bdde396a3b05243894431b67edb503
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450954
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
PS8751 does not restore all register contents when resuming
from low power mode. This change makes tcpm call board_init
when it stops auto-toggling so that register contents can be
restored.
BUG=b:35585399
BRACH=none
TEST=On Snappy, the board_init funciton is called every time a device
is plugged in and register contents are restored.
Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/454139
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Let's split the usb headers in 3 different parts, instead of having
usb_descriptor.h pull in usb_hw.h and usb_api.h.
- usb_api.h: EC functions related to usb (e.g. connect/disconnect)
- usb_descriptor.h: common USB names and structures
- usb_hw.h: Functions required for interactive with EC's USB HW
BRANCH=none
BUG=b:35587171
TEST=make buildall -j
Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e
Reviewed-on: https://chromium-review.googlesource.com/454861
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Increasing key length from 2048 bits to 3072 bits provides more
security, at the cost of about 2.25x the amount of time being
spent in verification (roughly 100ms instead of 45ms).
CQ-DEPEND=CL:449060
BRANCH=none
BUG=b:35582031
TEST=Flash hammer, verification succeeds.
Change-Id: I2ac7e87941c847bb4e9bd376034e6539988d1743
Reviewed-on: https://chromium-review.googlesource.com/449023
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450858
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When an x86 based system is reset, a pulse on the plt_rst_l line is
generated. This pulse is supposed to reset the system and the pulse'
rising edge is an interrupt trigger for H1 to reset the TPM. If H1 is
in sleep state at the time of the rising edge, the interrupt request
could be lost.
Luckily, the minimum plt_rst_l pulse duration is 1 ms, and the worst
case max time to wake up from sleep for H1 150 us. Let's wake up on
low level of plt_rst_l, this way by the time the rising edge comes
along the H1 would be awake and ready to process the interrupt.
BRANCH=cr50
BUG=b:35995492
TEST=verified that platform_KernelErrorPaths.CORRUPT_STACK passes
hundreds of times on a system were it was failing after a few
runs before this fix.
- verified that suspend_stress_test still succeeds at least 300
iterations
Change-Id: Ib9984efa08bdd185a95716dc9e48077cf4bb3c2a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455579
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable more hardware related console commands to help hardware
validation.
BUG=chrome-os-partner:62673
TEST=manual
build and load into Rowan
check console commands:
gpioget
spixfer
BRANCH=none
Change-Id: I86d3b74cef77ed9244a140290241a9fac6af3f84
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441486
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
EC controls SPI CS pin as GPIO. This CL remove the ALT function
config. And before trigger SPI hardware reset, the driver state needs to
be disable.
BUG=chrome-os-partner:62673
TEST=manual
load into Rowan and boot up AP.
check console command accelread
BRANCH=none
Change-Id: I511c5906efbbb42b09547c61414bcc24b0217ad3
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441485
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
