Assuming the dut has red/green battery led and a single power led
CONFIG_LED_POLICY_STD implements the chromeos spec:
* power led on in S0
* power led off in S5
* power led pulsing in S3
* battery led amber when charging
* battery led green when fully charged with AC
* battery led off when discharging
* battery led pulsing red when battery error
BUG=chrome-os-partner:35355
TEST=The Charging led behavior should match the cros spec
BRANCH=None
Change-Id: I645a939ecc2d44d73d2f52b295f9c7e8c923f77b
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240705
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Shorten some PD protocol printf's to save flash space and add
port information to a handful of important ones to help find
errors when both ports are in use on samus.
BUG=none
BRANCH=samus
TEST=load onto samus and connect to zinger
Change-Id: Ieecb2a35ebb8c8275c520ad2bd3018e7608b5ecb
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240482
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fix bug causing firefly to disconnect when changing voltage request
too fast.
BUG=chrome-os-partner:35330
BRANCH=samus
TEST=test with firefly and zinger.
Change-Id: I6efb2f6fdd1ff64cee2cc722a538164cca946380
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240460
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:35312
BRANCH=none
TEST=make buildall -j
I added a debug message to nrf51/hwtimer.c to show when the timer overflowed.
"forcetime 4 0xfffff000" overflows to 5.00000000 in 4096 microseconds.
Define CONFIG_CMD_FORCETIME to enable it.
Change-Id: I30835d038ef8cd639565ffb7a638979d95d0a684
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239968
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The check for overflow was originally in __hw_clock_source_read()
If it got interrupted, it would frequently see an overflow, because
"prev_read" would be less than "now".
1 - Use the comparator to check for overflow.
2 - Only check for overflow in the interrupt handler.
BUG=chrome-os-partner:35312
BRANCH=none
TEST=make buildall -j
use the keyboard code to type
use a console command "forcetime", to force the system time to overflow soon.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I7005724222289ba967e89af0ce8b9ef8f90a4ae4
Reviewed-on: https://chromium-review.googlesource.com/239967
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
If the RO firmware has a different view of the protection than
the RW copy, we should not change the option bytes (write protection
settings) in RW else we will trigger a reboot loop : RW protects and reset,
then RO unprotects, resets and jump to RW, RW protects and reset again ...
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35383
TEST=craft a firmware image whose RO partition doesn't include commit
42d0104 (no virtual WP, no RDP set) and RW partition has everything
including this patch, see that HoHo no longer reboots in a loop.
Change-Id: I4cbdbf25a96cb6fb7cbabc7f2d1dc76d3a2a9e36
Reviewed-on: https://chromium-review.googlesource.com/240561
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This adds some temp limits from the motherboard die sensors to
use in determining the desired fan speed.
I'm also bumping the minimum PECI temp up a bit, since it varies
rapidly. At room temp the motherboard sensors will generally
request a little bit of cooling, but in cool environments it's
likely that the PECI changes will become the major annoying factor.
BUG=chrome-os-partner:34789
BRANCH=ToT,samus
TEST=manual
Watch/listen to fans. They shouldn't turn off and on as much.
Change-Id: I309132a053a052b456808e42261844dbf6442675
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240435
Reviewed-by: Sameer Nanda <snanda@chromium.org>
When displaying the temps, if the sensor has valid entries to
control the target fan speed, show them. This lets us see which
sensor is the main player in the cooling needed without doing a
bunch of math.
BUG=none
BRANCH=none
TEST=manual
On the EC console:
> thermalget
sensor warn high halt fan_off fan_max name
0 368 370 372 316 358 PECI
1 0 0 0 0 0 ECInternal
2 0 0 0 314 328 I2C-Charger-Die
3 0 0 0 0 0 I2C-Charger-Object
4 0 0 0 308 322 I2C-CPU-Die
5 0 0 0 0 0 I2C-CPU-Object
6 0 0 0 301 317 I2C-Left C-Die
7 0 0 0 0 0 I2C-Left C-Object
8 0 0 0 302 316 I2C-Right C-Die
9 0 0 0 0 0 I2C-Right C-Object
10 0 0 0 303 317 I2C-Right D-Die
11 0 0 0 0 0 I2C-Right D-Object
12 0 0 0 316 327 I2C-Left D-Die
13 0 0 0 0 0 I2C-Left D-Object
Then, before this CL:
> temps
PECI : 308 K = 35 C
ECInternal : 309 K = 36 C
I2C-Charger-Die : 307 K = 34 C
I2C-Charger-Object : Not calibrated
I2C-CPU-Die : 304 K = 31 C
I2C-CPU-Object : Not calibrated
I2C-Left C-Die : 302 K = 29 C
I2C-Left C-Object : Not calibrated
I2C-Right C-Die : 303 K = 30 C
I2C-Right C-Object : Not calibrated
I2C-Right D-Die : 303 K = 30 C
I2C-Right D-Object : Not calibrated
I2C-Left D-Die : 306 K = 33 C
I2C-Left D-Object : Not calibrated
After this CL:
> temps
PECI : 308 K = 35 C 0%
ECInternal : 309 K = 36 C
I2C-Charger-Die : 307 K = 34 C 0%
I2C-Charger-Object : Not calibrated
I2C-CPU-Die : 304 K = 31 C 0%
I2C-CPU-Object : Not calibrated
I2C-Left C-Die : 302 K = 29 C 6%
I2C-Left C-Object : Not calibrated
I2C-Right C-Die : 303 K = 30 C 7%
I2C-Right C-Object : Not calibrated
I2C-Right D-Die : 303 K = 30 C 0%
I2C-Right D-Object : Not calibrated
I2C-Left D-Die : 306 K = 33 C 0%
I2C-Left D-Object : Not calibrated
Change-Id: I12bca5826e8a5a3325710fa5d39cec88f1cc95b1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240517
Increase discharge timeout delay to 275ms, which is the new
tSrcSettle time. Also, fix fault condition so that we reset
immediately upon receiving a fault.
BUG=chrome-os-partner:35330
BRANCH=samus
TEST=load on zinger and test with firefly many 20->5V transitions
without a discharge error
Change-Id: I13bc5d77889a37390603c6922c84b264c77d79ac
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240399
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change the reads of output enable and discharge gpio's to use
the output data register (ODR) instead of reading input data
register (IDR) because we are really intending to read it's output
state, what we have set it to.
BUG=none
BRANCH=zinger
TEST=make -j buildall. load on zinger and use it normally.
Change-Id: I308bbb659aa26a9d0bca8caef6d1257fc1146ae9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240398
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If we're charging on a port and the active port supplier changes, it is
an indication of a significant change. Re-set the port as active, to
give the board-level function an opportunity to reject the port, in case
charging is untenable.
BUG=None
TEST=Manual on Samus. Plug Zinger, verify that 20V is negotiated
correctly.
BRANCH=Samus
Change-Id: I4a530d5bab510498dd9b30f141208ce33b52ef6b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239250
Reviewed-by: Alec Berg <alecaberg@chromium.org>
MIPS host CPU does not access IO registers using a separate address space.
Remove for support of LPC for this host architecture.
Confine x86 function to Intel Architecture only.
BRANCH=none
TEST=Compile: Test on ARM, MIPS and X86: using emerge... ec-utils.
BUG=chromium:443783
Change-Id: I9d4276ec3588037adfcff96e596bbe8be74f22fd
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236687
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
prevent_hot_discharge and prevent_deep_discharge are near-identical
copies of one another, and can be combined without the loss of any
useful functionality.
BUG=chrome-os-partner:35188
TEST=Manual on Samus. Charge to 2% and boot system with 5V power supply.
Verify that warnings print to console and AP powers down after 30s. Also
pass unit tests.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0f1da5248825a3884f7910babc742dfa7eadf5a3
Reviewed-on: https://chromium-review.googlesource.com/240033
If we discharge directly the output voltage from 20V to 5V under load,
an undershot happens and we dip below the 5V UVP threshold.
So when doing a down voltage transition from 20V to 5V, split it into 2
steps : a 20V->12V transition then once we are reached 12V, a 12V->5V
transition.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:33794
TEST=connect Zinger to a Firefly and an electronic load.
Using Firefly, ask for 20V->5V, 12V->5V and 20V->12V
transitions, check the VBUS waveforms on the scope.
Change-Id: Ie1e091ae6f1fee1fb7d4e3bd72edbe7491acd5ea
Reviewed-on: https://chromium-review.googlesource.com/229732
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Allow VDO responses to be sent faster by taking out the check for
incoming packet when a VDO is pending. This check isn't needed
because we already check if the PD state machine is busy sending
something.
With this change, the turn around time for responding to Discover
Identity on zinger is ~200us.
BUG=chrome-os-partner:35327
BRANCH=samus
TEST=loaded onto zinger and used twinkie to verify that discover
identity is responded to in ~200us every time. used ectool to
perform remote update on zinger, now takes ~18s (compared to ~55s).
Also, used following bash loop to constantly sent PD voltage requests:
while true; do dut-control "usbpd_uart_cmd:pd 1 dev 5"; sleep 0.3;
dut-control "usbpd_uart_cmd:pd 1 dev 20"; sleep 0.3; done
Used bash loop while updating zinger via ectool. I programmed zinger
~50 times and verified:
- we never missed a PD voltage request
- never got any PD protocol or phy layer errors (no collisions)
- zinger successfully jumped to RW after each (no packets missed)
Note: sending any other PD traffic while programming zinger does
obviously slow down zinger update (~30s with my bash loop above).
Change-Id: I94d1ac01440d096671972fa9c21c149ea432863f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240150
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To ensure we respond fast enough to the Discover Identity VDM
(which timeout after 30ms), we need to pre-cache the RW hash at startup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35327
TEST=plug Zinger to a PD sink and check the PD protocol trace on Twinkie
Change-Id: I9decdff358dd1ab9ac373ce8bfdd0402f5e21f04
Reviewed-on: https://chromium-review.googlesource.com/240080
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Make sure the power role and the CC pull resistor match after
receiving hard reset command in the middle of a swap.
BUG=none
BRANCH=samus
TEST=on samus connect left and right ports together with C to C
cable. note that after some collisions and some hard resets, it
eventually stabilizes with one port in SNK_READY, the other in
SRC_READY. without this CL, we get stuck executing a power swap
and our power role and CC resistor get out of sync, requiring
a reboot.
Change-Id: Ia1385eb3a1c503052ad5bfd0d1595ecc096cd5f4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239976
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Avoid multiple power and data swaps on connect by clearing our
local flag for checking our role when we receive a role swap.
This means if the port partner sends a role swap on connect before
us and we accept, then we will not turn around and ask for another
swap.
BUG=none
BRANCH=samus
TEST=connect samus to samus and make sure only one swap on connect.
Change-Id: I2414b5bd5ffc54701b5758047e5d7e51ca3ff596
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239951
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Another fix for redundant requests. This time there can be
redundant requests if the maximum allowed voltage changes,
but we still fall into the samus PDO index and therefore are
asking for the same voltage. This fixes by checking the voltage
value we actually request vs. the max value we can request.
BUG=none
BRANCH=samus
TEST=samus to samus was causing redundant requests and now it's
not.
Change-Id: Ie49add1a42b86de97cee87f9d4637dd0578e2ce3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239950
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Implement the new type-C connect state machine which removes
lock and hold times and adds a debounce time to make sure
CC lines settle before going into the attached state.
This also adds detection of accessories, but doesn't do anything
when an accessory is detected.
BUG=chrome-os-partner:33680
BRANCH=samus
TEST=test samus connected zinger and samus connected to samus. make
sure that the connection is always formed. also tested with a third
party with old state machine implementation and formed a connection
every time.
Change-Id: I91a7a6031bc35082cc19d7697142e4aa92ef46f2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238210
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove PWM module which is not being used in order to save flash
space.
BUG=chrome-os-partner:34489
BRANCH=samus
TEST=make -j buildall. view .map file and see we save ~760 bytes.
Change-Id: Id107fb402a60c5ac7510982f8ace6bad46fb14d0
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239912
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If the EC controls the lightbar and sets the sequence when
it notices the chipset transitioning between states, we can't
make exceptions for cases where we don't want to activate the
lightbar, such as in dark resume. Instead, let's make it a
separate command that we expect from the kernel.
BUG=chrome-os-partner:32181
TEST=build on samus, verify lightbar does correct thing with
manual control set
BRANCH=ToT
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Change-Id: I5dc619cbbf2498e2ef03ce622831b33e14c7c495
Reviewed-on: https://chromium-review.googlesource.com/239215
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
History is written by the victors, except when they run out of flash
space.
BUG=chrome-os-partner:34489
TEST=Build samus_pd, check ec.RO.map and verify 756 bytes were saved.
Verify that 'history' no longer works on console and up arrow has no
function.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If512fe31f01cc35b0ef6fa60714b9df125818d64
Reviewed-on: https://chromium-review.googlesource.com/239971
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fix potential junk at end of PD TX transmit by adding to the DMA
transmit complete interrupt a blocking wait for SPI to finish and
then immediately disable SPI clock. This means we block in an
interrupt function for approximately 45us at the end of every
transmit. But, this is the highest priority thing going on anyway.
Note, there is still a potential for junk if both ports are
transmitting at the same time and finish very close to the same time.
BUG=chrome-os-partner:34600
BRANCH=samus
TEST=load onto samus and test communications with zinger. tested
specifically with an old zinger CL,
https://chromium-review.googlesource.com/#/c/226118/11,
which watchdogs when samus has junk at end of transmit. Tested
without this CL and verified we could never successfully flash zinger
over PD due to this watchdog and verified on scope presence of junk.
Then tested with this change and was able to successfully flash
zinger using ectool on both ports in both polarities.
Change-Id: If0cd9ab0551d36a7d7dc10232b6476dd56735972
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239244
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
VESA DisplayPort Alt Mode on USB Type-C Standard specifies:
When DisplayPort Configuration is not selected (and the converter is
driving its HPD output low), the converter shall track the current
state of HPD, ready for appropriate indication when DisplayPort
Configuration is subsequently selected.
Not only are we violating specification here but it also causes a race
between enabling DPout muxes to AUX line which in turn causes GPU to
timeout trying to read EDID/DPCD on occasion.
Change adds post_config function for DFPs alternate mode and in the
case of DP it sets the dp_on flag there. This allows attention
function to correctly defer HPD_HI that may accompany 'DP status' VDM
to be queued (deferred) until such time that AUX muxes are enabled
properly.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35219
TEST=manual, using hoho & dingdong
With kernel bootarg drm.debug=0x6 following cases all show these
drm debug lines:
[drm:i915_hotplug_work_func], Connector DP-2 (pin 5) received
hotplug event.
[drm:intel_dp_get_dpcd], DPCD: 12 14 c4 01 01 00 01 00 02 02 06 00
00 00 00
[drm:intel_hpd_irq_event], [CONNECTOR:38:DP-2] status updated from
disconnected to connected
case1: boot connected to external display
case2: attach dongle to external display then samus
case3: attach dongle to samus then to external display
case4: connect/disconnect rapidly on type-C side
case5: connect/disconnect rapidly on external display side.
Change-Id: I40eab797fdd5090c8ad13fae2cd053b740d9a307
Reviewed-on: https://chromium-review.googlesource.com/239420
Trybot-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Build a Twinkie firmware image with the regular Twinkie sniffer firmware
in the RO partition and a firmware behaving as a USB PD sink in the
RW partition.
The user can call the "twinkie sink" command to switch the USB PD sink
firmware in the RW partition (and call "reboot" if he changes his mind
and wants the sniffer back).
Restore the ability of building different tasklists which was broken
where the tests build was simplified.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
./board/twinkie/build_rw_variant
Try "twinkie sink" command on a Twinkie with the combined firmware.
Change-Id: Ie489ce97a774ae7a22ac639c49a3d6e412e62de8
Reviewed-on: https://chromium-review.googlesource.com/237221
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Ensure that we can re-etablish a proper USB communication after a
sysjump by properly disabling the USB stack before jumping.
So the host sees a USB disconnection and can properly re-initialize the
device when it re-appears.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=On Twinkie, use the "sysjump RW" command on the USB console
and see the prompt coming back after a few seconds.
Change-Id: Iaf4498333eb4e7a1dda0f51ee8be19a0c9f10349
Reviewed-on: https://chromium-review.googlesource.com/239227
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
It's not safe to sysjump with a DMA enabled as it can led to memory
corruption after we have landed in the new image before that piece of
hardware is re-configured.
Implement and call dma_disable_all() on all platforms with generic DMA.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=chrome-os-partner:34865
TEST=on various boards, call "sysjump rw".
Change-Id: I2a6b63ff19c2d932a5e31bc375bf468bc8ae5125
Reviewed-on: https://chromium-review.googlesource.com/237340
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
the VCONN INA is off by default to avoid a leakage path on CC2.
Turn it on when asking for a VCONN measurement ("twinkie vconn"),
then off aftwerwards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the Twinkie command-line, "tw vconn" with the Twinkie interposed
between a Samus and a DingDong.
Change-Id: I8cd78b285512644af0824a44c735585b684fee66
Reviewed-on: https://chromium-review.googlesource.com/239212
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
With CL:
5ef45ad pd: Add timeout for HC flash commands.
I thought I'd licked the timeout related issues with flashing dingdong
& hoho.
With further testing however I found I was occassionally hitting the
failure where I couldn't return from 'flash erase' on PD peripheral
prior to the 1 second limit for host command timeout.
That could be remedied by retrying the erase on the host side which
then succeeds quickly. That solution seems non-optimal however.
Additionally, even when erase does succeed in <1sec we have the shared
i2c bus pending. That too is non-optimal.
For those reasons I've decide to return immediately from flash erase
command and instead put the burden of waiting the necessary time on
the host which at least does have some wider perspective on what the
system is attached to and doing.
CL also adds following related changes:
1. corresponding ectool edit to delay 3sec after RW erase.
2. fixup to error returns from hc_remote_flash for timeouts.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:33947
TEST=flashing dingdong/hoho via ectool works reliably.
Change-Id: I8fbfb592f760273b26bcb16b67210d569454eee2
Reviewed-on: https://chromium-review.googlesource.com/239253
Trybot-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Refactor pd_exit_mode to be only a DFP function. Additionally make
pe_init a public function and call it during hard reset.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:33946
TEST=manual, using pdsetmode from later patches see proper exit and
resetting of pe struct.
Change-Id: I45afe1f82926f1c32f4d84eb60c65f1f39b19d81
Reviewed-on: https://chromium-review.googlesource.com/236958
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
If two identical suppliers are capable of supplying equal power, select
the port which is currently active.
BUG=chrome-os-partner:34912
TEST=Manual on Samus. Plug Zinger into right port, verify that it
becomes active. Plug a new Zinger into left port, verify that the right
port stays active.
BRANCH=Samus
Change-Id: Ib1baf4bd3f619169f0e31ec509a2fe7dbd8c897e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238766
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Remove clearing of the type-C pull-up supplier current limit
on hard reset. Hard reset is a PD command and should clear the
PD supplier current limit, but the type-C pull-up is independent
and is still connected, so should not reset.
BUG=none
BRANCH=samus
TEST=load on samus and plug in donette. without this CL, the
charging icon flashes off then on. with this CL, it doesn't flash
and still draws 3A.
Change-Id: I90f87f3970754ca3618d87466412c97acc0a4d6f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239269
Reviewed-by: Shawn N <shawnn@chromium.org>
Power up inhibit is intended to stop the AP from booting when the
battery is in certain states. It works most of the time, but sometimes
IN_PCH_SLP_S5_DEASSERTED is already set by the time we get to S5 and we
incorrectly boot the AP.
Thinking about this more, it's better to check the battery state in G3,
before we transition to S5, to prevent the needless transition back to
G3 if power up is indeed inhibited.
BUG=chrome-os-partner:35182
TEST=Manual on Samus. Drain battery to 1% and attach charger. Press
power button multiple times and verify that AP doesn't boot. Charge
better to 2% and press power button. Verify that AP boots.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib03c3f707f9d90d0a9cb07ada3738d00e2728c32
Reviewed-on: https://chromium-review.googlesource.com/239352
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Samus should reject request for a power swap if it is not in a
dual-role mode, for instance if in S3 or lower.
BUG=chrome-os-partner:35141
BRANCH=samus
TEST=load on two samus'. turn on samus off, then request a power
swap from the samus that is on and see that it is rejected.
Change-Id: Ifb23febac967c981251c3932856e1e942818694f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238963
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
These USB type-C accessories don't have a write-protect GPIO.
Add a configure flag (CONFIG_WP_ALWAYS) to force the flash
write-protection on the dongles.
Also set the read protection (by elevating RDP to level 1),
so trying to unprotect the flash will trigger a full erase.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35088
TEST=boot Hoho,
check the flash OBR and WRPR registers:
"rw 0x4002201c" / "rw 0x40022020"
and the option bytes write-protect bits: "rw 0x1FFFF808"
dump the logical state with "flashinfo" command.
> rw 0x4002201c
read 0x40022020 = 0xffff0002
> rw 0x40022020
read 0x40022020 = 0xffff0000
> rw 0x1FFFF808
read 0x1ffff808 = 0xff00ff00
> flashinfo
Physical: 128 KB
Usable: 128 KB
Write: 2 B (ideal 2 B)
Erase: 2048 B (to 1-bits)
Protect: 4096 B
Flags: wp_gpio_asserted ro_at_boot ro_now
Protected now:
YYYYYYYY YYYYYYYY ........ ........
Change-Id: I45bbc0bce40ecc174b6b8a1ebacf4f53d2fd372d
Reviewed-on: https://chromium-review.googlesource.com/238893
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
These versions of the queue add and remove methods support
using memcpy like routines to access regions of memory with
specific requirements. In particular, this will allow for
transfers between queues and USB packet RAM on the STM32
which has specific access requirements.
This change also includes an update to the mem* util routines
to make their prototypes compatible with C89 and POSIX
standards.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Test USB Echo functionality on discovery-stm32f072 board to
ensure that queues still function correctly.
Change-Id: I557064d99abfc3e8cfc98099a1d94334a976550c
Reviewed-on: https://chromium-review.googlesource.com/239217
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Previously there was just a memcpy_usbram that copied to
USB packet memory, and no routine to copy out. This adds
the "from" version and renames and improves to "to" version.
The improvement is that the new "to" version correctly
handles unaligned beginning and endings of the region to
be copied. These need to be read/modify/write accesses since
the USB packet ram has to be manipulated in 16-bit chunks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify that discovery-stm32f072 still enumerates and communicates
correctly over USB.
Change-Id: I94353e66ad0248d4e674abb29f9a88e979767655
Reviewed-on: https://chromium-review.googlesource.com/238764
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
The recent change to decrease the time to wake up from deep sleep when
not using LFIOSC was too agressive. Increase the time to wake up based
upon the worst observed case.
BUG=chrome-os-partner:35184
TEST=Manual on Samus. Go to deep sleep, verify that no "overslept by
Xus" prints are seen.
BRANCH=Samus
Change-Id: Ib9fe2eba5e29a112e03fffaedbc5ae53d6d650ff
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239242
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
If we sysjump while the AP is running, the AP_RUN sleep mask should be
preserved. Otherwise, the EC goes into low power idle while the AP is
still up.
BRANCH=Ryu
BUG=chrome-os-partner:34230
TEST=Without this change, bit 0 becomes 0 after a sysjump. With this, it
doesn't.
Change-Id: I55cecff3275402f7974c6078a9c203bafce2a2f9
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/238918
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
