tpm_reset just requests a tpm reset it doesn't reset the tpm. Rename the
function to reflect that.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I6f4763b5de578a8cf263b2fac98fad3af2c25d65
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434245
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The nvdc voltage has a kind of deep, so that rarely observed
NVDC down at this point because of back-boosting.
Our sequence to enable charger bit and setting vsysreg
is correct but rohm introduce charger may need some more time
to be stable when between chg_en and vsys_set to start charge
BUG=chrome-os-partner:60380
BRANCH=gru
TEST=Manual on kevin, trigger battery disconnect, re-attach AC, verify
system boots cleanly. and see voltage probing on c54@60380
Change-Id: Ic05091379322ffaac16fe827a47345c76c85f3e5
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/434252
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With introduction of encryption it is becoming impossible to read
NVMEM contents directly from flash. Decrypting the contents each time
there is a read request creates a significant performance hit. NVMEM
needs to be rearchitecture such that there is no need to run
decryption each time NVMEM read is performed.
This patch does just that, implementation details are described in the
header comment in common/nvmem.c.
To reduce memory impact the size of NVMEM is being decreased from 16K
to 12K. This is acceptable because eviction objects stored in NVMEM
serialized now, which dramatically reduces NVMEM size requirements.
The TPM2 NVMEM size definition must be kept in sync.
Another optimization this change introduces is bypassing writing into
the flash if NVMEM contents did not change, which is verified by
examining the hash of the cached storage.
A test is added to verify that the new commit scheme works as
expected, and the nvmem test is re-introduced to the list of test ran
on each 'make buildall'.
CQ-DEPEND=CL:433839
BRANCH=none
BUG=chrome-os-partner:62260,chrome-os-partner:62421
BUG=chrome-os-partner:62437
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I177daa3ceb4fd7aac299ca26b4506b863e31b946
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the chroot, we use ccache to speed up compilation. However, it's
possible for this cache to become corrupt which could lead to slower
builds. In order to keep things fresh, 'make clobber' should clean up
that ccache cache as well. This commit makes it so.
Note, this is NOT *clearing* the cache entirely.
BUG=chromium:681961
BRANCH=None
TEST=make clobber; verify that ccache is cleaned.
Change-Id: I8ccd7df4858c445485ed740843f3126af0abd33a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/433108
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On ANX port connecting hoho and issuing hard reset
never recovered. From TCPCI spec R1.0.4.7.2 "TCPM
writes to the RECEIVE_DETECT register to enable PD
message passing". This was missing when the port sent
HARD RESET when it acts as SRC.
BRANCH=none
BUG=chrome-os-partner:61377
TEST= On Electro, on anx port, connect hoho and issuing
pd 0 hard successfully recovers from hard rst
Change-Id: Ia2cfcaf52b88fbc24ee702c6a089389400eb42d1
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/433387
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
- Modified src attach state to enable vbus when debug accessory is
detected.
- servo_v4 has two pd ports, but each port requires a different default
power role. Port 0 can only ever be a SNK, but port 1 which acts is
intended to be a DTS port should default to a SRC so it can be be a
source debug accessory. It may also act as a sink debug accessory, but
is not intended to toggle automatically but will swap roles if
necessary via pd role swap messaging.
- Add hook for ccd enable/disable for DTS mode
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual Verfied that can still build servo_v4 project. All changes
in this CL are contingent on config option CONFIG_USB_PD_DTS being enabled.
Change-Id: Iab968b6fbdfc8f2d155c4f8618921b32f313b9ec
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428308
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Update tpmtest.py to handle a success command code
(i.e. return value of 0) as per change
12da6c23fb
This change makes the test suite runnable (not all
tests pass though - sha and upgrade tests are broken).
Also rename local variable subcmd to avoid a name collision.
BUG=none
BRANCH=none
TEST=tpmtest.py passes, except for sha & upgrade
Change-Id: I927ead775a1e41b9abf9f905b9f191e8bd5e108b
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/411535
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Enable the Clock Recovery Subsystem to automatically adjust the internal
HSI48 clock for proper USB operation on the STM32F0.
BUG=chrome-os-partner:34160
TEST=Manual testing on STM32F072B-DISCOVERY
Plugged in board and verified that device was detected with dmesg.
[1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd
[1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f
[1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[1400698.720072] usb 3-10: Product: PDeval-stm32f072
[1400698.720075] usb 3-10: Manufacturer: Google Inc.
BRANCH=none
Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236
Reviewed-on: https://chromium-review.googlesource.com/433059
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In Sink mode, on the receipt of a GotoMin message,
reduce the current consumption to some minimum level.
BUG=chrome-os-partner:33688
TEST=Manual testing
Used a Kevin, with test routine, to test GotoMin feature
on another Kevin unit.
Test routine:
if (!strcasecmp(argv[2], "gm")) {
ccprintf("send goto min\n");
send_control(port, PD_CTRL_GOTO_MIN);
send_control(port, PD_CTRL_PS_RDY);
}
Kevin with GotoMin feature:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4277mV / 3000mA, max 5000mV / 3000mA / 15000mW
Port 1: Disconnected
After Test routine is executed:
# ectool usbpdpower 0
Port 0: SNK DRP PD 4906mV / 500mA, max 5000mV / 500mA / 2500mW
Port 1: Disconnected
BRANCH=none
Change-Id: Iaac6e19706ceb10ccaff4d602d63fc086c808c8f
Reviewed-on: https://chromium-review.googlesource.com/425728
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds a separate CONFIG check for RO and RW.
Each section is built with the objects generated
based on it's own calculated CONFIGs, so that the
object list may be different for RO and RW.
The intent is to allow for differnt sized RO and
RW partitions to allow for a small RO and lager code
space for RW, for servo_v4 and hammer.
BRANCH=none
BUG=chrome-os-partner:61170
TEST=builds successfully
Change-Id: I5549cc7ac218e0c7681108074ecfd3b80d4af545
Reviewed-on: https://chromium-review.googlesource.com/433079
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Servo_v4 requires the ability to have a different default state per
port. In previous devices, the assumption was that each supported port
had the same default usb pd state and power role. This CL moves the
by the default power role which in turn is derived from
CONFIG_USB_PD_DUAL_ROLE. In addiiton to moving the location, it now
uses 'port' as argument so it can be port specific if required.
PD_DEFAULT_STATE was a board.h specific config, but in practice each
instance used to date was set to PD_STATE_SNK_DISCONNECTED if
CONFIG_USB_PD_DUAL_ROLE was defined and set to
PD_STATE_SRC_DISCONNECTED otherwise.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual run 'make -j buildall' to verify that all instances of
PD_DEFAULT_STATE were removed.
Change-Id: Iaf40718668732f525485ed7942ee7fc246d3f75d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431787
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If common layer called i2c_xfer() with only one byte read length and the
flag is I2C_XFER_STOP, the npcx's i2c driver will return error directly.
The reason is once ec read last byte of previous transaction, hardware
will release SCL and i2c slave start to send following byte. Ec might
not have chance to generate NACK in time. A additional dummy byte is
necessary to make sure ec generate NACK before STOP condition.
BRANCH=none
BUG=chrome-os-partner:60266
TEST=make BOARD=pyro; test battery command on pyro with CONFIG_CRC8 and
CONFIG_SMBUS.
Change-Id: I372ff494b49656cbfbd4044b99b00b13daf0b741
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/430569
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit 66828807af.
I messed up this port, and only got half of the commit. Even with the
other half it still seems to break charging completely and needs more
investigation. Remove it all for now.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=ensure Eve P1 charges properly when charger attached after boot
Change-Id: I0219c397ae420738d85d8b437cf89c067f014c5e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431005
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(From CL 431233)
Limit battery charge voltage to prevent battery over-charge, due to
regulation inaccuracy. Since RO FW may charge > 8656 mV, ensure the
battery is not full before charging.
BUG=chrome-os-partner:61906
BRANCH=none
TEST=Manual on Electro, sysjump with battery @ 99%, verify battery
discharges, then re-charges to 100%, before discharging once again.
Change-Id: I28212c83057a442fd75e39f8ad51927a7a1f2817
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/432857
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes incompatible changes to the nvmem layout: the header
is increased to accommodate a 16 byte sha ans a 16 byte padding for
future extensions.
The layout version field is also introduced to make it easier to track
changes in the future. When calculating SHA the entire partition above
the SHA field is processed. Encryption covers everything above the
header.
Introducing encryption makes it impossible to use flash contents
directly for read and compare operations.
The nvmem_setup function is modified to use the nvnem_save() instead
of writing into the flash directly.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=ran the following tests, all succeeded
make buildall -j
TEST_LIST_HOST=nvmem make runtests
tcg test suite
corp enroll on reef, reboot a few times, verify that enrollment sticks
Change-Id: I50b148ac0dc6bc924f4d65c67bc6610100d9dfc0
Reviewed-on: https://chromium-review.googlesource.com/428691
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On boards based on the g chip cryptographic functions come from
hardware, they should be implemented in chip/g as opposed to a
particular board.
The common modules (like nvmem) should be using some generic API,
which hopefully will be implemented by other chips, or could be
replaced by a purely software implementation where crypto hardware
support is not available.
Crypto API definition is being added in include/ and the g chip
implementation (a wrapper around dcrypto functions) is being added in
chip/g.
test/nvmem_vars.h needed to be edited to avoid conflict with
<string.h>.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=make buildall -j still passes. Booting reef with the new image
works fine too.
Change-Id: Ifef281215f89239966882ecbe3e90c8351b9b91a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431313
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
ISL9238 is able to measure currents when battery is discharging
(like ISL9237), and charging (new feature).
Reverse AMON (OTG output current) is also supported by ISL9238,
but isn't very interesting on our boards.
BRANCH=none
BUG=chrome-os-partner:61166
TEST=Plug charger, "amon" in EC console, check that values match
current meter + "battery" information. Unplug charger,
values match "battery" information.
Change-Id: I9ecae6bec9e2049d17ef1a4596dbd4e3ff59919e
Reviewed-on: https://chromium-review.googlesource.com/430474
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously only 1 pin DI0A1 was being read to distinguish between
SPI/I2C configurations. This change adds code to support reading 4
strapping pins DIOA9|DIOA1 and DIOA12|DIOA6 and enabling the internal
pullup/pulldown reistors to differentiate between weak and strong
external pull up/dn restistors. An 8 bit strap config id is produced
and then a config table is searched to match the config id with known
configuraitons. The board properties to be used are read from the
config table.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Modified the Cr50 dev board with 1M and 5k pullup/pulldown resistors
and connected them to 4 GPIOs (defined as strapping pins). Tested the
12 possible external pullup/pulldown configurations and verified that
the correct 5 bit value was produced for each configuration.
Tested with both Reef and Gru. On Reef the strap config = 0x12 and on
Gru it reads 0x2 as expected. Verfifed TPM was functional on both systems.
Change-Id: I18c625a2b6b904bf4bcdaf2665ed9c3cbdafeb54
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421580
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change attaches all events related to changes in the AP state to
hooks. Different boards will be using different mechanisms to detect the
AP state, so we shouldn't have anything tied directly to the detection
mechanism.
BUG=none
BRANCH=none
TEST=device detection still works and AP uart is still enabled/disabled
based on the AP and Servo state.
Change-Id: I423bb8a21a1d4adf06809437f646c563551fdb12
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With upcoming versioning of NVMEM contents let's replace term
'version' with term 'generation' in the existing nvmem implementation.
Generation would allow to tell between two instances of NVMEM stored
in flash memory. The upcoming version field in the header will be used
to tell between different nvmem layouts.
This patch was created by invoking the following command:
sed -i 's/VERSION/GENERATION/g;s/version/generation/g' \
common/nvmem.c include/nvmem.h test/nvmem.c
and then editing a few remaining capitalized instances.
This also fixes nvmem test broken by an earlier patch.
BRANCH=none
BUG=chrome-os-partner:62260
TEST=the following tests succeed:
make buildall -j
TEST_LIST_HOST=nvmem make runtests
booitng reef with cr50
Change-Id: I96e52dc93ca7c52c55794ba3e8c2774571212de0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431312
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Move GPIOs around so that VBUS detection is done via 2 GPIOs on
the EC side.
BRANCH=none
BUG=chrome-os-partner:61098
BUG=chrome-os-partner:61929
BUG=chrome-os-partner:61997
TEST=Rework board, VBUS detection works on both ports.
Change-Id: I5021b0877eff2e5710a42c7ba244faa557a361cb
Reviewed-on: https://chromium-review.googlesource.com/428485
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Base has 5.1K pull-down on detection pin, and there is a 100K
pull-up in the lid.
Accepts ADC values between 140 mV and 180 mV (4.4K to 5.8K) to
detect the base, and debounce for 5 ms. These values should be
verified later on with real hardware.
BRANCH=none
BUG=chrome-os-partner:61970
TEST=Manually with 5.1K resistor between BASE_DET_A and GND.
Change-Id: Ifded8475b06f8245e2636aa683beb0d2d0a9721d
Reviewed-on: https://chromium-review.googlesource.com/428733
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Each device keeps track of the last known state. If device_set_state
updates the device state to a new known state, then return true. Cr50
uses this returned value to check if the state has changed instead of
calculating it itself.
BUG=none
BRANCH=none
TEST=device detection still works
Change-Id: I8afac178c2c731def6f4f62ff7023fe169ec1479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also program EC_PLATFORM_RST as an out signal from the EC.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Compiles successfully for eve.
Change-Id: I41486e6050727ca822a27054244da3fed5ee3b7a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431194
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also program EC_PLATFORM_RST as an out signal from the EC.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Verified that reboot on EC console works fine for poppy. Board is
no longer stuck in G3.
Change-Id: I0a2b052790fec2d55417e32f5aea53a7438a038f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431193
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a config option that can be used by chipset to provide PMIC reset
using LDO_EN. This is required for ensuring that the AP is power
cycled properly. Implement the special pmic reset for skylake
chipsets.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Verified that reboot on EC console resets the AP and does not get
stuck in G3 on poppy.
Change-Id: I5f680fede5cb4effa86243f51edfdea09db4d975
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431192
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Enable basic tablet mode options using the tablet mode input.
Do not enable the lid angle mode yet as the sensors appear to
need some calibration before this is reliable.
For now TP is still disabled by EC in tablet mode, this also
needs re-evaluated and should in theory be done at the driver
level instead of by the EC.
BUG=chrome-os-partner:62223
BRANCH=none
TEST=ensure keyboard and trackpad stop at 360 position and
restored when opened
Change-Id: I4e1d16dc74ae7e53e731644538d9ef85ac0b12b6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431139
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To avoid inrush current from the external charger, enable
discharge on AC until the new charger is detected and
charge detect delay has passed.
BUG=chrome-os-partner:60547
BRANCH=none
TEST=multiple ramp resets
Change-Id: I9dbb028bc149589ac586e8ff1f5d4cc11ad4bb3f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431138
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Lid switch has an external pull-down so we should not
enable one here in hibernate
- LEDs should be high to turn off
BUG=chrome-os-partner:58666
BRANCH=none
TEST=manual testing:
1) power off and enter hibernate with alt+volup+h
2) ensure LEDs turn off
3) ensure system stays off when lid is closed
4) ensure system powers up when lid is opened
Change-Id: I3a13fa6e0fbcad4925f9fb1d96e6c38d7bb453c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/431137
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change introduces DCRYPTO_app_cipher(), an encrypt/decrypt
function that accepts an IV and corresponding data. Typical
restrictions on IV reuse apply. The key is derived from the hardware
based on the type of the RW image signature (dev vs prod).
A console command is added to exercise the cipher function.
Since stack requirements of the dcrypto code exceed the console task
allowance, the actual command is executed on the HOOKs task context.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=make buildall -j passes. Running the cipher command from the
console succeeds:
> cipher
original data ad67d44cb4feffff6b3b334635eb9612
rv 0x01, out data 861dc395a2fc745ca886a703cb02a897, time 16636 us
rv 0x01, orig. data ad67d44cb4feffff6b3b334635eb9612, time 17004 us
sha1 before and after match!
>
Change-Id: I7686d8c8489c1b8a984859c3be4f82c338573c6f
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Marius Schilder <mschilder@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428171
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Add and export chip_save_reset_flags to allow boards to use this
function when required.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Compiles successfully for poppy.
Change-Id: I6f96bc61135fc4e3abb62a01d47c2cba8eb45b60
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Remove all TP control because TP lose function.
Remove KB control because this action of disable KB in S3 work
after modify 'SENSOR_ACTIVE_S0' to 'SENSOR_ACTIVE_S0_S3'.
BUG=chrome-os-partner:62138
BRANCH=reef
TEST=check TP don't lose function after resume, then KB disable in
tablet mode and enable normal mode whether S0 or S3.
Change-Id: Ida023f8fa34cadb80dbcd071ee77927e94a5386d
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/430560
Commit-Ready: Aaron Durbin <adurbin@google.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add functions that derive application specific keys based
on FRK2. For the moment, derived keys need to be manually
copied into the AES engine. Since key-ladder state depends
on the code-signer (prod vs. dev), application derived keys
are also different in the two modes. Thus ciphertext blobs
produced by prod-signed code cannot be decrypted by dev-signed
code.
To minimize stack requirements on the hook_task, the SHA
context in DCRYPTO_appkey_init() is placed in allocated/freed
memory. This SHA object will become unnecessary once the
AES engine is seeded directly from the key-ladder.
BRANCH=none
BUG=chrome-os-partner:55331
TEST=pending
Change-Id: Ifb274b15e61be317e02ec31fc52f9a41e06dcba3
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Marius Schilder <mschilder@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428170
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Manually tested on Reef & Chell.
System can boot to OS. S3, S5, hibernate are working.
Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously in motion lid, we only considered the lid angle as unreliable
when the hinge is too closely aligned with the direction of gravity.
However, there are other cases where the lid angle can be unreliable.
For example, when the device is being shaken and is under acceleration
that's not solely due to gravity.
This commit adds some more checks for a reliable lid angle measurement.
- Checking if the device is significant motion by checking the
deviation of the magnitudes of the base and lid vectors.
- Making sure that the calculated angles agree with the current state
of the lid switch.
BUG=chrome-os-partner:59480
BUG=chrome-os-partner:59203
BRANCH=gru,cyan,glados,oak
TEST=Flash kevin; use ectool motionsense lid_angle and monitor the
instantaneous lid angle. Verify that unreliable is reported for cases
where the device is under significant motion.
TEST=Flash kevin; use evtest to monitor the tablet mode switch. Verify
that tablet mode switch is much more robust.
Change-Id: I4bd9e818e617b056364cce2e46385e743a7522d4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430344
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
For FAFT or debugging purposes we may want to leave ccd enabled no
matter what the voltages on the CC lines are. This change adds a 'ccd
force enable' which will keep ccd enabled until 'ccd disable' is run.
BUG=chrome-os-partner:61701
BRANCH=none
TEST=Plug in suzyq. Run 'ccd force enable'. Disconnect suzyq and on the
cr50 uart run 'ccd' to verify ccd is still enabled. Make sure the other
ccd commands work ok.
Change-Id: Ia7087ade3070a1320a74b985f4699533ecc396ef
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427346
Commit-Ready: Dan Shi <dshi@google.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There's no indication that the h/w AES function fails,
but checking the return value prevents applications
from silently proceeding and failing at a future time
(e.g. NVMEM encryption).
BRANCH=none
BUG=chrome-os-partner:55331
TEST=tpmtest.py passes
Change-Id: I8e3a9426ec31a1b0798aface55c636dc1c707b34
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430371
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
