memchr does not take into account end of string, so the test
`memchr("123", '4', 8)` actually does a buffer overflow. On some
boards, a '4' might be found in the 4 bytes that follow "123", and
the test might fail.
Fix another potential overflow as well.
BRANCH=none
BUG=none
TEST=Flash test-utils to hammer, test passes
Change-Id: I53755c0855bbd5b180801e4198341de1cec7b425
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1071409
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is mostly a clean up and refactoring change, which will make it
easier to extend rma_reset to supporting more EC curves.
BRANCH=none
BUG=b:73296606
TEST=verified that the same secret value is generated on the client
and server side by running
./rma_reset -t
./rma_reset -c <challenge generated by the previous command>
Change-Id: I15c010a4a62306bfaa56b97936318854b28a4945
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073756
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When invoking make with DEBUG=1 add '-g -O0' to the compiler
invocation to facilitate debugging with gdb.
BRANCH=none
BUG=b:73296606
TEST=verified that building with DEBUG=1 adds '-g -O0' to the compiler
invocation.
Change-Id: Idd80bd481091b91683200c78fe49dc7e9783a730
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1073755
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are still more ifdef than can be added: this just takes out
the low hanging fruits.
BRANCH=poppy
BUG=b:35647963
TEST=make buildall -j, see that we gain from 0 to 64 bytes on many
boards.
Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070948
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In rare cases, it is useful to be able to build tests for all boards:
buildall only builds the main image, but -paladin builders also builds
test cases for each board.
Also remove/fix tests for boards that currently fail.
BRANCH=none
BUG=b:35647963
TEST=make buildalltests -j, wait a long time, tests pass.
Change-Id: Id6d978705a40a2045731cb08ad2ca5d62cc12ebb
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072218
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow setting password from the AP, but not from USB. Remove the old
password control logic, which is no longer needed.
Allow open if:
- Not explicitly blocked
- Not blocked via FWMP
- One of the following is true:
- A password is set
- Battery is removed (also doesn't require physical presence)
- Dev mode is on, and request came from the AP
Reduces cr50 binary by 152 bytes.
BUG=b:79983505
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 build
ccd oops
ccd lock
ccd unlock -> fails
gsctool -U -> fails from host
gsctool -t -U -> fails from AP
ccd oops
ccd password foo -> fails from console
gsctool -P -> fails from host
gsctool -t -P -> works from AP
ccd get -> confirms password set
ccd lock
ccd unlock foo -> works
ccd lock
gsctool -U -> works from host, if correct password supplied
ccd lock
gsctool -t -U -> works from AP, if correct password supplied
ccd open foo -> works
ccd lock
gsctool -O -> works from host, if correct password supplied
ccd lock
gsctool -t -O -> works from AP, if correct password supplied
ccd oops
ccd lock
(remove battery)
ccd open -> works without physical presence
(reattach battery)
ccd lock
gsctool -O -> works from host
ccd lock
gsctool -t -O -> works from AP, if dev mode is enabled
Change-Id: I364b322d03db250e7dd140767d7a22dbb3ac1eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072957
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is needed so ccd_open() can see p->flags, for a subsequent
change. No change to existing command behavior or binary size.
BUG=b:79983505
BRANCH=cr50
TEST=gsctool -I still works
Change-Id: I614d8c410e8bc55a5045e253469b2ec222078684
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1072500
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Move code that will be common to Grunt and Careena to baseboard
to avoid duplication when creating the Careena board.
Add Careena board files. These are currently just a copy of Grunt
and will be modified for Careena next.
BUG=b:79704826
BRANCH=none
TEST=Grunt still boots ok.
Change-Id: I6dd0035bdd62e92a7f3664120fc6ac3f23a0af4d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070988
We need to disable under voltage protection because it prevents us from
enabling the sink path when there is not Vbus on the connector side. We
need to enable the sink path before we hibernate otherwise there is no
power power to get to the charger which will then assert ACOK. Without
this we won't wake up with the ACOK wake when USB power is inserted.
BRANCH=none
BUG=b:79948623
TEST=bip wakes with USB power insertion
Change-Id: Idf16a92dacde63cf943ef68b0258b320d11de44c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
PS8751 supports the TCPCI spec for controlling the power source and sink
path, which is done through GPIO0 and GPIO1, respectively, by default.
BRANCH=none
BUG=b:78896495,b:78021059
TEST=verified TCPC drives PPC via reworked yorp board.
Change-Id: Ie1de67495947b787ad9cd5aee0db3ca21bec5a10
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047796
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The BMI160 driver's init function generates a divide by 0 error
by calling config_interrupt before initializing the range defined
in struct accelgyro_saved_data_t. The explicit error is
generated by macro BMI160_TAP_TH that's called in config_interrupt.
BUG=b:80237518
BRANCH=None
TEST=`make -j buildall`
EVE boots from TOT
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I8b7a4a7c63c973bcc639779ee54958f3702f1b36
Reviewed-on: https://chromium-review.googlesource.com/1071847
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
When using larger block sizes (e.g. 4096 bytes), the write operations
take too long, which often causes a watchdog reset.
Fix this by reloading the watchdog after programming
every 64 bytes page.
BRANCH=poppy
BUG=b:80167548
TEST=Copy old touchpad FW to soraka, build staff, make sure FW
can be updated.
Change-Id: Ic6e7a3e3ef63877a4f2d5011e1fb0d49c04177a6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070952
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
bip also need to enable the sink path when going into hibernate
BRANCH=none
BUG=b:79948623
TEST=on bip, verfied that AC_OK, LID_OPEN, and POWER_BTN all wake the EC
up.
Change-Id: I2c1168f856cc45635b5c76f7ca409007fcf141cc
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1065203
I noticed data was getting dropped from my console output on
bip. Adding the cflush fixes it.
BRANCH=none
BUG=none
TEST=ppc_dump 0 on bip works
Change-Id: Ib71cb37c4c8728a7ab958905d3b2627b8c163faa
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070626
Saving space in RW, even if we are not critical in terms of size,
always helps to reduce verification time.
BRANCH=poppy
BUG=b:35647963
TEST=make newsize => Hammer shrinks by ~3k, verification time
down by ~12 ms.
Change-Id: I63741106fdc56c410871fb367c29605bf37f1b77
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070951
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On hammer, we do not need the console channels, so we can just
disable them to save flash size.
BRANCH=poppy
BUG=b:35647963
TEST=make newsizes, staff image size shrinks by 704 bytes
Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070949
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When grunt is connected via a Suzy-Q cable, it can only be flashed using
npcx_uut. Also when grunt is connected via a servo it shouldn't try to
use npcx_uut, but instead use npcx_spi. This change allows a board to
show up in multiple BOARDS_XXX lists. If there are multiples, it will
either look at the --chips flag, or it will check the VALID_CHIP_COMBO
array to see if chip is valid for the servo type.
BUG=b:77927814
BRANCH=none
TEST=Tested each leg of the logic by changing parameters and variables.
Tested using Suzy-Q: ./util/flash_ec --board=grunt
Also tested using ServoV2: ./util/flash_ec --board=grunt
Change-Id: I7068b5bab0cf20bd2d9ffdd3842a58df1f2f8810
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1044499
Commit-Ready: Martin Roth <martinroth@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
With the changes made to tcpci for alert handling and low power mode
entry, the anx7447 can operate with auto toggle and low power config
options.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:77544959
BRANCH=none
TEST=Verfied that low power mode is entered when nothing is attached
and that when an adapter is attached it connects and when removed
returns to low power mode.
Change-Id: I9c683c3f86ba98e55748ac355b3d4845799d89e5
Reviewed-on: https://chromium-review.googlesource.com/1049061
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
SERIIRQ# is by default deasserted level high. However, when using
eSPI, SERIRQ# is routed over virtual wire as interrupt event. As per
eSPI base spec (doc#327432), all virtual wire interrupt events are
deasserted level low. Thus, it is necessary to configure this
interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
signal appropriately over eSPI/LPC depending upon the selected mode.
BUG=b:79897267
BRANCH=None
TEST=Verified using evtest that keypresses are properly identified on
the OS side.
Change-Id: Ie3b92f20fa915ba8f17dcbcb600ebfe5cbfb4d57
Signed-off-by: Dino Li <dino.li@ite.corp-partner.google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069570
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This makes it easier to add params or flags for vendor commands
without changing all of the command handlers. It also reduces code
size by 56 bytes.
For now, existing command handlers continue to use
DECLARE_VENDOR_COMMAND(). Added DECLARE_VENDOR_COMMAND_P() for
handlers which take the params struct directly. The CCD command will
be the first user of that, since it will have different rules for
'open' based on where the command comes from.
No change to existing command behavior.
BUG=b:79983505
BRANCH=cr50
TEST=gsctool -I still works
Change-Id: I7ed288a9c45e381162e246b50ae88cf76e67490d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069538
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Previously, calls to tpm_alt_extension() were treated as if they came
from the AP via the TPM interface, even though they actually
originated from the cr50 console, which is accessible via the USB
interface.
This affects the following console commands:
spi_hash - was already allowed as both a safe console command and via
the USB vendor command interface. No change.
rma_auth - was allowed as a safe console command, but not via the USB
vendor command interface. Now allowed from both. No change in
security, since anyone could already do it via the console.
Unfortunately, getting a challenge fails because commands issued via
the USB vendor command interface have a maximum payload of 32 bytes
and the challenge is bigger than that; that's tracked in b:80098603.
ccd - was already allowed as a safe console command. This directly
called ccd_command_wrapper() for lock, open, and password subcommands.
It made an extra check for password set for the unlock subcommand.
Moved the unlock check to the vendor command handler. Also changed
the order of checks so that FWMP disabling unlock and open supersedes
an existing password; this matches go/ccd-open-simple. (That has no
effect on existing systems, because CCD is disabled at a higher
level.)
Reduces code size by 8 bytes.
BUG=b:79983505
BRANCH=cr50
TEST=manual, on a CR50_DEV=1 build
Compile with DEBUG_EXTENSION defined to print extra debug output
'ccd lock' now shows as coming from USB
'ccd unlock' fails because no password is set
'ccd unlock' and 'ccd open' fail if FWMP disallows unlock
'rma_auth' prints a challenge
'gsctool -t -r' prints a challenge from AP root shell
'gsctool -r 12345678' returns error 6 (incorrect challenge), rather
than error 127 (no such command).
'gsctool -I' works from the host
'gsctool -t -I' still works from AP root shell
Change-Id: I2cd1027f5135b9c336df97ee4b1b1a15354728b4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1068102
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Update rules for util/genvif to allow usb_pd_policy.c to be present
in just baseboard, or just board, or both.
BUG=b:78638238,b:79704826
BRANCH=none
TEST=make -j buildall
Change-Id: I4e2970a65c131d0681d2159fe2ea18b2639048c9
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067751
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Enable PWM control of backlight in EC for yorp and phaser. Proto build
of bip will not have backlight control in EC.
BRANCH=none
BUG=b:79422226
TEST=none (no hardware to test with)
Change-Id: Ib6ed4af4de3145b112ed43b4ca1ec9f931f3875f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1050785
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Need to enable PPC interrupts, otherwise system doesn't work correctly
include USB 2.0 not working (since the BC1.2 chip won't be powered after
the Vbus change)
BRANCH=none
BUG=b:79886742
TEST=USB 2.0 works on insertion on C0 on bip
Change-Id: I227dcfac22128389c3d3ab3efdddd045141dff7e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1066221
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Observed task stack sizes growing, especially PD related.
Adjust chip configuration for 64KB data.
Use RAM size config items in flash layout config items.
Update SPI image generator python script to not add
a Boot-ROM header to EC_RW and add a test mode for debugging
SPI read and hash calculations.
BRANCH=none
BUG=
TEST=Build boards based on chip mchp. Check RO and RW
EC binaries are correct size and located properly in
ec.bin
CQ-DEPEND=CL:1036258,CL:1053576
Change-Id: I12709a434d5aaa84fabe459176a3423365343308
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053948
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The values of CROS_EC_VERSION and VERSION variables generated by
getversion.sh are exactly the same. VERSION is used in more places
than CROS_EC_VERSION, let's keep VERSION and use it everywhere.
BRANCH=none
BUG=chromium:632937
TEST=make buildall
Change-Id: Ibec9ecdd4b67789a468dddfbc1c82565f90d48a8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069330
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added flags parameter to extension_route_command(). The caller now
specifies whether the command comes from the USB interface or the AP.
Moved USB-specific shuffling of response to embed result code into
usb_upgrade.c, so extension_route_command() can be more generic.
No change to permissions/behavior for existing commands.
ccd_command_wrapper() still sends vendor commands as if they come from
the AP. That's fixed in the next CL.
Reduces code size by 128 bytes
BUG=b:79983505
BRANCH=cr50
TEST=manual
Build with DEBUG_EXTENSION defined, to turn on printing each command
'ccd lock' comes from AP and works
From host, 'gscutil -I' comes from USB and fails
From AP, 'gscutil -t -I' comes from AP and works
Change-Id: I7136bb54073de9c5951a174c308151b1871c56f3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1068101
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The new GCC build shows a warning/error in clock-f.c:
'alarm_us' may be used uninitialized in this function
[-Werror=maybe-uninitialized]
This is actually a fake warning. In the context of the logic,
there is no way 'alarm_us' would be used uninitialized.
But let's still initialize 'alarm_us' to clear the compiler warning.
BUG=none
BRANCH=scarlet
TEST='USE=coreboot-sdk emerge-scarlet chromeos-ec'
TEST=make buildall -j
Change-Id: I7a0642cbe03c5a0adb6997ddc80c9cb797715749
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068256
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
We have converted all LPC-only configs to HOSTCMD_LPC so the remaining
CONFIG_LPC defines represent the common case.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067503
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
