Our maximum power is 45W so we don't need to keep this limit. Also we can
drop the TODO since we have a bug to track that work.
BUG=b:69683178
BRANCH=none
TEST=emerge-grunt chromeos-ec
Change-Id: Ie40847e3e88653225dc228563c1ac89cc0970316
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1031115
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Normally on lid open, if chipset is off, we pulse the power button
to wake the AP. If we are in PWRBTN_STATE_INIT_ON, then we are already
waiting to power on the AP so ignore the lid open to avoid turning
on the AP too soon.
BUG=b:77455171
BRANCH=none
TEST=Plug power into Grunt with no battery.
Change-Id: Ie57e998725af0ace525f9f2102a0f5a282382a57
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1031565
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w
to npcx7m7wb for better clafiication since it introduced new parameter
"b" for chip generation in the same family series.
In new npcx7 series naming rule, it follows:
Format: NPCX7(M)(N)(G/K/F)(B/C)
param M: 8: 128-pins package, 9: 144-pins package
param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
param G/K/F/W: Google EC depends on specific features.
param B/C: Chip generation in npcx7. (Generation A is ignored. It
follows nameing rule in npcx5.)
The all chip variants of npcx7 used in boards are also listed below:
npcx7m6g - for npcx7 ec without internal flash on npcx_evb.
npcx7m6f - for npcx7 ec with internal flash.
npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.
BRANCH=none
BUG=none
TEST=No build errors for npcx7 series.
Change-Id: I896ee33209efa5d7157c90515005db5f36318c76
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1025471
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In order to be able to recover from the AP and Cr50 getting out of
sync, this logging functionality gives Cr50 a way to track the
state changes of the merkle tree so that the AP can be updated to
the current state as long as it has a recent enough copy.
This involves packing the important information so it can be stored
efficiently on flash, and adding the necessary messages for the
replay.
CQ-DEPEND=CL:895395,CL:929430
BRANCH=none
BUG=chromium:809729, chromium:809745
TEST=cd ~/src/platform/ec && V=1 make run-weaver_ng -j
Change-Id: I40f98de2c8e9706cccb5b922215699f2132fa121
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/963773
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This connects the pinweaver code to the tpm vendor
specific command code.
CQ-DEPEND=CL:895395
BRANCH=none
BUG=chromium:809741
TEST=TBD
Change-Id: I2a6c4bf52ad77b7bf0395095404e925e1dd48dbc
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/929430
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This adds some of the ground work for hardware backed brute force
resistance on Cr50. The feature is called Pinweaver. It will
initially be used to enable PIN authentication on CrOS devices
without reducing the security of the platform. A Merkle tree is
used to validate encrypted metadata used to track login attempts.
The metadata tracks counts of failed attempts, a timestamp of the
last failed attempt, the secrets, and any associated parameters.
Instead of storing the metadata on Cr50 an AES-CTR is used with an
HMAC to encrypt the data so it can be stored off-chip and loaded
when needed.
The Merkle tree is used to track the current state of all the
metadata to prevent replay attacks of previously exported copies.
It is a tree of hashes whose root hash is stored on Cr50, and whose
leaves are the HMACs of the encrypted metadata.
BRANCH=none
BUG=chromium:809730, chromium:809741, chromium:809743, chromium:809747
TEST=cd ~/src/platform/ec && V=1 make run-pinweaver -j
Change-Id: Id10bb49d8ebc5a487dd90c6093bc0f51dadbd124
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/895395
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Also implement a few remaining usb function for bip
BRANCH=none
BUG=b:75972988,b:76218141,b:74132235,b:78344554
TEST=verified yorp still functions
Change-Id: I201408b5db689ac4a5bcab0011bc38698271b851
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024279
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1.5A is really too low for our bringup tests, increase it to max until we have
a battery driver.
BRANCH=none
BUG=b/74395451
TEST="gpioset EN_PP5000_A 1" should not brownout the system
TEST=Backlight can turn on
TEST=Kernel boots and is stable for swboyd
Change-Id: I789b18304c36f6f68296796c076699af722cb5d6
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024502
Reviewed-by: Wai-Hong Tam <waihong@google.com>
We need to tune the i2c parameters for the nuvoton chip on our yorp board
to be able to operate at 400kHz. Currently we do not need the extra speed
or bandwidth, so we are reverting to a lower speed where the default
timing parameters work well.
BRANCH=none
BUG=b:78554726,b:78225299
TEST=HDMI over TypeC works on yorp
This reverts commit 2e7e6665b1.
Change-Id: Ic4ba1d5ef25661bd6c7f9490450af65b4e1393ad
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This was missed on it83xx, but is helpful for servod
to work reliably. Refactor save_flags to use common code.
BUG=b:77830536
TEST=(not yet done) it waits 10 sec for external reboot.
Change-Id: Ia2aac1879d73ac11dd7f3dfc13a1dd871905473e
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1018597
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch adds LED control for Akali. Akali needs to show an irregular
pattern in S3 (On 1 sec off 3 sec). This patch adds 'alternate' mode
support. It allows an LED to extend off period. In alternate mode, an
LED goes through on-off-off-off cycles.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77827579
BRANCH=none
TEST=Verify on Nami.
Change-Id: Ia7541236a6c598173cb94089224ac8c0a3f63a68
Reviewed-on: https://chromium-review.googlesource.com/1024691
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Currently, if a board supports dual role power ports, the EC will
briefly apply Rp resistors on the CC lines upon initializing the PD
tasks. This was put in place such that the partner port is a known
state. In the case of an external PD charger, the presence of the Rp
will cause the charger to stop sourcing VBUS. We only apply the pull up
for reset cases where the EC did not just loose power (e.g. power on
reset or brownout).
This however presents a problem when booting off of AC only. If a user
types 'reboot ap-off', there will be an extra reset because VBUS is
dropped and the "ap-off" flag will be lost.
This commit simply checks to see if there is an explicit contract in
place for a port. If an explicit contract is in place and PD
communications are allowed, we will not apply the Rp resistors. The PD
state machine will then attempt to send a SoftReset to the port partner
in order to reset the PD protocol layer. If an explicit contract is not
in place, or if PD communications are not allowed, the Rp's will be
asserted briefly as before.
BUG=b:72838807,b:35587129,chromium:712746
BRANCH=None
TEST=Flash zoombini; Remove battery and plug in just AC; Enter `reboot
ap-off` and verify that AP remains off in the subsequent boot and there
is no extra reset.
TEST=Make zoombini locked. Have a PD contract in RW, reboot to RO and
verify that VBUS is dropped from a PD charger.
TEST=Repeat test on meowth.
CQ-DEPEND=CL:905922
Change-Id: Ie2e3fe5b6b318e166b2a42dfa3241646369ec571
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905390
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
According to PD spec:
- Data role shall not be reset on soft reset.
- Data role shall be reset to power-role default on hard reset.
Implement the above. Even if both ports follow spec, it's still possible
for a data role conflict to occur if, for example, data role swap occurs
(data role mismatches power role default) followed by a hardware reset
of one port (such that data role gets reset to power role default).
Handle such cases by taking error recovery actions.
BUG=b:71333840,chromium:805040
TEST=Connect scarlet to powered Apple accessory, verify scarlet comes up
in SNK-DFP after soft reset and issuing "reboot" on EC console. After
issuing a hard reset, the port comes up in SNK-UFP (which is the
power-role default).
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I65139f277d59a0612f8323d711080f52425ff5e7
Reviewed-on: https://chromium-review.googlesource.com/885462
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In order to re-initialize our PD state variables properly following a
reset, we need to save our current power role. This commit adds a bit
in the BBRAM PD flags for the power role.
BUG=b:71333840,chromium:805040
BRANCH=None
TEST=Add code to save data role and restore both roles, verify that both
are saved accordingly.
Change-Id: I156ae8179c8e12c63322132d1f0078990bd215f8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/979264
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
samus_pd is out of space again (groundhogday.jpg). Remove the `crash`
command. This command is needed for a FAFT test (firmware_ECSharedMem)
and you cannot qualify a firmware without it. However, for samus_pd, we
don't seem to run this test against samus_pd itself, but just samus.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I7e34a1a7a9fcdd36e1d97b1226b66dc3f25213f0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/917012
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Wheatley needs more space (probably to store his book collection
including works of Machiavelli). Therefore, enable
CONFIG_COMMON_GPIO_SHORTNAMES to save space.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: Ia5dc8d36c9ae8dea6272a28677609f229a835f96
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/917011
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
pd_get/set_saved_active() made the assumption that there were only two
ports. But now, we have a board that turned that port count all the way
up to 3. This commit adds in that new port BBRAM index. It also turns
the byte where the port information was stored into a byte of flags,
where bit 0 indicates whether there was an explicit contract in place or
not.
BUG=b:72838807
BRANCH=None
TEST=With some code to check for explicit contract state for port 2,
verify it's functional.
Change-Id: I6f062f67bd3c47dd43ea7e24e844a9286fa37af9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905923
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Currently, there's only one board with 3 PD ports and it uses NPCX.
Therefore, this commit just adds the index to NPCX which will be used to
save the fact that there was an explicit contract in place.
BUG=b:72838807
BRANCH=None
TEST=make -j buildall
CQ-DEPEND=CL:905390
Change-Id: Ic960f14a52f2a740adbe08bc340c45edfefbbf26
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905922
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When issuing a host command whose request packet length is equal to the
maximum size (ie max_request_packet_size as returned by
EC_CMD_GET_PROTOCOL_INFO), the command currently fails with STM32H7 over
SPI host protocol.
The finger template upload through the EC_CMD_FP_TEMPLATE host command
fails due to the issue as it 'optimizes' the chunk length to the maximum
size. For now, workaround this issue by removing a 32-bit word (aka 4 bytes)
to max_request_packet_size, so we never hit this corner case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:78544921
TEST=On Meowth, run 'ectool --name=cros_fp fptemplate finger0.bin'
and see it succeeding.
Change-Id: I52072ddeb12534045c37ab30df301a60c8841199
Reviewed-on: https://chromium-review.googlesource.com/1026680
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
While troubleshooting why a generic $19.99 Multiport (USB, HDMI, Type-C)
Type-C dongle didn't work on Scarlet, I noticed that Vconn Req and Vbus
Req were both set to zero in the AMA VDO. For a better user experience,
default to Vbus ON if both Vconn and Vbus Req are both zero.
BUG=b:78286905
BRANCH=NONE
TEST=manual
Tested the generic dongle with USB-Keyboard, TypeC power adapter,
and HP monitor.
Change-Id: I170eef1372c3621334de2c457bd4533eea744cc0
Signed-off-by: Sam Hurst <shurst@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1019611
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Apparently the symbol in the yorp schematic is incorrect for our part.
The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust
the gpio used for PMIC_EN.
Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD
functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables
gpio functionality by default. If that changes, the board options will
need to change as well.
BUG=b:78352179
TEST=Built. Booted. PMIC_EN goes up and down as expected.
BRANCH=none
Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1026375
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The PS8751 is only being used as mux with the option of
being a TCPC is we stuff resistor on the subboard. The
default resistor configuration uses ITE EC as C1 TCPC.
BRANCH=NONE
BUG=b:78341944
TEST=none
Change-Id: I4ccad314fa7eec0d205a155e42e52109cff5811f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024487
We need to use the PS8751 as the USB mux without configuring
it as the TCPC. Add mode that allows passing in i2c port
and address instead using tcpc_config_t values.
BRANCH=none
BUG=b:78341944
TEST=build using bip
Change-Id: I45b420ef890dfa8c5e5052864b7a2bb66d8734d6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024486
Add support for finding the cr50 uart given a servo port or being given
a servo console using -d. If servod is using ccd to run, we need to do
ccd_reset after the authcode reboot. Add support for that as well.
BUG=none
BRANCH=none
TEST=none
Change-Id: I972ce60a2e67cc68b604d550579fb2e99db8ac08
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1025267
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
BUG=b:74256016
BRANCH=scarlet
CQ-DEPEND=CL:1025118
TEST=On scarlet, run 'date; powerd_dbus_suspend --wakeup_timeout=10; date',
confirm alarm works and the sleep time is ~10 secs
TEST='idlestat' when scarlet is in S3, confirm scarlet enters sleep mode
and wakes up without missing wake deadline
TEST=Run 'power_Resume' test on scarlet for 10 times and see consistent
'seconds_system_resume'
Change-Id: I4b0cbc2a6b8a85047b682358aec374e8f05a4346
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1008838
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Once the PS8751 has new firmware, it will be able to detect VBus
at the appropriate time. After that, we can go back to using the
cached version of Vbus detection.
BRANCH=none
BUG=b:77639399
TEST=none
Change-Id: I691919f3bd2479a131aa58763c7906cb4f6919ff
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024531
Use servo to boot EC into the flashing mode. Use the unified control
ec_boot_mode to do so.
CQ-DEPEND=CL:1018206
BRANCH=none
BUG=b:68707064
TEST=Ran the flash_ec script on Cheza using servo-micro
TEST=Ran the flash_ec script on Meowth using CCD, with some servo
overlays to drive the ccd_ec_boot_mode control
Change-Id: I32dfe5baa82dd842b5237f38ea971c09e91c47d3
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1020159
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Side-band wake was only useful when the lid would go in deep-S3,
where the USB interface is disabled. Since we are using S0ix on
poppy and derivatives, the side band wake is useless, and, in
some rare case, may actually cause issues.
BRANCH=poppy
BUG=b:77828249
TEST=Flash staff, can wake soraka from suspend, or from USB
autosuspend.
Change-Id: I23398a792157b32a5d79505dcffc92aaffd4fec2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1011523
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Enabling the SPI slave interface and the host interface depending on the
detected PCH power state.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991
TEST=On Meowth, check that the MCU interrupt is seen on the CPU side and
we can still send host commands.
TEST=On ZerbleBarn, verify that the SPI slave interface is enabled at
startup.
Change-Id: Ie7b22e69178bc7d34be6ab28ab24db82fefd5a02
Reviewed-on: https://chromium-review.googlesource.com/966023
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Try to ensure the SPI host protocol byte codes (aka EC_SPI_xxx) are
transmitted and at the right time despite the errata and other brokenness
of the SPI HW controller in the STM32H7 rev Y silicon.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:73947203
TEST=on Meowth, run:
'while true; do ectool --name=cros_fp version || break ; done'
same thing with 'fpinfo', 'fptemplate', 'fpframe'.
Change-Id: Ia455dc0d4b2803a150122655460ef5c11afcda6c
Reviewed-on: https://chromium-review.googlesource.com/1012202
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, the base power was enabled when the base was detected by the
lid. However, we should only power the base when the AP is on since it
just wastes power otherwise. This commit adds a pair of chipset hooks
to kick the state machine on startup and disable it on shutdown.
BUG=None
BRANCH=None
TEST=Flash meowth, attach base with AP off, verify that base power is
not enabled.
TEST=Remove base and attach base, verify that base power is disabled
when removed and enabled when attached.
TEST=Shut AP down, verify that base power is disabled.
TEST=Remove base and attach base, verify that base power remains
disabled.
TEST=Power on AP with base detached, verify that base power remains off.
Change-Id: I4379789987dbe91c72d699c4d184b5c5cc812e5f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1020525
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
the latest schematics have been updated to reflect the I2C bus
numbering used in the chip datasheets. this updates the software to
be consistent with the new datasheets. this is only a renaming
exercise, there are no physical changes to the board.
BUG=b:75070158,b:78309559
BRANCH=none
TEST=it compiles
Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020721
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This patch makes the battery LED blink at 0.5 sec interval in white
when battery error is detected.
This patch also changes the pulse interval resolution from 1 sec to 100
msec. There is no functionality change.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:74940319
BRANCH=none
TEST=Verify pulsing and blinking are not affected. Verify battery LED
blinks as intended on Sona.
Change-Id: I0767a6004861b9f07bc846d2ba5bf0df9067a748
Reviewed-on: https://chromium-review.googlesource.com/1017305
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
