KSI2 get stuck when Refresh+Pwrbtn is used to reset EC,
so it was not able to detect the Esc key if it is also
pressed to enter recovery mode.
BUG=chrome-os-partner:55548
BRANCH=none
TEST=Reef EVT is able to enter recovery mode with Esc+Refresh+Pwrbtn
Change-Id: I0539e8fad9980cb563de94417079fe763c311887
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/366411
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
when the daughter board is not connected, TCPC1 INT# (USB_C1_PD_INT_ODL)
will be floating since the external pull-up is located on the daughter
board as well, and this floating signal will cause an interrupt storm
and eventually cause a watchdog.
BUG=chrome-os-partner:55488
BRANCH=none
TEST=verify board no longer has watchdog reset when daughter baord
is not connected.
Change-Id: If1d73fa7d90f6ac52fd1ab0ac563a6bf5fd10dc0
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365499
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reef doesn't have the battery temperature sense pin connected to
the charger, hence reading the battery temperature from the battery
registers.
BUG=chrome-os-partner:55834
BRANCH=none
TEST=Using 'battery' & 'temps' console command verified,
temperature readings are same from both the commands.
Change-Id: I897e453296151f31344f3e0434202baa67c7025d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/365970
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This adds a hook that will run every second and complain if the EC
firmware was built for the wrong board.
BUG=chrome-os-partner:54947
BRANCH=none
TEST=tested on proto and EVT units
Change-Id: I9799249f74f3cea9a3f6b66b2441af8f16be7e01
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365505
Reviewed-by: Martin Roth <martinroth@chromium.org>
ESC+F3+Power+AC removal puts the battery into a soft-disconnect state
where is stops supplying current. Revive batteries in this state by
supplying a precharge current.
BUG=chrome-os-partner:55858
BRANCH=None
TEST=Manual on reef. Put battery into soft-disconnect state. Attach
charger and verify EC doesn't lose power and battery again supplies
current.
Change-Id: I9a772bf02a8bd40edc1db51de66de135f7299212
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365495
Commit-Ready: Rachel Nancollas <rachelsn@google.com>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Only report alert status if the PD chip is not being held in reset.
(idea borrowed from Amenia's implementation)
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: Ic637b1ab4e20527c806311a45c149b9ea5f64362
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360020
Reviewed-by: Martin Roth <martinroth@chromium.org>
Proto brought up 5V, 3.3V, and PMIC very early in the EC boot process
due to dependencies in the power topology. This had some other side-
effects, for example, a lot of the power rails would already be up by
the time the EC got around to processing the power state machine thus
leaving it waiting for signal changes that were supposed to come
later but had already occurred instead.
This patch updates the nominal codepath for rail and PMIC init on EVT
while using IS_PROTO to retain the Proto sequence if desired.
BUG=chrome-os-partner:54962
BRANCH=none
TEST=built and booted on proto and evt boards with subsequent patches
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: If9ddd41044f132e719b0b7f0ab80ed908ddb1d9b
Reviewed-on: https://chromium-review.googlesource.com/358913
Reviewed-by: Martin Roth <martinroth@chromium.org>
Updates for EVT:
- TCPC0 interrupt polarity is now low, define GPIO_INT and set ANX74xx
internal polarity control based on IS_PROTO.
- Swapped pin assignments for USB_C1_PD_INT_ODL and EN_USB_C1_5V_OUT.
- Rename USB_PD_RST_ODL to USB_C0_PD_RST_L and make it push-pull.
- Add USB_C1_PD_RST_ODL
BUG=chrome-os-partner:54958,chrome-os-partner:54952,chrome-os-partner:55165
BRANCH=none
TEST=needs testing
Change-Id: I075934cced532d656f942841c30e3640a6f42568
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358944
Reviewed-by: Duncan Laurie <dlaurie@google.com>
This ensures that we're only checking the reset signal for the
corresponding interrupt. Otherwise we can hit a race condition
when both TCPC chips are taken out of reset.
(This is also how it's done on Amenia)
BUG=none
BRANCH=none
TEST=needs testing
Change-Id: I47513b3b47e947c8b4644f4d837ddc3fb1ee7a30
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361061
Reviewed-by: Shawn N <shawnn@chromium.org>
This makes board_set_tcpc_power_mode() a noop since that's controlled
by anx74xx code and we have another TCPC chip onboard. Instead, we'll
reset the TCPC chips in a hook that will run after board and I2C init.
This is more like what Amenia code does.
BUG=chrome-os-partner:54952
BRANCH=none
TEST=needs testing.
Change-Id: Id3af4af1014432235b699a9568ee19df63601b2c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361060
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The case close debug (CCD) feature is provided by the external security
chip. We add CONFIG_CASE_CLOSED_DEBUG_EXTERNAL to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, plug a SuzyQ (with Rd/Rd) either in S5 or
transition the device to S5 afterwards and see the debug USB endpoint
works.
Change-Id: Icef4209470463be77d43f4a46e32769ebf58f558
Reviewed-on: https://chromium-review.googlesource.com/363401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This will be used to hack around code that only works on proto.
The earlier method of attempting to use board ID to determine
codepath worked to a limited extent, but fell short due to pin
swappings. So the dream of having a single binary that would work
on multiple board revisions died, and now if someone wants to build
for an old proto board they need to set this #define to 1.
BUG=chrome-os-partner:54947
BRANCH=none
TEST=tested with upcoming patches in this series
Change-Id: I5468c252e5401d69b108c75fa00b3dfbbcf77c22
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360949
Reviewed-by: Shawn N <shawnn@chromium.org>
In order for the vstore to be unlocked one needs to enable
the CHIPSET_RESET_HOOK. Do that for reef.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I94a41a08ad8649423988372607835da01ec12b8b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362001
Reviewed-by: Shawn N <shawnn@chromium.org>
This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
Regulate the system voltage by setting the charging voltage to battery
maximum in case of battery LEARN, Cut-off & No-battery conditions.
BUG=chrome-os-partner:55292, chrome-os-partner:55255
BRANCH=none
TEST=Manually tested on Amenia using console command charger.
Charging voltage is set to battery max in LEARN, Cut-off &
No-battery conditions.
Change-Id: I74bbab8174fd63b5f8439b8b35098db4a506d72d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/360681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added code to get the VBUS level by reading the charger registers.
BUG=chrome-os-partner:55117
BRANCH=none
TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh)
registers are updated with the correct VBUS value on the
respective ports.
Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359416
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This just adds a print statement to display board version at the
EC console the first time board_get_version() is called.
BUG=none
BRANCH=none
TEST=print shows up as expected with follow-up patches applied.
Change-Id: Ib7eae79a90bdaa58165aa5b102bc446f21a98963
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proto had two pins for PROCHOT# - One to monitor and one to override.
Newer boards have only one pin that serves both purposes.
BUG=chrome-os-partner:54953
BRANCH=none
TEST=built and booted on reef
Change-Id: Ida4bc2766caf15562c26e7a4b792a07604361da2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358940
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes corrections to the board ID values and also adds a small
multiplier to allow for higher-than-ideal voltages to match.
Currently we see values that are below the ideal value by about
2.5%, so it seems like a good idea to also allow slightly above ideal
voltage to account for variations in Vref or PP3300_EC that could
cause the calculated value to become higher than expected.
BUG=none
BRANCH=none
TEST=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia091fbbad7ffce2da9a04c48c7676ad9b4a08dea
Reviewed-on: https://chromium-review.googlesource.com/358614
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
The ADC multiplier and divider factors were lazily set to 1 when
the board support was first added, so the value was not scaled
properly.
The conversion formula is: Vi = CHNnDAT * (Vfs / 1024) where
Vfs = Vref = 2.816V for Reef.
BUG=none
BRANCH=none
TEST=added debug print and reading now approximately matches
what the voltmeter reads.
Change-Id: Ic60a8bc1d84c4f9a7b5664e9daddfa331b6a890c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358613
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Rename from V5A_EN to PMIC_EN.
The name V5A_EN came from Amenia where it controls both
5V_A-Rail and PMIC_EN.
Reef has a separate 5V_A-Rail control (EN_PP5000) and
an another GPIO pin for PMIC_EN.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=buildall pass
Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354767
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The motion sensor drivers used to rely on #defines indicating I2C or
SPI port to tell which to use. However, these days the drivers get
that info passed in via the motion_sensor_t struct. Now this #define
simply decides whether to compile in SPI or I2C wrapper code. We
should eventually make it less confusing, but that's beyond the scope
for now.
BUG=none
BRANCH=none
TEST=reef motion sensor init works now
Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356822
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added console commands for the debugging purpose
psys - Can be used to measure the system power
amonbmon - Can be used to measure AMON/BMON voltage diff, current
BUG=chrome-os-partner:54273
BRANCH=none
TEST=Manually tested on Amenia
psys - Ran fish task and observed psys value changes.
amonbmon - AMON & BMON voltage & current are same as measured
across sense resistors.
Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/353043
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
On EC reset where PMIC_EN will be pulled low,
PMIC could get into an unknown state and will
not sequence properly on sub-sequent boot.
This is a temporary workaround for Reef Proto,
a hardware change will be implemented on EVT.
BUG=chrome-os-partner:53974,chrome-os-partner:54507
BRANCH=none
TEST=Reef powers to S0 and starts coreboot after EC reset
Tested with servo cold reset button
and console reboot command
Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354762
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54503
BRANCH=none
TEST=Manually tested using console commands on both the ports.
a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is
1 when AC connected & 0 when AC disconnected.
b. Issued 'hibernate' & on plugging in the AC, device
boots to S0.
Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354721
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The motion sensors array as well as the config variables were copied
from another board and mostly wrong for Reef.
BUG=none
BRANCH=none
TEST=sensors which are connected successfully initialize, still need
to test lid sensors.
Change-Id: If8e1ec79803c7f378b21f4e9423a56bd6763eb4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349733
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
LID_OPEN gpio is present on the daughter card and provided by the
EC. Add an internal pull-up on it for the cases when the daughter card
isn't plugged in.
This fix won't be required starting EVT.
BUG=chrome-os-partner:54143, chrome-os-partner:53566
BRANCH=None
TEST=Compiles successfully. "gpioget LID_OPEN" returns 1 without
daughter card.
Change-Id: Ieff281b489e4f3f8be184a55b7975fb2efcc1099
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/350460
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In no battery condition set the battery minimum voltage to the
battery maximum voltage so that the charger voltage is set to the
battery maximum voltage. This adds more reliability for the system
and also avoids system reboot due to voltage drop on VBATA.
BUG=chrome-os-partner:53968
BRANCH=none
TEST=If battery is not present, EC console command 'charger'
gives battery maximum value.
Change-Id: I1f7740977cbe7087c27de95036a0eb5c385c0a54
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348942
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This updates SMI/SCI-related config options on Reef so that
SMIs and SCIs are generated correctly.
BUG=chrome-os-partner:53726
BRANCH=none
TEST=built and booted on Reef EC, firmware seemed more stable
(stayed up longer), but still see watchdog timesouts in task 13.
Change-Id: I6717f48a7655e49207fe34e6a166957eb34a05fd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349711
Reviewed-by: Shawn N <shawnn@chromium.org>
The default mode for the LPC pins is actually LPC. Setting the
altnerate function mode makes them GPIOs.
BUG=none
BRANCH=none
TEST=build and booted on Reef EC. Didn't seem to make much of a
difference on its own but with the follow-up things seemed more
stable.
Change-Id: Ibbc62d23d8d909be48a9bec90da8acebb9905b50
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347443
Reviewed-by: Shawn N <shawnn@chromium.org>
Update power sequencing as per Rachel's recommendation. We currently
wait for PP5000_PG and PP3300_PG before enabling the PMIC. This changes
the order so that we don't wait for PP3300_PG before setting the PMIC
enable.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=see scope shots mentioned in the BUG
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I022a9ab21c1bcb70dc72f358dbf89acb656851b8
Reviewed-on: https://chromium-review.googlesource.com/349291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This moves PP5000 and PP3300 enable early into board_init() and
increases priority of board_init() so that it runs before any TCPC
or PD init hooks which communicate with the TCPCs via I2C.
This hack also makes it so we don't shut off PP3300 for the time
being, at least until we get the proper sequence down and can avoid
I2C errors.
This probably is not the permanent solution, but for now it prevents
a lot of I2C errors from occurring.
BUG=chrome-os-partner:53549
BRANCH=none
TEST=booted on reef, no longer see I2C wedge error messages
Change-Id: I87e2e99aa3e1152cd10a2bfdd749d6e0dbd981a8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Move power rail and pmic enable control to be handled at
board level due to specific board design.
Modify rsmrst where assertion is pass-through at all time
and de-assertion is only pass-through at power up.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=amenia is able to handle apreset warm/cold, pmic shutdown,
soc reset/shutdown.
Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347370
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
