Initial support for Parade PS8740 Type-C redriving switch.
BUG=chrome-os-partner:41696
TEST=Manual on Glados in subsequent commit. Verify set() and get()
functions set and return consistent values. Verify that USB SS device
functions when muxes are set to dock or USB.
BRANCH=None
Change-Id: Iedbe53cc76f30ecd969c2ca99a7377ed3b193729
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282280
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In preparation for adding support for additional USB-C mux chips, add a
new high-level USB-C mux interface usb_mux.c. usb_mux functions are now
called from pd code instead of board-level functions. usb_mux calls down
into a mux chip-specific driver (currently pi3usb30532) or
board-specific drivers which toggle GPIOs (for legacy boards).
BUG=chrome-os-partner:41696
TEST=Manual on Glados in subsequent commit. Verify set() and get()
functions set and return consistent values. Verify that USB SS device
functions when muxes are set to dock or USB. Also, verify that DP
dongle and USB SS device are functional on both PD ports on samus_pd.
BRANCH=None
Change-Id: Ib6477f489310f3be1430585ea09fea26f57e3752
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281435
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Refactor the tcpm/tcpc split such that the tcpm driver implements
the alert functionality since it may be unique for different tcpc
chips.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall. run on samus and glados.
Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281631
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The suspend signal from SoC of oak should be kept at least 50ms.
Add a debounce time for suspend singal detection, to avoid transient
state during SoC boot up.
BUG=chrome-os-partner:42023
BRANCH=none
TEST=plug PD power adaptor to type-c port C1,
The keyboard should be worked (Ensure EC communication is oaky)
Change-Id: I4a6bb4e8ba9d417fe2a3045846d38b2129516d78
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282471
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
Updated the VDM information to handle properly the DisplayPort alternate
mode.
Switch to 2+2 (DP+USB3.0) if mode D is entered else use 4 lanes of DP
for mode C.
Set the Multi-Function Preferred bit, so laptops select the mode D.
BUG=none
BRANCH=none
TEST=Tested with samus. Verified we get 36W of power + USB2.0 key +
USB3.0 key + external DP display.
Change-Id: I95e3b3640fd5952faeb24312e387468aed6266c7
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267688
Reviewed-by: Todd Broch <tbroch@chromium.org>
There are several cases in the EC code base where a CONFIG_* option is
used somewhere, but not defined within the include/config.h file. This
script aims to fix that. Eventually, it will become a presubmit hook to
actively prevent future offenses.
BUG=chrome-os-partner:26304
BRANCH=none
TEST=cros lint --debug util/config_option_check.py
TEST=Ran script and found offending config options.
TEST=make -j buildall tests
Change-Id: I999d32ebacc636b3fff9e857f3cc46feee475e80
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/281626
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
In S3, the EC isn't expecting AP host commands, so it's safe to enable
sleep.
BRANCH=Ryu
BUG=chrome-os-partner:36918
TEST=Check sleep mask in S0 and S3.
Also check sleep mask after sysjump with AP on and with AP off.
Change-Id: I67f0634631f62ee571e18d2870cd4a6926d4e090
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/251750
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Get the USB hub out of reset only when there is a USB host,
same thing for the DisplayPort hardware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:37078
TEST=Plug and un-plug Honeybuns to Samus. See both the USB devices
connected and the external display.
Change-Id: Iabbeb0650d18c4c0c3324f47d99f9aaa35601c16
Reviewed-on: https://chromium-review.googlesource.com/281927
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Switch it to a source-only PD device (as it is)
and add the voltage selection code.
For now, output 12V only for 20V request as the 5V->20V transition is
not monotonic, triggering disconnection detection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:37078 chrome-os-partner:41860
TEST=connect to Samus and see it negotiate 5V then 20V,
then manually switch to 12V.
Change-Id: I4fc198245999ff9ce8fec929f305681043d72965
Reviewed-on: https://chromium-review.googlesource.com/259113
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF
interrupt context, causing deadlock and assertion
in __wait_evt().
In the interrupt context it now checks for mutex lock first.
If the mutex is already locked,, it will disable ACPI
interrupts and defer the memmap mutex lock.
Added LPC interrupt disable/enable functions as needed.
Increased deferred function count where needed.
BRANCH=None
BUG=chrome-os-partner:40820
TEST=Test for suspend-resume, cold, warm reboots and
other general stability.
Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
This change enables tmp432 thermal sensor. Enter "tmp432"
or "temps" in ec console and get temperature information.
BRANCH=none
BUG=none
TEST=manual
Enter "tmp432" to get temperature information.
Connect the battery and enter "temps" to get temperature
information.
Change-Id: Ie7a9fb4541c5cb3cfa6a26e95f99fe4aacb3a3d3
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280956
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add the console command "power on/off" for AP power on/off.
BRANCH=none
BUG=none
TEST=manual
enter "power on/off" in the ec console to turn AP power on/off.
Change-Id: I16d2af72bc1bf045e7672acd9471dff0a672aff5
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280957
Reviewed-by: Alec Berg <alecaberg@chromium.org>
There were many CONFIG_* options that were not defined in
include/config.h. This commit fixes that by adding those config options
that were missing with a brief description of each.
BUG=chromium:496893
BRANCH=none
TEST=Verified that every mention of CONFIG_* is in include/config.h.
TEST=make -j buildall tests
Change-Id: Ie60756a8dd48d12b3e9b775639f409455dc5656f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/281785
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Create driver/tcpm/ folder to hold TCPM drivers. Currently the
two drivers are a stub driver which is used when TCPM and TCPC
are on the same MCU and can make direct calls between the two
and the TCPCI driver which implements the standard TCPCI protocol.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall
Change-Id: Ie4d9b36eb33155254f8b87b83861f98a7a80693a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281630
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Set the resistance compensation for the charger IC according to the EE
team measurements :
- Resistance compensation = 60 mOhm
- Voltage clamping = 160 mV
- Thermal regulation = 120C
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:38603
TEST=dump the BQ25892 registers by using the "bq25" command and see that
REG08 contains 0x77.
Change-Id: I90e9ea4569d77fd90ed0290ec78e66810d744648
Reviewed-on: https://chromium-review.googlesource.com/281660
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Send PD_EVENT_POWER_CHANGE events for all changes in the type-C/PD
configuration to ensure we are not missing any transition from the AP.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41676
TEST=On Ryu, plug and unplug type-C chargers, C-to-A receptacle
adapters and A-to-C cables and see the proper "extcon" traces in the
kernel log.
Change-Id: I918b9c42867f069852a2222b0f47ef0df8d124aa
Reviewed-on: https://chromium-review.googlesource.com/280870
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Since the reset cause was not recorded correctly
recovery mode(Esc+Refresh+Power) was not working.
With this change power-on reset state and VCC1_RST# only state
are distinguinshed.
BUG=chrome-os-partner:41479
BRANCH=none
TEST=Esc+Refresh+Power boots to recovery screen
Refresh+Power reboots the system
Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280782
Reviewed-by: Shawn N <shawnn@chromium.org>
Base board configuration to evaluate USB PD interface chip by
connecting them a STM32F072 Discovery board.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:41497
TEST=Flash the STM32F072 discovery using the following command:
make flash BOARD=pdeval-stm32f072
then connect to the EC console through the USB port.
Change-Id: Ie3f5dcd04c077be49fbacc020f7af4f298039e8a
Reviewed-on: https://chromium-review.googlesource.com/277713
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Modify PDCMD task to allow for TCPCs that do not support host
commands.
CONFIG_HOSTCMD_PD is a new config option to be used by TCPCs
that implement our host command protocol such as the PD MCU on
glados and oak. Otherwise, the PDCMD task will not send host
commands and will be used simply to check TCPC interrupt status.
BUG=none
BRANCH=none
TEST=test on glados and samus and make sure we can send host
commands from the EC to the PD and that we can negotiate a PD
contract.
Change-Id: I618badb5db3f9e490ae4eedfdb2a0c54513496ff
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278215
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Changed the alert function to hold the ec_int line until
all of the alert bits are cleared. Added support for the
alert_mask register. In addition, created ec_int_status
variable to distinguish which of 3 ec_int sources is
driving the pd_mcu_int line.
BUG=none
BRANCH=tot
TEST=Tested Zinger to Glados and Zinger to Samus and verified
that it established a power contract in both cases. Did not
test Oak, but put exact same changes in board.c as in glados.
Change-Id: I372e75b8fd5d66a0c01db18b46100b86fd9ac064
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278256
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix USB PD check power and data swap functions after those
functions have been refactored and the args changed.
BUG=chrome-os-partner:41739
BRANCH=none
TEST=make -j buildall
Change-Id: I746774563d475710dc23c7290328fab150eaac6a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/280993
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no need for the usb flag, remove it.
There is no need for the unprotect flag, remove it.
BRANCH=none
BUG=chrome-os-partner:22990
TEST=run flash_ec before and after
Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update the recovery key combination to: power key + volume up when the
AP is off.
Add a fastboot key combination: power key + volume down when the AP is
off.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41629
TEST=on Ryu, shutdown the AP, press "power+volup" or "power+voldown" and
see the right trace.
Change-Id: I42cf368d42885717758fc4b494af5c8a16fc58b0
Reviewed-on: https://chromium-review.googlesource.com/278323
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
For the few platforms without gpio.inc, use this
enum gpio_signal {
GPIO_COUNT
};
instead of this
enum gpio_signal {
NULL
};
The only reason this worked at all is that the headers are
included in a particular order.
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I81533f3614d0b4c7389f9edd42cd8ac018581f46
Reviewed-on: https://chromium-review.googlesource.com/278120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Console command 'batter' reaches STM32F0's TASK_STACK_SIZE(488). Oak
needs a larger stack in development stage.
BRANCH=none
BUG=none
TEST=manual
load on oak and type 'battery' in console.
Change-Id: Iab3d0bd23837932acb873ecdeb194af74f10f29c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277979
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use the right rounding function for the charging voltage selection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41594
TEST=On Smaug EVT2, check that the battery is charging to 100% and
compare the voltage requested by the battery (using "battery" command)
to the voltage set by using "charger" command.
Change-Id: Ic5076f23242d1fac31ad34e0c8c9bfe0a868a91e
Reviewed-on: https://chromium-review.googlesource.com/278260
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Setup wakeup source and enable hibernate support.
BRANCH=none
BUG=chrome-os-partner:40752
TEST=manual
start servod:
sudo servod -b oak -c oak.xml
in EC console, type 'hibernate' to enter hibernate mode.
check ec 3.3v current and power consumption:
dut-control ec_3v3_ma ec_3v3_mw
check wakeup source:
open lid, press power button or plug in charger
Change-Id: Ic32c3879b0b9dac86c5e08ab9f3daba428c58720
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277978
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This just makes the LEDs blink continually, because I have a
development board sitting on my desk and I like to see it doing
something.
You can still force the GPIOs on and off using the tool in
extra/usb_gpio/.
BUG=none
BRANCH=none
TEST=make buildall
Try it:
sudo make BOARD=discovery-stm32f072 flash
The LEDs blink.
Force them on and off with:
cd extra/usb_gpio
make
./usb_gpio write -1 0
./usb_gpio write 0 -1
./usb_gpio write 2 0
./usb_gpio write 4 2
To resume blinking, use
./usb_gpio write 0 0
Change-Id: Iadbe7436c02de5b6eae81885d95bad154ca3692c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274131
Reviewed-by: Anton Staaf <robotboy@chromium.org>
This change enables USB3/DP superspeed mux. Oak's two type-C ports share
one DP hardware. When both ports connect to DP output device, only the
first DP signal will be routed to SoC. On exit dp mode, oak sends HPD
again if the other port's DP flag is on.
BRANCH=none
BUG=chrome-os-partner:41404
TEST=none
Change-Id: I7eebc0b2354f93d7421bf83796294a6b2acf4c3b
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277000
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add functions and associated test to read/write a 32 bit register
BRANCH=smaug
TEST=Test on smaug with bm160 driver
BUG=chromium:39900
Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277535
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
