The console and interpreter are usually killed by KeyboardInterrupt
whether or not it's run standalone or by servod. This commit tries to
make the exit graceful by closing pipes, file descriptors, and exiting
each process.
BUG=chromium:570526
BRANCH=None
TEST=Run ec3po standalone and hit Ctrl+C to kill it. Observe no
traceback and no leftover processes.
TEST=Repeat above test, but inside servod
TEST=cros lint --debug util/ec3po/console.py
TEST=cros lint --debug util/ec3po/interpreter.py
TEST=python2 -b util/ec3po/console_interpreter.py
TEST=python2 -b util/ec3po/console_interpreter.py
Change-Id: Ia151b9ede8adf7f8dec6c07277f62d097c13e63e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/319252
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
This is a rewrite of the Cr50 USB Device Control Endpoint
implementation, using the instructions in the DWC USB 2.0 OTG
Programmer's Guide (such as they are). Some of the major
differences:
* Not every USB interrupt indicates the receipt of an incoming
packet. Many merely provide updates on packet transfer status,
transaction stages, or other activity. We handle those
cases correctly.
* We may need to start a new Control transaction at any point,
even in the middle of an existing transaction.
* Large IN data transfers can be handled with one interrupt by
chaining multiple together.
* Logical separation of the phases of each transaction (Setup,
Data, Status).
That said, while this CL matches the Programmer's Guide fairly
closely, that Guide is pretty crappy and this is just the first
commit. There is still a fair amount to do (marked with comments
and bug reports). However, it works at least as well as the
previous version and is much closer to what the supplier claims
is the correct implementation.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
We also connected this device to Windows, and Mac laptops (and a
Chromebook) and used a USB bus analyzer to monitor the behavior.
It works on machines those, too.
Change-Id: Ic515ea83e217a8d0552d61ac5eb19693661fcd15
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/318864
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
[symptom]
The 'vboot_hash_start()' always return busy error and variable 'in_progress'
got a strange value(should be 0 or 1).
'start_irq_handler()' causes scratchpad overflow in first context switch.
It must be called after SP switch to system stack in ISR.
NOTE:
The scratchpad is still also need more size even if
'start_irq_handler()' is using system stack. following is detail:
1. uint32_t scratchpad[19] 0x81d34 ~ 0x81d7f
[__task_start:]
2. /* put the dummy stack pointer at the top of the stack in scratchpad */
addi $sp, $r3, 4 * 18
-> SP 0x81d7c
3. syscall push return address (-4)
-> SP 0x81d78
[ISR:]
4. push r15, fp, lp, and sp (-0x10)
-> SP 0x81d68
5. push r0 ~ r5 (-0x18)
-> SP 0x81d50
[__switch_task:]
6. /* save ipsw, ipc, r6, r7, r8, r9, r10 on the current process stack */ (-0x1C)
-> SP 0x81d34
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. hash done.
2. console command 'taskinfo'.
3. the scratchpad does not overflow after first context switch.
Change-Id: If5d89ff5c945a777010492fcfb54bf41f434ed69
Reviewed-on: https://chromium-review.googlesource.com/317468
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In 0% battery case, if the charger can provide power at least
15 Watt(CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW), will allow system to
boot up.
BUG=chrome-os-partner:48339
BRANCH=none
TEST=Verified in Kunimitsu system, system with 0% battery can boot up
normally once charger power is 15 Watt.
Change-Id: I0c7b23d4ac1e7bd2807ceeb068fc9018a99a03c4
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/318891
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
During power up, system will wait at most CHARGER_INITIALIZED_TRIES
delay to check if battery percentage or negociated charger power can
meet minimum requirement. In some cases, it takes longer time(observed
negotiated to min power took 2 seconds). So increase
CHARGER_INITIALIZED_TRIES from 10 to 40 to give total 4 seconds delay.
BUG=chrome-os-partner:48339
BRANCH=none
TEST=Verified in Kunimitsu system, negotiation to 5V@3A is done within
retry/delay.
Change-Id: I18c5fc676076f8d37d0a5360543f54aa85f48f77
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/318652
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This allocates more space for FIFO buffers, according to the
instructions in the Programmer's Guide. Many more comments and
some slight refactoring was added to explain the configuration
more clearly.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I1a870a4b1dc628729f7cd1b80bab7ec6dfd11f37
Reviewed-on: https://chromium-review.googlesource.com/318262
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for
keyboard scan function.
2. Critical section for gpio_set_level().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: gpioset, gpioget, and version.
Change-Id: I8edae122525e6dcebaa3489116642d8e48520569
Reviewed-on: https://chromium-review.googlesource.com/318112
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The double-mapping modules(CIR, BRAM, SSPI, PECI, and UART) won't work
if GPD2 pin's status is low and GCR register's setting is at default.
We move 'IT83XX_GPIO_GCR = 0x06;' to 'gpio_pre_init()'
to prevent this case.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Register 'GCR'=0x6 after init.
2. GPD2 is low and UART works.
Change-Id: I71b4436ab6c2a8f9e77e0d6f5116e5327a3167e7
Reviewed-on: https://chromium-review.googlesource.com/318131
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
keyboard_scan_enable() is called from several contexts. From a skim of
the code I found:
* keyboard_lid_change(), which is called from HOOK_LID_CHANGE
* enable_keyboard(), which is called from HOOK_CHIPSET_RESUME
* lidangle_keyscan_update(), which is called from motion_sense_task.
* check_for_power_off_event() which is called from power_handle_state()
which is called from chipset_task.
* power_button_interrupt(), which is an interrupt
* power_button_change_deferred(), which is a deferred function
So, ummm, it's probably not a good idea to do a read-modify-write of a
variable without any locking. ...and then to act on the resultant state
in various different contexts.
It's presumed that's just what happened to poor Julius. Julius found
himself in the unfortunate situation where he resumed his device (with
the power button, I believe) and that everything worked (including
reading the battery state and including the accelerometer) but the
keyboard didn't work. Now, it should be noted that Julius is a little
strange. Well, maybe he's not strange and maybe just the way he uses
his laptop is strange. He uses his veyron_minnie device as a smart
keyboard/trackpad. Said another way: it is in tablet mode but is docked
to an HDMI monitor, the screen is face flat on his table, and he uses
the builtin keyboard and trackpad. Nobody else that I know does this.
It's pretty darn cool, but I just don't think anyone else would think of
it. Anyway, that might have something to do with how he reproduced
this. ...or it might not. He does that a lot and hasn't seen the
problem before now.
Anyway, I managed to reproduce a number of problems similar to what poor
Julius saw by adding a 200ms sleep in keyboard_scan_enable() after we
read disable_scanning_mask but before we did anything to it (I skipped
the sleep if this happened to be one of those people who was calling
from interrupt).
Since there appears to be no spin_lock_irqsave() in the EC, let's just
have the EC use atomic operations to mess with its masks. Then we'll
leave all heavy lifting to the task.
This requires thinking through the task code a bit.
Conflicts:
common/keyboard_scan.c
...due to commit 6112f20679 ("common: keyboard_scan: Add items to
.bss.slow.") in ToT.
BRANCH=ToT
BUG=chrome-os-partner:48470
TEST=Poke a lot with power button and lid; NTF.
Change-Id: I61b906505100186b0ca2c48e7b1a7ffaaa8a7d3e
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317896
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 98ab7484d331a78fced870b58b4d82e79e2e0f4e)
Reviewed-on: https://chromium-review.googlesource.com/318292
No new functionality, just a little refactoring and general
cleanup of the USB initialization steps.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317376
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: Ia6922acf82a793759870a61217562f4e63608a80
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317319
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
No new functionality, just adding stub handlers for some
additional USB interupts that we'll eventually need to deal with.
BUG=chrome-os-partner:34893
BRANCH=none
CQ-DEPEND=CL:317354
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I805ac00432c31735d2904227c5d19ad53cfa7ccb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317376
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
The control endpoint (EP0) can receive some Setup packets that
are specific to individual Interfaces. The USB_DECLARE_IFACE
macro is used to register the callbacks that an interface
implementation provides to handle those Setup packets.
This change cleans up the callback API a bit, so that we don't
have to export the internal workings of the Cr50's EP0 interrupt
handler.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I9ac22f6a74f360f201c58e9ef39e3576834578a8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317269
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Enabling of ALS is done during resume hook.
During EC sw sync, resume hook is not called
and hence ALS task wont run.
Adding init hook to wake up the ALS task.
BUG=chrome-os-partner:48418
BRANCH=none
TEST= On Kunimitsu board, ensure sw sync is enabled.
In OS, cat /sys/bus/iio/devices/iio:devicesx/in_illuminace_input
should output valid value and not zero.
Change-Id: Iba1a3ab2cf7bfc2d8aa36cf9bb9b762f398882c3
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/317030
Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
No functional changes, just making the code prettier.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I1301c035eafc054567c1f317a80539197fcdeef4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317354
Enable the RSA verification of the RW partition,
so we are using the RW partition by default and
the USB PD flashing VDMs are able to update
the firmware over the Control Channel.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:47823
TEST=run the following sequence on a Samus connected to Honeybuns :
ectool --name=cros_pd infopddev 1
ectool --name=cros_pd flashpd 5 1 ec.RW.bin
ectool --name=cros_pd version
and see the honeybuns properly updated and running the new version.
Change-Id: I8f1612ee153a412620bae5822d1b354ad8072916
Reviewed-on: https://chromium-review.googlesource.com/312998
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
No functional changes, just some additional debug stuff that's
not normally compiled.
BUG=none
BRANCH=none
TEST=make buildall, manual
Connect the Cr50 to my workstation via USB:
* /bin/dmesg reports no errors
* verify EP0 with lsusb -v -d 18d1:5014
* verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses
case of input text)
* verify EP2 with the 'hid' command on the EC console (types a 'g')
Change-Id: I32b4944c01006f2e9c8cdb2e732a4b1710a60e19
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317560
The startup message includes the type of the image it is running (RO
vs RW currently). cr50 reports RW as RO, which this patch fixes. This
issue requires a bit more attention though: first, the RO type can be
deduced at compile time. Second, RW and RW_B should be accommodated.
RW_B should also be accounted in other places in the code where now
only two options are considered: RO vs RW.
BRANCH=none
BUG=chromium:567938
TEST=the startup message now reads:
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: RW, cr50_v1.1.4162-f1e71a6-dirty 2015-12-08 16:39:00 vbendeb@eskimo.mtv.corp.google.com]
Change-Id: I0db2db4413a13ebe915e1081b47cd4a6f85cbdd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316922
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds a setup script for the ec3po package. This is
necessary such that ec3po can be included as a part of ec-devutils.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=Update the ec-devutils ebuild to install the ec3po package.
sudo emerge ec-devutils; `python -c 'import ec3po'; print ec3po`
in the chroot. Verify that ec3po is installed in the site-packages.
TEST=Verify that interpreter and console modules are exported in the
package.
CQ-DEPEND=CL:316479
Change-Id: I5c8856b530936dc4ce3b09e38802f1e015c4576b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316701
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
It was brought to my attention that there were some issues with the
ec3po code. This commit addresses those issues raised.
- executable bits dropped from __init__.py and interpreter.py.
- sys.argv[1:] is now passed into console.py:main().
- Added blank lines at top of header.
- Removed dummy exception class (MoveCursorError).
- Added name of modules in the logger, so that it's not just 'root'
when included in other modules.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=./util/ec3po/console_unittest.py -b
TEST=./util/ec3po/interpreter_unittest.py -b
TEST=cros lint --debug ./util/ec3po/console.py
TEST=cros lint --debug ./util/ec3po/console_unittest.py
TEST=cros lint --debug ./util/ec3po/interpreter.py
TEST=cros lint --debug ./util/ec3po/interpreter_unittest.py
Change-Id: I00db368906958d1089c3662eb253be23f81cc70c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Newer versions of glibc have moved to _DEFAULT_SOURCE and away from
_BSD_SOURCE. Trying to use the BSD define by itself leads to warnings
which causes build failures.
BRANCH=none
BUG=None
TEST=precq still works
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Change-Id: Ice24b84dc6a540695fc7b76e8f22a4c85c301976
Reviewed-on: https://chromium-review.googlesource.com/316730
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we haven't sent a stop condition, make note of that, and send a
repeated start next time.
BUG=chrome-os-partner:48294
BRANCH=None
TEST=Verify "ectool i2cxfer 1 0x25 1 2" succeeds on glados. Also verify
`i2cscan` on EC console succeeds.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id45bfc6540dc1cc3a3d1e9f6916a238bce5ae33f
Reviewed-on: https://chromium-review.googlesource.com/316022
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When AP is suspended, only predefined events could wakeup AP.
Check EC_MKBP_EVENT_KEY_MATRIX event when we use embedded keyboard to make AP
wakeup from S3 power state.
BRANCH=none
BUG=chrome-os-partner:47554
TEST=Enter "powerd_dbus_suspend" in AP console to make system
suspend and then press embedded keyboard to wakeup AP.
Change-Id: I79f91776c39554a4e488e50841d3537fe85fea13
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/312156
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
two port PD will keep interrupt low, and cause
EC.PDCMD task stuck with exchange status loop before
entering task-while-loop
BUG=chrome-os-partner:48232
BRANCH=lars
TEST=`make BOARD=lars -j`, OS can boot up normally
Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/315362
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add 2 bytes into the TX byte count register used in
TCPC interface.
BUG=chrome-os-partner:48256
BRANCH=none
TEST=load on glados and attach zinger, make sure
PD negotiation successful.
Change-Id: Ie57d79f20def861c22f6e2e023545a65825ab3b4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315879
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previous HW didn't correctly support 20V charging. The HW has been
corrected and now there is no need to keep 20V mode disabled in FW.
BUG=chrome-os-partner:48217
BRANCH=none
TEST=Tested in the lab by jguerin@ against Samus
Change-Id: I952872affb302c7aa2ddb97466cd5ce459d2ac54
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315219
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow boards to customize both the PWM frequency / period and the
enabling of complementary output signals.
BUG=chrome-os-partner:48044
TEST=Manual with snoball w/ subsequent commit. Run `pwm <ch> 50` for
each channel, verify with `adc` that each PD output voltage is
approximately VBUCK / 2.
BRANCH=None
Change-Id: I61cbb4a5b656f41ec7cec59339f5247902256295
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315141
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If we're still in DISCONNECTED or DISCONNECTED_DEBOUNCE state, don't check
CC lines to detect a disconnect since CC polarity has not yet been
established.
BUG=chrome-os-partner:48220
BRANCH=None
TEST=Verify PD contact can be negotiated on Snoball with either polarity.
Change-Id: Iacde14446c0ff5d2170936b650f56668038f613e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315780
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
A new extended subcommand code (1) is being added to handle hash
testing.
The new subcommand handler keeps track of multiple sha1 and sha256
contexts the host might want to exercise. The number of available
contexts is limited by the amount of available free memory.
One of four hash operations could be requested by the host: 'Start',
'Continue', 'Finish' - when hashing a single stream over multiple
extended command messages, and 'Single' when the entire message to be
hashed is included in one extended command payload.
The command payload had the following format:
* field | size | note
* ===================================================================
* mode | 1 | 0 - start, 1 - cont., 2 - finish, 3 - single
* hash_mode | 1 | 0 - sha1, 1 - sha256
* handle | 1 | seassion handle, ignored in 'single' mode
* text_len | 2 | size of the text to process, big endian
* text | text_len | text to hash
As soon as the first 'Start' message is encountered, the handler tries
to allocate shared memory to keep track of the test contexts, the
amount of available memory determines how many contexts the handler
can support concurrently.
As soon as the last 'Finish' command is encountered, the handler
returns the shared memory to the 'heap'.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=after adding the host side implementation and fixing a couple of
bugs, hash tests pass (see upcoming patches).
Change-Id: Iae18552d6220d670d1c6f32294f0af1a8d0d5c90
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314692
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Currently the EC waits until it reads a battery status with the flag
STATUS_INITIALIZED set, but the EC does not use this flag for charging
or any other battery operation. If this flag is not set, it does not
mean that the battery is unusable, it just means that its values may not
be trustworthy.
This change will remove the check for STATUS_INITIALIZED and just check
that the battery responds. The battery response shows that the battery
is connected and can be used by the EC.
BRANCH=none
BUG=chromium:564893
TEST=see that device without STATUS_INITIALIZED set will exit
battery_wait_for_stable() without timing out.
Change-Id: I07778e8570b6d9400b61beec6b2e222984a40692
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315200
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When none of temp sensors' temp/fan speed profile is not set(zero),
thermal control will set 0% duty over initial fan speed setting.
This patch allows fan under EC control at inital max speed
till host's DPTF sets proper fan speed.
BRANCH=master
BUG=none
TEST=1. check if fan is running at max speed until ChromeOS UI comes up.
2. check if fan is running when system is in recovery mode.
Change-Id: I1b3e69b003ba1045779e263b25ac35b103fe457e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314363
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Stack space is pretty tight on cr50, and since there is no need to
support SHA digest sizes in excess of 256 bits, the digest buffer size
should be reduced.
This patch makes the maximum expected digest size dependent on the set
of configured hash algorithms, moves hash size related asserts from
run time to compile time, and passes compile time definition to the
TPM2 library to increase its hash state container (it became too small
when SHA384 was disabled).
The sw context requirements should be reduced, but this is a task for
another day. We also do not have to store a local digest copy if the
API allowed reading a partial digest.
CQ-DEPEND=CL:314883
BRANCH=none
BUG=chrome-os-partner:43025, chromium:564862
TEST=all tests pass:
$ ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
SUCCESS: AES:CTR256I 1
SUCCESS: sha1:single 0
SUCCESS: sha256:single 0
/New max timeout: 1 s
SUCCESS: sha256:finish 1
SUCCESS: sha1:finish 3
SUCCESS: sha256:finish 2
Change-Id: Iaef3a230469de129e72418814e1d113b447c0137
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314695
Reviewed-by: Nagendra Modadugu <ngm@google.com>
