Reads to RTC_SSR may be invalid if they occur close to the RTCCLK edge.
As suggested by the datasheet, perform consecutive identical reads to
ensure the read is valid.
BUG=chrome-os-partner:37216
TEST=Manual on Samus. Repeatedly call rtc_read in test function, verify
that RTC_SSR never incorrectly ticks up.
BRANCH=Samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib26fbfab4a07263f638c580066e993675dd8c451
Reviewed-on: https://chromium-review.googlesource.com/254725
Reviewed-by: Alec Berg <alecaberg@chromium.org>
All current boards in ToT place pstate at the end of the RO section.
Remove the unused option to place it at the end of the RW section;
we'll never do that again.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I0d279a4c9786bb33367a7387423481cc9b94e115
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/253636
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The npcx chip and evb use a SPI flash chip to hold the EC image. They
don't need pstate, and should use the SPI flash status register
directly.
1. Remove CONFIG_FLASH_PSTATE from npcx_evb.
2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect
line to the SPI flash chip).
3. Change the npcx flash driver so that it directly reads/writes the SPI
status register instead of mucking with pstate.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=manual
Add a switch or jumper to the EVB so R1 can be closed.
Toggle the switch and see that WP_L state changes. Leave enabled.
flashinfo -> nothing is protected, WP_L is enabled (=0)
(also do this after each flashwp command to check the protection status)
flashwp enable -> RO is protected now and at boot.
reboot
flashwp enable -> RO is still protected.
flashwp disable -> RO is still protected. (because WP switch is enabled).
Toggle the switch so WP_L is disabled (=1)
flashwp disable -> Succeeds, flash is not protected
Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/253633
Reviewed-by: Shawn N <shawnn@chromium.org>
This signs the RW firmware (with a non-secret key). The RO
firmware will verify the RW firmware and jump to it if it's good.
Note that this isn't the final solution, just the beginning.
BUG=chrome-os-partner:37071
BRANCH=none
TEST=manual
Build and install it. You'll see something like this:
--- UART initialized after reboot ---
[Reset cause: reset-pin hard]
[Image: RO, cr50_v1.1.2929-27e1b82-dirty 2015-02-24 14:36:29 wfrichar@wfrichar-glaptop]
[0.000444 Verifying RW image...]
[0.423742 RW image verified]
[0.423946 Jumping to image RW[0.428492 UART initialized after sysjump]
[Image: RW, cr50_v1.1.2929-27e1b82-dirty 2015-02-24 14:36:29 wfrichar@wfrichar-glaptop]
[0.428931 Inits done]
Console is enabled; type HELP for help.
>
> sysinfo
Reset flags: 0x00000c02 (reset-pin sysjump hard)
Copy: RW
Jumped: yes
Flags: unlocked
>
Change-Id: Icafa554baca135ff1f80cbce4dad5f980e7fc122
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/253081
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Refactoring effort to unify the set of PD intialization tasks that
need to occur. Those areas include:
1. host mode as it relates to power & pull-ups/downs
2. PD tx init
3. PD mux settings
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:36481
TEST=manual,
1. compiles and functions on samus_pd
2. If sysjump w/ dongle connected than alternate mode re-entered
properly including muxing and HPD
Change-Id: I47f32acaeccbd7745e1e01a8b085b1804c4c5000
Reviewed-on: https://chromium-review.googlesource.com/249273
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Issues fixed on 0216:
1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c
2.Modified warm_reset checking in gpio.c
3.Modified system_get_chip_name in system.c for package info.
4.Modified fan.c and pwm.c for:
● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low.
● Fan stall condition event:
If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called.
5. Change cycle_pluses to 480 in board.c
Issues fixed:
1. Jump data at top of RAM is getting corrupted. Changed the flag to
RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST
issue.
2. Hibernate wake need to report whether wake reason was GPIO or RTC
3. Hibernate wake must be distinguishable from watchdog reset. The
booter will log reset reason in Code RAM. I copy the log data to
battery-backup RAM in little FW. And system driver will refer this
data to distinguish if it's watchdog reset or not.
4. Watchdog reset flag is not set. Same fix as 3.
5. Should return error if unable to clear SPI flash status register.
6. Remove chip_temp_sensor.c
7. Remove use of pstate from flash driver
8. Remove support for watchdog warm reset
9. Keyboard raw driver must support COL2 inverted
10. LPC memory mapped data must be read-only from host
11. LPC should support PLTRST# signal
12. Problems reading chip type/version. Use core registers and ROM data to read IDs.
13. When chip type/version is unknown, report hex value.
14. Watchdog does not consistently print panic information.
15. Remove console force enable logic.
16. Enable only the peripheral clocks that are needed. Please notice
user should add bit mask in CGC_XXX_MASK if they want to enable
additional module. For example, if user wants to enable PWM3, he must
add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK.
Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions.
If I turn off all I2C modules in system_pre_init and turn on the
modules I need in i2c_init, I found its freq is not correct. The root
cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in
clock_init) before i2c_init. At this time, i2c modules are power-down
and writing to freq register is useless. I re-execute freq-changed
hook function after turning on modules again.
17. MPU properly configured to prevent code execution from data RAM
18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM.
Additional items we also modified:
1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by
determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func
array to support it)
2. ec_npcxflash.c: Use definition to replace constant value. Stop
watchdog during flash programing.
3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock
MPU commands for Data RAM.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=manually verify changes
Change-Id: I722a77d29e7543b054819480c7b7477af4263119
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/248670
Previously the STM32F3 support was non-functional due to
it being a cut and paste of the STM32F0, and the clocks
are not set up the same way on the two platforms. Also,
the STM32F initialization code was incorrectly calling
the F0/L buad rate setup code.
This change has the variant specific USART code pass the
input frequency to the baud rate divisor clock to the
baud rate setup code, instead of that code calling
clock_get_freq() to determine the input clock frequency.
This is required because the STM32F3 is not configured
such that the clock_get_freq value and the input to
the USART baud rate divisor match.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify USART works on discovery as well as Ryu
Change-Id: I71248d83b53969d0e7020747a9bb9570803f30ac
Reviewed-on: https://chromium-review.googlesource.com/250920
Reviewed-by: Vic Yang <victoryang@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Fix bug in RTC module for stm32f0 in which it doesn't handle the
24 hour rollover appropriately and can cause a watchdog reset
if in deep sleep during rollover.
BUG=chrome-os-partner:36920
BRANCH=samus
TEST=add line to rtc_init()
STM32_RTC_TR = 0x00235952
This initializes RTC clock to 8 seconds before rollover. Using samus
make sure unit is allowed to go to deep sleep (S3/S5 and not charging)
and see that without this CL we watchdog most of the time, and with
this CL we don't watchdog ever.
Change-Id: I3f4b4b1ab7b2be1d4e344477d5eaaa0dc916773a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/251852
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Depending on the hardware, each ADC channel may need a different
sampling time. To keep things simple, let's allow per-board ADC sampling
time configuration instead of per-channel configuration.
BRANCH=Ryu
BUG=None
TEST=Configure sampling time to 3 and measure IADP on Ryu P4 and check
it's more accurate.
Change-Id: I3c1eeea22439c0340f84fdeb3624fc84450358ca
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/251701
Tested-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
This separates the configuration of the ARM core GPIOs from the
routing of internal peripherals to external pins. Both are still
described in the gpio.inc file, but are less dependent on each
other.
BUG=chrome-os-partner:33818
BRANCH=none
TEST=manual
Before this CL, running "sysjump rw" or trying to use more than 8
GPIOs caused hangs and reboots. Now it doesn't.
Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/251015
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
A change to the toolchain or environment surfaced an issue where the writes to
packet RAM were being split into two 16-bit writes. This was interacting
poorly with the AHB2APB bridge.
Marking the packet RAM destination pointer volatile forces the compiler to use
full 32-bit writes.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Check that Ryu's console is accessible over USB
Change-Id: I0c3db08c704389a627570b90ef97bce81ab553fa
Reviewed-on: https://chromium-review.googlesource.com/248840
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Change the idle task overslept warning printf to save stack space.
The current warning uses CPRINTF which adds too much to the stack
and overflows the idle stack.
BUG=chrome-os-partner:33138, chrome-os-partner:36636
BRANCH=samus
TEST=comment out the if (margin_us < 0) check and always print
warning message. Without this CL stack overflows. With this CL,
stack does not overflow and gets to 168/256, which is plenty of
headroom considering the task doesn't do much.
Change-Id: I19a8336b8584d2a1342e7b9290aad471d326a060
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/250300
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If 2 interrupts happen at the same time, there is a chance that the nested
interrupt will not call svc_handler when it needs to. In extreme cases this
could lead to tasks not getting woken up when they're supposed to and watchdog
resetting.
The reason stuff worked was because there were enough other interrupts
around to eventually call the scheduler and switch to the ready task.
This change modifies the interrupt calls to not call the scheduler directly
(because in nested interrupt situation this causes problems), but defer the
call to scheduling until after the irq finishes by triggering a low priority
interrupt which will for sure call svc_host at the end. The PendSV irq was
used for this purpose.
BUG=chrome-os-partner:36193
TEST=No more SPI errors caused by scheduler problems
TEST=usleeps now are more accurate, they're guaranteed to not take forever now
BRANCH=veyron
Change-Id: I42acde6b3eb7be2540a0de9a8562dee2ea2be7ab
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/248902
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
The new toolchain is putting again the __enter_hibernate function in
flash (.text) rather than in SRAM (.iram.text) after inlining both the
hibernate() and __enter_hibernate() function.
Workaround this issue by forcing "noinline" on __enter_hibernate().
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=chrome-os-partner:35774
TEST=make BOARD=samus dis
and check the disassembly, the __enter_hibernate is called in SRAM
through a veneer.
Change-Id: I015928ebe18ba8fd93252eece3e8a0fcf4b2a037
Reviewed-on: https://chromium-review.googlesource.com/242691
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
If the AP ignores the LPC_ST_BUSY bit (which is software-defined) and
tries to send a second host command while the first one is still
processed, we discard it.
This doesn't prevent the host to re-write the command arguments stored
in LPC shared mem (aka LPC_POOL_CMD_DATA) but when we will call
host_packet_receive, we will have either the old arguments or the new
arguments (or even a mix of both, which is less unlikely to pass the
checksum check), and we will copy them once before calling the HOSTCMD
task. So the host command task will have a single coherent (not
changing) view of the arguments when performing its input validation.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:31492 chrome-os-partner:23806
TEST=Boot Samus and play with ectool
Change-Id: I9aa1b8cdac05e323b91998188bd873826e83c274
Reviewed-on: https://chromium-review.googlesource.com/242593
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
The current header location is too large for small SPI flash chips.
Since this value is only used for private EC SPI, it doesn't really
matter what it is. Let's just move it to 0x0.
Note that this doesn't affect shared SPI case, as we need a more
sophisticated packer for that.
BRANCH=None
BUG=chrome-os-partner:35308
TEST=Build for Glower and check the size of ec.spi.bin.
Change-Id: I96871d1677999e7cc1c7385b749563b8c09a318a
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/241114
Tested-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
Before enabling GPIO interrupts on boot, we should clear pending
interrupt status to make sure the interrupts don't fire unexpectedly.
BRANCH=None
BUG=chrome-os-partner:35308
TEST=Boot on Glower and make sure GPIO interrupts aren't triggered on
boot.
Change-Id: I2729b4a5046063e4ee4c08dcb7084a329bfdf042
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/241112
Tested-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
Chipset sometimes needs I2C, therefore i2c_init should have a higher priority
than power_common_init so i2c is available by the time the chipset might be
talking to the battery.
BUG=chrome-os-partner:35502, chrome-os-partner:35173
TEST=There is no "battery not responding" message at startup on veyron
TEST=EC boot takes less than 1 second on veyron
BRANCH=none
Change-Id: Ib10b653decc7703e706d4dd1976abf0fdbc25ac2
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/241102
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The RTC delay is always less than a day (see the assert at the beginning
of set_rtc_alarm), so remove the useless module to save a few bytes of
flash.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=make buildall
and see the zinger firmware is smaller by 16 bytes
(more than the 8 bytes I need to submit the following CL)
Change-Id: If0374ff5897f13e69574018d2123428075b2264e
Reviewed-on: https://chromium-review.googlesource.com/240564
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
The check for overflow was originally in __hw_clock_source_read()
If it got interrupted, it would frequently see an overflow, because
"prev_read" would be less than "now".
1 - Use the comparator to check for overflow.
2 - Only check for overflow in the interrupt handler.
BUG=chrome-os-partner:35312
BRANCH=none
TEST=make buildall -j
use the keyboard code to type
use a console command "forcetime", to force the system time to overflow soon.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I7005724222289ba967e89af0ce8b9ef8f90a4ae4
Reviewed-on: https://chromium-review.googlesource.com/239967
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
If the RO firmware has a different view of the protection than
the RW copy, we should not change the option bytes (write protection
settings) in RW else we will trigger a reboot loop : RW protects and reset,
then RO unprotects, resets and jump to RW, RW protects and reset again ...
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35383
TEST=craft a firmware image whose RO partition doesn't include commit
42d0104 (no virtual WP, no RDP set) and RW partition has everything
including this patch, see that HoHo no longer reboots in a loop.
Change-Id: I4cbdbf25a96cb6fb7cbabc7f2d1dc76d3a2a9e36
Reviewed-on: https://chromium-review.googlesource.com/240561
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix potential junk at end of PD TX transmit by adding to the DMA
transmit complete interrupt a blocking wait for SPI to finish and
then immediately disable SPI clock. This means we block in an
interrupt function for approximately 45us at the end of every
transmit. But, this is the highest priority thing going on anyway.
Note, there is still a potential for junk if both ports are
transmitting at the same time and finish very close to the same time.
BUG=chrome-os-partner:34600
BRANCH=samus
TEST=load onto samus and test communications with zinger. tested
specifically with an old zinger CL,
https://chromium-review.googlesource.com/#/c/226118/11,
which watchdogs when samus has junk at end of transmit. Tested
without this CL and verified we could never successfully flash zinger
over PD due to this watchdog and verified on scope presence of junk.
Then tested with this change and was able to successfully flash
zinger using ectool on both ports in both polarities.
Change-Id: If0cd9ab0551d36a7d7dc10232b6476dd56735972
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239244
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Ensure that we can re-etablish a proper USB communication after a
sysjump by properly disabling the USB stack before jumping.
So the host sees a USB disconnection and can properly re-initialize the
device when it re-appears.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=On Twinkie, use the "sysjump RW" command on the USB console
and see the prompt coming back after a few seconds.
Change-Id: Iaf4498333eb4e7a1dda0f51ee8be19a0c9f10349
Reviewed-on: https://chromium-review.googlesource.com/239227
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
It's not safe to sysjump with a DMA enabled as it can led to memory
corruption after we have landed in the new image before that piece of
hardware is re-configured.
Implement and call dma_disable_all() on all platforms with generic DMA.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=chrome-os-partner:34865
TEST=on various boards, call "sysjump rw".
Change-Id: I2a6b63ff19c2d932a5e31bc375bf468bc8ae5125
Reviewed-on: https://chromium-review.googlesource.com/237340
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
These USB type-C accessories don't have a write-protect GPIO.
Add a configure flag (CONFIG_WP_ALWAYS) to force the flash
write-protection on the dongles.
Also set the read protection (by elevating RDP to level 1),
so trying to unprotect the flash will trigger a full erase.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35088
TEST=boot Hoho,
check the flash OBR and WRPR registers:
"rw 0x4002201c" / "rw 0x40022020"
and the option bytes write-protect bits: "rw 0x1FFFF808"
dump the logical state with "flashinfo" command.
> rw 0x4002201c
read 0x40022020 = 0xffff0002
> rw 0x40022020
read 0x40022020 = 0xffff0000
> rw 0x1FFFF808
read 0x1ffff808 = 0xff00ff00
> flashinfo
Physical: 128 KB
Usable: 128 KB
Write: 2 B (ideal 2 B)
Erase: 2048 B (to 1-bits)
Protect: 4096 B
Flags: wp_gpio_asserted ro_at_boot ro_now
Protected now:
YYYYYYYY YYYYYYYY ........ ........
Change-Id: I45bbc0bce40ecc174b6b8a1ebacf4f53d2fd372d
Reviewed-on: https://chromium-review.googlesource.com/238893
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Previously there was just a memcpy_usbram that copied to
USB packet memory, and no routine to copy out. This adds
the "from" version and renames and improves to "to" version.
The improvement is that the new "to" version correctly
handles unaligned beginning and endings of the region to
be copied. These need to be read/modify/write accesses since
the USB packet ram has to be manipulated in 16-bit chunks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify that discovery-stm32f072 still enumerates and communicates
correctly over USB.
Change-Id: I94353e66ad0248d4e674abb29f9a88e979767655
Reviewed-on: https://chromium-review.googlesource.com/238764
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
The recent change to decrease the time to wake up from deep sleep when
not using LFIOSC was too agressive. Increase the time to wake up based
upon the worst observed case.
BUG=chrome-os-partner:35184
TEST=Manual on Samus. Go to deep sleep, verify that no "overslept by
Xus" prints are seen.
BRANCH=Samus
Change-Id: Ib9fe2eba5e29a112e03fffaedbc5ae53d6d650ff
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/239242
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Currently, we are seeing problem with adc_read_all_channels() for
STM32F, and thus 'adc' console command reports incorrect values. Before
that's fixed, read ADC channels one by one to work around this problem.
BRANCH=Ryu
BUG=chrome-os-partner:33971
TEST='adc' on Ryu
Signed-off-by: Vic Yang <victoryang@chromium.org>
Change-Id: Iae92b82b24f6a843b9d46a8804da1e51d33ed7cb
Reviewed-on: https://chromium-review.googlesource.com/231125
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Decrease the time to wake up from deep sleep when not using
LFIOSC (when using PIOSC in deep sleep). This helps keep us
in deep sleep longer and therefore save power.
BUG=none
BRANCH=samus
TEST=Load onto samus and run for a couple of hours, varying from
S0 to S5, with and without EC. Use idlestats to check that closest
we get to missing deadline is 86us away.
Change-Id: I3eee908e9f42a1c5b549e93d63588a3cb6e29a5d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/238412
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Check the flash protection at startup, if the RDP is still at level 0
(no read protection) or if the RO partition is not write protected :
- set the write protection on the first 16KB of flash (4 LSB of WRP0)
- push the RDP to level 1, so SWD/serial monitor needs to fully erase
the part before re-writing the code or the write-protection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:34935
TEST=dump the content of the option bytes.
Change-Id: I11af64365a6fbc34327b2e463eb8e2d369ffacd2
Reviewed-on: https://chromium-review.googlesource.com/238262
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Use the PORT event for keyboard inputs.
Make a column mask for driving all outputs at once.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used hadoken and the Ryu base keyboard to check that the keys are all
functional, that the keyboard polls while keys are held, and that it waits
for interrupts when the keys are released.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: Ie1dd1ca17b21ed76b2d412bf25fe87e45c5ba757
Reviewed-on: https://chromium-review.googlesource.com/234394
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add structures to keep track of which interrupts are associated with which pin.
There are IN[] events, and one PORT event. The IN[] events have an array.
The PORT event can be used for multiple pins at once.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured pins as IN[] events and PORT events, and saw console output.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I129a6586dca4d5eb141c86fd92fbfbb70080bc2a
Reviewed-on: https://chromium-review.googlesource.com/234392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Updated to use parameters for GPIOTE_OUT, GPIOTE_IN, and GPIOTE_CONFIG
Updated with NRF51_GPIOTE_IN_COUNT to remove the magic number.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Configured IN[] events and PORT events and checked that they triggered
events and wrote to the console.
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I2021ecbee67c39571f277c97082378dce4de024f
Reviewed-on: https://chromium-review.googlesource.com/234289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Add support for alternate functions for nrf51.
Add more register definitions for the nrf51.
Use assertions for conditions that should never happen.
Use BUILD_ASSERT to keep the sources in sync.
Add three more GPIOs to hadoken.
BQ27621_GPOUT - Configurable output from the fuel gauge.
LID_PRESENT_L - The input for the hall sensor.
IND_CHRG_DISABLE - The output to control inductive charging.
BUG=chrome-os-partner:34477
BRANCH=none
TEST=Used gpioget and magnets for LID_PRESENT_L
Used fuel gauge console commands to trigger BQ27621_GPOUT
Tested the assertions with gdb
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I508f79ae45127104fa14f9f75fbf545f226387e4
Reviewed-on: https://chromium-review.googlesource.com/234286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
