The first time you use this with a particular th,
connect only th and run ./cts.py --th
Then connect both boards and you can run
./cts.py to build/flash both boards.
BRANCH=None
BUG=None
TEST=manual
- Enter chroot
- Navigate to ec/cts
- Connect only th
- 'sudo ./cts.py --th'
- './cts.py -b'
- Exit chroot
- Connect both boards
- './cts.py -f'
Each board should flash successfully
Change-Id: Ib14fccabcd9fdad04f9b92817da597bc0dcb3d89
Reviewed-on: https://chromium-review.googlesource.com/358100
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have more than enough memory for that, and it makes it possible
to poll the logs from AP much more unfrequently.
BRANCH=oak
BUG=chromium:527904
TEST=make buildall -j
TEST=Boot elm, cat /sys/kernel/debug/cros_ec/console_log does not
miss any data.
Change-Id: I8cce88e39d00a94397b6fc852a371b4595870b24
Reviewed-on: https://chromium-review.googlesource.com/358181
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms. Even when hcdebug is set to off, we still
get command errors.
BRANCH=oak
BUG=chrome-os-partner:55001
TEST=make buildall -j
TEST=Flash elm EC, see that output is fairly quiet.
Change-Id: I0a5ab2950911648e2e34f4ab1b6886e3e4bff774
Reviewed-on: https://chromium-review.googlesource.com/358438
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The EC asserts system reset on init, and Cr50 asserts ec_rst when it is
rebooted. Having the EC and Cr50 keep resetting each other prevents the
system from booting. We only care that Cr50 is restarted when the system
is restarted, so if it gets a system reset call when it is still
initializing everything it is okay to ignore it.
This change expects the EC to do a system reset on init, so it ignores
the first system reset. It will automatically enable the hard resets
two seconds after the board is initialized if it doesn't detect the
initial system reset.
BUG=none
BRANCH=none
TEST=reef and kevin can boot normally. Verify asserting sys_rst_l after
boot resets Cr50 and the rest of the system.
Change-Id: I198208950c526efd3ee0171812de3052785555f2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358943
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This just adds a print statement to display board version at the
EC console the first time board_get_version() is called.
BUG=none
BRANCH=none
TEST=print shows up as expected with follow-up patches applied.
Change-Id: Ib7eae79a90bdaa58165aa5b102bc446f21a98963
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proto had two pins for PROCHOT# - One to monitor and one to override.
Newer boards have only one pin that serves both purposes.
BUG=chrome-os-partner:54953
BRANCH=none
TEST=built and booted on reef
Change-Id: Ida4bc2766caf15562c26e7a4b792a07604361da2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358940
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes corrections to the board ID values and also adds a small
multiplier to allow for higher-than-ideal voltages to match.
Currently we see values that are below the ideal value by about
2.5%, so it seems like a good idea to also allow slightly above ideal
voltage to account for variations in Vref or PP3300_EC that could
cause the calculated value to become higher than expected.
BUG=none
BRANCH=none
TEST=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia091fbbad7ffce2da9a04c48c7676ad9b4a08dea
Reviewed-on: https://chromium-review.googlesource.com/358614
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
The ADC multiplier and divider factors were lazily set to 1 when
the board support was first added, so the value was not scaled
properly.
The conversion formula is: Vi = CHNnDAT * (Vfs / 1024) where
Vfs = Vref = 2.816V for Reef.
BUG=none
BRANCH=none
TEST=added debug print and reading now approximately matches
what the voltmeter reads.
Change-Id: Ic60a8bc1d84c4f9a7b5664e9daddfa331b6a890c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358613
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Rename from V5A_EN to PMIC_EN.
The name V5A_EN came from Amenia where it controls both
5V_A-Rail and PMIC_EN.
Reef has a separate 5V_A-Rail control (EN_PP5000) and
an another GPIO pin for PMIC_EN.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=buildall pass
Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354767
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Since we are targeting a 45W solution, set max power to 45W.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Zinger and make sure 20V/2.25A is used instead of 20V/3A
Change-Id: Ie57a1df39f0cc642fe3644535aa1b5aa92f1ff35
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/358320
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch replaces a long standing stub. When the EC asserts this
signal, the CR50 must reset.
But this signal could be driven by CR50 itself as well, and in that
case the signal's assertion should not be causing the CR50 reset.
Ideally it should be possible to tell if the pin is configured as
output and ignore its assertion in that case. But there is no API for
checking the pin configuration settings at this time. An API function
is added to check if the AP Flash is being programmed, the GPIO
configuration access API is left for future enhancements.
BRANCH=none
BUG=chrome-os-partner:52366, chrome-os-partner:54982
TEST=issue 'reboot' command from the bash command line.
- verify on the cr50 console that it reboots along with the rest of
the device
- observe that reading of the NVRam spaces is still fully
functional, and Kevin can boot all the way up to the login
screen.
- try flashing AP firmware through CR50, verify that it succeed.
Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357967
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow at least 10ms for the 'version' cap to charge in order to have a
voltage on the ADC pin that reflects our voltage divider circuit.
BUG=chrome-os-partner:54768
BRANCH=None
TEST=Manual on kevin. Run 'ver', verify that rev3 board is recognized as
version 3.
Change-Id: I1f3326f4c99a165d77363834d5671aa357a89007
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357970
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
For certain board configurations, KSI2 will be stuck asserted for all
scan columns if the power button is held. We must be aware of this case
in order to correctly handle recovery mode key combinations.
BUG=chrome-os-partner:54602
BRANCH=None
TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I03d76e1121107484f79520745858388f6cae096c
Reviewed-on: https://chromium-review.googlesource.com/357590
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The motion sensor drivers used to rely on #defines indicating I2C or
SPI port to tell which to use. However, these days the drivers get
that info passed in via the motion_sensor_t struct. Now this #define
simply decides whether to compile in SPI or I2C wrapper code. We
should eventually make it less confusing, but that's beyond the scope
for now.
BUG=none
BRANCH=none
TEST=reef motion sensor init works now
Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356822
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a test that verifies RSA keygen from a fixed seed and
template from the TCG EK Credential Profile spec.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpmtest pass
Change-Id: I2f1cfb8460a0497c93079b89b9ff4e031eaff358
Reviewed-on: https://chromium-review.googlesource.com/356561
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
To achieve higher power efficiency, we want the input voltage to be as
low as possible. If the PD source advertise several choices over
PD_MAX_POWER_MW, choose the one with the lowest voltage.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Liteon charger and make sure 15V/3A is selected
Change-Id: I6157eb94a1cb45cd537acc79c377db2cff09d922
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/356317
Reviewed-by: Rong Chang <rongchang@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added console commands for the debugging purpose
psys - Can be used to measure the system power
amonbmon - Can be used to measure AMON/BMON voltage diff, current
BUG=chrome-os-partner:54273
BRANCH=none
TEST=Manually tested on Amenia
psys - Ran fish task and observed psys value changes.
amonbmon - AMON & BMON voltage & current are same as measured
across sense resistors.
Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/353043
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The highsec jittery clock was breaking the USB peripheral, because it
would use bank values that mapped to frequencies less than 15MHz. This
change modifies stepx16 to keep the bankvalues mapped to frequencies
above 18MHz to ensure the USB peripheral can work with the high
security jittery clock.
BUG=chrome-os-partner:53952
BRANCH=none
TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin
Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Change-Id: I5459cb587badd46c03d1c433f13fdf21a5dc63ed
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355282
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On EC reset where PMIC_EN will be pulled low,
PMIC could get into an unknown state and will
not sequence properly on sub-sequent boot.
This is a temporary workaround for Reef Proto,
a hardware change will be implemented on EVT.
BUG=chrome-os-partner:53974,chrome-os-partner:54507
BRANCH=none
TEST=Reef powers to S0 and starts coreboot after EC reset
Tested with servo cold reset button
and console reboot command
Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354762
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54503
BRANCH=none
TEST=Manually tested using console commands on both the ports.
a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is
1 when AC connected & 0 when AC disconnected.
b. Issued 'hibernate' & on plugging in the AC, device
boots to S0.
Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354721
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
following Change#227416 to meet client's spec.
BUG=chrome-os-partner:54263
BRANCH=master
TEST=`make -j BOARD=elm`, check factory force IDLE, works good
Change-Id: I1f0abdcbd56eeab379a6258869ccc133ff80736d
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/353521
Reviewed-by: Shawn N <shawnn@chromium.org>
BD99955 DCDC wiil turn off Vsys voltage under VSYSVAL_THL_SET
or VREF_BAT<VBAT if Charging Voltage set under actual battery
voltage or VSYSVAL_THL_SET.
BUG=chrome-os-partner:53777
BRANCH=none
TEST=boot-up without battery. using zinger or oem supplier
used kevin rev2, rev3
Change-Id: I03c5c52790b2d481be3fa942054516fbefa3ce98
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/348563
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54551
BRANCH=None
TEST=Manual on kevin. Verify negotiation to 20V when zinger is plugged.
Also verify "pd 0 dev 12" and "pd 0 dev 5" cause 12V/5V to be requested
from zinger.
Change-Id: I0298d535b791fa0c6f8ca077a6fd09a27e8ce77b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Implement the standard LED control scheme for gru, using a single PWM to
set the battery status LED color rather than the traditional GPIOs.
BUG=chrome-os-partner:54379
BRANCH=None
TEST=Manual on gru. Verify LED is green when charging w/ nearly full
battery, off when discharging w/ nearly full battery, amber when
charging otherwise.
Also verify LED control host commands work as expected:
ectool led battery green=1 // green
ectool led battery amber=1 // amber
ectool led battery red=1 // red
ectool led battery red=0 // off
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I184e72c552e6d2196aef2724af9292806e0ea8c0
Reviewed-on: https://chromium-review.googlesource.com/352520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This makes the boot time less painful since it requires a long delay
for FW loading after power on this chip. This also makes it easier to
upgrade FW as we don't need to power on the chip before doing upgrade.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=plug and unplug dongle and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: Ia344c748697a3b1d06c9b442e1bf1d7227861f9b
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/347181
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX7688 is a TCPCI compatible port controller with HDMI to DP converter.
The HDMI converter needs a reset every time after enabling its function.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
boot elm proto
plug and unplug dingdong and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/340371
Commit-Ready: Koro Chen <koro.chen@mediatek.com>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable charger interrupt for VBUS / BC1.2 detection on kevin / gru.
Also, keep our USB data switches connected while we figure out how to
implement USB mux control.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Change-Id: I602e7bd3180110d351ec4c2916a6b8612c7e5f82
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352821
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shelley Chen <shchen@chromium.org>
This change implements distinct key derivation trees for
ECC and RSA key generation. The seed used for derivation
is HMAC(primary_seed, ALG), where ALG is either
"ECC", or "RSA".
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Iee85731bdac02b7b1061e9220786bee52dbf6289
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351750
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Leave USB-A charging enabled in S3, and move gru-specific code into
board hooks, out of the power state driver.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and
deasserted in G3.
Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351670
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The motion sensors array as well as the config variables were copied
from another board and mostly wrong for Reef.
BUG=none
BRANCH=none
TEST=sensors which are connected successfully initialize, still need
to test lid sensors.
Change-Id: If8e1ec79803c7f378b21f4e9423a56bd6763eb4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349733
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a certificate verifier, so that endorsement
certificates may be verified upon installation.
Doing so allows for catching certificate errors early.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I9339a6bc36e4d82ae875ce774e31848ae983fa1f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351031
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
LID_OPEN gpio is present on the daughter card and provided by the
EC. Add an internal pull-up on it for the cases when the daughter card
isn't plugged in.
This fix won't be required starting EVT.
BUG=chrome-os-partner:54143, chrome-os-partner:53566
BRANCH=None
TEST=Compiles successfully. "gpioget LID_OPEN" returns 1 without
daughter card.
Change-Id: Ieff281b489e4f3f8be184a55b7975fb2efcc1099
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/350460
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
