Add initial support for Oak rev1 board. This is just the
EC and includes battery charging but does not include
USB PD.
BUG=none
BRANCH=none
TEST=load on oak board and get console
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777
Reviewed-on: https://chromium-review.googlesource.com/261678
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Move parts of usb_pd_config.h that are not part of the phy layer
out of usb_pd_config.h and into board.h. This cleans up the
division between the TCPC and TCPM as only the TCPC needs to
use usb_pd_config.h.
Also cleans up the use of the CC detection voltage thresholds
by creating standard macros to use based on Rp strength for the
board.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I946cceb38bea8233095b8a4b287102bb8a3a296d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270337
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
New led control from Yuna since it is close to CrOS UI.
BUG=chrome-os-partner:37576
BRANCH=cyan
TEST="make BOARD=cyan" and check the two factors in CrOS:
shutdown=4% and full= 97%.
Change-Id: I8aa7ae5f35a3f3f6f15c6131a1f8fb581025de2d
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/272815
Reviewed-by: Mohammed Habibulla <moch@google.com>
Previously the Producer and Consumer interfaces tracked the
Consumer and Producer respectively at the other end of the
queue that they interacted with. This was done to avoid
modifying the queue implementation, but resulted in a rougher
interface that required additional initialization steps and
prevented alternative configurations; many producers and one
consumer for example.
This commit uses the new queue policies to track this
information. The new direct policy behaves as the old producer
and consumers did. Now the producers and consumers are just
named references to the queue that they work on and a convenient
location for a notification callback when the queue is updated in
a way that is relevent to the producer or consumer.
All users of Producer and Consumer have been updated including the
stream adaptors which are in use by the echo test code and the
mcdp28x0 driver. Use of the stream adaptors has also been
simplified.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manual testing of Ryu (P5) and discovery board echo task
Change-Id: I704be6378a31b4e20f5063295eff9943e4900409
Reviewed-on: https://chromium-review.googlesource.com/271792
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
it was not needed before, it's now harmful for the new VBUS detection
circuit on EVT2.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on Ryu P6 reworked with the new VBUS detection circuit, probed
voltages and did "gpioget CHGR_ACOK" with type-C unplugged.
Change-Id: I1d99f249c1949aa35f98a896e7ac8ee019295e19
Reviewed-on: https://chromium-review.googlesource.com/273006
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add config options for various parts of USB PD stack:
CONFIG_USB_POWER_DELIVERY: The use of this option has changed
slightly. It now represents whether or not to include the USB
PD protocol and policy layers of the software stack.
CONFIG_USB_PD_TCPC: Compile in type-C port controller module
which performs the phy layer of the PD stack.
CONFIG_USB_PD_TCPM_STUB and CONFIG_USB_PD_TCPM_TCPCI: If
CONFIG_USB_POWER_DELIVERY is defined, then one TCPM needs to
be defined to declare which port management module to use
to drive the TCPC.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I41aa65a478e36925745cd37a6707f242c0dfbf91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270171
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The battery of cyan only support specific shipmode command.
BUG=chrome-os-partner:40464
BRANCH=cyan
TEST=verify that "ectool batterycutoff" and "ectool batterycutoff
at-shutdown" are workable.
Change-Id: I48538d57eda77ae798b3b843252df297c2d8fa81
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/272414
Reviewed-by: Mohammed Habibulla <moch@google.com>
EVT board should enable it (low) since we need a workable track pad in factory.
Pre-EVT board work fine because of unstuffed resistor.
BUG=none
BRANCH=cyan
TEST=Check the pin is low by ec console.
Change-Id: I9602534aeadca76e24915d12701b3cd4e801746a
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/272103
Reviewed-by: Shawn N <shawnn@chromium.org>
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.
Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)
Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Common battery cut-off host command / console command infrastructure
already exists behind CONFIG_BATTERY_CUT_OFF, so add the config rather
duplicating the code at the board level.
BUG=chromium:488157
TEST=Manual on Squawks. Verify that both "cutoff" on the ec console and
"ectool batterycutoff" succeed to cut-off the battery.
BRANCH=None
Change-Id: I159026d54924e058ea0262db04d8770c663ee613
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271513
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The HotPlug Detect signal generated by the PD stack in DisplayPort
alternate mode is connected to a 1.8V GPIO on the T210 AP, we need to
set the GPIO output as open-drain.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=manual, probe the level with a voltmeter and see 1.8V.
Change-Id: I627befc61ed06c75dd7e32a8541bd6d8f8e95642
Reviewed-on: https://chromium-review.googlesource.com/271553
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Add Primitive support for Bosh Sensor.
Neither gesture nor FIFO are supported.
BUG=chrome-os-partner:39900
BRANCH=none
TEST=Running accelinfo.
From user space, check values via /sys/class/iio/devices/...
Change-Id: I62dbe230c9064ec7c0fa8e343bbe6eae843e3ac0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270455
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move structure used by lms6ds0 to motion_sense.h,
so that bosh driver can use the same mechanism.
Use code to avoid reading chip range when reading data.
BUG=none
BRANCH=none
TEST=Check Bosh driver is working as expected.
Change-Id: Id8b5bb8735e479a122ef32ab9a400fba189d7488
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270453
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
- allow power swap only when we are dual-role toggling (ie in S0).
- enable the VCONN swap feature to support more type-C dongles.
and allow it using the same rule as power swap.
- become a power sink when we are connected to an externally powered
DRP.
- by default, try to be a data UFP for USB.
so Dual Role Device such as laptops can get our data.
- add a message to inform the AP that our USB role has changed
(but the host events are fully wired yet on Ryu)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: Id0f9027b140cb20f105bcdbc00cac5cb5f44c9e0
Reviewed-on: https://chromium-review.googlesource.com/269857
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The CR50 device will have to have two different drivers, for SPI slave
and master modes. This patch adds the slave driver which is called
SPS.
CR50 SPS controller uses 2KB buffer split evenly between receive and
transmit directions as two FIFOs. RX write and TX read pointers are
maintained by hardware, RX read and TX write pointers are maintained
by software.
The FIFO area allows only 32 bit writes from the CPU core, which
complicates the function placing TX data into the FIFO. There is no
limit to read access size.
Another complication is that the hardware pointers in the FIFO in fact
have 11 bits (instead of 10 required to address 1K), so the software
needs to use 10 bits when accessing the FIFO, but 11 bits when writing
the pointers into the registers.
Driver API provides three functions:
- transmit a packet of a certain size, runs on the task context and can
exit before the entire packet is transmitted.,
- register a receive callback. The callback is running in interrupt
context. Registering the callback (re)initializes the interface.
- unregister receive callback.
A CLI command is added to help testing this driver. When invoked, it
installs the callback function to handle receive data. The data is
expected to be of the following format:
<size/256> <size%256> [<size> bytes of payload]
where size should not exceed 1098 bytes.
Received frames are saved in a buffer and once received are
transmitted back to the host.
BRANCH=none
BUG=none
TEST=used the enhanced 'spiraw' utility which sends frames of random
size in 10..1010 bytes, and then clocks the line to receive the
same amount of bytes back, syncs up in the returning stream of
bytes and compares received and transmitted data.
# run 'sps 100' on the target
$ src/examples/spiraw.py -l 100 -f 2000000
FT232H Future Technology Devices International, Ltd initialized at 2000000 hertz
$
which is an indication of the successful loop back of 100 frames.
The cli command on the target exits and reports the stats:
> sps 100
Processed 100 frames
rx count 108532, tx count 51366, tx_empty count 100, max rx batch 11
Change-Id: I62956753eb09086b5fca7504f2241605c0afe613
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269794
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The code in board/cr50 and board/cr50_a1 directories is pretty much
identical apart from a few lines related to USB. Let's consolidate the
both board variants in the same source directory.
The command to build the cr50 board remains the same. The command to
build cr50_a1 becomes
$ make BOARD=cr50 CHIP_VARIANT=cr50_a1 out=build/cr50_a1
This is a small inconvenience to pay to avoid duplicating many patches
in two subdirectories.
BRANCH=none
BUG=none
TEST='make buildall' still succeeds
compared map files for cr50_a1 before and after the change. They
are identical modulo addition of the empty function
send_hid_event() in board.o.
Change-Id: I7584c8f215945b8b33eea4eff50c872a09ef349d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269160
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Enable the support to be a USB-PD alternate mode DFP and add
configuration for the DisplayPort alternate mode and the GFU mode.
Only on Ryu P6 as the P5 board is using the HPD line for the power
sequencing workaround.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:39946 chrome-os-partner:38689
TEST=on Ryu P6, plug a Hoho dongle, see that the superspeed muxes are in
DP1 or DP2 mode (using the "typec 0" command), plug and unplug an HDMI
monitor and see the HPD line moving when typing "gpioget USBC_DP_HPD".
> pd 0 state
Port C0, Ena - Role: SRC-DFP-VC Polarity: CC1 Flags: 0x1150, State:
SRC_READY
> adc
VBUS = 4980
CC1_PD = 992
CC2_PD = 57
> typec 0
Port C0: CC1 993 mV CC2 58 mV (polarity:CC1)
Superspeed DP1
> gpioget USBC_DP_HPD
0 USBC_DP_HPD
<--- PLUG monitor --->
> gpioget USBC_DP_HPD
1* USBC_DP_HPD
Change-Id: Ie25a3bb0d6331c1d931b7f542fbc637270c20b3b
Reviewed-on: https://chromium-review.googlesource.com/269855
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add setting the Pericom D+/D- switch state to board_set_usb_mux().
This is useful on Ryu because we have to fully debounce the type-C
CC lines before setting the SS muxes, ~100ms, and we don't want
the host to give up on enumerating SS while we are debouncing. So,
instead, we keep the D+/D- lines disconnected until after we
debounce and right before setting type-C muxes for SS.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ifb7c06d82e35c312ebfce871bff0056a83b4887a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/269250
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The charger chip is supposed to handle this feature in hardware.
Let's disable the software version to exercise the hardware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38603
TEST=on Ryu P6, plug BC1.2 chargers through legacy A-to-C cable.
Change-Id: I074eee0621ba8d23c7ef87dd251ce8fbf86a0265
Reviewed-on: https://chromium-review.googlesource.com/269518
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
the USBC_CC_PUENx resistors are actually stuffed on P6,
we need to drive the corresponding GPIOs to set the high side of the Rp
pull-ups when we are a power source.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on Ryu P6, check the ADC values on CC lines when dual role
toggling.
Change-Id: Ic8943268615597f114672df7c42a0292c985e994
Reviewed-on: https://chromium-review.googlesource.com/269517
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The USB power is off in S5 with previous ChromeBook.
The braswell platfrom should be the same as before.
BUG=chrome-os-partner:39507
BRANCH=cyan
TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console.
Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/267451
Reviewed-by: Shawn N <shawnn@chromium.org>
In S3 state, sensors loose their power. Prevent any initiation of
communication with the sensors.
BUG=None
TEST=With Servo connected, verify that no I2C failures are reported
on EC Console when system is brought to S3.
BRANCH=None
Change-Id: I1988c40aa9de48403e9e3a6be5aec3b7267c29e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/268481
Reviewed-by: Shawn N <shawnn@chromium.org>
The new charger has a different input voltage range and has now a 5V
boost providing 1.5A when sourcing VBUS (along with an updated 1.5A Rp),
update the PD descriptors and voltage thresholds accordingly.
Overall, there is no functional change.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38603
TEST=build and verify 5V and 12V charging is still working
Change-Id: Ie3d54956c940781d06039fccd52966f37d7d48e4
Reviewed-on: https://chromium-review.googlesource.com/269261
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Add explicit setting of USB D+/D- switch when setting the type-C
muxes. This fixes a bug in which we would open D+/D- switch when
entering DP mode and lose USB2.0 connection.
BUG=chrome-os-partner:39766
BRANCH=samus
TEST=add printf to board_set_usb_switches() on samus and make sure
we don't open the D+/D- switch when entering DP mode.
Change-Id: I2b5bb2185298794ddb4cc457f3695ce6adabd9f8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/268993
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
On P5, the lid detection interrupt has been hijacked to workaround the
power sequencing issue. So the lid state is sometimes inconsistent, so
we need to ignore the current lid state when the power button is
pressed, else we sometimes ignore the power-request by wrongly thinking
that the lid is closed.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38689
TEST=on Ryu P5, switch on the system by pressing the power button either
on the servo board or the casing and see the system turning on.
Change-Id: I88b2e1f06ed8b4a155a42dac640f8b946db214ea
Reviewed-on: https://chromium-review.googlesource.com/269132
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
- use the TI BQ25892 instead of the BQ24773 as the battery charger,
update the board configuration accordingly.
=> this change is NOT backward compatible with previous boards
- upate GPIOs configuration
- Use the BQ25892 5V boost to source VBUS.
- on the type-C port, Rp has been set to 1.5A, update the USB PD source
limit accordingly and set the boost limit to 1.65A.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38603 chrome-os-partner:39202
TEST=make buildall
run on a P4 modified board with BQ25890 and see the battery charging and
the system running on AC and battery. Plug on C-to-A receptacle adapter
and see 5V.
Change-Id: Id28c9dbd155fe5aedc328bf5ab4da4420495e1f5
Reviewed-on: https://chromium-review.googlesource.com/266021
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Remove all Ryu Proto 4 specific support to make space for Proto 6
configuration : support for both D12 and B8 as PMIC_THERM_L GPIO,
old SuperSpeed mux config.
People with P4/P5 boards can use the ryu_p4p5 board support instead.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38333
TEST=make buildall
Change-Id: I0c5ab5e098d0e4828bee8f576461cd75bbb7b422
Reviewed-on: https://chromium-review.googlesource.com/266020
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Change the EC_CMD_USB_PD_POWER_INFO host command to report the input
current limit and the max current theoretically possible given the
charger. The input current limit field is useful for logging purposes
and the max current field is useful to give to powerd to determine
if we have a low power charger connected.
The max current is determined by checking if the charge supplier is
allowed to ramp. If the charge supplier is allowed to ramp and has
not completed ramping yet, then max current is the max current that
we are allowed to ramp up to. Once the ramp has completed, then max
current is the stable charging current. If the charge supplier is not
allowed to ramp, then max current is simply the max current as
registered with charge_manager. The point here is to keep the max as
high as possible until we know for sure it is lower to avoid showing
the user the low power notification until we know for sure.
This CL also adds a new charger type, USB_CHG_TYPE_UNKNOWN. For a short
period after a charger is plugged in, the supplier type may change and
PD negotiation is still in process, and therefore we tell the host we
have an unknown charger type. This allows powerd to show the charging
icon, but delay determining if this is a low power charger until we
know for sure.
BUG=chrome-os-partner:38548
BRANCH=samus
TEST=tested with zinger, a DCP, an SDP, and a proprietary charger.
tested that low power notification never pops up with zinger, even
if you purposely wedge charge circuit with "charger voltage 7000" on
EC console. tested that the other chargers all pop up low power
notification once the supplier changes from UNKNOWN to the real
supplier. used "ectool --name=cros_pd usbpdpower" to check current
values.
Change-Id: If8a9a1799504cc2a13238f4e6ec917d25d972b22
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/265066
Reviewed-by: Sameer Nanda <snanda@chromium.org>
- Added config option CONFIG_USBC_SS_MUX_DFP_ONLY
- If this options is enabled, then the mux is set to
TYPEC_USB_MUX only is data role is DFP.
- If this option is not enabled, the mux is set for
both UFP and DFP (i.e. RYU)
BUG=chrome-os-partner:39059
TEST=Manual samus to plankton, switching between source and sink modes.
Forced data role swap via ec console command.
BRANCH=Samus
Change-Id: Ibc2fb0ad42d0fe415d3338d38da94ad4b041513b
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/266916
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
If we are switching from DP mode to USB mode, reset the USB hub to make
sure the hub recognizes USB connection properly. Note that we only reset
the hub when making the switch by pressing the button on the board. This
is to prevent disrupting BFT test flow, during which we don't want to
reset the hub so as to maintain the USB link between the test host and
Plankton MCU.
BRANCH=None
BUG=chrome-os-partner:34296
TEST=Press the button to toggle between DP and USB mode. Measure USB hub
reset signal with a scope.
Change-Id: I69bdee292fe414abbe0a4778b8f5e8041e4534c1
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237606
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
When a DP cable is attached, if we toggle the USB/DP mux to USB mode,
the DP data link is broken. In this case, we should send a HPD event to
notify the host. Similarily, when we switch back to DP mode when a cable
is attached, we should send a HPD attachment event and then a HPD IRQ to
notify the host that the DP link is ready.
BRANCH=None
BUG=chrome-os-partner:34296
TEST=Connect Plankton to Samus. Perform the following tests:
1. Attach a cable, and switch between USB and DP mode.
2. Attach a cable in DP mode, switch to USB mode, unplug the
cable, and then switch back to DP mode.
3. Similar to 2 but start without the cable.
Change-Id: I5db0c036ce45850b2f4ca142957f4a235673df6f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/237604
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Sometimes default buffer size in not enough to collect debug
information generated before console is initialized.
This helps when debugging, allowing to enable fairly large amount of
data printed before console is available, could be reduced if memory
becomes tight.
BRANCH=none
BUG=none
TEST=early debug information previously truncated is printed fully
now.
Change-Id: I647c6064a44f7558414f72f399280b5780a4b1ec
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/268640
HPD needs to be transported over USB PD as both SBU lines are consumed
for differential AUX signalling.
This CL does the following:
1. Enables GPIO DPSRC_HPD as interrupt.
2. Sends debounced HPD across CC via the SVDM DP status message.
3. Adds polling for GPIO_DBG_20V_TO_DUT_L as it shares the same
interrupt as DPSRC_HPD.
4. Configures DP redriver in presence of HPD high.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=chrome-os-partner:33132,chrome-os-partner:33761
TEST=manual,
1. Connect samus -> plankton via type-C
2. Connect plankton -> DP monitor via displayport
See initial SVDM discovery on samus console
See EDID information
See SVDM status message correct when plug/unplug DP cable from plankton
3. Press 'CHARGING_20V_TO_DUT_L' button and see below on plankton console.
Button 8 = 0
Change-Id: Id95567a3bfa073ffa2c699335be8c5bf0327675f
Reviewed-on: https://chromium-review.googlesource.com/229429
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit, '0016de8 - plankton: Initialize re-driver', didn't account for
the state of the redriver at the time it was being initialized in
manual training mode. This led to inconsitencies of manual training
configuration.
This CL resets the SN75DP130 via software to guarantee configuration
regardless of cold versus warm boot.
Additionally I learned that manual training requires setting of both
the link_bw_set (5.4gbps) and lane_count_set (4) in order make the
back side of the redriver happy. This can ONLY be done however in the
presence of HPD high. Future CL will incorporate this DPCD init into
HDP interrupt handler as well.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=chrome-os-partner:35153
TEST=manual,
samus + plankton successfully drives Samsung U28D590 from cold or warm
boot of either plankton or samus in both polarities. Note DisplayPort
cable must be connected to external monitor prior to power on or reset.
macbook (2015 type-C) + plankton also works.
Change-Id: I8b34341d10f64abfa55c18f70c842a4446f36fa8
Reviewed-on: https://chromium-review.googlesource.com/266526
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
