The name BIGNUM collides with a namesake struct
in openssl. It would be convenient to write
test code that compares results between openssl
and dcrypto, hence this rename.
Also rename some #defines that conflict with
openssl names.
CQ-DEPEND=CL:*270476
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115
TEST=build succeeds
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360346
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a15b495497728a6b212bd87e92f6ba5ba463f985)
Change-Id: Ic53ce805cfcc591c68fbc1ef90ff2f92cec973a6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362112
Reviewed-by: Nagendra Modadugu <ngm@google.com>
BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th
and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results print their test name followed
by a space and and integer error code
Change-Id: If52e9b50705779b3a291e2d0f6b0721a5b6197d8
Reviewed-on: https://chromium-review.googlesource.com/359988
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This copies the generic USB update code into common
so it can be used on other platforms. There should be
no functional change. cr50 folks want no change to their
code so vbendeb@chomium.org will refactor this back
together at a later date.
BUG=chromium:571476
TEST=none
BRANCH=none
Change-Id: I710afb22940013e7db5d8694898b90c0ae245777
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In certain test scenarios the tpm task is hogging all resource and
causes watchdog resets. Let's kick the watchdog in every loop, Long
calculations already have watchdog kicking in place.
BRANCH=ToT
BUG=none
TEST=tests executed in rapid succession do not cause watchdog resets
any more.
(cherry picked from commit de8fb11bfd07d3fea2048b6848b8a183c31e2580)
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360229
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Change-Id: Ifaad6f9b4af2218f601412a36a075b4b4275d56f
Reviewed-on: https://chromium-review.googlesource.com/362170
Let's not force the linux kernel description format on cherry picked
patchs, especially since this check sometimes gets false positive, and
since this formwat is not used in the ec codebase.
BRANCH=none
BUG=none
TEST=no more annoying error reports on cherry-picked patches
Change-Id: I903bb87c48998932bc9308245d158f212a57fdd1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362074
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The SHA config register should be cleared, so that
only required bits are set on init().
Doing so ensures that previous settings that used
the engine in a different mode, e.g HMAC, do not
survive.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds; tpmtest.py tests pass; manufacture works
(cherry picked from commit 9b3619ddd7304359ee17e243923f1e47c925cb21)
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/359418
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: If5a79af06ea7512f19775a2f34d741b144f211f7
Reviewed-on: https://chromium-review.googlesource.com/358982
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
In order for the vstore to be unlocked one needs to enable
the CHIPSET_RESET_HOOK. Do that for reef.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I94a41a08ad8649423988372607835da01ec12b8b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362001
Reviewed-by: Shawn N <shawnn@chromium.org>
Different actions need to be taken on PLTRST_L depending on
if it is asserted or deasserted. The vstore module needs to
reset its locks when PLTRST_L is asserted (host is in reset).
The interrupt was previously on occurring on a deassertion of
PLTRST_L (rising edge). That's not conducive for handling
actions which are required for assertion (falling edge).
Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be
called when PLTRST_L is asserted.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362000
Reviewed-by: Shawn N <shawnn@chromium.org>
usb-stream is used by USB updater as well as uart
forwarding. Add parameter for custom USB class define.
BUG=chromium:571476
TEST=builds
BRANCH=none
Change-Id: Id6294709de0c5408b10ed366b261be1bc7da7767
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361832
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
MODULE_SHI is used for the SPI master interface pins, so don't
reconfigure those. Instead manually configure the SHI pins using the
appropriate DEVALT bit.
BUG=chrome-os-partner:54328
BRANCH=None
TEST=Manual on kevin. Verify SHI continues to function on cold boot,
sysjump and resume from S3. Verify SPI sensors now function on resume
from S3 - `accelinit 0` succeeds.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180
Reviewed-on: https://chromium-review.googlesource.com/362061
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Remove GPIO USB endpoint to make room for update endpoint.
* Change GPIO mapping slightly to support servo micro v2.
BUG=chromium:571477
BRANCH=None
TEST=run servod, see new controls.
Change-Id: Id3b85b4c77b8f21afd9636b2ee459ace6f42f68e
Reviewed-on: https://chromium-review.googlesource.com/361383
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Having uart0 RX enabled can cause serious issues. This change adds a
config option to disable uart0 rx no matter what.
BUG=none
BRANCH=none
TEST=On B2 check that the ultradebug console is now read only
Change-Id: Icaec6954ffd3cbf0fda3f53581f6e4020d555267
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361976
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Programmable Peripheral Interconnect is a shared resource.
This CL adds code for allocating PPIs to devices.
BUG=None
BRANCH=None
TEST=Modify the I2C code to use this PPI allocation code and test
I2C communication (using experimental MXT touch controller code)
Change-Id: I8ec27867d041982ef18e8515d6434c5de2c189c5
Signed-off-by: Myles Watson <mylesgw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361405
Commit-Ready: Myles Watson <mylesgw@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
The battery on kevin apparently requests 0A / 0V when extremely low, so
ignore this request and apply the pre-charge current.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Verify Kevin powers on with dead battery and battery charges as
expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef
Reviewed-on: https://chromium-review.googlesource.com/361994
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Pre-charge vs fast-charge mode depends on battery voltage relative to
VSYS. Rather than checking battery voltage (which may change), set
pre-charge and fast-charge currents whenever charger_set_current() is
called.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I68c06108c6d85ceede396294bedd1a017ddddd52
Reviewed-on: https://chromium-review.googlesource.com/361993
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
During pre-charge, batteries may request < 512 mA. Allow battery
charging at this low current, and only apply the 512 mA floor when no
battery is present.
BUG=chrome-os-partner:54821
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Change-Id: Ia10e732a6b21587917ffa5e34035507f5be74dd3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361589
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There was a mistake in the initial driver implementation
regarding the MDAC field in the measure register (address 0x04).
The header file and associated code defined this 6 bit field
to be the upper 6 bits of the 8 bit register. However, the
data sheet for both rev A and B silicon show this field as
being the lower 6 bits of this register.
In addition, when using this threshold to distinguish between
a Rd and Ra attach, the threshold test logic was backwards.
If the threhold bit is set, then it means the voltage is
higher than the 200mV setting and should indicate a Rd attach.
BUG=chrome-os-partner:54790
BRANCH=none
TEST=manual
Tested with Anker TypeC hub using known polarity (CC1). Previously,
would see CC2 be selected as the active polarity. This resulted
in USB PD state machine getting stuck in SRC_DISCOVERY due to
SRC_CAP messages not being received correctly. With the changes,
verified that correct CC polarity is always detected and results
in reaching SRC_READY state.
Change-Id: Ia522abdac31642ff99bbf13ccc73a0a77bbdb32d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361614
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Remove "task_disable_irq()" function call in EC_RTC_ALARM_CLEAR case.
Host command "RTC_SET_ALARM" with 0 second does not disable volume key interrupt.
BUG=chrome-os-partner:55401
BRANCH=none
TEST=check EC UART log message.
If you press volume up/down button
- Before HC 0x47 (RTC_SET_ALARM Command with 0 second)
Log : Button 'Volume Up/Down' was released.
- After HC0x47
Log : Button 'Volume Up/Down' was released.
GPIO volume key is still enable.
Change-Id: I8d8a4fa4927046b76a49ac4833b6a710db2e05be
Signed-off-by: younghun kim <young-h.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/361670
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Younghun Kim <young-h.kim@samsung.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This workaround ensure that we can successfully get
register latch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:55044
TEST=We simulate the delay time between first and second read,
and prove this method can avoid latch fail.
Change-Id: I7cafb53a8efbb2eee09af29d7365806dc0deb762
Reviewed-on: https://chromium-review.googlesource.com/358730
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
MKBP can now support buttons, so this commit adds the
keyboard_update_button() function which will be used to handle the
non-matrixed buttons.
BUG=chrome-os-partner:54976
BUG=chromium:626863
BRANCH=None
TEST=Flash kevin, press volume and power buttons and verify that
keyboard is still functional.
TEST=make -j buildall
CQ-DEPEND=CL:358633
Change-Id: I1c2d36d2113715cf6bd8c6fa7b26fe9253f6ac9f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/358634
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, the matrix keyboard protocol does not have support for
handling non-matrixed keys. This commit adds support for buttons which
do not appear in the keyboard matrix as well as switches.
Additionally, the keyboard FIFO is now just a general MKBP events FIFO
which MKBP events are free to use. Now, buttons and switches wil join
the key matrix event.
BUG=chrome-os-partner:54988
BUG=chrome-os-partner:54976
BUG=chromium:626863
BRANCH=None
TEST=Flash kevin, and verify that keyboard is still functional.
TEST=make -j buildall
CQ-DEPEND=CL:358926
Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/358633
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
USB is only used for CCD. USB should not be enabled as a wakeup source
unless a debug accessory is detected, because that is the only USB
traffic we care about. The rest may be from other sources like the HID
interface or something else using those signals. This change disables
the utmi wake source when the debug accessory is attached and enables it
when it is connected.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=manual
The SPI_CS_L pin still gets triggered and will wake up cr50
before usb so disable wake up pins as a wakeup source.
Verify Cr50 goes to sleep and plugging in a SuzyQ will wake it
up and after removing it Cr50 will go back to sleep.
Change-Id: Ib97244016b0af244c340259915def9f4d8f97569
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360693
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Call rdd_attach or detach based on the current CC state and initialize
the debug map to the proper state.
BUG=none
BRANCH=none
TEST=reboot cr50 with suzyq plugged in and check ccd is initialized.
reboot cr50 with suzyq disconnected and verify ccd is disabled.
Change-Id: I61eb9f357ee4309030b06225502add4f5e43ac31
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361596
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
As of EVT2, remove I2C (TWI).
Use the pins for analog sensing of the battery level.
BUG=None
BRANCH=None
TEST=Sense the battery level and use the serial port.
Change-Id: I3d5d2401e61e6e7d203e933d2566f6f3cd65c054
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361546
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
Blink the LED in S3 as well as S0iX states so there is no user visible
difference in their behavior.
BUG=chrome-os-partner:55225
BRANCH=glados
TEST=Enter S0iX on cave and verify LED blinks.
Also verify that the LED still blinks in S3.
Change-Id: I883147b1c8e599de077c9f06e567a63d535a01f8
Signed-off-by: james_chao <james_chao@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/359985
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Servo V4 rev2 has slightly different gpio mappings.
Note that this change will cause rev1 to not work.
Allow uservo routing before servod init. Further
work is needed on uservo port preinit as servod will
reset the port on startup, disconnecting uservo.
BRANCH=none
BUG=chromium:571476
TEST=Boot, use dut-control, see uservo.
Change-Id: I6436eed030cfdd329c5bd0cbca49038b268c2b71
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359620
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There's a new OTP change for the BD99955 and therefore the following
changes needed to be made.
- Change VFASTCHG_SET1 to 8.704V before CHG_EN is set to 1.
- Change VSYS_REG to 6.144V when starting Fast Charging.
- Change VSYS_REG back to 8.906V when Fast Charge is finished.
- Wait for 50ms to set CHG_EN to off (0) after Fast Charging has ended.
BUG=chrome-os-partner:55220
BUG=chrome-os-partner:55238
BRANCH=None
TEST=Flash kevin, plug discharged battery in. Plug AC in. `bd99955 r
0x11 1' and verify that VSYSREG is set to 0x1800 (6144mV).
TEST=`bd99955 r 0x1a 1' and verify that VFASTCHARGE is set to
0x2200 (8704mV).
TEST=Remove battery. `bd99955 r 0x11 1' and verify that VSYSREG is set
to 0x2300 (8960 mV).
TEST=Plug in battery and let charge to full. Verify that VSYSREG is set
to 0x2300 (8960 mV).
Change-Id: I5e5ca2cdcd4ead383416901c904df1e6fe5a9e28
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360421
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Regulate the system voltage by setting the charging voltage to battery
maximum in case of battery LEARN, Cut-off & No-battery conditions.
BUG=chrome-os-partner:55292, chrome-os-partner:55255
BRANCH=none
TEST=Manually tested on Amenia using console command charger.
Charging voltage is set to battery max in LEARN, Cut-off &
No-battery conditions.
Change-Id: I74bbab8174fd63b5f8439b8b35098db4a506d72d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/360681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before, as soon as the EC started booting, it would unconditionally boot
the AP (unless explicitly told not to. ie: "reboot ap-off"). However,
we weren't waiting for our power to settle which was causing some
brownouts. This would happen when trying to boot without the battery.
This commit causes the EC to inhibit powering on the AP until we have
sufficient power.
BUG=chrome-os-partner:55289
BRANCH=None
TEST=Flash EVT2; verify can boot normally.
TEST=Remove battery and insert charger. Verify that DUT can boot up.
TEST=Insert drained battery. Verify power on is inhbited. Plug in
charger and verify that DUT can power on.
Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361005
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54944
BRANCH=master
TEST=Manual on Elm. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Change-Id: I7782d333da89b872e33ea31304f878ca490329cf
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/360781
Reviewed-by: YH Huang <yh.huang@mediatek.com>
Reviewed-by: Rong Chang <rongchang@chromium.org>
It's imported from test/interrupt.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=make buildall. Test passed on stm32l476-geval and nucleo-f072rb.
Change-Id: Ie948d284cebad60d97aab1512bb9e3af8838004e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360660
Reviewed-by: Chris Chen <twothreecc@google.com>
It's imported from test/hooks.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=make buildall. Test passed on stm32l476-geval and nucleo-f072rb.
Change-Id: I70673f2c0f8316a2b1fd9472eeb7db350fdc2d84
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360631
Reviewed-by: Chris Chen <twothreecc@google.com>
It's imported from test/mutex.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=Test passed on stm32l476-geval and nucleo-f072rb. make -j buildall
Change-Id: I8cab0541ecbb1daa26b4d728fbd3e45e903ee512
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360600
Reviewed-by: Chris Chen <twothreecc@google.com>
Test functions are listed in cts.testlist and shared by th.c and dut.c.
This way, we can gurantee the two files are in sync. Also, cts.testlist
is used to count the number of tests automatically.
This allows us to use a for loop to execute each test.
BUG=none
BRANCH=none
TEST=build buildall
Change-Id: I0c811405134fad04f5c6914b1ac38835e212cbd2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359619
