Make it clearer what the new key is about.
CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/950263
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There's a new pin being added for board versions. Additionally, the
endianness is different than what was implemented.
BUG=b:73260349
BRANCH=stabilize-meowth-10444.B
TEST=Flash meowth; verify board version is as expected.
Change-Id: I97fb66f6c6aaf20d0ea4ed5994301490234ab812
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/949054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1. Enable fan feature and update fan setting.
2. Enable SW and chipset throttle feature.
3. Fix the issue that cannot set fan duty by "fanduty" in EC console.
BUG=b:72974136
BRANCH=none
TEST=Check fan command(fanduty/fanset/fanauto) in EC console can work and
check below condition.
1.AP throttling soft
--> Increased temperature to over trigger point, then to check
EC notify event in EC console.
2.AP throttling hard
--> Increased temperature to over trigger point, then to check
EC notify event and CPU_PROCHOT pin status in EC console.
3.Fan controlled in s3/s5 as expected (by EC)
--> Check Fan turn off in s3/s5.
4.Fan controlled in S0 as expected (by DPTF)
--> Check Fan keep 100% duty and no see DPTF to set fan duty.
But fan duty can be control by "fanduty" in EC console.
Change-Id: If9fd7f64c123ff54742052b6310023f0d4b0113a
Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/906086
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Move the RW signature verification in a dedicated task rather than on
the synchronous startup path, in order to be compatible with our flashrom
update mechanisms (but at the expense of additional latency in RO).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=flashrom -p ec:type=fp -w ec.bin
Change-Id: If9ae66bfde0c5922db86dc9acfd4ee766089fa1d
Reviewed-on: https://chromium-review.googlesource.com/936542
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In the case of almost full battery, without this
change the battery will keep charging even
if charging is not allowed when external power
is kept attached.
BUG=b:71364739
BRANCH=master
TEST=On glkrvp, let battery charge to 100% and verify after that
it starts discharging to 95% and then starts charging back.
Change-Id: I71935f795909d11ad93fd56caaa3683b54104c65
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/927798
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Things that need it will request it to turn on.
The only reason accel is on by default is because we need to be able to
poll it from time to time.
TEST=Motion related things still work
BUG=While looking at b/67743747
BRANCH=master
Change-Id: I08ea487058fb93ce6ff5fcc9054243d83e189e21
Suggested-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887947
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The fuel gauge (max17055) on Scarlet is powered by VBAT.
To use max17055 to detect batttery presence, we want to keep
it alive even if battery is disconnected.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops
Change-Id: Ice27384ded257be75ee29a28c0ada9f73b173f6c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/930572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
When running the spihash command using gsctool (as opposed to the
running it from the Cr50 console), the operator needs to be prompted
when the PP button needs to be pressed.
This patch extends spihash command implementation by adding a new
subcommand for polling physical presence.
BRANCH=cr50, cr50-mp
BUG=b:73668125
TEST=with the appropriate gsctool changes the user is periodically
prompted to press the physical presence button, and eventually it
is possible to set up spi hash access to AP and EC.
Change-Id: I96aed1619d364c80a2f35ca8dc41241f1a444103
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/930568
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have been using upstart script to force VR decay in runtime S0ix
for a while now and haven't seen any issues. This change pushes the
fix in EC so that we don't need the upstart script hack any more.
BUG=b:70881268
BRANCH=None
TEST=Verified by reverting upstart script that PMIC registers are
programmed as required to enable VR decay in S0 and S0ix.
Change-Id: I19729e907d2ae065758e69933d0b1d3e5b43d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/856856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cr50 cannot override the state of the power button. It was possible with
dev cr50 chips, but the capability was removed in prod chips. Change the
console command, so it is only used to get the state of the power
button.
Remove all of the commands used to override the power button.
BUG=b:73557298
BRANCH=none
TEST=none
Change-Id: I99cb5e8a18dd972fba460c434364702f06a26305
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/926964
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Release the reset of the FP MCU later after loading the proper spidev
kernel module else the STM DFU bootloader is confused by the SPI state
and fails half of the time.
Also update the SPI device for the current board configuration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=On Meowth, run a lot of 'flash_fp_mcu ec.bin'
Change-Id: I634fbc91fc5da52b07c48696594661f88338d986
Reviewed-on: https://chromium-review.googlesource.com/924284
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
BUG=chromium:803955
BRANCH=none
TEST=Verify counters are printed every hour and before sysjump as follows:
[12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0]
Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912150
Currently CBI data offset and size are fixed. This patch makes them
variable. Each data item consists of <tag><size><value> where <tag>
is a numeric value assigned to each data item, <size> is the number
of bytes used for <value>.
BUG=b:70294260
BRANCH=none
TEST=Use 'ectool cbi set' to set board version, oem, sku.
Verify the contents by cbi console command and ectool cbi get.
1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2)
2. ectool cbi set 1 1 1 (write oem id of size 1)
3. ectool cbi set 2 2 1 (write sku id of size 1)
4. ectool cbi get 0
514 (0x202)
5. ectool cbi get 1
1 (0x1)
6. ectool cbi get 2
2 (0x2)
7. Run cbi console command:
CBI_VERSION: 0x0000
TOTAL_SIZE: 18
BOARD_VERSION: 514 (0x202)
OEM_ID: 1 (0x1)
SKU_ID: 2 (0x2)
43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02
01 02
Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/920905
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the current led code with an implementation that uses the new
led_pwm interface. Grunt has a blue LED which we use for power and an
amber LED which we use for battery.
The colours used are documented in update_leds() in led_pwm.c
BUG=b:71902053
BRANCH=none
TEST=manual
Check for the various states:
* Solid Amber == Charging
* Solid Blue == Charging (near full)
* Fast Flash Amber == Charging error or battery not present
Did not test low / critical battery
Change-Id: Ie46075855ab17e6e7301025b62e57db2c596b2a4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919765
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
The EC_BATT_PRES_ODL is an open drain signal. The SN74LVC1G07
IC which drives that signal is an open drain buffer. There is
no external pull. Therefore, an internal pullup is required.
BRANCH=none
BUG=b:73286869
TEST=gpioget shows 0 with battery and 1 without
Change-Id: I98e18f54b62ddd558bedd9cec65aa003589a0681
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/923102
Commit-Ready: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch also removes make rules to stop producing CBI blobs.
CBI blobs will be produced by another protage package.
BUG=b:73123025,chromium:809250
BRANCH=none
TEST=emerge-fizz chromeos-firmware-fizz and verify
/build/fizz/firmware/cbi contains EEPROM images.
Verify emerge ec-utils ec-devutils succeeds.
Change-Id: I13744b0ab97675afa0247046bffa3edac3e62ceb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/909692
The console command now calls the vendor command to do the work.
Otherwise, the same as before.
BUG=chromium:804507
BRANCH=cr50 release (after testing)
TEST=manual:
# Sample sequence
spihash ap -> requires physical presence; tap power button
spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin
spihash dump 0 128 -> dumps first 128 bytes; compare with image.bin
spihash 128 128 -> offset works
spihash 0 0x100000 -> gives a hash; doesn't watchdog reset
spihdev ec
spihash 0 1024 -> compare with ec.bin
spihash disable
# Test timeout
spihash ap
# Wait 30 seconds
spihash 0 1024 -> still works
# Wait 60 seconds; goes back disabled automatically
spihash 0 1024 -> fails because spihash is disabled
# Presence not required when CCD opened
ccd open
spihash ap -> no PP required
spihash 0 1024 -> works
spihash disable
# Possible for owner to disable via CCD config
ccd -> HashFlash is "Always"
ccd set HashFlash IfOpened
ccd lock
spihash ap -> access denied
# Cleanup
ccd open
ccd reset
ccd lock
Change-Id: Ife9335a1e402a7596d99bf515ec89ff94e8a0044
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910083
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
we need to enable CONFIG_CMD_PD_CONTROL so the AP (depthcharge) can do
TCPC firmware update. this was left disabled for bringup.
BUG=b:69010531
BRANCH=none
TEST=booted on meowth, was able to update TCPC firmware
Change-Id: If383cff27c7b79f46f451c6380585d1300fc3413
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910322
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The new key ID is set to zero.
BRANCH=cr50, cr50-eve
BUG=b:70891959
TEST=verified that prod server properly responds to the challenge
generated by a CR50 running on Robo device.
Change-Id: I1e0da4a2cebca7f985c5f2a6da509c850924a874
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/915503
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Michael Tang <ntang@chromium.org>
EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A.
These should be off in G3 and on in S5 and higher.
VGATE (S0 power) is pulled high in G3 when SPOK (system power,
S5) is low because PP5000_A turns off, so add a check for this
and only pass through high VGATE when SPOK is also high.
Leave kahlee behavior unchanged (power stays on in G3).
BUG=b:72744306
BRANCH=none
TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3
Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/904729
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Deep Sleep states (DS3, DS5) are a special mode of the Intel PCH chipset
that has very limited wake capabilities and breaks a number of common
user expected behahviors.
In particular, when in Deep S3 the USB ports are turned off and cannot
continue to charge, wake the system, or maintain their internal state
as they will lose 5V power. This is particularly painful with gnubby
devices as they will need unlocked after every DS3 suspend/resume cycle.
The only external signal that the PCH uses to determine whether or not
to enter Deep Sx states is the ACPRESENT (aka ACOK) pin.
Currently this pin is simply buffered from the charger and will be
asserted whenever a charger is connected. This change extends the EC
control over the pin to also assert ACPRESENT if either Type-C port is
currently supplying VBUS.
Now when a USB device is inserted the system will be enter S3 state,
but not go into Deep S3 state. This allows the USB device to continue
to charge, maintain it's internal state, and wake the system.
BUG=b:64406191
BRANCH=eve
TEST=verify GPIO_PCH_ACOK pin from the EC in different scenarios and
test that system goes into S3 or DS3 state as expected:
1) no charger, no USB device: ACOK not asserted, DS3 enabled
2) charger but no USB device: ACOK asserted, DS3 disabled
3) no charger but USB device: ACOK asserted, DS3 disabled
4) charger and USB device: ACOK asserted, DS3 disabled
Change-Id: I1cd132459194382e418970d29b1b195d8132cfad
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/896164
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Disable sensor power (lid accel, gyro) in G3+S5. Enable
it in S3+S0. We want it on in S3 for calculating the lid
angle (needed on convertibles to disable resume from
keyboard in tablet mode).
BUG=b:72741289
BRANCH=none
TEST=GPIO_EN_PP1800_SENSOR =0 in G3+S5 and =1 in S3+S0
Change-Id: I043b880b9fbd44242df0d2ac01c92a066d6b4377
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/912452
Reviewed-by: Lann Martin <lannm@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Configure the fingerprint to be compile only in the RW partition for
size reason, and keep the RO for firmware update only.
Enable the RW signature to jump automatically to RW.
The dev key was generated with the following command:
openssl genrsa -3 -out board/meowth_fp/dev_key.pem 3072
Enable the new STM32H7 internal flash support along the way.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=run on ZerbleBarn and see the firmware jumping to RW,
then run 'fptest' console command and get a proper capture.
CQ-DEPEND=CL:*552559
Change-Id: Icc894b8a59b255b4c6a139f177e99d0fde7c4e19
Reviewed-on: https://chromium-review.googlesource.com/880955
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This allows hashing or dumping SPI flash from the Cr50 console even on
a locked device, so you can verify the RO Firmware on a system via CCD.
See design doc: go/verify-ro-firmware
(more specifically, "Cr50 console commands for option 1")
BUG=chromium:804507
BRANCH=cr50 release (after testing)
TEST=manual:
# Sample sequence
spihash ap -> requires physical presence; tap power button
spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin
spihash 0 128 dump -> dumps first 128 bytes; compare with image.bin
spihash 128 128 -> offset works
spihash 0 0x100000 -> gives a hash; doesn't watchdog reset
spihdev ec
spihash 0 1024 -> compare with ec.bin
spihash disable
# Test timeout
spihash ap
# Wait 30 seconds
spihash 0 1024 -> still works
# Wait 60 seconds; goes back disabled automatically
spihash 0 1024 -> fails because spihash is disabled
# Presence not required when CCD opened
ccd open
spihash ap -> no PP required
spihash 0 1024 -> works
spihash disable
# Possible for owner to disable via CCD config
ccd -> HashFlash is "Always"
ccd set HashFlash IfOpened
ccd lock
spihash ap -> access denied
# Cleanup
ccd open
ccd reset
ccd lock
Change-Id: I27b5054730dea6b27fbad1b1c4aa0a650e3b4f99
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/889725
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
1. Prochot/Shutdown Point
a. Prochot on: >=81C, off: <=77C
b. Shutodwn: >=82C
2. custom fan table
There are three projects sharing two tables, and
use Kench & Teemo's table before getting correct OEM ID
because it raises fan speed quicker than the other one.
a. Kench & Teemo & default
b. Sion
BUG=b:70294260
BRANCH=master
TEST=EC can get two fan tables with different cbi value.
Change-Id: Ie1bffbcf5c353a9aae5806f6c2b41554eed22b7d
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/886121
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
BRANCH=none
BUG=b:72722179
TEST=lidopen/lidclose, see that USB interface is getting enabled/disabled
TEST=Close/open sensor with a magnet, see that USB interface is getting
enabled/disabled
TEST=Boot with sensor open, USB interface is on
Change-Id: Ic738fa2f2adea03cd29914bb5fc96a1fa6834122
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/894783
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fizz has three FETs connected to three registers: PR257, PR258,
PR7824. These control the thresholds of the current monitoring
system.
PR257 PR7824 PR258
For BJ (65W or 90W) off off off
For 4.35A (87W) on off off
For 3.25A (65W) off off on
For 3.00A (60W) off on off
The system power consumption is capped by PR259, which is stuffed
differently depending on the SKU (65W v.s. 90W or U42 v.s. U22).
So, we only need to monitor type-c adapters. For example:
a 90W system powered by 65W type-c charger
b 65W system powered by 60W type-c charger
c 65W system powered by 87W type-c charger
In a case such as (c), we actually do not need to monitor the current
because the max is capped by PR259.
AP is expected to read type-c adapter wattage from EC and control
power consumption to avoid over-current or system browns out.
The current monitoring system doesn't support less than 3A
(e.g. 2.25A, 2.00A). These currents most likely won't be enough to
power the system. However, if they're needed, EC can monitor
PMON_PSYS and trigger H_PROCHOT by itself.
BUG=b:72883633,b:64442692,b:72710630
BRANCH=none
TEST=Boot Fizz on 60W/87W/BJ charger. Verify GPIOs are set as expected.
Change-Id: Ic4c0e599f94b24b5e6c02bbf1998b0b89ecad7bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/900491
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When RMA procedure is completed WP needs to be enabled back.
BRANCH=cr50, cr50-mp
BUG=b:37952913, b:73075443
TEST=on a Robo device, verified that WP is enabled, took the device
through RMA unlock, verified that WP is disabled, took the device
through RMA disable, verified that WP is enabled again.
Also confirmed that after RMA is disabled WP status follows the
battery.
Change-Id: Iad6af7d16aadcd10d580f709aeb942cf508a8489
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/905926
Reviewed-by: Randall Spangler <rspangler@chromium.org>
