Make it clearer what the new key is about.
CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/950263
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Cr50 lacks native instructions for 64-bit integers and an ABI
function can be used by the compiler to take the place of the
needed instructions. This CL adds support for a right bitwise
shift of 64-bit integers.
BRANCH=none
BUG=chromium:794010
TEST=Set CONFIG_LLSR_TEST, build, update cr50, and run llsrtest
on the console.
Change-Id: Iae66c86720c531454ba29f15b3cc6a07959f5ef2
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/931932
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There's a new pin being added for board versions. Additionally, the
endianness is different than what was implemented.
BUG=b:73260349
BRANCH=stabilize-meowth-10444.B
TEST=Flash meowth; verify board version is as expected.
Change-Id: I97fb66f6c6aaf20d0ea4ed5994301490234ab812
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/949054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BRANCH=none
BUG=b:73528930
BUG=b:73660652
TEST=Flash lux, check that lux adc VBUS voltage when only no
charger is connected is around 12V.
Change-Id: Iccc245c96ca3c83674446f96f78f1ce15ffa7de2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/948322
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a new module ID 'MODULE_FAST_CPU'.
When it is enabled with clock_enable_module(MODULE_FAST_CPU, 1), switch
the system clocking to the fast 400-Mhz PLL.
For now, I consider that a single task/user is calling
clock_enable_module(MODULE_FAST_CPU, x), so we don't need to count users
(in a complicated atomic fashion). It's good enough for the current
use-case and we can add the complexity later if we have a real need.
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, with follow-up CL setting
clock_enable_module(MODULE_FAST_CPU,x) around the computation block,
see that computations are fast and the clock goes back to HSI after.
Change-Id: I2aef3ad673ddbffd6fc64c591c54297e94896fa6
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/945688
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Set the PLL frequency to 400 Mhz (max value) and the AHB frequency to
200 Mhz.
Fix the PLL clocking code for STM32H7 :
- fix the frequency computation.
- adjust the timer divider depending on the system clock.
- the 64Mhz HSI is already setup properly at startup, takes it into
account.
- set the SPI ports on the fixed 64-Mhz HSI, so clocking changes don't
mess up their frequencies or stability.
Note: this is just modifying the CPU frequency when the system is
clocked by the PLL, by default the system is still clocked by the 64-Mhz
HSI. Currently, one have to use the 'clock pll' console command to test
this PLL mode, some code will be added soon to switch on-demand for
heavy computations.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508, b:72879097
TEST=On ZerbleBarn, do 'clock pll', check 'gettime' against wall clock,
run image capture and enrollment.
TEST=on ZerbleBarn, verify on the scope that the SPI master frequency is
4 Mhz in both configuration.
Change-Id: I92a2216999337cf9831fb5dfc2797ab1cce71a8f
Reviewed-on: https://chromium-review.googlesource.com/941226
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
1. Enable fan feature and update fan setting.
2. Enable SW and chipset throttle feature.
3. Fix the issue that cannot set fan duty by "fanduty" in EC console.
BUG=b:72974136
BRANCH=none
TEST=Check fan command(fanduty/fanset/fanauto) in EC console can work and
check below condition.
1.AP throttling soft
--> Increased temperature to over trigger point, then to check
EC notify event in EC console.
2.AP throttling hard
--> Increased temperature to over trigger point, then to check
EC notify event and CPU_PROCHOT pin status in EC console.
3.Fan controlled in s3/s5 as expected (by EC)
--> Check Fan turn off in s3/s5.
4.Fan controlled in S0 as expected (by DPTF)
--> Check Fan keep 100% duty and no see DPTF to set fan duty.
But fan duty can be control by "fanduty" in EC console.
Change-Id: If9fd7f64c123ff54742052b6310023f0d4b0113a
Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/906086
Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set
so that the hardwire signals for SCI, SMI and RCIN are connected to VW
input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has
made it configurable.
NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change
ensures that they are preserved while initializing VWEVSM2 registers
BUG=b:74111394
BRANCH=None
TEST=Verified that SCI works on glkrvp and meowth with NPCX7.
Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/943801
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When checking the RMA authentication code the code currently just
verifies the value, but does not act on it.
This patch directs the user input through the same vendor command path
which is used when the RMA operation is controlled using gsctool.
BRANCH=cr50, cr50-mp
BUG=b:74080723
TEST=verified that issuing 'rma_auth <code>' on the Cr50 console now
trigger CCD open and reboot.
Change-Id: Ib3fab131b6a24b65618f0b1f2504638f8df11a4b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/945311
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The ARMv7-M ISA defines standard (and optional) mechanism to manage the
CPU caches through the SCB (System Control Block) registers.
So far, only the Cortex-M7 core implements such as a mechanism (e.g. the
Cortex-M4 with caches we have are using a proprietary mechanism for the
management).
Define the functions to use the I-Cache,
and enable them on STM32H7 which is our only supported Cortex-M7 core.
The D-Cache mechanism is still To Be Done, as it involves a bit more
support in the firmware for the DMA memory areas.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR
(e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload
without crash and with a speed-up.
Change-Id: I6af1021d65048b787630387f7d95797db15d069c
Reviewed-on: https://chromium-review.googlesource.com/943445
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The DBP bit needs to be set in the PWR_CR1 register before doing the RTC
configuration (in order to be able to right RTC registers).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, dump the RTC_TR register and it is incrementing
every second, e.g. 'rw 0x58004000'.
Change-Id: I02dc6c6f1852ced934bccf3e401f4fdc1aad57d9
Reviewed-on: https://chromium-review.googlesource.com/941224
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Set GscFullConsole to Always in RMA open. We need this to be accessible
after rma open, so that we can use RMA open as a ccd open testlab
replacement.
Commands like rddkeepalive and bitbang are needed for testlab use, so
they should be accessible after open.
BUG=b:74019846
BRANCH=cr50, cr50-mp
TEST=build, do rma open, verify commands are not locked out, and do rma
disable
Change-Id: Iaeb89cea94d478dc0eb25c92bb09d488d14cad41
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/942309
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Move the RW signature verification in a dedicated task rather than on
the synchronous startup path, in order to be compatible with our flashrom
update mechanisms (but at the expense of additional latency in RO).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=flashrom -p ec:type=fp -w ec.bin
Change-Id: If9ae66bfde0c5922db86dc9acfd4ee766089fa1d
Reviewed-on: https://chromium-review.googlesource.com/936542
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Also define the EC_FEATURE_RWSIG feature bit if the RO firmware contains
the RWSIG task but not the RW.
Given the RWSIG verification task is not terribly useful in RW
(where it is never executed), it can be skipped there but the host
program trying to detect RWSIG usage (e.g. flashrom) still wants to be
able to detect it.
In order to be able to do so, add the HAS_TASK_xXx_RO and
HAS_TASK_xXx_RW flags which define the tasks defined in the other
partition (at compilation-time you might still run a frankeinstein combo).
Fix ectool 'inventory' to avoid segfaulting on missing feature string
definition.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=on ZerbleBarn, run 'ectool inventory', also uses flashrom to
re-flash the RW partition.
Change-Id: I224a6cc4aef956204792a2cc04ad12aaed5abf47
Reviewed-on: https://chromium-review.googlesource.com/937262
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Using only a Carriage Return as done to have a nice spinner is not
terribly compatible with logging the output of the tool to a file or
piping it to anything.
Add another option to have a simple progress-bar instead.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=on Meowth, run flash_fp_mcu from the factory UI.
Change-Id: I0c37689d2ed1e45dff54b7f1eb2be515ea37e004
Reviewed-on: https://chromium-review.googlesource.com/936766
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
The shmem console command was looping with the wrong iterators,
doing an infinite loop when there was more than one allocated or
free block.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=build software with CONFIG_MALLOC and CONFIG_CMD_SHMEM, then run
'shmem' on the console at different time without hitting watchdog reset.
Change-Id: I93a9cff3811669ab895fa8753d1571e90aeb4f33
Reviewed-on: https://chromium-review.googlesource.com/943070
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Currently, if there is a fan which isn't in RPM mode, the rest of the
fans are not controlled even if they're in RPM mode. This patch gives
a chance to all the fans.
BUG=b:35543471
BRANCH=none
TEST=none
Change-Id: I6f930bad313bc2a31497f46647ab2b08e328dfff
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/940813
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In the case of almost full battery, without this
change the battery will keep charging even
if charging is not allowed when external power
is kept attached.
BUG=b:71364739
BRANCH=master
TEST=On glkrvp, let battery charge to 100% and verify after that
it starts discharging to 95% and then starts charging back.
Change-Id: I71935f795909d11ad93fd56caaa3683b54104c65
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/927798
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Things that need it will request it to turn on.
The only reason accel is on by default is because we need to be able to
poll it from time to time.
TEST=Motion related things still work
BUG=While looking at b/67743747
BRANCH=master
Change-Id: I08ea487058fb93ce6ff5fcc9054243d83e189e21
Suggested-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887947
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The fuel gauge (max17055) on Scarlet is powered by VBAT.
To use max17055 to detect batttery presence, we want to keep
it alive even if battery is disconnected.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops
Change-Id: Ice27384ded257be75ee29a28c0ada9f73b173f6c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/930572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
BRANCH=none
BUG=b:72961003,b:72956593
TEST=verified with grunt that parade TCPC will no longer shut down when
PPC sources Vconn
Change-Id: I6c1cee4dd8a40a992813841ec227a6af04de5313
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/935301
This will make sure that Cr50 images built from dev branch can take
over images built from either MP or pre-MP branches.
BRANCH=none
BUG=none
TEST=verified that it is possible to overwrite pre-MP Cr50 version of
0.2.2.
Change-Id: I929cb2be857ea90c544f83160d6820c73e23c69d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/938946
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Fan enable state is controlled in common/fan.c. This patch prevents
npcx fan driver from enabling it.
BUG=b:73127788
BRANCH=none
TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the
fan spins in S0.
Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/937941
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This field allows multiple product families to be independently versioned
and released, without risk of having one product family's image flashed
to another product family's chip.
BUG=b:73728151
BRANCH=none
TEST=make buildall -J
Change-Id: I53f5e5b1e9ac7ea19997f8d1228a568e66c43d39
Reviewed-on: https://chromium-review.googlesource.com/935759
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Nadim Taha <ntaha@google.com>
Thermal protection is by default enabled on rt946x, but we
disable it in rt946x_init() and only rely on the fuel gauge
to do thermal measurement.
Thus when we init rt946x too late, rt946x could trigger thermal
protection during boot and brown out the fuel gauge temporarily.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops
Change-Id: I54eadd80bd4fd8a6e47309b13c4d46ee01dec04a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/933703
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
For boards using max17055 and dumb battery, we can always
read battery parameters from max17055 regs, even if the
read values are out of whack.
So it doesn't make sense to determine battery is present
because we can read these parameters from max17055.
Meanwhile, we have to set CONFIG.TSEL on max17055 as early
as possible because this is required for max17055 to detect
battery presense.
BUG=b:72697658
BRANCH=scarlet
TEST=boot scarlet rev3 w/o battery on Type-C/PD chargers
Change-Id: Id190f0c2aa5bcd62dbe3edccca6460bf145cff01
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/933702
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Skip the empty blocks when writing even if they are in the middle of the
firmware.
This greatly improves flashing speed when the firmware contains a
signature at the end of the RW.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36125319
TEST=./util/flash_ec --board=meowth_fp
Change-Id: I3cd1c1bd2670be23d3d9daf9b87d9af0bdfc8963
Reviewed-on: https://chromium-review.googlesource.com/880956
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
When using the watchdog (IWDG) to perform the cold reset, set the Key
register to 'RELOAD' (0xAAAA) rather than 'START' (0xCCCC) to ensure
that the reset is performed immediately rather than at the end of the
current watchdog period (which might be 1 to 5s away).
Replace the Key register special values by their symbolic constants.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=On ZerbleBarn using a STM32H7, run 'ectool reboot_ec cold' and see
the MCU rebooting immediately rather than after 5s.
Change-Id: Ib49c703e3ec973389e4d774eda53f3be7ec4dd2e
Reviewed-on: https://chromium-review.googlesource.com/936764
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This patch enhances the gsctool utility to allow to verify RO sections
of the target AP and EC flash memory.
The only command line parameter required for the new option ('O') is
the file name of the target descriptors database, containing memory
description sections for one or more Chrome OS devices.
Memory description sections are of two types (both types could be
referring AP or EC memory):
- hash descriptor, this section includes the address range of the
memory and one or more hash values for the contents of that address
range. Multiple hashes are needed in case when the same device has
mnore than one RO firmware releases in circulation.
- dump descriptor, this is a request for this utility to display on
the console the contents of the certain area of flash memory on the
target.
When this utility starts the process, the target might request that
the operator confirms physical presence, in this case the utility
keeps prompting the operator to press the physical presence button
until DUT is satisfied,
BRANCH=none
BUG=b:73668125
TEST=created a descriptor database for a Robo device feeding it with
values retrieved on the device by locally running spihash command
on the device.
Then ran this utility to verify successful hash and dump
retrievals, comparing dump values with values obtained through
Cr50 console directly.
Created additional dummy hash variants and verified that the
utility succeeds only if all matches happen at the same variant
index in different hash sections.
Change-Id: Ib43cf4eb642d141b7cd7f129ef412e14bd59f30b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/933545
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This is a lateral move allowing to share some data structures and
functions previously limited to the gsctool.c scope.
This will allow adding new functionality in a separate .c file, and
further refactor gsctool.c which little by little became quite
unwieldy.
BRANCH=none
BUG=b:73668125
TEST=gsctool utility still works for uploading Cr50 images.
Change-Id: Ib56db3e0b983c53a228a658467a3059abcf2166e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/933543
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch adds code which would parse the RO hash/dump descriptor
file including a database listing expected values of hashes for
various ranges of target SPI flash devices, or areas which need to be
printed out (hex dumped) for operator inspection.
Lines starting with '#' are completely ignored. The rest of the
logical lines could actually split into multiple text lines in the
file, so to separate one logical line from another at least one empty
line is required.
Hash descriptor database file consists of sections for various Chrome
OS boards. Each board description section starts with a logical line
of 4 characters which is the board ID (the same as the board's RLZ
code).
Each board description section includes variable number of range
descriptor entries, each entry being a logical line, potentially split
into multiple text lines.
Each entry consists of semicolon separated fields:
{a|e|g}:{h|d}:base_addr:size[:value[:value[:value...]]]]
Where
- the first sindgle character field defines the way the range is
accessed:
a - AP flash
e - EC flash
g - EC flash requiring gang programming mode
- the second single character field defines the range type
h - Cr50 returns the hash of the range
d - Cr50 returns actual contents of the range (hex dump)
- the third and and forth fields are base address and size of the range
- ranges of type 'h' include one or more values for the hash of the
range, each hash is a 64 byte hex string. Ranges of type 'd' do
not include any data.
All values are expressed in hex.
The parser API provides functions to open the passed in hash
descriptor file and find there the section for a particular board, a
function to advance to the next entry in the board's section, and a
function to close the file when board entries scanning is completed.
When scanning the entries, the parser verifies their sanity, i.e.
conformance with the above described format, that all hashes are of
the right size, that there are no hashes attached to 'dump' entries
and there is at least one hash attached to the 'hash' entries, and
that there are no invalid characters in the hashes and address range
definitions.
The parser is not yet used by the gsctool, but when the new module is
compiled stand alone with -DTEST_PARSER passed to the compiler, it
becomes an executable which can be given the test hash database (the
new file, sample_descriptor) to interpret and report success or
failure.
BRANCH=none
BUG=chromium:812880
TEST=ran the following commands:
$ gcc -DTEST_PARSER desc_parser.c -o dp
$ ./dp sample_descriptor
Section 1, rv 0
Section 2, rv 0
Section 3, rv 0
Unexpected data in section 4
Section 4, rv -22
Invalid hash 1 size 0 in section 5
Section 5, rv -22
Invalid hash 1 size 0 in section 6
Section 6, rv -22
Invalid hash 1 size 63 in section 7
Section 7, rv -22
Invalid hash 1 size 65 in section 8
Section 8, rv -22
Invalid hash 1 value in section 9
Section 9, rv -22
Unexpected number of variants in section 10
Section 10, rv -22
Invalid hex value 10x in section 11
Section 11, rv -22
Section 12, rv -61
$
Change-Id: I14b2754a5f6ba26b3c56ddc26d45cb4574514b69
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/923419
Reviewed-by: Andrey Pronin <apronin@chromium.org>
CONFIG_IGNORE_G_UPDATE_CHECKS currently drops all upgrade checks.
Now with CONFIG_BOARD_ID_SUPPORT only check for board_id match.
CR50_DEV still retains full no check behavior.
TEST=buildall -j8
BRANCH=none
BUG=none
Change-Id: I0d085a26c814cd0f35450f0a0db06fe8525ab896
Reviewed-on: https://chromium-review.googlesource.com/933589
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
