BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
If PS8751 goes into low power mode during sysjump, then tcpm_init will
fail since PS8751 is not accessible via I2C, so force it to wake up
during hook_init.
BUG=chrome-os-partner:59693
BRANCH=none
TEST=Verified PS8751 port on reef is functional after sysjump.
Change-Id: I2aa5a80b2ea9c17a01e4cba04493f83cb0a39955
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410132
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Various cryptographic operations leak timing
information if comparisons are not executed
in constant time. This change adds DCRYPTO_equals(),
a constant runtime comparator.
Also replace crypto related callsites that used
memcmp() as a binary comparator.
BUG=none
BRANCH=none
TEST=tcg tests pass
Change-Id: I3d3da3c0524c3a349d60675902d1f2d338ad455f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/410163
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The firmware provision job running in the lab calls the flash_ec
script with the --chip parameter, instead of the --board parameter.
So only check if the board name is in the raiden list if it is a
non-empty board.
BRANCH=none
BUG=chrome-os-partner:58039
TEST=Manually triggered the flash_ec command:
$ flash_ec --chip=npcx_spi --image=${IMAGE} --port=9999 --raiden
Change-Id: I25fef906d93803a94c544f7699ce494a84c46bd8
Reviewed-on: https://chromium-review.googlesource.com/410162
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CTS task wakes up A and C then goes to sleep:
CTS -> A, C -> A -> B -> C
Since C has a higher priority, C should run first. This should result
in C running one more time than A (or B).
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: I89c733ba3aab09b293edf8583d6ed73791531e59
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Task A wakes up B and goes to sleep. Task B wakes up C then goes to
sleep. Task C wakes up A then goes to sleep. This is repeated
repeat_count times:
A -> B -> C -> A -> ...
It's expected all tasks to run exactly repeat_count times. Tick task
runs to inject some irregularity.
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: Ib7227f05f09b7a49f8528aff6e6e8d3e6df93ba7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409534
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These keys are much quicker to verify (259ms to 51ms on a -M0 at
48 Mhz), so they can be used when timing is critical and
verification needs to be performed on the board.
BRANCH=none
BUG=chromium:663631
TEST=make buildall -j && make run-rsa
TEST=make run-rsa3 (next commit)
Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8
Reviewed-on: https://chromium-review.googlesource.com/408006
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When bus obfuscation is enabled we have the chance of doing a security
reset when resuming from sleep. Since we cannot disable bus obfuscation
on current boards, we need to disable sleep.
BUG=chrome-os-partner:57994
BRANCH=none
TEST=make buildall
Change-Id: I6f49278a9b41c1d15c646838044e34f03b979479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409576
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When kernel get EC_HOST_EVENT_PD_MCU event and query power state, we may
not done refresh here. Delay EC_HOST_EVENT_PD_MCU event to avoid this
race.
BUG=chrome-os-partner:59499
BRANCH=gru
TEST=Manual on kevin, check power state correct after unplug charger
Change-Id: Ib88acf5a39c2780c6e40144ccebfba17cf84f77c
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/408131
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a nested interrupt test to eCTS. Higher priority IRQ is fired,
followed by lower priority IRQ. Handlers should be executed
sequentially.
P1 *-----*
/ \
P2 / *-----*
/ \
task_cts ----* *----
B C A D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m interrupt; make buildall
Change-Id: Ia9f1bf4205cefe8bdc11cc0aa3ad2057359b73ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409611
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a nested interrupt test to eCTS. Lower priority IRQ is fired,
followed by higher priority IRQ. Handler executions should be nested.
P1 *-----*
/ \
P2 *----* *----*
/ \
task_cts ----* *----
A B C D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer; make buildall
Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f
Reviewed-on: https://chromium-review.googlesource.com/408797
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After a board is reset for setting up a tty port, the host should
wait for a few seconds before flushing the port as the board may
still be booting. This should prevent output from the previous boot
from creeping into a test run.
BUG=none
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer
Change-Id: I1fb567a3a8ddcfff61865b6db3866c56be386c4a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/408759
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If our 32-bit usec timer is close to overflow, we may deep sleep several
times in succession without making any adjustment to our count, causing
deadlines on the other side (eg. HOOK_TICK expiration) to be reached much
slower than expected. Avoid this by not entering deep sleep if our timer
is about to overflow. This will result in a <= HOOK_TICK_INTERVAL (200ms
interval) period of not entering deep sleep, every ~4300 seconds.
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Verify 3x kevin units survive 16 hours in S3 without EC watchdog.
Change-Id: I2126458be8820f78212e19c2bb79242ff1194f6f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409673
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Wait for ITEN bit to be set / cleared, since writing this bit just
sets a 'request'.
- Ensure ITIM_EVENT_NO reg is set with minimum value 1, per the
datasheet.
- Don't dsleep if our wake event is in the past (eg. wake event will
occur any time now)
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Manual on kevin, verify that dsleep period never exceeds expected
wait period. Also verify that EC watchdog doesn't occur after 5 hours in
S3.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iedb2723c3f12b74dea66082b1d8b8ce1b6e7d945
Reviewed-on: https://chromium-review.googlesource.com/409672
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Since we are out of host event bits, add a bit to indicate extended host
event exists. This is put in as a placeholder for now so that we don't
lose out the last available hostevent bit.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully
Change-Id: If35a246f3da511fde9f8c0bba419afb76a1a9827
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds new key combination (Left_Shift+Esc+Refresh+Power) that triggers
recovery mode by setting a new host event
EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT. This host event can be used
whenever user wants to request entry into recovery mode by
reinitializing all the hardware state (e.g. memory retraining).
BUG=chrome-os-partner:56643,chrome-os-partner:59352
BRANCH=None
TEST=Verified that device retrains memory in recovery mode
with (Left_Shift+Esc+Refresh+Power) on reef.
Change-Id: I2e08997acfd9e22270b8ce7a5b589cd5630645f8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407827
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Simple API to set/get the tablet mode. It can be set via lid angle
calculation or if a board has a dedicated HAL sensor/GPIO.
Merged from glados branch, add MKBP switch support.
BUG=chromium:606718
BRANCH=gru
TEST=Check with Cave that both mode works.
Reviewed-on: https://chromium-review.googlesource.com/402089
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e)
Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404915
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We were getting occasional stack overflow and watchdog timeouts
when clearing NVMEM. Bump up the stack size a bit in the HOOKS
task, and pet the watchdog before invoking the tpm2 init
functions.
BUG=chrome-os-partner:59419
BRANCH=none
TEST=make buildall, manual
Lock the console, then unlock it. This will reboot the EC & AP,
but should never reboot the Cr50.
Before this CL, it did about half the time.
After, it doesn't.
Change-Id: I33adfeb7360bf7d146a55ef16c923a1a0416393d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407847
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When attaching a dump (not PD protocol) TypeC charger, the incorrect
charger type was being selected and therefore it was not enabling 3A
charging. I tracked this issue down to the anx74xx_tcpm_get_cc()
function returning a incorrect value. The expected value was
TYPEC_CC_VOLT_SNK_3_0, but instead it was returning
TYPEC_CC_VOLT_SNK_DEF.
The reason the incorrect cc type was being returned is because the if,
else if, construct didn't work properly for the 3A case where the
upper 2 bits are set. Modified this routine to use a case statement
and consolidated the checks for both cc1 and cc2 into one helper
function.
BRANCH=none
BUG=chrome-os-partner:58738
TEST=manual
Connected zinger and guppy chargers and verified correct cc type was
being returned. In addition tested hoho/dingdong adapters as well as
suzyq. Tested both cable orientations to verify that cc1 and cc2
returned the correct values.
With guppy connected, now see this output on ec console:
C0 HARD RST TX
C0 st5
C0 st36
C0 st37
C0 HARD RST TX
C0 st5
[1921.980074 AC on]
[1922.008140 charge_request(8688mV, 9280mA)]
C0 st6
[1922.910539 Ramp p0 st5 3000mA 3000mA]
Change-Id: I8b31c7ce366f383dfcc2f6e850b76a83340a02a1
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406642
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Since PD task are highest priority, the 50msec delay between was intended
allow other tasks to execute if PD has continuous interrupt. With two
separate TCPC handled by host_command_pd task, interrupt from one TCPC will
block the interrupt handling of another TCPC by this 50msec and cause
error in the PD negotiation.
Reduced to 5msec to ensure TCPC interrupt is handled as soon as possible
while allow other tasks to execute if needed.
BUG=chrome-os-partner:59061
BRANCH=none
TEST=Verify zinger can negotiate to 20V, hoho can get display. Also tested
with faking PD interrupt always asserted to check for watchdog reset.
Change-Id: I9b71277a3d65923f1f5bbfd744b3399e34fd0e6c
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407542
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This change is a safegaurd to ensure that TPM register data is always
placed in the correct location in the HW read I2CS fifo. It is only
checked for 1 or 4 byte regsiter reads. Because of the way in which a
TPM command is sent and the response is read, there are multiple reads
of the STS register prior to reading the TPM fifo register. Therefore
ensuring the fifo has zero depth when 1 or 4 byte regsiter reads,
improves the robustness of the design.
Added a counter to track the number of times the fifo is adjusted and
a new console command 'i2cs disp|rst' to display the count and reset
it to 0 if desired.
Removed section in code for TPM fifo register reads intended to handle
the case where there was a mismatch between how many bytes were copied
into the fifo and the number read by the host. Since the burstcount
field in the status register always contains a valid amount of data
that can be read by the host, there should not be cases where the
host reads less data than was copied from the TPM fifo register. In
the unexpected cases where the host may not drain all of the I2CS read
fifo data during a TPM register read, the I2CS fifo depth will be
corrected the next time that it reads either the access or STS
register which happens prior to the start of any TPM transaction.
BRANCH=none
BUG=chrome-os-partner:57338,chrome-os-partner:59191
TEST=manual
Booted Reef and verfied that TPM functionality is working.
Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382689
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The jittery clock and trng security features require high permissions to
be initialized. In the future these initializations and the permission
level drop may be moved to RO.
This change adds permission level checks before trying to access any
registers that require high permission, so when we update RO to change
the permission RW can still function fine.
BUG=chrome-os-partner:59107
BRANCH=none
TEST=Move the permission drop to the beginning of main and verify the
system still boots.
Change-Id: I5b7cb856decd0640288ad3476f875ec9edc42635
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405840
Don't queue non-wake events, and ensure wake events (and all subsequent
events) always get queued.
BUG=chrome-os-partner:59248, chrome-os-partner:59336
BRANCH=gru
TEST=Manual on kevin, go to suspend, press volume keys dozens of times,
press 'shift', verify device wakes. Place cursor on URL bar, go to
suspend, type "google" quickly, verify device wakes and "google" appears
on URL bar. Go to suspend, press 'VolUp' key 5 times, press keyboard,
verify device wakes and no volume meter is seen on display.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibe761187fbcefd686776a512786550970a6fc067
Reviewed-on: https://chromium-review.googlesource.com/405717
Commit-Queue: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit aa2f01566314604404e104d7975c6c755c22a601)
Reviewed-on: https://chromium-review.googlesource.com/407958
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Previously the memmap'd host event mask copy wasn't always updated. Be
consistent with other mkbp code and call host_get_event() to get our
current mask.
BUG=chrome-os-partner:59241
BRANCH=gru
TEST=Manual on kevin, close lid to suspend, press volume keys, verify
device doesn't wake. Open lid, verify device wakes. Run
'powerd_dbus_suspend', press volume keys, verify device doesn't wake.
Press keyboard key, verify device wakes.
Change-Id: I3de49efa1ebc53a9c56bed57007c48356c7e97bb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406547
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 763d3b2c6f26d41e7147f860e59755af2fe87fe4)
Reviewed-on: https://chromium-review.googlesource.com/407957
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This patch adds the initial support for ISH chip to enable the EC
firmware to boot on Intel Integrated Sensor Hub (ISH). The following are
enabled:
1. Inter-Processor Communication (IPC) driver that enables the ISH to
communicate with the host Operating system via shared registers.
2. High Precision Event Timer (HPET) driver that provides configurable
timers for the FW to use in task scheduling.
3. I2C bus driver for accessing sensors.
4. UART console driver with TX support only.
BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`
Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336710
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Jaiber J John <jaiber.j.john@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Jaiber J John <jaiber.j.john@intel.com>
Reviewed-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Let sensor be powered on in S3. It is useful for Android and if we want to
disable keyboard wakeup based on lid angle.
Allow EC to disable touchpad and not send keyboard events when lid angle
is greater than 180.
BUG=chrome-os-partner:57510,chromium:620633
BRANCH=gru
TEST=In S3, check the sensors are readable.
Check that when in S3 and lid angle is < 180 EC sends keyboard events.
Check that when in S3 and lid angle is > 180 EC does not send keyboard
events.
Change-Id: I4e7959ed37bc5dfdf9c105ecae94c314b253d77f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406739
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We previously used binary extended Euclid. That does not perform well
when inverting a small public exponent.
We also abused that routine to perform the division of n by one of its
factors. Really did not perform well there either.
This CL introduces a classic Knuth long division and a normal extended
Euclid based on that.
This drops the execution time of the common inversions into the single
msec range (vs. multiple seconds before..)
TEST=tcg_tests pass the usual 381/391; test/tpm_test/bn_test passes.
BUG=chrome-os-partner:57422
BRANCH=none
Change-Id: Ic9b4aecd0356fcab3e823dbd60c5b228a87447d3
Reviewed-on: https://chromium-review.googlesource.com/406940
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In the current implementation, it's hard to tell
when led turns from amber to green.
BUG=chrome-os-partner:57079
BRANCH=None
TEST=Verify LED is green when charging w/ nearly full battery.
Also verify LED control host commands work as expected:
ectool led battery green=1 // green
ectool led battery amber=1 // amber
ectool led battery red=1 // red
ectool led battery red=0 // off
Change-Id: Ie18162fd1608a0548e25472faeca026f1995fc8d
Reviewed-on: https://chromium-review.googlesource.com/406471
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This combines stm32 and chip/g usb_i2c interfaces so they
will not diverge. Note that this fixes the chip/g implementation
to use 8-bit i2c addresses.
BUG=chrome-os-partner:57059
BRANCH=none
TEST=servod interacts with servo_micro and servo_v4
Change-Id: Ibff217d84b132556202c8a71e3d42c07d546c634
Reviewed-on: https://chromium-review.googlesource.com/405108
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
BUG=chrome-os-partner:54668
BRANCH=none
TEST=Verified SNK is detected in S0 (toggle on), S3 (toggle off),
and S5 (force sink). SRC is detect in S0 only, stays detected when
entered S3, but unplug/plug while in S3 will not re-detect until
system back in S0. When go to S5, SRC will get disconnected until
back in S0, and hotplug SRC in S5 will not get detected. Checked
power role swap with another chromebook in the above scenario also.
Change-Id: I2a487fca5cb04c45524aa3efde84fcd10ff0579e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The i2c_xfer API assumes it's getting an 8 bit slave address, but the
driver was assuming a 7 bit slave address was being passed in. Fixed
the location where this is used to shift it back to 7 bits.
BRANCH=none
BUG=chrome-os-partner:57059
TEST=manual
Cr50 console 'ccd i2c on' then
> i2cxfer r16 0 0x40 0
Unknown error
Usage: i2cxfer r/r16/rlen/w/w16 port addr offset [value | len]
> i2cxfer r16 0 0x80 0
0x2771 [10097]
Shows that it's now assuming an 8 bit address
Change-Id: I791b7c136a741856749c281dd4c8166b5cf97ef9
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405780
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Take into account the rotation matrix to do calibration.
In particular the Z axis: if board is upside down, we need to use
MINUS_1G instead of PLUS_1G when setting online calibration.
BRANCH=kevin
BUG=none
TEST=Before, calibration would not work on the Z axis.
Change-Id: Ifaec331aac40a4be0e34fcab5dd3752d2d59b91f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405854
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
sweetberry takes a bit longer to erase flash and seems to be timing
out. This fix gets sweetberry to update reliably.
BUG=chromium:608039
TEST=update sweetberry firmware
BRANCH=None
Change-Id: I9a0cbeae3b7ce0e4b87840fe8bf24bb2e10777e9
Reviewed-on: https://chromium-review.googlesource.com/404710
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
