EC-3PO is the console interpreter that will one day replace the EC console
that we have today. EC-3PO aims to migrate our rich debug console from
the EC itself to the host. This allows us to maintain our rich debug
console without impacting our EC image sizes while also allowing us to
add new features.
This commit is the 1st of three phases, the insertion phase. The main
goal of this insertion phase is to get EC-3PO in place between servo and
the EC UART, while not modifying the behaviour of the console too
much. At this point, EC-3PO is capable of the following things:
- Replicate command editing.
- Save command history.
- Performs error checking with console commands.
The command editing should be at parity with the current EC console.
With EC-3PO, one can have a much longer command history which also
persists across EC reboots. And lastly, with a cooperating EC image,
EC-3PO can perform error checking with console commands. Automatically
retrying console commands if the command was incorrectly received at the
EC end.
Currently, commands are sent to the EC in a "packed" plaintext form.
The next phase will introduce the host command packet communication.
console.py is the module that provides the console interface between the
user and the interpreter. It handles the presentation of the console
including command editing.
It also has an accompanying set of unit tests in console_unittest.py.
It currently has 1 test suite to test the various console editing
methods.
interpreter.py is the module that provides the interpretation layer
between the EC and the user. It also is responsible for the automatic
command retrying. It requires pipe connections to be made to it for
command and debug data communication.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=util/ec3po/console_unittest.py
TEST=Flash GLaDOS with a modified EC build. Run console.py passing the
EC UART, verify that I can edit commands, send commands, view command
history, and receive output from the EC.
TEST=cros lint --log-level debug ./util/ec3po/console.py
TEST=cros lint --log-level debug ./util/ec3po/interpreter.py
TEST=cros lint --log-level debug ./util/ec3po/console_unittest.py
Change-Id: I38ae425836efd69044334e1ed0daf3f88a95917c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/308615
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Add support for flash the ite ec from usb gpio port
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
BRANCH=none
BUG=none
TEST=Test OK on ITE8390CX from both GPIO PORT (C1,C2) (H5,H6)
You can run "make -j BOARD=it8380dev" to build ec.bin
and flash the ec.bin via
"sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin"
/* ==SNAPSHOT START== */
(cr) (br-iteflash) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin
Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB
Done.
CHIPID 8390, CHIPVER 82, Flash size 256 kB
Erasing chip...
/100%
Writing 262144 bytes at 0x00000000
Done.
/* ==SNAPSHOT END== */
Change-Id: I422db6f7007622f8be624a534a482e24d53a061a
Reviewed-on: https://chromium-review.googlesource.com/311205
Commit-Ready: Donald Huang <donald.huang@ite.com.tw>
Tested-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Donald Huang <donald.huang@ite.com.tw>
The signer running on the build host and the loader running on the
target must be in sync as of the structure of the signature header.
To be able to use the same definition in both programs, remove the
system includes from the .h file which needs to be shared. Rearrange
includes in image.cc to follow the coding conventions.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applied the code successfully boots,
which indicates that the signer is in fact working properly. (See
the top patch for testing details).
Change-Id: I6bc9c57ebea55ac256fcdac8338c5566f16b6371
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311420
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This key is meant to be used by the RO image when verifying the RW.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches in place (in particular, this key's
public counterpart used in chip/g/load/verify.c), the RW is
successfully verified by RO.
Change-Id: Iddcc21d88518e402da614d20d913aeed162b0042
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311315
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When signer code was ported and enhanced to work with binaries (in
addition to hex), a bug was introduced, where the signed image is
considered to always to be based at the bottom of the flash. In fact
the image could be anywhere in the flash, the actual address derived
from the input elf file should be used.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that when enabled, RW image is signed properly
(build/cr50/RW/ec.RW.flat starts with a signature).
Change-Id: I194bd02f932529165adcbebf4bcbd9020fc261dc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311314
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Register descriptions generate by the hardware tools always use the
block index when naming the base address of the bock, but the macros
compiling addresses out of register names do not use the index if
there is just one instance of the block in the design.
The problem is addresses by aliasing these definitions in registers.h
in the chip directory. This patch automates this aliasing and ensures
that the generated file has the aliases included, no need to add them
manually to registers.h.
BRANCH=none
BUG=none
TEST=re-generated cr50_regs.h, observed proper aliases created, built
and ran cr50 with the new registers file.
Change-Id: If037e082841a1510f7cad66737fd8b775dc667ea
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311371
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In fact this provides support for three FPGA images:
20151104_011218 - full crypto, no USB
20151104_041733 - tiny crypto, full USB
20151104_065845 - full crypto, full USB (only for hard-to-get boards)
We can tell these FPGA images apart at run-time by looking at
some SWDP registers:
register crypto usb full
GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135
GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3
This CL includes a run-time check for the USB features so that
it's safe to build the firmware with CONFIG_USB and run it on a
non-USB FPGA image.
Here are the differences I could find in the top-level image
header files:
All three FPGA images define different (apparently arbitrary)
default values for the PMU_PWRDN_SCRATCHn registers, but other
than that, the usb and full images differ only in the BUILD_TIME
and FPGA_CONFIG register values.
I'm not sure why, but function uart_init() in file
chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn
registers, but nothing seems to read it again.
The crypto image defines these values which don't appear in the
other images:
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52
#define PINMUX_USB0_EXT_RX_DMI_SEL 0x53
#define PINMUX_USB0_EXT_RX_DPI_SEL 0x54
#define PINMUX_USB0_EXT_RX_RCV_SEL 0x55
#define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56
#define PINMUX_USB0_EXT_TX_DMO_SEL 0x57
#define PINMUX_USB0_EXT_TX_DPO_SEL 0x58
#define PINMUX_USB0_EXT_TX_OEB_SEL 0x59
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240
#define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244
#define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248
#define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c
#define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250
#define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254
#define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258
#define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0
The crypto image also differs in this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c
instead of this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230
The rest of the differences between the crypto and usb versions
are in these values, which I don't think we care about. At least,
I can't find any place where they're used.
PINMUX_EXITEDGE0_DIOAn_OFFSET
PINMUX_EXITEDGE0_DIOBn_OFFSET
PINMUX_EXITEDGE0_DIOMn_OFFSET
PINMUX_EXITEDGE0_VIOn_OFFSET
PINMUX_EXITEDGE0_OFFSET
PINMUX_EXITEN0_DIOAn_OFFSET
PINMUX_EXITEN0_DIOBn_OFFSET
PINMUX_EXITEN0_DIOMn_OFFSET
PINMUX_EXITEN0_VIOn_OFFSET
PINMUX_EXITEN0_OFFSET
PINMUX_EXITINV0_DIOAn_OFFSET
PINMUX_EXITINV0_DIOBn_OFFSET
PINMUX_EXITINV0_DIOMn_OFFSET
PINMUX_EXITINV0_VIOn_OFFSET
PINMUX_EXITINV0_OFFSET
PINMUX_HOLD_OFFSET
PINMUX_SEL_COUNT
PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET
PINMUX_XO0_TESTBUSn_SEL
PINMUX_XO0_TESTBUSn_SEL_OFFSET
I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h
BRANCH=none
BUG=chrome-os-partner:43791
CQ-DEPEND=CL:310978
TEST=make buildall
I also built a single Cr50 firmware and tried it on both the
crypto and usb FPGA images. Both worked as expected.
Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311211
Add support for two new configs to specify critical energy battery
percentage and critical external charger power. When we are under both
thresholds, set the LIMIT_POWER charger parameter to inform the AP that it
should conserve power to avoid brownout, and consider jumping to EC RW
to negotiate PD.
In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
to allow power-up regardless of power level if a 15W+ charger is
attached, since there is a reasonable chance it may speak PD and provide
sufficient power to boot the AP.
BUG=chromium:537269
TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify
that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also
veify that system can boot with Donette.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad
Reviewed-on: https://chromium-review.googlesource.com/306774
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add chell_pd to the STM32 list and the USBPD override list.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=successfully run "flash_ec --board=chell_pd"
Change-Id: Ic4ddbe51a0586c563211fd76f20a85428e565546
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308726
Reviewed-by: Shawn N <shawnn@chromium.org>
FAFT and the lab infra calls the flash_ec by giving the chip name as
an argument, instead of the board name. The script should use the
chip name to check if it is a stm32 board.
BUG=chromium:546063
BRANCH=none
TEST=Call the script: flash_ec --chip stm32 --image /tmp/ec.bin
Change-Id: I8e9a029fb6e0aca5ea0f65876f48f6f465664c1c
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/307822
Commit-Ready: Wai-Hong Tam <waihong@chromium.org>
Tested-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This enables support for a new FPGA image with tighter timing
constraints. Some USB functions perform better using this model.
There are also changes to the signing code.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall
Change-Id: I608c2424d76b4ea566bf56fa0fed3810436216bb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308063
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We've been converting the FPGA headers to our headers using a
script that we've passed around via email. Let's check it in so
we don't diverge.
BUG=none
BRANCH=none
TEST=manual
Run ./util/cr50_regs on the latest FPGA header, compare the
output with chip/g/cr50_fpga_regdefs.h. They match.
Change-Id: I6b435755a047265ea91d1af4e3e753e7555d149d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/306290
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch updates the EC codebase to match the suggested USB
build. The spiflash utility must come from the same tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
boot_rom 20151012_041715@75660
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I4e21151d03d1050999ea2045b2be4b99886ff15c
Reviewed-on: https://chromium-review.googlesource.com/305260
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This patch updates the EC codebase to match the suggested USB
build. The spiflash utility must come from the same tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from:
BootRom 20151007_064811@75052
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Iccd8f202493951f803393395273caa83467655df
Reviewed-on: https://chromium-review.googlesource.com/304622
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch updates the EC codebase to match the suggested USB build
(20151005_041713). The spiflash utility must come from the same
tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version.
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Change-Id: Iff778087149ae3e7570f8fd4d81c2857a4ea5367
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/304123
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This patch brings in the enhanced signer utility published along with
FPGA version 20150925_21715, and the image.cc file updated to fix the
bug where it was not picking up the initialized data segment from the
elf file.
The new signed image header format, among other things, describes
memory areas as read-only and read-execute, which allows the bootrom
to configure the MMU appropriately.
Makefiles had to be modified to reflect the fact that the signed image
now depends on .elf, not on .raw, and that building the signer
requires more source files. Note that some signer features are not yet
being utilized (like processing xml files describing fuses or
retrieving keys from gnubby), the source are kept for completeness.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=build the cr50 image and boot in on the FPGA board using the
spiflash utility outside chroot. Observe the target starting the
console session.
Change-Id: Ib59b8ebbeb98a8146d4d997e1f78178c4fbc031a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303070
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This commit adds the "hibdelay" command which will set the time before
the EC hibernates.
BUG=chrome-os-partner:45608
BUG=chrome-os-partner:44831
BRANCH=None
TEST=Build and flash samus EC with hibernation delay host command
added. Use ectool to set the hibernation delay and verify that the
hibernation delay was changed.
CQ-DEPEND=302197
Change-Id: I91141ee48a648c1052f0a3930a810ea4f551e0a4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302198
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For signed EC RW images (CONFIG_RWSIG), there's no point in
embedding the public key or signature into the image itself since
it will just be replaced by the signer (either as the next step
in the build process, or after the fact for MP releases). This
takes that out and just points to where the pubkey and signature
will be placed.
BUG=none
BRANCH=none
TEST=make buildall
I also checked the signatures with
futility show -t build/*/ec.bin
They still look good, and the one signed image I booted (Cr50)
works as before.
Change-Id: Ib39b7c508914851f81a1bebb2450e08ef0def76c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302630
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have been using the time of compilation to determine the
version string. This CL will keep doing that if the git repo has
uncommitted changes, but if the repo is clean we'll just use the
author date of the last commit. This ensures that the same source
will produce bitwise-identical builds (assuming no toolchain
changes, of course).
BUG=chrome-os-partner:45616
BRANCH=none
TEST=manual
cd src/platform/ec
make buildall
mv build build.one
make buildall
md5sum build{,.one}/*/ec.bin | sort
Observe that successive builds produce identical binaries.
Change-Id: Ie2ef44b216586097589c9c15f12e05c87a53f991
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302140
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Make sure to restore boot_mode gpio for all MCUs. Previously,
only usbpd_boot_mode was restored, but not ec_boot_mode which
is used on lucid.
BUG=none
BRANCH=none
TEST=flashed lucid (ec_boot_mode), glados_pd (usbpd_boot_mode),
and zinger (boot_mode) and verified that the boot_mode gpio was
restored to off at the end of flashing.
Change-Id: Ib6fcddcac6d00465e31a0e710bae3b8318bac659
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301338
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Allow the host to enable/disable double tap.
Send event when double tap is present.
Also fix a bug when scanning for gestures.
BRANCH=smaug
BUG=chrome-os-partner:44754
TEST=compile. Check on Ryu.
Change-Id: I50d008cd3823072ab1c1e2d21f1276cd2185d797
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/298683
Add more flags to EC_CMD_USB_PD_CONTROL including whether
the port partner is PD capable, and if the port partner has
any of the following flags set in its capabilities: dual-role
power, dual-role data, USB comms capable, and externally
powered.
BUG=none
BRANCH=smaug
TEST=tested on samus using 'ectool --dev=1 usbpd 0'. Tested
with zinger, guppy, another samus, and other third party
devices to verify the flags are set as advertised in src/snk
capabilities packet
Change-Id: I4d78d1880073fdacce57516111ac6cab37b93f27
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300953
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add an interface with the host to set up gesture recognition.
Today, only significant motion is supported.
Add a virtual sensor for concentrating gesture support from host.
BRANCH=smaug
BUG=b:23570481
TEST=On ryu, enable significant motion from host.
Change-Id: I906fa2d2d7b4ca2771ea2f58b91de8d97bf4e2e3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296213
When this script is searching through CONFIG_* options used in the repo,
it should ignore hidden files. I uncovered this by accidentally having
modified a file and the presubmit hook failed. This is because emacs
auto-saves files with the format ".#filename.ext". Now, the script will
ignore hidden files.
BUG=None
BRANCH=None
TEST=Use emacs to modify a c file but not save it. Run the script and
verify that no errors occur.
TEST=make -j buildall tests
Change-Id: Ie09cfcf66f2e416aeed99847945cb5168b457d1a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/300954
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit makes all prints with the TERR error level print to standard
error so that it's more obvious what's wrong when an error occurs.
BUG=None
BRANCH=None
TEST=Checkout tree @ 5dfe8d2. Build npcx_evb and see that the error is
displayed during the build process.
TEST=make buildall tests
Change-Id: I4117dd83a9a85ae81baf533302b0b70f4da174bc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/300613
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ectool is only sending payload. kernel is adding header for v3 commands.
(length, crc, ...)
Put back the header I previously deleted in cl:274086
BRANCH=ryu
BUG=chrome-os-partner:45304
TEST=ectool flashwrite now works.
Change-Id: I40fa30bc477a090261048eb51b382483f28d4ab1
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/300024
Reviewed-by: Shawn N <shawnn@chromium.org>
Add all swap commands to USB_PD_CONTROL host command: data,
power, and vconn swap.
BUG=none
BRANCH=smaug
TEST=tested on both samus and ryu while connected to each other.
Change-Id: I280a0da2d3c5a5436243134ab3f2ec353ebf6ab8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299290
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit enhances the config_option_check.py script a little bit
more.
Firstly, I fixed a bug where lines beginning with an '*' were treated as a
comment where it was not so.
ex: *status = (CONFIG_BAR_PORT & 0x23);
Additionally, I added support for considering deletions. This allows
the script to check to see if a CONFIG_* option being removed is being
used anywhere else in the repo. If the option isn't used elsewhere,
then it appears to be the removal of the last use. An error is flagged
informing the user to remove that option from the main config file.
This helps to keep the config file up to date without leaving stale
CONFIG_* options where one might not know if they still work or not.
Debug config options are always assumed to be used as those are
typically enabled locally.
BUG=chromium:510672
BRANCH=None
TEST=Used a new config option without adding it to the main config file
and watched the error be flagged.
TEST=Removed the last use of a CONFIG_* option while leaving the option
in the main config file. Observed that it was flagged.
TEST=cros lint --debug util/config_option_check.py
TEST=make -j buildall tests
Change-Id: I8702ad06d9856c14f7bcd4592e917a5d3fcb6b57
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/294620
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
The signer utility needs to be built and the flat image needs to be
signed. The signer utility is written in C++, supporting this required
adding a new make command to Makefile.rules and a build file for the
utility.
The signing now needs to be a part of generating the .flat file. To
achieve this an alternative set of rules is defined in Makfile.rules
for targets where RO image needs to be signed.
Rules for converting elf to hex have been consolidated as there is no
need to omit the --set-section-flags when it does not apply.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=as follows:
- ran 'rm build/cr50; make BOARD=cr50'
- observed that both build/cr50/ec.bin and
build/cr50/RO/ec.RO.flat have the required signature header in
the first 1024 bytes.
- verified that the cr50 board can be booted over SPI using the
image in build/cr50/RO/ec.RO.flat
Change-Id: Iacc22561de67fadfaf8e049bf9578cbd08cfad86
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295291
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This utility reads a binary file, verifies that the first 1024 bytes
of the file are set to zero and replaces this block with a header,
containing the signature and other information required by the recent
CR50 ROM.
A test private key is included, it matches the FPGA ROM public key.
The use convention is simple: two parameters are required, the private
key file name and the binary file name. The signed binary file is saved
in the file with extension ".signed".
BRANCH=none
BUG=chrome-os-partner:43025
TEST=the utility builds using
g++ -std=c++0x -I . -o signer codesigner.cc publickey.cc -lcrypto
ec.RO.flat signed with this utility can be successfully bootstrapped
a CR50 over SPS
Change-Id: I046b13d20f0dd8cff884e37ef966593e01dcb043
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295208
Reviewed-by: Marius Schilder <mschilder@chromium.org>
PD charger voltage + current can now be limited with
EC_CMD_EXTERNAL_POWER_LIMIT. The limit is automatically cleared when the
AP transitions out of S0 into S3 / suspend.
BUG=chrome-os-partner:43285
TEST=Manual on Samus w/ zinger.
- Plug zinger, verify charging at 20V/3A.
- `ectool extpwrlimit 3000 12000 --dev=1`, verify charging at 12V/3A
- `ectool extpwrlimit 1000 5000 --dev=1`, verify charging at 5V/1A
- Plug zinger into other port, verify still charging at 5V/1A
- `powerd_dbus_suspend`, verify charging at 20V/3A
- `chglim 2000 12000`, verify charging at 12V/2A
- `ectool extpwrlimit 0xffff 0xffff --dev=1`, verify charging at 20V/3A
- `chglim 1000 20000`, verify charging at 20V/1A
- `chglim`, verify charging at 20V/3A
BRANCH=ryu
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6cd5377be91b3df75f99cb414fd3fa5a463b56cb
Reviewed-on: https://chromium-review.googlesource.com/293954
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fixed bug during polling port 0x204 by BIOS.
We should set processing flag before reading command byte in ISR to prevent
EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low.
Modified drivers:
1. gpio.c: Add LRESET ISR.
2. lpc.c: Fixed bug during polling port 0x204 by BIOS.
3. flash_ec: Reset ec before flashing ec
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/291210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
The flash_ec script is called by the lab infrastructure to flash
the EC firmware of DUT. To prevent the EC flashing tool hanged
forever (may be caused by some bugs), set a 10-minute timeout to
force it to be killed.
BRANCH=none
BUG=chromium:514810
TEST=Patched the change to servo v3. Triggered flash_ec to flash EC
on Jerry. Set the timeout to a small value to force to kill itself.
test2:
./flash_ec --board=hadoken # or samus, anything using openocd
remove the USB cable half way through (openocd hangs)
ps au | grep openocd
Change-Id: I39ad8659b41764fd0dba30a86eca301fbbc5243f
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289247
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Jerry is being used for FAFT in the lab. Remove Pinky instead.
BUG=chromium:511324
TEST=make buildall -j
BRANCH=none0
CQ-DEPEND=CL:288258
Change-Id: I03ddc74a4e72353f3408da8e374ad925baf00a35
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288237
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
This commit enhances the config option check python script to
significantly reduce the number of false positives.
- Now only checks committed changes.
- Only checks additions, not the whole file.
- Only checks uses of CONFIG_* not in a comment for both C-style and
Make-style files.
- Suports a whitelist.
BUG=chromium:510672
BRANCH=None
TEST=Detected missing configs in Makefiles and C source files.
TEST=/* CONFIG_FOO */ was not detected.
TEST=' board-$(CONFIG_OPT)=board.o # CONFIG_OPT2' only CONFIG_OPT was
detected.
TEST=Changes in working dir were not detected.
TEST=Changes to config_option_check.py were not detected.
TEST=cros lint --debug util/config_option_check.py
TEST=CONFIG_FOO in a multi-line C comment was not detected.
Change-Id: I5fc2ccc77bb4f319a3c85b7d81c83027959dc96b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/287519
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
The flash_ec uses the given board name to select a proper flashing
method. It keeps a mapping from board name to chip name.
This approach is not scalable if we want this script to work on
all supported board variants, like the pinky family which has many
boards: jerry, minnie, speedy, etc.
This change adds a new argument of chip name, such that we can only
keep the mapping of major boards. Other boards not listed can use
the chip argument to select a proper flashing method.
BRANCH=none
BUG=chromium:505003
TEST=Ran the script on Beaglebone/Servo v3 connected with Jerry:
$ flash_ec --chip stm32 --image ec.bin
Change-Id: I553ee68f82a7985a37548dfb6e89b364eaffd0f1
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287445
Reviewed-by: Dan Shi <dshi@chromium.org>
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Remove ryu_p4p5 EC board code along the "splitted" Sensor hub board
(ryu_sh/ryu_sh_loader): It's time to get rid of oldies.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:38333
TEST=make buildall
CQ-DEPEND=*I6df51d7b4be2be7217604da60462b8c9d0cde1d2
Change-Id: Iebc4022267afccb5057c856d624e56a850ecbd70
Reviewed-on: https://chromium-review.googlesource.com/286780
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
As of now this check results in false positives, for instance
'CONFIG_' found in the comments results in an error report.
This patch makes the script a bit more robust:
- consider only those options mentioned in include/config.h as
explicitly defined or undefined.
- do not scan include/config.h for new added CONFIG_ options
- ignore comments in .mk files
Ideally the script should be scanning only added lines of code and
much smarter about what should be considered a comment and what files
should be examined.
BRANCH=none
BUG=chromium:510672
TEST=the false positives triggered by comments in various build.mk
files are gone now. Adding an undescribed CONFIG_xxx text still
triggers the error.
Change-Id: Ib9858775bcd9899dec629682a1c7965e7c2fec96
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285926
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
