EC-3PO is the console interpreter that will one day replace the EC console
that we have today. EC-3PO aims to migrate our rich debug console from
the EC itself to the host. This allows us to maintain our rich debug
console without impacting our EC image sizes while also allowing us to
add new features.
This commit is the 1st of three phases, the insertion phase. The main
goal of this insertion phase is to get EC-3PO in place between servo and
the EC UART, while not modifying the behaviour of the console too
much. At this point, EC-3PO is capable of the following things:
- Replicate command editing.
- Save command history.
- Performs error checking with console commands.
The command editing should be at parity with the current EC console.
With EC-3PO, one can have a much longer command history which also
persists across EC reboots. And lastly, with a cooperating EC image,
EC-3PO can perform error checking with console commands. Automatically
retrying console commands if the command was incorrectly received at the
EC end.
Currently, commands are sent to the EC in a "packed" plaintext form.
The next phase will introduce the host command packet communication.
console.py is the module that provides the console interface between the
user and the interpreter. It handles the presentation of the console
including command editing.
It also has an accompanying set of unit tests in console_unittest.py.
It currently has 1 test suite to test the various console editing
methods.
interpreter.py is the module that provides the interpretation layer
between the EC and the user. It also is responsible for the automatic
command retrying. It requires pipe connections to be made to it for
command and debug data communication.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=util/ec3po/console_unittest.py
TEST=Flash GLaDOS with a modified EC build. Run console.py passing the
EC UART, verify that I can edit commands, send commands, view command
history, and receive output from the EC.
TEST=cros lint --log-level debug ./util/ec3po/console.py
TEST=cros lint --log-level debug ./util/ec3po/interpreter.py
TEST=cros lint --log-level debug ./util/ec3po/console_unittest.py
Change-Id: I38ae425836efd69044334e1ed0daf3f88a95917c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/308615
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Fix bug with the new VBUS_NEVER_LOW flag in which if a BC1.2 charger
is attached on boot, we will not set the charger as a dedicated
charger and therefore not charge from it, until the charger is
disconnected and reconnected. This happens because in SNK_DISCOVERY
we will send soft reset first, and then when the charger doesn't
respond, we send hard reset. But, registering the charger as a
dedicated charger previously only happened when we send hard reset
directly after SNK_DISCOVERY state.
BUG=none
BRANCH=none
TEST=tested on glados. sysjump with bc1.2 charger plugged in and make
sure we charge from it.
Change-Id: Ida89304092a2186bcb2aa885917d706231490288
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311364
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When SPI CS is deasserted, SPI MISO is floating, which leads to leakage.
BUG=chrome-os-partner:42104
BRANCH=None
TEST=Manual on glados. Verify S5 power drops by ~1.5mW and sysjump / EC
RW hashing continues to function.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0ba8fcab1618f396adc32984da93e37c5ff770a4
Reviewed-on: https://chromium-review.googlesource.com/311821
Commit-Ready: Shawn N <shawnn@gmail.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Re-order logic in BC1.2 detection task so that we open the
USB switches immediately upon detecting a connection, then
debounce the connection, then reset the pericom and determine
BC1.2 charger type.
This fixes two problems:
- Problem where host could enumerate dut, detect disconnect,
and then re-enumerate.
- Problem where sometimes dut would detect a host workstation
as a proprietary charger because we weren't delaying long
enough after opening USB switches before triggering pericom
reset.
BUG=chrome-os-partner:47219
BRANCH=smaug
TEST=tested by connecting workstation to ryu (tested both
pluggin in A side first and C side first). Without this patch,
my workstation often see's disconnect and reconnect. With
this change we only get one connect.
Change-Id: I07cc3473ff32953fad3cc6d1db01b86b44969c4e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311804
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable the option to reset the EC when the PD panics.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=verify that if PD is in RW and reboots then the EC
will panic and print "PD crash".
Change-Id: I69ab08914aef08b5ef0eaa447c142444113c526c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311308
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Until we update the naming for our various images in the
Makefiles, let's change the bootloader message slighty, so that
instead of seeing two "RO" images:
CR50 RO, 20151104_41733@78962
Valid image found at 0x00044000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv.
corp.google.com]
[0.000897 Verifying RW image...]
we see the bootloader, and then what we've been calling the RO
image, and then the RW image:
cr50 bootloader, 20151104_41733@78962
Valid image found at 0x00044000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv.
corp.google.com]
[0.000897 Verifying RW image...]
BUG=none
BRANCH=none
TEST=make buildall, try it
No new functionality, just a different message on the console.
Change-Id: Ia8dce600c7d159416dc6dabbbf0c0cc4129a988d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311831
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We were just checking to see if the UART TX unit was idle. We
also need to be sure there aren't any bytes in the TX FIFO that
haven't been clocked out yet.
BUG=none
BRANCH=none
TEST=make buildall, manual
Before, "crash watchdog" would truncate the trace dump as it
rebooted. Now it doesn't.
Change-Id: Icff828445801ce61a0a8f296b3d3e9fb300b7efc
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311299
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When we lower the runlevel for security purposes, the standard
ARM watchdog interrupt is no longer enough to cause a full
reboot. We'll manually trigger a system reset instead. For now,
it's a soft reset. Should it be hard?
BUG=chrome-os-partner:47289
BRANCH=none
CQ-DEPEND=CL:310975
TEST=make buildall, manual
From the console, run "crash watchdog". After a second or to,
the watchdog trace dump appears and the system reboots.
Change-Id: I99fcaf19b32728563e3b051755d65267cc11156c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311298
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Add support for flash the ite ec from usb gpio port
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
BRANCH=none
BUG=none
TEST=Test OK on ITE8390CX from both GPIO PORT (C1,C2) (H5,H6)
You can run "make -j BOARD=it8380dev" to build ec.bin
and flash the ec.bin via
"sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin"
/* ==SNAPSHOT START== */
(cr) (br-iteflash) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin
Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB
Done.
CHIPID 8390, CHIPVER 82, Flash size 256 kB
Erasing chip...
/100%
Writing 262144 bytes at 0x00000000
Done.
/* ==SNAPSHOT END== */
Change-Id: I422db6f7007622f8be624a534a482e24d53a061a
Reviewed-on: https://chromium-review.googlesource.com/311205
Commit-Ready: Donald Huang <donald.huang@ite.com.tw>
Tested-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Donald Huang <donald.huang@ite.com.tw>
This patch completes introduction of building of proper RO and RW
images for cr50.
A few small mods were required:
- both RO and RW images have to be signed, using the same dedicated
signer, but with different keys, dev_key.pem is not needed any more.
- the RW image offset is not at the half of available flash, a chip
specific value of 16K is used instead.
The suggested new image layout is as follows:
+----------------------------------------+
| 1KB RO signature header. |
+----------------------------------------+
- -
| 15KB RO image. |
- -
+========================================+
| 1KB RW-A signature header. |
+----------------------------------------+
- -
- -
| 239K RW-A image. |
- -
- -
+========================================+
- -
| 16 KB NVRAM, shared |
- -
+========================================+
| 1KB RW-B signature header. |
+----------------------------------------+
- -
- -
| 239K RW-B image. |
- -
- -
+========================================+
BRANCH=none
BUG=chrome-os-partner:43025
TEST=The combined image (build/cr50/ec.hex) is successfully loaded and
started by the spiflash utility from the latest FPGA tarball.
Corrupting a byte in the generated image in the RW section causes
failure to verify.
Change-Id: I41a05168b0d4e9f88efa1003f261b6dd03972a24
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311422
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
With the proper RO in place, RW must be signed in the same manner, as
RO. This patch makes sure that there is room in the RW header for the
signature.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applies the RO successfully boots up
the RW.
Change-Id: I1538195e0181c23c874ddd300887cf5da8c5a867
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311421
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This code is a port of the sample loader application included in the
FPGA update. Only the pieces relevant to straight verification and
boot were ported.
The loader generates a hash, inputs to which are the image body, state
of fuses and state of flash INFO region, and the output is the value,
which will unlock the region for execution, if it is correct.
Only one image load is attempted, the image is supposed to be located
in the flash at the offset of CONFIG_RW_MEM_OFF.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applied the RO image successfully
verifies and starts up the RW image.
Change-Id: I26e1fbdaeb8b23d519c1a328526a3422231bb322
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311316
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The values are there, we just need to be able to access them from the
code to be able to calculate how much of the flash space needs to be
made accessible for the image to run.
BRANCH=none
BUG=none
TEST=used by later patches
Change-Id: I4eb59525a50177cc7cc725871c3eab2ff390667b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311319
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The signer running on the build host and the loader running on the
target must be in sync as of the structure of the signature header.
To be able to use the same definition in both programs, remove the
system includes from the .h file which needs to be shared. Rearrange
includes in image.cc to follow the coding conventions.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applied the code successfully boots,
which indicates that the signer is in fact working properly. (See
the top patch for testing details).
Change-Id: I6bc9c57ebea55ac256fcdac8338c5566f16b6371
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311420
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This key is meant to be used by the RO image when verifying the RW.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches in place (in particular, this key's
public counterpart used in chip/g/load/verify.c), the RW is
successfully verified by RO.
Change-Id: Iddcc21d88518e402da614d20d913aeed162b0042
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311315
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When signer code was ported and enhanced to work with binaries (in
addition to hex), a bug was introduced, where the signed image is
considered to always to be based at the bottom of the flash. In fact
the image could be anywhere in the flash, the actual address derived
from the input elf file should be used.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that when enabled, RW image is signed properly
(build/cr50/RW/ec.RW.flat starts with a signature).
Change-Id: I194bd02f932529165adcbebf4bcbd9020fc261dc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311314
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
New aliases are created automatically, there is no need to include
them in registers.h manually any more.
BRANCH=none
BUG=none
TEST=built and ran cr50 successfully
Change-Id: I9c12c9a66d231723f8c986dd0c598f1e03aaca3a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311372
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Register descriptions generate by the hardware tools always use the
block index when naming the base address of the bock, but the macros
compiling addresses out of register names do not use the index if
there is just one instance of the block in the design.
The problem is addresses by aliasing these definitions in registers.h
in the chip directory. This patch automates this aliasing and ensures
that the generated file has the aliases included, no need to add them
manually to registers.h.
BRANCH=none
BUG=none
TEST=re-generated cr50_regs.h, observed proper aliases created, built
and ran cr50 with the new registers file.
Change-Id: If037e082841a1510f7cad66737fd8b775dc667ea
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311371
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Turn on LTO for GLaDOS and Kunimitsu. This saves about 5k from the
image on GLaDOS. Also, LTO is disabled for the loader since it actually
causes it to bloat in size for some reason.
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Build and flash on GLaDOS with charger inserted. Verify that EC
boot is successful. sysjump to RW and verify that the jump is
successful.
TEST=make -j buildall tests
Change-Id: I9892edfc724f290acaf6cceba181c177702d63bf
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/311208
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Change ADC channels on mec1322 boards to use scaling based on ADC
reference voltage of 3.0V instead of 3.3V. Also, setup the scaling
for AMON_BMON which reads the adapter input current or battery
current in mA.
BUG=none
BRANCH=none
TEST=tested on glados. use adc console command and verify it
roughly matches twinkie voltage and current.
Change-Id: Id6ed72012ebb1c23cf98a14ee6c156ec0f5fb586
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311302
Reviewed-by: Shawn N <shawnn@chromium.org>
Most of the pd ECs have CONFIG_LTO enabled which turns on GCC
Link-Time Optimizations. Unless protected, this removes the
FMAP data from the generated EC images.
BUG=chrome-os-partner:46442
TEST=Manually tested pd programming on Kunimitsu.
flashrom -p ec:dev=1 -w ec.bin is successful
BRANCH=none
Change-Id: I3badd1b245ab7490d75331be8074a0557f7b4d4b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310879
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:46056
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Enabled CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS; Build and
flash; Verify that AP and EC boot. Verify that AC notifications are sent
to the AP. Verify that I can set temperature thresholds.
TEST='sysjump rw' and repeat above tests.
TEST=make -j buildall tests
CQ-DEPEND=CL:311209
Change-Id: If2a7b0ce08b37e30362ab77eee1317c8a86b90dd
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/311344
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add HW charge ramping option and enable on glados.
Modify charge_manager to enable/disable HW charge ramping
when option is defined.
Unfortunately, the isl9237 doesn't have a way to determine
what the input current limit has settled on, so the EC will
always report the max input current for that supplier.
BUG=chrome-os-partner:47335
BRANCH=none
TEST=plug in CDP, SDP, DCP, type-C, and PD charger. Make sure
we ramp to a reasonable value for the correct suppliers.
Make sure we don't ramp for type-C and PD chargers.
Change-Id: Ib541fa0be48d8f4d261c71b853b0ee72b2adbf6b
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311301
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a new configuration struct tcpc_config_t that initially defines the
i2c host port and i2c slave address of all TCPCs present on the board.
This will allow us to create boards with multiple TCPCs on different i2c
ports, with arbitrary i2c slave addresses.
BUG=chromium:551078
TEST=Manual on glados. Verify PD communication / charging is still
functional on both PD ports.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9b2bde85d7f1642e8727c052e064371be7967619
Reviewed-on: https://chromium-review.googlesource.com/311000
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
BUG=chrome-os-partner:46056
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS. Build,
flash, and verify that AP and EC boot. Plug in a charger on both ports
and use ectool to view the PD log.
TEST=make -j buildall tests
CQ-DEPEND=CL:311209
Change-Id: I54ae617e03c645d24319d83da6cc8b7d1d6528a3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/311413
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Some ECs such as the MEC1322 have a data RAM optimized region as well as
a code RAM optimized region. We discovered that we could save quite a
bit more space by reusing the a portion of the code RAM region as an
additional .bss section. However, this region resides in the code RAM
region. If on the same cycle the processor fetches an instruction and
does a load or store to this code RAM region, the data access will be
delayed by one cycle. Hence, the naming of ``.bss.slow" section.
For boards which do not define CONFIG_REUSE_LOADER_WITH_BSS_SLOW, all
objects bearing this tag will be simply appended to the existing .bss
section.
BUG=chrome-os-partner:46056
BUG=chrome-os-partner:46063
BRANCH=None
TEST=make -j buildall tests
CQ-DEPEND=CL:306173
Change-Id: I126fbeee5255732a6dd6fea1d4557fc2b2c62c96
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/311209
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The point at which we reloaded the loader was too early. When items are
placed into .bss.slow via CONFIG_REPLACE_LOADER_WITH_BSS_SLOW, other
tasks could still access their variables that may have been in that
region after we had replaced those contents with the loader. This
commit moves the reloading of the loader to as late as possible once all
tasks have done their HOOK_SYSJUMP work.
Also, fixed a bug with the .bss.slow section. If a board is not using
the config option but items are placed in that section, that part of RAM
would not be cleared out.
BUG=chrome-os-partner:46056
BRANCH=None
TEST=Enable config option on GLaDOS and add a few variables to the
.bss.slow section. 'sysjump' between RO and RW and verify that no data
bus error is encountered.
TEST=make -j buildall tests
Change-Id: I3084700b9d5c144e86e2e408b72d2e3075a67413
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/306173
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Permission registers only reset on power cycle,
so a soft reboot will fail unless a minimum power
cycle is performed.
BRANCH=none
BUG=chrome-os-partner:47289,chrome-os-partner:43025
TEST=hard / soft reboot from ec shell
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I8f0f1bc80a2748b031a9b7a3715485577f2b5b3b
Reviewed-on: https://chromium-review.googlesource.com/310975
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Commit-Queue: Nagendra Modadugu <ngm@google.com>
Trybot-Ready: Nagendra Modadugu <ngm@google.com>
In fact this provides support for three FPGA images:
20151104_011218 - full crypto, no USB
20151104_041733 - tiny crypto, full USB
20151104_065845 - full crypto, full USB (only for hard-to-get boards)
We can tell these FPGA images apart at run-time by looking at
some SWDP registers:
register crypto usb full
GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135
GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3
This CL includes a run-time check for the USB features so that
it's safe to build the firmware with CONFIG_USB and run it on a
non-USB FPGA image.
Here are the differences I could find in the top-level image
header files:
All three FPGA images define different (apparently arbitrary)
default values for the PMU_PWRDN_SCRATCHn registers, but other
than that, the usb and full images differ only in the BUILD_TIME
and FPGA_CONFIG register values.
I'm not sure why, but function uart_init() in file
chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn
registers, but nothing seems to read it again.
The crypto image defines these values which don't appear in the
other images:
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52
#define PINMUX_USB0_EXT_RX_DMI_SEL 0x53
#define PINMUX_USB0_EXT_RX_DPI_SEL 0x54
#define PINMUX_USB0_EXT_RX_RCV_SEL 0x55
#define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56
#define PINMUX_USB0_EXT_TX_DMO_SEL 0x57
#define PINMUX_USB0_EXT_TX_DPO_SEL 0x58
#define PINMUX_USB0_EXT_TX_OEB_SEL 0x59
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240
#define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244
#define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248
#define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c
#define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250
#define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254
#define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258
#define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0
The crypto image also differs in this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c
instead of this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230
The rest of the differences between the crypto and usb versions
are in these values, which I don't think we care about. At least,
I can't find any place where they're used.
PINMUX_EXITEDGE0_DIOAn_OFFSET
PINMUX_EXITEDGE0_DIOBn_OFFSET
PINMUX_EXITEDGE0_DIOMn_OFFSET
PINMUX_EXITEDGE0_VIOn_OFFSET
PINMUX_EXITEDGE0_OFFSET
PINMUX_EXITEN0_DIOAn_OFFSET
PINMUX_EXITEN0_DIOBn_OFFSET
PINMUX_EXITEN0_DIOMn_OFFSET
PINMUX_EXITEN0_VIOn_OFFSET
PINMUX_EXITEN0_OFFSET
PINMUX_EXITINV0_DIOAn_OFFSET
PINMUX_EXITINV0_DIOBn_OFFSET
PINMUX_EXITINV0_DIOMn_OFFSET
PINMUX_EXITINV0_VIOn_OFFSET
PINMUX_EXITINV0_OFFSET
PINMUX_HOLD_OFFSET
PINMUX_SEL_COUNT
PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET
PINMUX_XO0_TESTBUSn_SEL
PINMUX_XO0_TESTBUSn_SEL_OFFSET
I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h
BRANCH=none
BUG=chrome-os-partner:43791
CQ-DEPEND=CL:310978
TEST=make buildall
I also built a single Cr50 firmware and tried it on both the
crypto and usb FPGA images. Both worked as expected.
Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311211
A previous commit caused ToT to use a not-yet-working bootloader.
This disables that bootloader by default so that the rest of us
can continue to work. ;-)
A configuration option is added to be able to address this issue in
the future with other boards as well.
BRANCH=None
BUG=chrome-os-partner:43025, chromium:551151
TEST=make buildall -j
Also verified that both normal and customized cr50 RO images build
and work as expected.
Change-Id: Ie433b07860cb1b04c12b2609c6fa39025fc0e515
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310978
The CR50 board will have to have a very different RO image, let's make
it possible to override the default list of objects compiled by the
top level makefile with a board/chip specific list compiled in the
appropriate build.mk file.
The CR50 RO will never run on its own for long time, it will always
load an RW and go straight to it, so there is no need in running under
the OS control, using sophisticated console channel controls, etc.
The gist of the functionality is verifying the RW image to run and
setting up the hardware to allow the picked image to execute, it will
be added in the following patches. This change just provides the
plumbing and shows the 'hello world' implementation for the customized
RO image.
A better solution could be the ability to create distinct sets of make
variables for RO and RW, a tracker item was created to look into this.
BRANCH=None
BUG=chrome-os-partner:43025, chromium:551151
TEST=built and started ec.RO.hex on cr50, observed the 'hello world'
message on the console.
Change-Id: Ie67ff28bec3a9788898e99483eedb0ef77de38cd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310410
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
1. In combinational mode and clock source is 8MHz,
if timer 3 counter register always equals to 7, then timer 4 will be a
32-bit MHz free-running counter.
2. Fix TIMER_32P768K_CNT_TO_US(), each count should be 30.5175 us,
not 32.768us.
3. Fix TIMER_CNT_8M_32P768K().
4. Make sure LPC wake up interrupt is enabled before entering doze /
deep doze mode.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Console commands: 'gettime', 'timerinfo', 'waitms', and 'forcetime'.
2. Enabled Hook debug, no warning message received (48hrs).
3. Tested ectool command 'version' x 2000.
Change-Id: I796d985361d3c18bc5813c58705b41923e28c5b1
Reviewed-on: https://chromium-review.googlesource.com/310039
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Under NVDC, BGATE natively has a body diode. Hence there's a discharging
path if VSYS is lower than VBAT. This change keeps VSYS voltage when
turning off charging.
BRANCH=none
BUG=chrome-os-partner:46698
TEST=manual
make buildall -j
load on boards with isl9237 charger.
charge the battery to full, and check charging voltage and current.
Change-Id: I8a6046444dd40a3b57f034be124b9e8fe281de40
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309289
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Oops. I was losing one of the args when the USB debugging output
was enabled. And with a lot of messages I was also losing some
of the output.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall, manual test of Cr50 USB:
1. Plug into a USB jack on a Linux host.
2. In src/platform/ec/extra/usb_console, run
make
./usb_console -p 5014 -e 1
3. Type something, hit return
4. See whatever you typed come back with swapped case
5. ^D to quit
Change-Id: I284606aa91a76262644cfce60913a91ccc36ae60
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310846
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This just adds a .gitignore entry so that git doesn't complain
about the executable you may have built in the extra/usb_console/
directory.
BUG=none
BRANCH=none
TEST=make buildall
This has no effect on the EC code at all. The things in the
extra/ directory are optional and unsupported.
Change-Id: Ib4915f712f9d14caf7418ef4b03aa41e8764fd36
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310840
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reduce system stack size from 4096 to 1024.
Increase code RAM size to 104K and reduce data RAM size
to 20K.
BUG=chrome-os-partner:45690
BRANCH=None
TEST=Tested on Kunimitsu
1. Flash EC, boot up, force to S5/G3, back to S0;
and powerd_dbus_suspend to S3, all work fine.
2. Use console command to dump system stack memory values,
the size used is around 350, >600 still available.
Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310581
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
LED activity is triggered by HOOK_SECOND. Updated value of led
constants to make sure blinking interval is correct.
BUG=chrome-os-partner:47243
BRANCH=none
TEST=Verified on Kunimitsu battery LED blinks at interval expected.
Change-Id: Ibd1089f3c12b1f449d81aeee9cf430981ae214ea
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310545
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1. refer to commit 8bd44bf4, oak has similar issue:
if power good is lost and the power button still press, we need
cancel the long press timer, otherwise EC will crash.
2. Furthermore, EC will crash too if long press timer is still active
during entering S3.
3. The debounce of suspend & power_good signal can be removed on rev4
because rev4 doesn't adopt level shifter.
BRANCH=None
BUG=chrome-os-partner:46857
TEST=Manual
1. press power button during coreboot, and it can shutdown normally, or
2. run test case:
> test_that -b oak <DUT IP> firmware_FwScreenPressPower
Change-Id: I584d8beeb31b6c01289bfe4790453a4a3bd35b1c
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/309942
Reviewed-by: Rong Chang <rongchang@chromium.org>
When building EC image, in the majority of cases the RW and RO images
are built from exactly the same set of object files, and the RO set of
objects is used as a template to derive the RW set of objects.
This is not necessarily correct in all cases, let's just create an
abstract set of object files and use it to derive the sets for RO, RW
and sharedlib as appropriate.
BRANCH=None
BUG=chrome-os-partner:43025
TEST=tested as follows:
- changed the Makefile to sort all object files in a single list
(instead of sorting them by directory, with the directory list
unchanged). Built all targets, saved all .smap files. Then applied
this change and again built all targets. Compare all smap files,
there were no differences.
- modified board/samus/board.h to trigger building sharedlib
objects, verified that build/samus/sharedlib built fine.
Change-Id: Ie563aca62028cae9e16f067ba20b5e2930355cf5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310389
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This has been bothering me literally for years: once in a while there
would be tons of files in /tmp directory named tmpXXXXXX where XXXXXXX
is some random string.
Finally, it became clear that the files are generated when 'make
buildall -j' is called in the ec directory. Next step - it looks like
one of the culprits is building for board named 'chell'. Indeed, this
board uses its own version of cmd_obj_to_bin make function, which,
among other things invokes the pack_ec script to pack the image.
The script was creating temporary files and leaving them behind.
This patch makes the name pattern of the temp files better
recognizable, juts in case, and makes sure that the files are deleted
once they are not needed.
BRANCH=none
BUG=none
TEST=invoking 'make buildall -j' still succeeds but does not result in
leaving temp files behind.
Change-Id: I50c511773caa87d4e92980c4c9a36768b0c3101f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310586
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
