This is a specific option for it83xx chip and is used to
include EC2I module.
And we won't need it without LPC module enabled, so just
depend on CONFIG_LPC.
BUG=none
BRANCH=none
TEST=make buildall -j, boot to kernel on reef_it8320.
Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/987674
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When building the `tests` target for a specific board that uses the
ite EC chip, it will fail to find the lpc_kbc_obe_interrupt function.
Adding #define around code similar to npcx set up.
This is needed because the unibuild system uses the tests target when
compiling chromeos-ec.
BRANCH=none
BUG=b:77274422
TEST=Can now successfully `make BOARD=bip tests`
Change-Id: I971aebe1667eb90e8ccccbe6047c5aa959c76c4b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986634
Reviewed-by: Scott Collyer <scollyer@chromium.org>
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
This patch splits struct fan_t into two parts: base configuration
and RPM configuration. RPMs are expected to be different from
model to model while a base configuration is most likely shared.
BUG=b:73720175
BRANCH=none
TEST=make buildall
Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949382
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to change PLL settings if host apply eSPI operating
frequency higher than 50MHz, because FND clock is required
to be higher than half of operating frequency.
BRANCH=none
BUG=b:70537592
TEST=Change PLL succeed with chip select is low.
Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/817717
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The PNPCFG (EC2I control module) is used to set I/O port base
address and IRQ number.
On it8320, PNPCFG will be reset while system event PLTRST_L
is asserted. This means we can't decode I/O cycles correctly
until we re-initialize PNPCFG.
We disable this reset source, then we don't need to re-initialize
PNPCFG for each PLTRST_L asserted.
BRANCH=none
BUG=none
TEST=MECC board with it8320 + Intel SKL-Y RVP3 and boot to shell.
Change-Id: I7efe8f726939245424237c1d153df4f83b39ae6b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/810428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
- We have more flash space to use with nds32 toolchain GCC6.3.0,
so we enable a few console commands that were disabled previously.
And we also enable LTO to reduce the size of FW image.
- Put "__wait_evt" function into ram_code section to
fill the gap of flash and improving performance of code-fetch.
BUG=none
BRANCH=none
TEST=boot to kernel on reef_it8320.
Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/788712
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add espi control module for it83xx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell.
2. console command "kbpress 1 4" to test keyboard data.
(board code for espi module test on CL:392587)
Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d
Reviewed-on: https://chromium-review.googlesource.com/394471
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With this change, we can keep a PWM channel active during
low-power idle (EC deep doze).
BRANCH=none
BUG=none
TEST=The pwm channel is function normally in deep doze mode.
And tested pwm frequency setting are:
300, 250, 200, 150, 100, 50, and 10 (Hz)
Change-Id: Ie94cd96e819c869bdde6d7675d8f1a6cfc627f3b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/752702
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With these changes
$ CROSS_COMPILE_nds32=/opt/coreboot-sdk/bin/nds32le-elf- \
make BOARD=it83xx_evb
works for me.
The -mno-gp-direct option is replaced with -mcmodel=large in new
compilers, as indicated in private email with Andes Tech. It was also
used as a work-around and leaving out the option altogether reduces the
code size significantly, so it's now dropped.
BRANCH=none
BUG=b:35572628
TEST=the above command creates an image
Change-Id: Ib580d65e6e52f291fdb920b7b65fb22cfda9f736
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/753623
Commit-Ready: Stefan Reinauer <reinauer@google.com>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Add a common hook handler on CHIPSET_RESUME to log port80 resume
message instead of duplicating the same code in all chip lpc_resume.
BUG=b:68669668
BRANCH=None
TEST=Verified that port80 resume is logged on S0ix and S3 resume.
Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of duplicating the handling of host events and host event
masks in chip lpc drivers, add routines in common code to provide
basic functions like setting/getting of masks, setting/getting of
events and handling of masks transitions across sysjump.
BUG=None
BRANCH=None
TEST=make -j buildall. Verified following:
1. Event masks are correctly retained across sysjumps.
2. Wake from S3 works fine.
3. Wake from S0ix works fine.
4. SCI generated correctly.
Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/707771
Reviewed-by: Shawn N <shawnn@chromium.org>
If we don't use IT8320's PD module, we should dis-connect resistor
to GND and disable CC related function to make sure these pins can
work as other function.
BRANCH=none
BUG=none
TEST=CCCSR register setting is 0xff after initialization if
we don't enable CONFIG_USB_PD_TCPM_ITE83XX.
Change-Id: I97e019ec1c9c852cd758b364a5e7913de1fc84f4
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/689435
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- To i2c channel(d/e/f), we remove instructions that aren't necessary.
- Changes of i2c_reset():
Before the change, we try to send a START/STOP bit if we get a reset.
But i2c_unwedge() already done it, so we just need reset i2c module
in i2c_reset().
- Add enhanced_i2c_start() to channel(d/e/f) for each transaction start:
We prepare transaction start by calling i2c_reset(),
but this doesn't match the definition of i2c_reset(),
so we correct it.
BRANCH=none
BUG=none
TEST=1. console commands: "i2cscan", "charger" and "battery".
2. sensors, battery, charger and mux work on reef_it8320.
Change-Id: I4e3595479e04a5994a5b19409cfc4e9a46f63d4f
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/674467
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We disable i2c interface immediately after stop bit is set.
This might caused bus busy bit of status register unable to clear
(bus busy bit will be set at start condition and cleared at
stop condition).
So the next transaction, we won't get a good state to start.
This change also fix incorrect stop bit for write transaction:
IT83XX_I2C_CTR(p_ch) = xx
BRANCH=none
BUG=none
TEST=Ensure i2c interface is disabled after i2c stop condition.
Change-Id: I5416bfcef3f95357c6771dead6b0611b908f787e
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/645407
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Default setting of embedded flash's clock is 24 or 32 MHz
and PLL is 48 or 96 MHz correspondingly.
And it8320 supports e-flash clock up to 48 MHz,so we add
a new config option to support it.
BRANCH=none
BUG=none
TEST=Run FAFT with e-flash 48MHz and test results are passed.
Change-Id: I096ae3abc8fec9bd7e0556c57605e87a31ac3b07
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/645466
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Use existed macro instead of creating new one.
BRANCH=none
BUG=none
TEST=plug USB-C power adapter and USB-C to hdmi adapter, both work.
Change-Id: I133142232ac6abfa7f285c289eb03c4d65e84d5f
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/554655
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Because N8 CPU doesn't have floating point unit,
so we implement an extra floating point engine
(single-precision addition, subtraction, multiplication,
and division) into it8320 to improve performance of
floating point operation.
To make CPU's instruction compatible, we use register (DLMB)
to switch ALU (Arithmetic Logic Unit). eg:
Instruction 'ADD45' adds the contents of two registers then
writes the result to the source register.
But if we switch ALU to floating point operation mode,
this instruction will do a floating-point addition instead.
For the other FPU that we don't support as far,
we have to use soft float library routines of nds32.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=add the following console command and test different
scenarios by changing variable a and b.
#define PRINTF_FLOAT(x) ((int)((x) * 1000.0f))
static int it83xx_fpu_test(int argc, char **argv)
{
volatile float a = 1.23f;
volatile float b = 4.56f;
volatile float c;
c = a + b;
ccprintf("__addsf3: (%d)\n", PRINTF_FLOAT(c));
c = a - b;
ccprintf("__subsf3: (%d)\n", PRINTF_FLOAT(c));
c = a * b;
ccprintf("__mulsf3: (%d)\n", PRINTF_FLOAT(c));
c = a / b;
ccprintf("__divsf3: (%d)\n", PRINTF_FLOAT(c));
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(fpu, it83xx_fpu_test, "", "");
Change-Id: I4fc1c08d8c2376156bec9f098491187675c4a88f
Reviewed-on: https://chromium-review.googlesource.com/427640
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The trimmed value of CC parameter setting registers
(port0: ff3760h ~ ff3763h, port1: ff3860h ~ ff3863h)
will be reset to default after a soft reset (system_reset()).
BRANCH=none
BUG=none
TEST=Console command 'reboot' and checking if the value of
cc parameter setting registers are correct (trimmed).
Change-Id: Ibf9c72e8aeef36701d72bcb64529735295295cdf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/513744
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Disable USB debug interface:
If we don't use GPIOH.5/6 pins for debugging,
we should disable it to prevent any chances of entering debug mode.
2. command_idle_stats() behind CONFIG_CMD_IDLE_STATS:
We can exclude this console command if we don't use it.
3. Remove 'dsleep' console command:
DEEP_SLEEP_ALLOWED macro is enough for us.
BRANCH=none
BUG=none
TEST=bit7 at 0xF02030(MCCR register) is cleared after initialization.
Change-Id: If34e9738351459891be8c9a6619384adbfe26335
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487843
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We can get the correct chip info after the change was made.
BRANCH=none
BUG=none
TEST=console message:
[0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
[0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487767
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This timeout is described in SMBus specification (25ms).
Some I2C devices may required longer clock stretch
(The I2C specification does not specify any timeout conditions
for clock stretching).
So we increase this timeout to maximum.
NOTE:
Because this codebase already handle timeout of an I2C transfer,
so maybe we can disable this mechanism.
But we don't have any register to execute this,
so we maximize the timeout.
BRANCH=none
BUG=none
TEST=console commands: i2cscan, battery, charger, and accelinfo.
Change-Id: I5025f640c027105152247212fc688388f645c5ba
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/485203
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently if an interrupt is pending before it is enabled the interrupt
will fire immediately. In most cases this is fine, but if we want to
use the interrupt to trigger something like waking the AP it should be
sure that it won't immediately fire once enabled.
For example: on the Eve board we have the trackpad interrupt run to the
AP and the EC in order to support wake from Deep S3 (magic AP state that
only the EC can wake it from). This interrupt is used in S0 by the AP
while ignored by the EC, and then enabled on the transition to S3 in
order to be able to wake. Since it has been active the interrupt may
be pending in the EC (depending on the chip), which can result in the
interrupt firing immediately and waking the AP.
BUG=chrome-os-partner:62224
BRANCH=none
TEST=This has been functionally tested on npcx only as that is what I
have a use case and system for, the others compile and look right but
have not been directly tested.
Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446962
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add generic routines to read or write a byte to battery-backed RAM, and
implement vbnvcontext get/set using these routines.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, with subsequent commit, run "cutoff" on the console,
reattach AC, and verify device successfully wakes. Also verify Rp is
dropped on console 'reboot' and F3 + power from RW.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d
Reviewed-on: https://chromium-review.googlesource.com/444444
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Before the change was made, the "__ro_end" was at 00013520h.
We change to 00012760h.
- Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE"
this is because we don't support reconfiguration at board-level.
- Put some task functions into "__ram_code" section to
fill the gap and improving performance of code-fetch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: flasherase, flashwrite, and flashread.
Change-Id: I2f2906a2a0b6971aadd00120c282801161447808
Reviewed-on: https://chromium-review.googlesource.com/424248
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO
states to ROM POR values. Therefore, it is necessary to re-init GPIO
states once again based on board-level GPIO settings.
BUG=chrome-os-partner:58077
BRANCH=gru
TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify
actual register values are printed rather than zeros.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717
Reviewed-on: https://chromium-review.googlesource.com/395426
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
spi_transaction() can be called from motionsense, hooks, hostcmd,
console, and chipset tasks, so add a mutex to ensure an in-process
transaction isn't preempted by another transaction.
BUG=chrome-os-partner:57912
BRANCH=gru
TEST=On kevin, run "while true; do ectool motionsense odr 0 0; sleep 1;
ectool motionsense odr 0 1000000; sleep 1; done", verify watchdog crash
not encountered after 20 minutes.
Change-Id: I7ec495bab295dc03ce02372c20e5c7c5c196715d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391892
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit eabdea443775fab834aaabbb7afae871306c7530)
Reviewed-on: https://chromium-review.googlesource.com/392226
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The application may need to read/write/erase the flash memory,
but we not want console users to do so. This CL adds
CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH
to be undefined while still providing the chip-specific
flash_physical_* accessor functions.
There aren't many board.h files that needed changes, since
CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
See that it still boots, updates, wipes, restores, etc. without
linking common/flash.o in the production image; and that the
flash commands are still there in the dev build.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93
Reviewed-on: https://chromium-review.googlesource.com/391188
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The typical power consumption in sleep mode is 65uA.
IT83xx uses deep doze mode for low power idle task. The typical power
consumption in this state is 280uA (depends on EC tasks, it should be more)
and the wake up time is in microsecond. We are using deep doze mode for
low power idle task instead of sleep mode is because the wake up time
will be 6ms more.
While in system hibernate (EC sleep mode), EC won't wake up frequently so
we can keep the power consumption at 65uA.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=- hibernate 0 [1|999999]
- hibernate [1|5|10|600]
- hibernate then press power button.
- hibernate then lid open.
Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d
Reviewed-on: https://chromium-review.googlesource.com/383332
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Remove timeout to avoid fetching unknown instruction from e-flash
and causing exception.
Also fixed:
- To make sure immu(dynamic cache) is reset after a erasing/writing
operation.
- Verify function is in critical section.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: "flasherase" and "flashwrite".
Change-Id: I0c84282ac4689cd762159071afae3efeea31d281
Reviewed-on: https://chromium-review.googlesource.com/380500
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
