This preserves the selected idle action (wfi, sleep, deep sleep)
across soft reboots, which includes deep sleep. Hard reboots will
restore the default which is to not sleep at all.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
Use the "idle d" console command to put the Cr50 into deep sleep
when idle (refer to previous commit messages for the setup
required).
Wake it up, then let it sleep again. It should go back to the
deep sleep state.
Change-Id: Iaad82b725d2b32a19205fa403dbaab9a31c35630
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336834
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
modify g781.c/.h to g78x.c/.h to suppor both G781/G782 temp sensor
based on CONFIG_TEMP_SENSOR_G781 or CONFIG_TEMP_SENSOR_G782
BUG=none
BRANCH=none
TEST=make buildall; able to get temperature data on board with G782
Change-Id: Ia32c85e9964bfd7c0c5263f04368bc001a27fe10
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/334228
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds the SPI slave bus and TPM task to the things that
can prevent deep sleep. Even when things are quiet, we wait at
least a second
With this CL, it will wait at least one second after the last SPS
transaction before sleeping. Since most TPM-protocol commands are
built up of a number of back-to-back SPS messages, if we don't
wait we'll keep trying to sleep in the middle of active commands.
Even if everything is quiet, we wait 0.2 seconds anyway to give
the UART buffers time to drain.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; extensive tests on Cr50
Testing is a pain.
In addition to ALL the steps listed in commit
d917d3f1867e96369ff25bf6906043a5f488a6fb, loading the firmware
with the spiflash tool leaves SPS_CS_L low, so you have to drive
it high manually. The easiest way is to build and run
test/tpm_test/tpmtest.py for a few seconds then interrupt it with
Ctrl-C.
Note that because the system wakes from deep sleep when it sees
SPS_CS_L go low but it can't get ready fast enough to capture the
incoming bits, that first SPI transaction will be garbled or
lost. You'll have to either retry it, or wake the system another
way first.
Change-Id: Iae2fe5ef33869c48e98a3afecd6b98991a51a488
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336690
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After a charger is attached, we may set a charge limit based upon BC1.2
or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds
for all negotiation to complete. Previously this behavior was implicit
when using SW charge ramp.
BUG=chrome-os-partner:51280
BRANCH=glados
TEST=Manual on chell. Insert stock charger, verify that it is detected
as TYPE_UNKNOWN until timeout.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028
Reviewed-on: https://chromium-review.googlesource.com/334312
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is keyboard test mechanism request for "multiple key press test",
we can thru the testing to scan out kso ksi pins shortting or keyboard has
multiple key pressing, below was the testing steps:
1. Turn off internal keyboard scan function.
2. Set all scan & sense pins to input and internal push up.
3. Set start one pin to output low.
4. check other pins status if any sense low level.
5. repeat step 3~4 for all keyboard KSO/KSI pins.
6. Turn on internal keyboard scan function.
BUG=chrome-os-partner:49235
BRANCH=ToT
TEST=manual
Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed.
if no pins short together, it shows passed.
Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/332322
Reviewed-by: Shawn N <shawnn@chromium.org>
cr50 has three UARTs that it will be using. This change modifies the
uart api to specify which uart to use.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the
different UARTs can be used.
Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333402
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is still in testing mode, so you have to take special steps
to enable it (keep reading). But if you do the right dance, it
does go into deep sleep for USB suspend, and resumes correctly.
However, it doesn't yet wake for any other reason. That's coming next.
Normal sleep is not yet supported, either.
BUG=chrome-os-partner:49955, chrome-os-partner:50721
BRANCH=none
TEST=make buildall; extensive tests on Cr50
Testing is a pain.
First, you can't print anything in the idle task, because that
just makes it stop being idle, so the only way to detect when
it's triggered is by wiring up a GPIO and instrumenting things.
Second, you have to manually reenable USB suspend on the host
every time the Cr50 boots with
echo auto > /sys/bus/usb/devices/<BLEH>/power/control
where <BLEH> is the correct device.
Third, for reasons probably related to the mysteries of HID
devices combined with crbug.com/431886, you have to build the
firmware without CONFIG_USB_HID (and the related items in
board.h)
Finally, because it's still a work in progress, you have to type
idle d
at the serial console after every boot (or resume) to reenable
deep sleep in the idle task.
If you do all that, then you'll see that it does go into deep
sleep. Ping it again with "lsusb -v -d 18d1:5014" or
./test/usb_test/device_configuration, and it wakes up and
responds!
If you disconnect the USB while it's in deep sleep, it stays
asleep. When you plug it in again, it wakes up, but it correctly
recognizes that it shouldn't resume and does a normal reset
instead.
Change-Id: I3cc66e48ce671142a4d12edbe0eb9fdacecea0d9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336279
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
Add support for charge port switching and extpower detection, which are
not part of the standard charger API.
In addition, add a console command for dumping all regs, which is
helpful for debug.
BUG=chrome-os-partner:51722
TEST=Manual with subsequent commit. Verify kevin charges at 3A input current
when zinger is inserted, and verify battery actually charges.
BRANCH=None
Change-Id: I98a0c0142d26facc0e0b9ef7f1dcd003ebffd9c1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335537
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
NULL padding (aka vanilla RSA) support is required by
the TPM2 test suite (referred to as TPM_ALG_NULL in the
tpm2 source).
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/328830
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Some of the reset causes are found in another register when
resuming from a low-power state. We know we'll need to
distinguish among them eventually, so we might as well decode
them now.
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
I forced the system into deep sleep and observed that the reset
cause is accurately recorded on resume. Doing that requires a
fair amount of hacks and manual effort, and can't happen by
accident. Future CLs will make use of this.
The current, normal behavior is completely unaffected.
Change-Id: I5a7b19dee8bff1ff1703fbbcc84cff4e374cf872
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336314
Reviewed-by: Randall Spangler <rspangler@chromium.org>
A resume from deep sleep looks a lot like a cold boot, but there
are some registers that need updating quickly. We need to disable
the settings that triggered deep sleep so that it isn't
accidentally invoked again, and we need to unfreeze any modules
or pins that were frozen during the deep sleep.
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
Since we aren't yet triggering deep sleep, this doesn't do
anything noticeable, which is the point. It shouldn't have any
effect unless we are entering deep sleep and DON'T do this when
it resumes. FWIW, I have tested that too, but it's coming in a
later CL.
Change-Id: I4b32fd2e24fe089d3f659154df26d275b41b4c1b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336450
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This just adds the framework to use for implementing sleep and
deep-sleep. This provides a custom idle task, and a new "idle"
console command to control what that task should do (nothing,
yet).
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
Other than the new idle command which does nothing, there is no
visible change. This is just a stub.
Change-Id: I8a9b82ca68dd6d1e3e7275f4f6753a23a7448f1d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336420
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds USB support to Set and Get the Device Configuration.
These control transfers are standard device requests that need to
be added in order to behave properly for USB suspend/resume (and
in general). Before this CL, the Get command always failed and
the Set command had no effect internally. With this CL it works.
Note that this particular change only supports ONE configuration
for the Cr50. If/when we add additional configuration
descriptors, we'll need to update it again.
BUG=chrome-os-partner:50721
BRANCH=none
TEST=make buildall; manual tests on Cr50
This CL includes a test program. Connect the Cr50 to the build
host, and use that program to read and change the configuration.
cd test/usb_test
make
./device_configuration
./device_configuration 0
./device_configuration 1
./device_configuration 2
You may need to use sudo if your device permissions aren't sufficient.
Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335878
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Fan will disable when S3 and S5 by pwm_fan_s3_s5,
which call set_enabled(fan, 0) to disable it.
But the pwn_fan_resume called fan_set_enabled() which not setting
GPIO_FAN_PWR_DIF_L to 1, we should use set_enabled() instead.
BUG=chrome-os-partner:50372
BRANCH=master
TEST=check fan enable after system resume
Signed-off-by: Keith Tzeng <Keith.Tzeng@quantatw.com>
Change-Id: Id0bd4dd0afc7e02bcfa6e20401d6e9dfe8a81423
Reviewed-on: https://chromium-review.googlesource.com/335693
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Update the GPIO mapping based on the Kevin P0 schematic and drive the EC
and AP select signals low.
BUG=chrome-os-partner:50728
BRANCH=none
TEST=test that DIOB2 and B3 default to low, but can be set high or low.
Change-Id: If574436913ad0271540bcce2939fe1f4574dae97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335381
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When a pin power-on default is input, it is necessary to configure output
level, pull up, etc. before setting the pin to output. Otherwise, the
pin may be set to an undesired logic level for a short time.
BUG=chrome-os-partner:51722
TEST=Power-up kevin, verify that CR50_RESET_L (default input, configured
as high + open drain output by default) does not go low for a short
period at boot.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ieaa08e14e6ea15a908f3ff4ee9188e14b17583cf
Reviewed-on: https://chromium-review.googlesource.com/335344
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
- Fix incorrect use of pwm functions which take a channel number.
- Set power-down register according to PWMs that are actually enabled.
BUG=chrome-os-partner:51722
TEST=Run 'pwm 1 50` on kevin and verify that LED lights up.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If7bcc812b55d3b72f215cf41c264d34827db7e29
Reviewed-on: https://chromium-review.googlesource.com/335372
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
When EC receives many flash write requests from host and
PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the
HOOK task may not get scheduled in time to pet the watchdog
resulting in an EC reset.
BUG=chrome-os-partner:51438
BRANCH=None
TEST=Manual on lars, determine two EC versions that have enough
differences so that replacing one image with the other will
require all or most of the flash pages to be updated. Alternate
between flashing the two images with flashrom using a script.
Atleast 1000 iterations should pass.
Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/334457
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52)
Reviewed-on: https://chromium-review.googlesource.com/334903
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
We clear global NAKs by writing bits in the USB_DCTL register.
However, prior to this CL we were overwriting the entire
register, not just touching individual bits.
Since we've never actually set any global NAKs, this mistake
didn't have any noticeable effects. But we should still do the
right thing in case we need it later.
BUG=chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
No visible change; everything continues to work.
Change-Id: Ia25d95dc6211e5460132622ac005723f43b00e24
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335190
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We were referring to unhandled USB control messages as errors,
but they aren't necessarily. Sometimes they're optional things
that aren't fatal. We should still address them, but we don't
have to freak out.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50
Change-Id: I892acec2d89b8ec95353cdc09f3e49aa78b1704d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335200
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There were some unnecessary shifts and conditionals. This just
makes the code a little more readable.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hw
Change-Id: I084f191675d1b51101e9dc55c2e5a12b0b345d33
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334870
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This config option allowed us to disable the TPM protocol on the
SPI slave bus and replace it with our EC-style host command
protocol. We only used this for early testing and don't need it
anymore, so we can get rid of it completely for this SoC.
BUG=none
BRANCH=none
TEST=make buildall; test on cr50
Change-Id: I2126537e8bcc78e583cf426a3a83962c9ff1a121
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334762
Reviewed-by: Scott Collyer <scollyer@chromium.org>
BRANCH=none
BUG=none
TEST=Test OK on ITE8390CX.
You can run "make -j BOARD=it8380dev" to build ec.bin
and flash the ec.bin via
"sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin"
Change-Id: I2077012114bdbd5a8cc8f7dc29e43cdcb77d65b6
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/334176
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On oak battery, when the battery is dead it reports 0 for desired
voltage, current, and state of charge. In this case we should allow
charging.
Added a CONFIG option for this that should be removed as soon as
the battery side is fixed.
With this CL, when a dead oak battery is used and a charger is
connected, we attempt to charge it.
BUG=chrome-os-partner:51454
BRANCH=none
TEST=test on an oak with a dead battery. w/o this CL, the battery
never charges because the charging not allowed flag is set. With this
CL, the battery charges.
Change-Id: If9f1250cd41aec265838e1d109f53c1bcd58c111
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/334471
Reviewed-by: Rong Chang <rongchang@chromium.org>
1. Always use wake-up control interrupt for keyboard KSI. This can also
wake-up EC from deep doze / sleep mode.
2. In keyboard ISR, we just clear interrupt status to prevent keyboard
interrupt can't be re-enabled.
(for example, a KSI interrupt wakes up keyboard scan task,
but keyboard_raw_read_rows() got 0.)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=keyboard function is normally.
Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312
Reviewed-on: https://chromium-review.googlesource.com/333865
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The channel enum and string name array were out of sync (when
CONFIG_EXTENSION_COMMAND is defined). This was caused by the two lists
being specified separately. I argue that this is a good reason to merge
the lists into a separate X-Macro include file.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I81d143f550a0fe6ef0c64e3c8357ed18aee4bfdc
Reviewed-on: https://chromium-review.googlesource.com/334381
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
isl9237 uses HW ramping but has no way to monitor the ramp current. Zero
is not a good estimate of the ramp current and scares users into
thinking their device isn't charging, so use the nominal current limit
instead.
BUG=chrome-os-partner:51286
BRANCH=Glados
TEST=Verify "ectool usbpdpower" on chell reports "14xxxmV / 2668mA"
rather than "... / 0mA" with stock charger attached.
Change-Id: I0a29c8092b4994fda68dc3db8e02be2e0f234fd9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334237
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit cef36e872f72db9e060dd0cc7e5bced3062fbfd1)
Reviewed-on: https://chromium-review.googlesource.com/334395
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Re-write smbus driver to fix arbitrary length read and improve code
organization.
BUG=chromium:576911
BRANCH=None
TEST=Manual on sentry. Verify that smbus communication with battery is
functional.
Change-Id: I63c4bc3df40755cd41b3d9956af0ab9d2145a253
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333787
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Building a single buffer for crc calculation is often inefficient, so
add a new function that calculates crc8 from an existing crc8.
BUG=chromium:576911
BRANCH=None
TEST=Manual on sentry with subsequent commit. Verify that smbus
communication with battery is functional.
Change-Id: I05ffedb81ffcf0c126acda5f6212b3147b1580a1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333786
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
`tempsinfo all` will probe all 24 sensor IDs, which will produce stderr
output due to host command failure if a given sensor does not exist.
Therefore, check memmap data for presence before probing a given ID.
BUG=chrome-os-partner:51026
BRANCH=None
TEST=Manual on Sentry. Verify "ectool tempsinfo all" dumps info on 4
temperature sensors and prints nothing to stderr.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14d65c1ad03eafafc21db41781c434b3ed74cb7e
Reviewed-on: https://chromium-review.googlesource.com/333779
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
During the resume sequence of S0ix EC can receive host commands early
in the resume path when LPC is still disabled in EC. Host messages
will be lost if the LPC interface with the kernel is down.
Clock control was programed to 2 which means ring oscillator is
shut down after completion of everty LPC transaction.To restart
the oscillator EC should enable a wake interrupt on LPC LFRAME number
and this mode can cause an increase in the time to
respond to the LPC transactions.
Keeping LPC always on shows minimal power impact as per datasheet
Pg.390. The impact is < 0.45mW.
BUG=chrome-os-partner:50627
TEST=Enter into S0ix and exit reliably.
BRANCH=firmware-glados-7820.B
Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332333
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4)
Reviewed-on: https://chromium-review.googlesource.com/332791
* Update flash_ec to allow flashing servo_micro
* Add servo_micro build
BUG=chromium:571477
BRANCH=None
TEST=updated servod is able to control gpio, gpio extender,
SPI flash, ec uart, ap uart on test yoshi
Signed-off-by: Nick Sanders <nsanders@google.com>
Change-Id: I4d69c83ae581cb41da928a27c39b7152475d7ca8
Reviewed-on: https://chromium-review.googlesource.com/327214
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The debounce timer might be too slow to actually update the state of
debounced_power_pressed by the time we do power_button_is_pressed in
the S3->S5 state transition.
Call power_button_wait_for_release() instead of wait_for_power_button_release()
to make sure there are no deferred actions.
BRANCH=none
BUG=chrome-os-partner:50362, chrome-os-partner:51109
TEST=During dev mode screen, press power button, note the device stays off
TEST=sudo test_that -b oak <DUT_IP> firmware_FwScreenPressPower
Change-Id: Ic60c1847ba461ef874dea5bf7d03675622f24beb
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332310
Reviewed-by: Rong Chang <rongchang@chromium.org>
