Some STM32 variants have a 32-bit timer in addition the bunch of 16-bit
timers.
Add the option to use the 32-bit timer as the system clock source to
lower the overhead of the timer code compared to a pair of 16-bit
timers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run the EC on STM32F072 Discovery board with 32-bit TIM2 as the
clock source.
Change-Id: If55c4e23a3f68dd8f6ca32e93f3a27c1743c767b
Reviewed-on: https://chromium-review.googlesource.com/189861
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
After Alex's CL 8a9817a, the i2c driver no longer hardcodes the
I2C port pin (Ya!). Remove the conflict pin setting in board files.
BRANCH=nyan,big
BUG=chrome-os-partner:26620
TEST=build and run on nyan board. Everything looks good.
Change-Id: Iee2c5f10f642da7ad00f503b6e615cb6aa472459
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189245
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When measuring speed gain of mem*() in utils test on host, there are too
many reasons that the results may be fluctuate. This gets even worse
when the unit tests run on buildbots. Let's only check for speed gain on
device.
BUG=chromium:351870
TEST=Check the speed gain check assertion is not compiled.
BRANCH=None
Change-Id: I0369d07d1da8cbb469d3a2a9d846406415c06745
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189804
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove power_led_task and add the big-specific LED logic
BRANCH=big
BUG=None
TEST=manually
>> ectool led power blue: PWR LED blue
>> ectool led power yellow: PWR LED orange
>> ectool led power off: PWR LED off
>> ectool led power auto: PWR LED auto control
>> ectool led battery blue: BAT LED blue
>> ectool led battery yellow: BAT LED orange
>> ectool led battery off: BAT LED off
>> ectool led battery auto: BAT LED auto control
Signed-off-by: Cloud Lin <cloud_lin@compal.com>
Change-Id: I5ded361a46c627e4e4e6fcb6bddea9b487a46768
Reviewed-on: https://chromium-review.googlesource.com/188631
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Lin Cloud <cloud_lin@compal.com>
Tested-by: Lin Cloud <cloud_lin@compal.com>
Put each functions in a separate section by using -ffunction-sections,
then discard the non-referenced ones in the linker with -gc-sections.
Force keeping a few special symbols by using the KEEP() linker
directive.
This modification is not saving a lot of spaces per se, but will enable
larger code pruning with future optional features.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall, manually check discarded symbols in the .map file
and run on Spring and Link.
The size delta is the following:
Link: total 85.7k -> 84.9k (.text 60.3k -> 59.5k)
Spring: total 59.2k -> 57.2k (.text 44.4k -> 42.5k)
Change-Id: Ib6eb0d3f2cc4fc172c9fc26acac2e486921690a3
Reviewed-on: https://chromium-review.googlesource.com/189224
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
we don't want to get a __packed symbol,
so we need to define __package attribute before using it for
"struct version_struct".
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST="make buildall" and verify that we no longer have a __packed
symbol in any of the build/<board/ec.{RO|RW}.map.
Change-Id: I4c229660f9b751a9149c08261fe71154067e6e62
Reviewed-on: https://chromium-review.googlesource.com/189223
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Until we have real hardware, use the STM32F072B Discovery board as a
test vehicle and do a configuration compatible with both boards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board,
and pass all available unit-tests on target.
Change-Id: Ica691f9fc915d2873761025e7c019f8a6484b9b1
Reviewed-on: https://chromium-review.googlesource.com/188984
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Add support for the STM32F0xx family of devices using a Cortex-M0 core
and slightly newer peripherals than F1xx family.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board.
and pass all available unit-tests on target.
Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735
Reviewed-on: https://chromium-review.googlesource.com/188983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
When we are calling the re-scheduling routine at the end of an irq
handling routine, we need to ensure that the high registers are not
currently saved on the system stack.
On Cortex-M3/M4, the compiler is normally doing tail-call optimization
there and behaving properly, but this fixes the fact that insanely large
interrupt handling routines where sometimes not compile and not running
properly (aka issue 24515).
This also prepares for one more core-specific DECLARE_IRQ routine on
Cortex-M0.
Note: now on, the IRQ handling routines should no longer be "static".
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:24515
TEST=make -j buildall
revert the workaround for 24515, see the issue happening only without
this CL.
Change-Id: Ic419369231925568df05815fd079ed191a5446db
Reviewed-on: https://chromium-review.googlesource.com/189153
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Fixed a potential bug in accelerometer initialization that could result
in failing to write the desired accelereometer settings. Before writing
the desired settings, we first send a command to perform a software reset.
While waiting for software reset to complete, if we have an I2C error,
then we could interpret this as software reset complete and go on to write
the accelerometer settings before the reset has actually completed.
BUG=none
BRANCH=rambi
TEST=Code inspection. I haven't actually seen this bug, I just saw the
potential for it.
Change-Id: I78757106291ffbaeff27f94aa6f74c9cea81e0b9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189064
(cherry picked from commit 521a99e38428fcfe928616f4932b5d1167e2f6cb)
Reviewed-on: https://chromium-review.googlesource.com/189233
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is needed to calibrate the tmp006 remote sensor values.
BUG=chrome-os-partner:26581
BRANCH=none
TEST='ectool tmp006raw N' works for N=0,1,2,3
And fails with invalid param for N=4.
Data matches result of tmp006 ec console command.
Change-Id: I04ec093c7727b55caca7d02baaf373d1ff234731
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189207
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On some CPU cores, the compiler needs an helper to perform the 64-bit
multiplication. As the only remaining 64-bit multiplication in the code base
is not necessary, fix it rather than adding the helper.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=build for Cortex-M0 platform.
Change-Id: I88dd7a4f2eabeca5b03fb3db232bbca9a037dcf8
Reviewed-on: https://chromium-review.googlesource.com/189151
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This works around an issue where LCDVCC falls too slowly. The impact
is to slow shutdown by 7 ms, which isn't noticeable to the user.
BUG=chrome-os-partner:26561
BRANCH=rambi
TEST=shut down rambi; still shuts down, and ~7 ms more time is spent
in S0->S3 state.
before:
[429.933010 power state 3 = S0, in 0x043f]
[429.933240 power state 7 = S0->S3, in 0x043f]
[429.933614 power state 2 = S3, in 0x042b]
[429.934013 power state 8 = S3->S5, in 0x0428]
after:
[20.355975 power state 3 = S0, in 0x003f]
[20.356194 power state 7 = S0->S3, in 0x003f]
[20.363957 power state 2 = S3, in 0x002c]
[20.364179 power state 8 = S3->S5, in 0x002c]
[20.364877 power state 1 = S5, in 0x0008]
Change-Id: Ie843bdcf740f3dbc1b866a0356cea2a8b42d4194
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189092
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Big can't be powered on by using 4s LGC AC14B8K battery.
Thus, add 4s battery definition to ec.
BRANCH=big
BUG=chrome-os-partner:26533
TEST=flash ec to big device and confirm battery works
Change-Id: I32d2eb2fabc70f3fc075a49a67c1fd4d30975981
Signed-off-by: MilesDY_Chen <MilesDY_Chen@compal.com>
Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188651
We don't have available GPIO pin for power button as the hibernate
(stand-by) wake-up source. Also, we don't want to do board change.
So, put the EC in a decent infinite loop to pretend the hibernate mode
and wait for particular wake-up event. This should be fine because
the AP is already down before EC hibernates.
BUG=chrome-os-partner:25435
BRANCH=Nyan
TEST=see comment #6 of issue for detailed test steps.
Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186061
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This command wedges the I2C bus by writing part of a byte to or reading part
of the response from the slave device.
To enabled the wedge command you must define CONFIG_CMD_I2CWEDGE and you must
define I2C_PORT_HOST, the i2c port to use the wedge command.
BUG=chrome-os-partner:19286
TEST=Manual test on peach pit, spring, and glimmer. Define config in board.h
to enable the command:
On the EC console, execute the following "i2cwedge" command
i2cwedge 0x90 0 1 (wedge write)
or
i2cwedge 0x90 0 2 (wedge read)
and then "battery". Observe that the command reports an error.
Similarly, execute
i2cwedge 0x90 0 5 (wedge write + reboot)
or
i2cwedge 0x90 0 6 (wedge read + reboot)
on the EC console and observe a reboot. Then execute "battery" and observe
that the command works properly.
BRANCH=none
Change-Id: I10ccb21b047df907a4dfdbd84c0f582cfa2d939a
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/66389
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Move the CLZ instruction emulation C code to the common directory, so it
can be reused for all CPU cores missing a CLZ instruction (e.g. CortexM0).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board with Cortex-M0 core,
and pass all available unit-tests on target.
Change-Id: Ief56cac7430fcb0fbced8a8925250c89cbd0bcfc
Reviewed-on: https://chromium-review.googlesource.com/188981
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
On some CPU cores, the compiler needs an helper to perform the 64-bit
multiplication.
As the only 64-bit multiplication in the code base is not necessary, fix
it rather than adding the helper.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=build for Cortex-M0 platform.
Change-Id: Id5d6b4b6641f81732a456dacb78dee7262f6729d
Reviewed-on: https://chromium-review.googlesource.com/188980
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The charger task was holding this either on or off in S3, no matter what we
wanted. We really only need to set it at S3->S0 or S3->S5, or when the
lid opens or closes. The rest of the time we should be able to turn it off
and on with gpioset, for testing purposes.
BUG=chrome-os-partner:26502
BRANCH=ToT
TEST=manual
Check the state with
gpioget TOUCHSCREEN_RESET_L
Open and close the lid, suspend the AP with powerd_dbus_suspend, etc. The
touchscreen should be on when the lid is open and the AP is in either S3 or
S0, off when the lid is closed or the AP is off.
Then
gpioset TOUCHSCREEN_RESET_L 1
gpioget TOUCHSCREEN_RESET_L
gpioset TOUCHSCREEN_RESET_L 0
gpioget TOUCHSCREEN_RESET_L
The change should persist as long as nothing else changes.
Change-Id: If7b6f809b1b28ae2699d0fbc6c9b2305fc57cbff
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188869
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Refactored the i2c unwedge code to place it in the common directory
so that any EC chip can use it.
Added to the STM32F and LM4 boards, code to automatically detect and
unwedge the i2c bus at the start of an i2c transaction. Note that STM32L
already had this ability.
To enable unwedging of the i2c port though, the gpio pins for SDA and
SCL must be defined in the i2c_ports[] array in the board.c file. This
allows the i2c module to bit bang the unwedging for the given port. If
SDA and SCL are not defined for the port, then the unwedge code will
not run.
BUG=chrome-os-partner:26315, chrome-os-partner:23802
BRANCH=none
TEST=Manual testing on machines with different EC chips.
Testing made extensive use of https://chromium-review.googlesource.com/66389
in order to force wedging of the i2c bus so that we can attempt to unwedge
it. Note that you can easily test if the bus is wedged by running i2cscan.
On pit and spring:
On pit, after each of the following, I verified that the bus was automatically
unwedged.
On spring, the unwedge only runs at reboot, so, for the non-reboot wedge
commands, I manually ran console command unwedge, and verified that the bus
became unwedged.
(1) Bit bang a transaction but only read part of the response.
Command to wedge: i2cwedge 0x90 0 2 2
(2) Bit bang a transaction to do a "write" and stop while the other side is
acking. Command to wedge: i2cwedge 0x90 0 1
(3) Same as (1) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
Command to wedge: i2cwedge 0x90 0 6 2
(4) Same as (2) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
Command to wedge: i2cwedge 0x90 0 5
On glimmer:
Added code to call i2c_unwedge in accel_init(). Then tested unwedging the
accelerometer with the following. One extra difficulty testing this with
the accelerometer is that sometimes the bit you stop on is high, which
means it won't be wedged at all, the next start transaction will reset
the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes
it will depending on the acceleration data.
(1) Big bang transaction to do a "read" of accelerometer and stop partway:
i2cwedge 0x1c 0x0f 2 2
i2cscan to make sure bus is actually wedged
i2cunwedge
i2cscan to make sure bus is now unwedged.
(2) Bit bang transaction to do a "read" and stop partway, then reboot:
i2cwedge 0x1c 0x0f 6 2.
i2cscan to verify that the bus is working after the reboot.
Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188422
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Compiling with coverage enabled screws up the time that things take, so
don't test for a particular speedup in that case. It fails unreliably.
BUG=chrome-os-partner:20881
BRANCH=ToT
TEST=manual
cd src/platform/ec
make coverage
Before, it failed about half the time. Now it doesn't.
Change-Id: I535f0193bf450a922b486777b296fea1b2768a1a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188790
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The EC had inputs with internal pullups on SUS_STAT#, SUSPWRDNACK, and
SLP_SX#. But we never used those signals for anything. The pullups
cost 1.5 mW power in S3. So, remove those signals and their pullups.
They can be turned back on via CONFIG_CHIPSET_DEBUG.
BUG=chrome-os-partner:25568
BRANCH=rambi
TEST=build with and without CONFIG_CHIPSET_DEBUG. Verify gpioget and
powerindebug show the signals only when it's defined.
Change-Id: I0851243615c91a3aa8aa1b28df70809b578d2e74
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188389
Reviewed-by: Dave Parker <dparker@chromium.org>
This speeds up memset by copying a word at a time.
Ran the unit test on Peppy:
> runtest
...
Running test_memset... (speed gain: 141532 -> 32136 us) OK
...
Ran make buildall:
...
Running test_memset... (speed gain: 1338 -> 280 us) OK
...
TEST=Described above.
BUG=chrome-os-partner:23720
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: If34b06ad70f448d950535a4bea4f6556627a9b6f
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Reviewed-on: https://chromium-review.googlesource.com/185936
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Two bugs are:
- Need to grab the I2C port mutex before performing i2cxfer.
- Added sending software reset command to accelerometers on init.
This is necessary because the accelerometers can be powered
through an EC reboot, and it's important we restore them to a
known state.
BUG=none
BRANCH=rambi
TEST=Manually set accelerometer setting, rebooted, manually read
that setting and verified it was restored to default.
Change-Id: Ic3034ae39c936e07ca28458a60557b9623674ff1
Original-Change-Id: I0ea571f3a8dc46052128def24cbb5c1c29638469
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188349
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188387
Changed speed of accelerometer i2c bus to 400kHz.
Added an accelerometers present bit to the status byte for host shared
memory so that the host knows whether this system has accelerometers or
not.
BUG=chrome-os-partner:25599
BRANCH=rambi
TEST=manual test with a glimmer.
To test speed, just ran for a while at 400kHz and made sure there were
no i2c errors and the data looked accurate using the lidangle on command.
To test the accelerometers present bit, I used the kernel patch for the
cros_ec_accel driver. First, I verified that without this patch, the kernel
driver throws an error when loading the module. Second, I verified that
with this patch the module was loaded successfully.
Change-Id: I19b8e800748b0d45dc1da6c59118e92b4908ee2f
Original-Change-Id: If931b37bf057df96659852ef9699b3e6029275c7
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187732
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188386
Added rotation of accelerometer data into a standard reference frame
so that the host does not have to know about the orientation of the
sensors.
Also added a calibration routine to calibrate the rotation matrix to
get to the standard reference frame. Cleanup up calibration in the
process to make it more user friendly.
Changed the default accelerometer sampling rate to 100Hz.
BUG=chrome-os-partner:25599
BRANCH=rambi
TEST=Tested the full calibration routine on a glimmer at my desk.
Used 'taskinfo' and verified that the higher sampling rate does not
bog down the EC. I found that the motion sense task is running for
about 200ms every 10 seconds, so about 2% CPU load.
Change-Id: I9ca1a4252f62a54016009c7d5e43b4cb1adf7e1d
Original-Change-Id: Id554511f7cc9549dfc9ed2d6337216bfa639359d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187172
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188385
The BQ24192 driver exports some functions that should be static. Let's mark
them so, mostly so I don't keep finding them when I search through the code
for common functions.
Note that nothing in the ToT branch uses this module anyway.
BUG=chrome-os-partner:23815
BRANCH=ToT
TEST=make buildall -j
Change-Id: I012111a2c9b9b84f0f3bfacc3bdc8804a83116a6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188179
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This was always supposed to be open drain.
BUG=chrome-os-partner:22870
BRANCH=ToT,samus
TEST=manual
Try turning it off and back on again. ;-)
gpioset TOUCHSCREEN_RESET_L 0
gpioset TOUCHSCREEN_RESET_L 1
gpioset TOUCHSCREEN_RESET_L 0
Change-Id: I5e2a49c979294f68b86e2c91d2ccee5f6128ef5a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188045
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Dynamic Power Management enables proper regulation of
the input adapter current set in board.h.
BUG=chrome-os-partner:24933
BRANCH=None
TEST=Power a DUT with a bench supply. Verify the
input current doesn't exceed the input current limit
set in board.h while the system is under load and
charging the battery.
Change-Id: Ie68d92afe0ef89c691f460d120f8574cb17e2c4e
Original-Change-Id: Ida6b05f1d89b21d7cf1553f5e9936360679f8149
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187517
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187911
There's already a host command, but no console command. We should add one.
BUG=none
BRANCH=ToT, Samus
TEST=manual
From the EC console, run
lightbar version
It should display the version number and flags value.
Change-Id: Ide3517c0a71b5d78c4c4d849a952ccc1d908ea23
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187679
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The EC already provided this information, but ectool wouldn't print it.
BUG=chrome-os-partner:23803
BRANCH=samus
TEST=from ec console, 'fanset 0 3000' and 'fanset 1 1000'
ectool pwmfangetrpm -> prints both fans
ectool pwmfangetrpm all -> prints both fans
ectool pwmfangetrpm 0 -> prints ~3000
ectool pwmfangetrpm 1 -> prints ~1000
Change-Id: I19d3081d09edd42c16bf8b0cdbc48ca58d134027
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187454
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Previously, the AP could only set the current wireless power state.
It couldn't determine what the EC would do in S3, nor could it get the
current wireless power state. Extend the wireless command to do so,
and add an EC console command to aid in debugging.
BUG=chrome-os-partner:25655
BRANCH=rambi
TEST=manual; expected numbers are from EC 'wireless' command
AP off -> 0x0, 0x9
AP on -> 0xd 0x9
AP suspended -> 0x9 0x9
AP on -> 0xd 0x9
ectool wireless 0x1 -> 0x1 0x9
ectool wireless 0xd -> 0xd 0x9
ectool wireless 0 0 0 0 -> 0xd 0x9 (and prints 0xd 0x9 to root shell)
ectool wireless 5 -1 -1 0 -> 0x5 0x9
AP suspended -> 0x1 0x9 (doesn't turn on 0x8, just turns off 0x4)
AP on -> 0xd 0x9
ectool wireless 0 0 0 -1 -> 0xd 0x0
AP suspended -> 0x0 0x0
AP on -> 0xd 0x9
Change-Id: I8ead2d4a4423b51ec4f638bf94c62de98726b25c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187273
After each read of the accelerometers, add accelerometer
data to LPC shared memory.
BUG=none
Original-BUG=chrome-os-partner:25599
BRANCH=rambi
TEST=Manual test by reading the LPC shared memory through cros_ec
in the kernel.
Original-Change-Id: If66df3fcb32b5423f4fa7dd471c219a1c4df7095
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186456
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 919ea7fe1f830235ae56829a8ee4435679dec124)
Change-Id: I10525c45e868d0b04aa84c27cab3b6baeda2b0d5
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187435
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added motion sense task to Clapper and Glimmer. This task samples
the accelerometers and calculate a lid angle. Note that as
the machine is rotated towards the hinge angle aligning
with gravity, the lid calculation becomes less trustworthy.
Added a math_util file to hold various mathematical functions
useful for calculating lid angle that may be helpful in other
places.
For each board with accelerometers we need to define some
orientation specific data in board.c. There is a calibration
procedure through the EC console that can be enabled by
defining CONFIG_ACCEL_CALIBRATE. The calibration procedure can
help determine the orientation data required.
For debugging purposes there is a console command to regularly
print to the EC console the accelerometer data and derived lid
angle. The console command can be enabled by defining
CONFIG_CMD_LID_ANGLE.
BUG=none
Original-BUG=chrome-os-partner:24703
BRANCH=rambi
TEST=Ran the calibration procedure on a Glimmer unit, and then
rotated the machine in space. Verified that the lid angle
calculated roughly matched actual lid angle.
Original-Change-Id: I63a5e384b7f6b628b4ea01de49843355fb8d6ebe
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
(cherry picked from commit efb07945a5159fa0e7a746c666b2519ebdca9c22)
Conflicts:
board/clapper/board.c
board/clapper/ec.tasklist
board/glimmer/board.c
board/glimmer/ec.tasklist
Change-Id: Ibc492ef5c11e7084e87f01338c4d7775f9a08c18
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187433
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added accelerometer driver for kxcj9 accelerometers. Currently
the accelerometers aren't being used by anything, but there are
console commands, accelwrite and accelread, to perform transactions.
BUG=none
BRANCH=rambi
TEST=Used EC console commands to test that accelerometers respond
and data looks reasonable.
Original-Change-Id: I6ddcf04ec278adeacb148c19b10c3c296b467954
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184693
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 5e1d2052b034b2400b98b2126243e01397a2ce56)
Conflicts:
board/clapper/board.c
board/clapper/board.h
board/glimmer/board.c
board/glimmer/board.h
Change-Id: If8744ddc3273fc08e29830adfd068dc302dd120a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187432
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously, it would only set the fan RPM, but not actually enable the
fan so it can spin at the requested speed. Compare with setting fan
duty cycle, which always enabled the fan.
BUG=chrome-os-partner:23803
BRANCH=samus
TEST=with fans off, 'ectool pwmsetfanrpm 1000' should spin both fans,
and the ec 'faninfo' command should show both fans enabled.
Change-Id: I37d7fb05309944ab6f98333e2cf3b38ea2dd38e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187386
Reviewed-by: Sameer Nanda <snanda@chromium.org>
This is just an example, demonstrating how a userspace program can access
and control the Pixel lighbar. This change reflects the new unprivileged
access methods. You can run this program to drive the lightbar without being
root.
BUG=chromium:239205
BRANCH=none
TEST=manual
Nothing builds this by default, but you can test it with
cd src/platform/ec
gcc -static util/lbplay.c
then copy a.out to your Pixel and run it (from /tmp, since other directories
are mounted noexec).
Change-Id: I7c07512087c924d16c1c03df6176fba995fcd4f4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186672
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Nyan uses common/charge_state instead. So, fix the dependence.
Since snow/spring/pit are using common/pmu_tps65090_charger, keep them.
BUG=None
BRANCH=Nyan
TEST=build and works fine on Nyan 3.2
Change-Id: I985f7980578ac22602b1fbffa51edf039078bc05
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This speeds up memmove by copying a word at a time.
Ran the unit test on Peppy:
> runtest
...
Running test_memmove... (speed gain: 2156 -> 592 us) OK
...
Ran make buildall:
...
Running test_memmove... (speed gain: 143918 -> 32367 us) OK
...
TEST=Described above.
BUG=chrome-os-partner:23720
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Change-Id: I6a3ac6aed27a404c3bef227b6c886a59414b51d7
Reviewed-on: https://chromium-review.googlesource.com/186020
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Samsung change the temperature range in battery discharing state from (0
<=temp < 100) to (-20 <= temp < 70) from this year. That's why we have to
change the battery_temperature_range structure value as soon as possible
so that our reliability team check the battery.
BUG=chrome-os-partner:25731
TEST=Boot on the pit / pi and then check the battery is working or
not in the oven.
BRANCH=pit
Change-Id: I3289d22176af043e80a881f1626da386e823d857
Signed-off-by: Jaehoon Kim <jh228.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/186040
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This speeds up memcpy by copying a word at a time if source and destination are
aligned in mod 4. That is, if n and m are a positive integer:
4n -> 4m: aligned, 4x speed.
4n -> 4m+1: misaligned.
4n+1 -> 4m+1: aligned in mod 4, 4x speed.
Ran the unit test on Peppy:
> runtest
...
Running test_memcpy... (speed gain: 120300 -> 38103 us) OK
...
Ran make buildall -j:
...
Running test_memcpy... (speed gain: 2084 -> 549 us) OK
...
Note misaligned case is also optimized. Unit test runs in 298 us on Peppy while
it takes about 475 with the original memcpy.
TEST=Described above.
BUG=chrome-os-partner:23720
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ic12260451c5efd0896d6353017cd45d29cb672db
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Reviewed-on: https://chromium-review.googlesource.com/185618
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
