Move calibration in the EC to returns raw value with offset already
applied, as recommended by iio interface.
BRANCH=smaug
TEST=On Samus, with kernel change CL:283103
Check raw value are returned properly.
BUG=chromium:506101
Change-Id: I3dcb4f2fcfff35639e3bfdcc6c1468bdb5e53c45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283161
Reviewed-by: Alec Berg <alecaberg@chromium.org>
1. Added new config option CONFIG_USB_PD_TRY_SRC
2. Added pd_try_source_enable global flag with console command
3. Added bit to pd.flags to indicate Try.SRC states are active
BUG=chrome-os-partner:39724
TEST=Manual samus to samus with the Try.SRC enabled on both and just
one samus. Tested Samus to Honeybuns and Samus to Zinger connections.
BRANCH=TOT
Change-Id: Ifa5d5d82e443f376e546aaf852ff24d92ef04d72
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282052
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
1. Add flash control module for emulation board.
2. Fix system jump for Andes core.
3. Change the physical size of the flash on the chip to 256KB.
note:
1. Only IT839x series supports flash write protect by registers.
2. Static DMA method of flash code only for IT839x series and IT838x Dx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command flashwp and flashinfo
1-a. flashwp enable
1-b. WP asserted and reboot
1-c. flashinfo RO protected now
1-d. WP deasserted and reboot
1-e. No protected
1-f. flashwp disable
1-g. WP asserted and reboot
1-h. No protected
2. console sysjump and sysinfo
2-a. sysjump rw
2-b. jumping to image RW
2-c. sysinfo, Copy : RW, Jumped : yes
2-d. sysjump ro
2-e. jumping to image RO
2-f. sysinfo, Copy : RO, Jumped : yes
3. RO/RW firmware image test
3-a. sysjump rw
3-b. use console command "eflash" to erase RO region,
erase OK and system still work.
3-c. reflash firmware
3-d. sysjump rw, sysjump ro
3-e. use console command "eflash" to erase RW region,
erase OK and system still work.
Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8
Reviewed-on: https://chromium-review.googlesource.com/271390
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
"RO" is a workaround for GP base instructions.
And now we have added "-mno-gp-direct" option in the NDS32 toolchain.
So the compiler would not generate GP base instructions directly,
and we can remove this "RO".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:24378
TEST=console "version" and "gpioget"
Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5
Signed-off-by: Dino Li <dino.li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/281862
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
DP Alternate mode specification defines two bytes in the DP
capabilities payload with respect to pin configs. One that governs
the DFP and the other the UFP. The one that the DP source needs to
examine depends upon whether the UFP is a receptacle or a plug.
Previously we just examined the DFP pin config which was correct for
all UFP plugs but not UFP receptacles. This change fixes that by
examining bit <6> of capability message to determe plug vs receptacle
and in case of receptacle choosing the UFP ping config instead.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chromium:505652
TEST=manual, hoho & apple (UFP_D plugs) still work.
While I don't have a test for UFP_D receptacle partner device reports
following for its DP caps which should now decode correctly.
<31:24> 00 Reserved/SBZ
<23:16> 1C UFP pin config == C, D, E
<15:08> 00 DFP pin config zero
<07:00> C5 <6> == 1 == receptacle
Change-Id: Ib9e3a808828ff6b8c062baf0fc3c23b3da33c2c3
Reviewed-on: https://chromium-review.googlesource.com/282621
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
If flash is being written, any pending hash calculation is likely to
be invalid.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no
read, erase or write errors
Change-Id: I915f8db7998c56fc12e7d85173232882fb7ed80d
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282211
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
When the USB2.0 port is used in device mode, having the D+/D- lines
connected just before resetting the PI3USB9281 (for the 2nd detection
used a BC1.2 debouncing) triggers a misdetection where DCP chargers are
seen as Apple 2.4A chargers.
To avoid this, disconnect the D+/D- lines and let them relax before
triggering the PI3USB9281 reset.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42048
TEST=connect and disconnect a DCP charger to the Smaug type-C port
with the AP running, see it constantly detected as DCP and no Pericom
interrupt storm.
Change-Id: I8f6043439c2c6b52f2689b4947baffe51f62eba8
Reviewed-on: https://chromium-review.googlesource.com/282594
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Take profit of the hardware input current ramping/back-off integrated
in the BQ2589x charger by setting the current limits higher for BC1.2
USB modes and letting the hardware adjust to the actual charger
limitation depending on the VBUS voltage droop.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42045
TEST=Connect a Nexus 9 DCP charger to Smaug and see the input current
adjusted to 1650mA without brown-out, read back the value properly from
the AP:
$ ectool usbpdpower
Port 0: SNK Charger DCP 4958mV / 1650mA, max 5000mV / 1650mA / 8250mW
Change-Id: I348e5ee4980a5652f72f279ab4e3a7126583b093
Reviewed-on: https://chromium-review.googlesource.com/282584
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Use the new TCPC initialization complete bit in alert register to
signal TCPC readiness instead of checking for USB VID to be set.
BUG=none
BRANCH=none
TEST=load on glados, make sure we can boot without battery.
Change-Id: I4b25c973ece0de6dd3f419c5901cff1d8d05ed95
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/282593
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In preparation for adding support for additional USB-C mux chips, add a
new high-level USB-C mux interface usb_mux.c. usb_mux functions are now
called from pd code instead of board-level functions. usb_mux calls down
into a mux chip-specific driver (currently pi3usb30532) or
board-specific drivers which toggle GPIOs (for legacy boards).
BUG=chrome-os-partner:41696
TEST=Manual on Glados in subsequent commit. Verify set() and get()
functions set and return consistent values. Verify that USB SS device
functions when muxes are set to dock or USB. Also, verify that DP
dongle and USB SS device are functional on both PD ports on samus_pd.
BRANCH=None
Change-Id: Ib6477f489310f3be1430585ea09fea26f57e3752
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281435
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Refactor the tcpm/tcpc split such that the tcpm driver implements
the alert functionality since it may be unique for different tcpc
chips.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall. run on samus and glados.
Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281631
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF
interrupt context, causing deadlock and assertion
in __wait_evt().
In the interrupt context it now checks for mutex lock first.
If the mutex is already locked,, it will disable ACPI
interrupts and defer the memmap mutex lock.
Added LPC interrupt disable/enable functions as needed.
Increased deferred function count where needed.
BRANCH=None
BUG=chrome-os-partner:40820
TEST=Test for suspend-resume, cold, warm reboots and
other general stability.
Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Create driver/tcpm/ folder to hold TCPM drivers. Currently the
two drivers are a stub driver which is used when TCPM and TCPC
are on the same MCU and can make direct calls between the two
and the TCPCI driver which implements the standard TCPCI protocol.
BUG=chrome-os-partner:41842
BRANCH=none
TEST=make -j buildall
Change-Id: Ie4d9b36eb33155254f8b87b83861f98a7a80693a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/281630
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify PDCMD task to allow for TCPCs that do not support host
commands.
CONFIG_HOSTCMD_PD is a new config option to be used by TCPCs
that implement our host command protocol such as the PD MCU on
glados and oak. Otherwise, the PDCMD task will not send host
commands and will be used simply to check TCPC interrupt status.
BUG=none
BRANCH=none
TEST=test on glados and samus and make sure we can send host
commands from the EC to the PD and that we can negotiate a PD
contract.
Change-Id: I618badb5db3f9e490ae4eedfdb2a0c54513496ff
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278215
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Changed the alert function to hold the ec_int line until
all of the alert bits are cleared. Added support for the
alert_mask register. In addition, created ec_int_status
variable to distinguish which of 3 ec_int sources is
driving the pd_mcu_int line.
BUG=none
BRANCH=tot
TEST=Tested Zinger to Glados and Zinger to Samus and verified
that it established a power contract in both cases. Did not
test Oak, but put exact same changes in board.c as in glados.
Change-Id: I372e75b8fd5d66a0c01db18b46100b86fd9ac064
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/278256
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add functions and associated test to read/write a 32 bit register
BRANCH=smaug
TEST=Test on smaug with bm160 driver
BUG=chromium:39900
Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277535
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add TCPC support for USB VID register and use that register
from the TCPM side to know when the TCPC is ready. TCPC is
ready when phy layer is initialized and CC ADC channels have
been read.
BUG=chrome-os-partner:40920, chrome-os-partner:41258
BRANCH=none
TEST=load and run glados. verify that glados EC doesn't
start sending TCPC commands until it can successfully
read TCPC VID. verify that we can boot with zinger and no
battery.
Change-Id: Iafbab529a16ff904cdb817901baac5e72e3d7220
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277710
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Initialize CC termination variable based on the default PD role.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=load on glados. test by rebooting PD from PD console with
nothing plugged into the type-C ports. Without this change, the
EC gets stuck in SNK_DISCONNECTED_DEBOUNCE, because the PD defaults
to using the wrong termination and so the PD thinks the CC ADC
readings represent Ra. At this point you have to reboot EC to get
back to normal functionality. With this change, rebooting PD does
not wedge the PD protocol state machine.
Change-Id: I4eb6d881d8fc995be4d6a99ffa69e484141343f2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277666
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:41063
TEST=Enable Software Sync in Coreboot and Depthcharge.
Enable hash computation in EC. Compile EC followed by
Coreboot and program Coreboot followed by EC on a Cyan
system. System should boot to Chrome Login Screen.
BRANCH=none
Change-Id: I4b53e9e55e4da279366eb1283a11a010c52b865f
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276305
Reviewed-by: Shawn N <shawnn@chromium.org>
changes added to support flashrom are:
sysjump support to be able to copy the RO/RW image
and jump to it without causing AP to reboot while
its alreday ON.
LPC init should be reinitialized on sysjump
corrected gpio_set_flags_by_mask to make sure we
update the register only for GPIO_LOW condition and not
all else conditions.
BUG=chrome-os-partner:38103
TEST=commands : flashrom -p ec -w ec.bin
flashrom -p ec -r ec.bin
BRANCH=none
Change-Id: I23892f0378d756052030e73034c3acdd41477e34
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/272000
Reviewed-by: Shawn N <shawnn@chromium.org>
Change TCPC to not sample CC ADC channels immediately after transmit
because we are likely to get a response immediately after transmit
and this could cause us to sample while traffic is on the line and
cause us to record the wrong voltage.
BUG=none
BRANCH=smaug
TEST=test on glados. put a print when TCPM is notified of CC voltage
change. without this CL, we occasionally get a false CC voltage
change. with this change, CC status stays consistent.
Change-Id: I9199a0ed98632b1f26b2b5b98f34928e4de328bf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277296
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When we are going to S5 with a debug accessory plugged, we cannot
transition through the 'PD_DRP_FORCE_SINK' else we would
disable/re-enable the USB muxes triggering disconnections/glitches on
the USB debug console.
So, rework the management of the dual role toggling special case
(used to detect debug accessories) : remove the special DRP state and
re-write the conditions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41399
TEST=on Ryu, connect to the EC console through Suzy-Q and issue
the "apshutdown" command, then see the EC USB console is randomly
disconnected/re-connected or acting up.
Change-Id: Id44a9360a836e7c10a30f5afb2971bc7c3d01a5c
Reviewed-on: https://chromium-review.googlesource.com/277275
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
The case closed debugging feature is using the USB controller, so it
needs to disable the low power STOP mode of the MCU which is
incompatible with USB communication.
As the possibility of doing PD communication when a PD debug accessory
is plugged "re-appeared", just set/use the USB_PD sleep disable bit with
the debug accessory rather than creating a new one.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:41399
TEST=on Ryu, connect to the EC console through Suzy-Q and issue the
"apshutdown" command, then see the EC USB console is still alive.
Change-Id: I8668b28220202ce6419f18cff13d57d410e3e9f3
Reviewed-on: https://chromium-review.googlesource.com/277116
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
We normally do not charge from non-dedicated chargers. The process of
determining whether a charger is dedicated or not involves PD protocol
communication, so it can take some time to reach a determination. If no
battery is attached, the charger is likely our only source of power, so
don't cut it off.
BUG=chrome-os-partner:41258
TEST=Attach donette to glados system with no battery, verify that glados
boots to EC console and doesn't reset or panic.
BRANCH=None
Change-Id: I7c9cfcbd37b37ef16010cf1f246d8fddba6f6283
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277074
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Page Boundary.
If SPI Flash write is at an offset within the page and the length
is greater than remainder of the page, the Flash page gets
corrupted as addressing wraps to the beginning of page and
previously written data gets overwritten. This change splits SPI
Flash writes in such cases into two operations in different pages.
BUG=None
BRANCH=None
TEST=During Software Sync, Depthcharge sends Flash write chunks that
cross page boundary. With this change, the RW parition does not get
corrupted. This can be confirmed by executing a successful
"sysjump RW" after a Software Sync.
Change-Id: I46349eea0d8e927353de7cb55a61e9960291adb6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/275760
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously we supported using a single pi3usb9281 chip, or using two
chips on the same i2c bus behind a mux. Now that we need to support a
third configuration of multiple chips on different busses, it makes
sense to be able to configure the configuration freely at the board
level.
BUG=chrome-os-partner:40920
TEST=Manual on samus_pd. Plug USB charger, verify detection is correct
on both charge ports.
BRANCH=None
Change-Id: I120dcb1c3ceb6f013b92407effcd8cb66e7ffcce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276511
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Change pd_transmit() to wait specifically for the TX complete
event using task_wait_event_mask(). This fixes a bug that if
another event, it will now restore that event instead of
consuming it.
BUG=chrome-os-partner:40920, chrome-os-partner:41290
BRANCH=smaug
TEST=load onto glados and zinger and attach them a bunch of
times and get stable contract with no hard resets.
Change-Id: I36514ea45b5e2b5fd42acdad94e5786da5bd90b6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276745
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The in_stream and out_stream interfaces were a first attempt
at providing an abstraction for multiple stream like devices
(usart, USB, I2C/LPC host interfaces...). But, by baking
the queue into the device it proved to be hard to use and
required additional resources (task or deferred hook) to handle
passing data from one stream to another.
Since then the queue policy and producer/consumer interfaces
have replaced the stream interfaces. This CL removes the old
stream interfaces and updates the only users (deleting the
test echo code from the discovery-stm32f072 board and updating
the mcdp28x0 driver to use the queue interfaces).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ic0d2abf81eafc4fb2e61172540151f2d0ba45caf
Reviewed-on: https://chromium-review.googlesource.com/276163
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Move the task responsible for detection of USB chargers to common code
to reduce code duplication.
BUG=chrome-os-partner:40920
TEST=Manual on samus_pd. Plug USB charger, verify detection is correct
on both charge ports.
BRANCH=None
Change-Id: I362f8b5b51741509e459c66928131f1f6d2a3b1d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276210
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Now that we've removed boards from ToT, also delete board-specific
code used only by the removed boards.
There are still more things to remove (unused charging chips, LED
drivers, COMx support). More CLs coming.
BUG=chromium:493866
BRANCH=none
TEST=make buildall -j
Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276524
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enable charging through debug accessory by setting input
current limit to 3A when debug accessory is detected.
Add new dual-role toggling state for stay sink unless VBUS
is detected, which allows us to detect debug accessory
when we are not normally dual-role toggling.
BUG=none
BRANCH=smaug
TEST=plug suzyQ into ryu in S0 and in S5 and make sure that
we go to the SRC_ACCESSORY state and set charger input
current limit appropriately.
Change-Id: I6262c9d6cd0ae7159f343d36e19d290c2f2e0181
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276368
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add queue_peek_memcpy to peek at queue and move the element using
specific memcpy function.
Also change memcpy prototype argument from void const * to const void*.
BUG=none
BRANCH=none
TEST=Compile and use.
Change-Id: I8c582563e7d204ee5568637f819d63404624faf6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274226
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Add workaround to limit the max input current to 1.5A due to
i2c communication problems at higher currents. Note that this
max should be removed when possible.
This introduces a new CONFIG option to define the maximum input
current limit for a board, as opposed to the already existing
default input current limit.
BUG=none
BRANCH=none
TEST=load on glados, charge with zinger, make sure input current
is set to 1.5A and no recurring i2c errors talking to battery
and charger.
Change-Id: Ib7070772e1bf5475e98a2dc946ae75bf08047b70
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276169
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the PDCMD task to handle PD MCU interrupts, and use it
to trigger the tcpc_alert().
Note this fixes bug on Glados and Oak that could cause watchdog
reset because tcpc_alert() which uses i2c to talk to tcpc was
called from hooks task and can delay tickling watchdog.
BUG=chrome-os-partner:40920
BRANCH=none
TEST=load on glados and plug zinger into both ports many times.
make sure we get a stable contract and no watchdog reset.
Change-Id: I37625fae2ca0057d2ee8fa1eea6974f2d26d1b91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275296
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
sysjump could happen anytime during an I2C transaction. After sysjump and EC
reset, I2C pin will be programmed back as GPIO instead of alternate function,
which will cause the I2C transacation to failed.
MEC1322 I2C also depends on interrupt to handle the I2C transaction, however,
sysjump will disable interrupt, which will cause watchdog timeout/reset since
interupt for I2C transaction are disabled.
BUG=none
TEST=After "sysjump <RO/RW>", "i2cscan" is functional and no watchdog reset.
BRANCH=none
Change-Id: I181084822f0769173c724e48afb59d7099fa1566
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/273710
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
This adds a new task and endpoints to handle large opaque (to the
USB) chunks of data. The expected use case is that the USB
endpoint accepts bytes from the host and passes them blindly to
the blob-handling task. At some point, the blob-handling task may
wish to send bytes back to the host. What those bytes are and
what they mean is determined at higher levels of abstraction.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This CL doesn't enable the blob-handler; it just makes it
available. The next CL will enable and test it.
Change-Id: I6eba8e8010466e71efe9c5e06848b9f403df835f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275131
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Holding the power button is currently the best known way to bring the AP
back to a state where it is shutdown and not powered.
BUG=chrome-os-partner:40826, chrome-os-partner:40677
TEST=Run `apshutdown` on glados, verify that power state machine transitions
to G3 after several seconds. Run `powerbtn`, verify that state machine
transitions back to S0.
BRANCH=None
Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275060
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MOTIONSENSE_CMD_DATA return the value of a sinlge sensor.
BRANCH=none
BUG=chrome-os-partner:39900
TEST=On Smaug, using the new cros-ec-sensors driver,
check sensors data using iio sysfs interface.
Change-Id: I618ff050e0c7b4247ac56cfb0ca25e351270e1d6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274824
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Implement the TCPC RX Detect register and use it for the TCPM to
enable and disable PD communication. When no type-C connection,
disable TCPC RX so that we don't send goodCRC when we are not
ready. Once TCPM establishes a type-C connection, enable TCPC RX.
BUG=none
BRANCH=none
TEST=tested on glados and on samus. On glados, without this change,
sometimes when you plug in zinger, we get into a hard reset loop
because TCPC is sending goodCRC to source cap while TCPM is still
debouncing CC and is not ready. With this change, we reliably form
PD contract.
Also tested enabling and disabling PD comms from the TCPM console
with "pd enable 0|1".
Change-Id: I8c9e696f2597978436f6ceccfe06ffb021c95ea3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274811
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
I'm planning to add functionality to the kernel which periodically
dumps the EC console log and concatenates it so we can use it in bug
reports and feedback. However, stitching together logs collected
using the existing SNAPSHOT/READ commands is difficult. This adds a
new version of READ which acts mostly the same but will only give you
the difference between the two most recent snapshots when you pass
the corresponding argument.
BRANCH=ToT
BUG=chromium:492721
TEST=On samus with kernel interface, cat
/sys/kernel/debug/cros_ec/console_log
and verify that the most recent bit of the log is printed,
use spammy commands like 'accelinfo on' and make sure nothing breaks,
check that 'ectool console' behavior has not changed
Change-Id: Ib8216caa917715820c3e265400f0db2125e8808b
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273581
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add TCPM on EC side and TCPC on PD side to allow PD
communication. Enable PD communication on port 0.
BUG=none
BRANCH=none
TEST=load on oak. plug in hoho on port 0, and make sure
we successfully negotiate a PD contract. (note: you have
to manually enable 5V VBUS right now)
Change-Id: I0ce7c016545bc56c5e10f66b49b73722187f12dc
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271829
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Commit-Queue: Sheng-liang Song <ssl@chromium.org>
When CONFIG_MKBP_EVENT is enabled, the current code is incorrect because
we have a race condition when sending a new event (we force first the
interrupt, then send the actual event content to the mkbp event
framework which forces again the interrupt level).
If the software still called EC_CMD_MKBP_STATE while CONFIG_MKBP_EVENT
is enabled, this will kill the interrupt as soon as the FIFO is empty
even though other events are pending in order to be backward compatible
with firmware using the interrupt has a hint when polling the keyboard.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:33194
TEST=make buildall
fiddle with keyboard on Oak.
Change-Id: Iafaf4174124934328c4a0172adeca651e5551f28
Reviewed-on: https://chromium-review.googlesource.com/274070
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Fix tcpc_alert() so it can handle multiple alert bits. This is
needed since the initial version of tcpc_alert() is read/clear
and so we need to service all bits or else it will get lost.
BUG=none
BRANCH=none
TEST=test on glados. see multiple alert bits and handle both
of them.
Change-Id: I4d2a19a5d5d6f85cad3d67a96217d65e6e65715c
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274084
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
