This fixes a rare problem in which the EC could shutdown due to
a false over-temperature when entering S0 on Haswell architectures.
The fix involves requiring two valid reads of the temperature
sensor (out of the last 4 readings) in order to report it.
BUG=chrome-os-partner:24204
BRANCH=none
TEST=See bug report for a patch that recreates the bug at a
significantly higher rate then it would occur on its own. Using
that patch, I implemented this fix, and made sure that there
were no false over-temperatures reported.
Change-Id: I0454eca1b96fd2fa1833b080026ed8f1caeeddc4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177963
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds the driver for MEC1322 I2C controller.
BUG=chrome-os-partner:24107
TEST=Hook up TSU6721 to eval board. Do the following tests:
- 'i2cscan' and see TSU6721.
- Read device ID register and get correct value.
- Add 3 tasks randomly doing I2C read and writes. Check there is
no error.
BRANCH=None
Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178591
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Move the non-core dependent code out of core/$(CORE) directory to
common/ directory.
Put all panic printing code in common/panic_output.c
Put timer management code in common/timer.c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23574
TEST=./util/make_all.sh
use "crash divzero" and "panicinfo" on Link.
Change-Id: Ia4e1ebc74cd53da55fe24f69e96f39f512b9336d
Reviewed-on: https://chromium-review.googlesource.com/178871
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This adds the driver for PWM duty cycle based and RPM based fan control.
BUG=chrome-os-partner:24107
TEST='fanset 5000' and fan spins up.
'fanset 8000' and fan spins faster.
'fanset 0' and fan stops.
'fanduty 30' and fan spins up.
'fanduty 50' and fan spins faster.
'fanduty 30' and fan slows down.
'fanset 6000' and fan goes to ~6000 RPM.
Unplug fan power and see 'fan 0 stalled'.
Plug power back and doesn't see stall warning anymore.
BRANCH=None
Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178402
With this, basic host command functionality is working.
We don't have the correct description of LPC memory BAR register yet, so
we have to use EMI (embedded memory interface) module for 0x800-0x9ff
region. This requires a slightly different protocol, which is in the
next CL.
BUG=chrome-os-partner:24107
TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working.
BRANCH=None
Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178250
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If CONFIG_WATCHDOG_HELP is defined, a 16-bit timer is used as an
auxiliary timer to interrupt us 50ms before the watchdog expires. When
the auxiliary timer expires, the stack trace is printed. Watchdog then
expires 50ms after and reboots the system.
BUG=chrome-os-partner:24107
TEST=Define CONFIG_WATCHDOG_HELP, and see stack trace on 'waitms 2000'.
TEST=Undefine CONFIG_WATCHDOG_HELP, and check watchdog still works
without printing stack trace.
BRANCH=None
Change-Id: I2555d3f86a15c83bb03a00c6807f77d9dddaf333
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178284
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds a PWM driver, which now generates 30KHz PWM output. Note that
this is different from fan control module driver.
BUG=chrome-os-partner:24107
TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output.
- Set to active high and 30%, see 30% duty PWM at ~29.1KHz.
- Set to active low and 20%, see 80% duty PWM at ~29.1KHz.
BRANCH=None
Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178391
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
So far we can only reliably sense a watchdog reset, but this
saving/checking reset cause will at least make 'ap-off' flag work.
BUG=chrome-os-partner:24107
TEST='waitms 2000' and see reset cause = 'watchdog'
TEST='reboot ap-off' and see reset cause includes 'ap-off'
TEST='reboot preserve' and see previous reset cause is preserved.
BRANCH=None
Change-Id: Id47a72d615489c9d9cd0b8761cfa699f08c724df
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178277
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This will be used for saving data across reboots.
BUG=chrome-os-partner:24107
TEST=Enable scratchpad command and check value is preserved across
watchdog reboot.
BRANCH=None
Change-Id: Ifd68541a3f842c466b6ff49bcc654c92df48aac6
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178276
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
DUMMY() is ugly and DUMMY_int() makes repo complain. Replace them with
explicit functions.
BUG=chrome-os-partner:24107
TEST=Build mec1322_evb
BRANCH=None
Change-Id: I155b769c12cafaf432c7f53fd46806feada3cfca
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178275
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
iRESET_OUT must be deasserted before the host can boot, and it's also
the gating source of the internal nSIO_RESET signal. There is a delay
between deasserting iRESET_OUT and nSIO_RESET inactivated, so let's
deassert iRESET_OUT as early as possible.
BUG=chrome-os-partner:24107
TEST=Boot EVB and check iRESET_OUT value
BRANCH=None
Change-Id: I6647da00567e2651c2b49e1e767adee2d5276493
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178171
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With this, we can now define and trigger interrupt on GPIO status.
BUG=chrome-os-partner:24107
TEST=Test GPIO036 with following cases:
- Pulled up and rising edge trigger. Pull down externally and
then release.
- Pulled up and falling edge trigger. Pull down externally.
- Pulled up and both edge trigger. Pull down and then release.
- Pulled up and low level trigger. Pull down externally.
BRANCH=None
Change-Id: Id9bfd2ba9dd8a75bcf2c5691ffe2aa6518076925
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177560
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This script is needed for packing EC binary into SPI flash for MEC1322.
This includes adding tag and header at appropriate location and signing
the image. Signing key, for obvious reason, is not included here until
we are sure what key we want to check in.
BUG=chrome-os-partner:24107
TEST=Build and boot on eval board
BRANCH=None
Change-Id: I92db7d2ba2c76c14a9c6611a04dbd6a2c3eb8d83
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177324
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This implements the basic watchdog support. For now, the watchdog
doesn't warn us before it expires. This functionality will be added
later using a basic timer.
BUG=chrome-os-partner:24107
TEST='waitms 700' and the EC stays alive.
TEST='waitms 1200' and the EC reboots.
BRANCH=None
Change-Id: I1cc48978ed09577ae88cc2f7a6087867e5854973
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177736
For historical reasons on LM4, we defined GPIO_INT_F_BOTH separately
from GPIO_INT_F_RISING and GPIO_INT_F_FALLING. This means that the
code has weird checks like BOTH || (RISING && FALLING), which have
propagated in error-prone ways across the other chips.
Instead, explcitly define BOTH to be RISING|FALLING.
Ideally, we would have called it GPIO_INT_EDGE to match
GPIO_INT_LEVEL, but changing that now would be a big find-replace.
Which might still be a good idea, but that is best done in its own CL.
BUG=chrome-os-partner:24204
BRANCH=none
TEST=build and boot pit, spring, and link; that covers STM32F, STM32L, and LM4.
Change-Id: I23ba05a3f41bb14b09af61dc52a178f710f5c1bb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177643
Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
These boards are unloved and unsupported. They'll never grow up to be
laptops, and hardware is increasingly hard to come by.
Comparable functionality is available in the other, more-loved boards.
Removing these boards speeds up util/make_all.sh by 40%. (If you're
not running that before every upload, you should be...)
BUG=chrome-os-partner:24062
BRANCH=none
TEST=build all remaining platforms and pass unit tests
Change-Id: I4d8a49e4d52d7393471f1b1cbef059c8db4a4f77
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177373
This adds include/dptf.h to define the DPTF interface functions.
As the first DPTF feature, it also adds a register to the EC's ACPI
interface block. Register 0x04 is used to get and set the fan's target duty
cycle, as a percentage value. Writing a 0 to this register will set the
target duty cycle to 0, writing a 100 (0x64) will set it to 100%. Writing
any other value will return the fan control to the EC, rather than driving
it manually from the host.
Likewise, reading from this register returns the current fan target duty
cycle, as a percentage. If the EC is controlling the fan automatically, the
returned value will be 0xFF.
BUG=chrome-os-partner:23972
BRANCH=none
TEST=manual
You can monitor the fan state from the EC console with the "faninfo"
command. From the host side, test this interface from a root shell.
Read fan duty:
iotools io_write8 0x66 0x80
iotools io_write8 0x62 4
iotools io_read8 0x62
Set fan duty to 100%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 100
Set fan duty to 50%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 50
Set fan duty to 0%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 0
Set fan control back to automatic:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 -1
Change-Id: I91ec463095cfd17adf452f0967da3944b254d558
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177423
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On certain boards it's no feasible to use the SERIRQ
method for generating the kebyboard interrupt. To that
end provide CONFIG_KEYBOARD_IRQ_GPIO option which
specifies the negative edge-triggered gpio for the
keyaboard interrupt.
BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi using this option. Keyboard
works in kernel with interrupts for i8042 device.
Change-Id: I64f7e9530841c184d2a33821126ec446c96bb0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177188
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is the initial commit of mec1322 support. This includes:
- Basic GPIO driver. Interrupt not supported yet.
- Microsecond timer
- UART driver
The script to pack the firmware binary will be checked in in
following-up CL.
BUG=chrome-os-partner:24107
TEST=Build and boot on eval board
BRANCH=None
Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175716
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Not sure why, but it doesn't seem to work consistently on my Spring.
Transmit works fine, but on some boots receive doesn't seem to pick up
received characters. Rather than churning Spring to fix this, just
disable receive DMA - which doesn't benefit Spring much anyway,
because it never downclocks its core to 1 MHz.
BUG=chrome-os-partner:24141
BRANCH=none
TEST=Boot Spring; typing into console works. After 'apshutdown', typing still
works (including arrow keys). Repeat 20 times. Repeat on Pit.
Change-Id: I5d9875b583c8e2a38b9070c4dfa31fd5a982a144
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177352
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Otherwise UART output gets garbled because there's a delay between
changing core clock and the UART divider. Fortunately, the glitch is
cosmetic and doesn't affect proper EC operation.
BUG=chrome-os-partner:23982
BRANCH=none
TEST=power on, power off on pit or nyan --> no UART glitch
Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177087
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
The LPC module has a dedicated control for SCI#.
However, certain situations require a dedicated
GPIO for asserting the SCI# signal.
Introduce CONFIG_SCI_GPIO to meet this requirement.
BUG=chrome-os-partner:24003
BRANCH=None
TEST=Built and booted rambi with dependency change. 'lidclose' and
'lidopen' cause ACPI interrupts.
Change-Id: I34c5f0ba5ff60151972921f251c71d3769a9ef8b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We read a counted string (byte 0 = count, bytes 1 - count = chars) and
convert it to a null-terminated string. Since both have a 1-byte
overhead, we can use the destination buffer instead of using a
stack-based buffer.
BUG=chrome-os-partner:23928
BRANCH=none (pit is affected, but battery console command isn't used on
end user systems)
TEST=battery command shows correct strings (SDI / 4302D40 / LiP), and doesn't
stack overflow.
Change-Id: Ic0f111cde2d57b41d6ce9287e0c771acc09a8869
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176116
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Temporary fix to the bug in which we miss wake events when in deep
sleep with the LFIOSC (32kHz) clock and the EC is cold. This fix
involves simply using a faster clock, 250kHz, when in low speed
deep sleep. This fix consumes more power but solves the bug.
Renamed EC console command dsleepmask to dsleep.
BRANCH=none
BUG=chrome-os-partner:23678
TEST=Go in to low speed deep sleep by going into either S3 or G3
and letting the EC console timeout. Then freeze-spray the EC chip.
Wake up the EC via the console and make sure that the idlestats
show that we have not missed a deadline.
Change-Id: I4f9844f1937bc8c95cf1540502f7d8fb4cbc097e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175614
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fan no longer needs a special priority to wait for the host memmap to
become available, since LPC inits earlier.
I2C and PECI don't need explicit ordering on freq change.
Thermal now uses the explicit prio for temp sensors done.
Commented hook test.
BUG=chromium:314768
BRANCH=none
TEST=boot link; enable/disable PLL; verify fanset and temps commands work afterwards.
Change-Id: I71766614dff2950dd307acd0635405e6b59e330a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175601
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cortex-M3 and Cortex-M4 are not using exactly the same instruction set.
Cortex-M3 is using ARMv7-M ISA which is a subset of the ARMv7E-M used by
the Cortex-M4 core (even though the delta is small).
Let's restrict each core to the right subset of instruction by pushing
the -mcpu/-march configuration in the chip specific area.
Note: GCC 4.8 is now using the full ARMv7E-M instruction set and will emit
"undefined instruction" on Cortex-M3 without this patch.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:314194
TEST=build *and* run on Spring and Link.
Change-Id: I2f9b87fec689e8d1097809cab437a2bd32dfa194
Reviewed-on: https://chromium-review.googlesource.com/175487
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This adds explicit "int fan" args to the exported functions from
common/fan.c: fan_set_percent_needed() and fan_percent_to_rpm(). Within that
file, multiple fans are handled independently.
This is not complete, though. Host commands and sysjump support still only
handle a single fan, so at the moment multiple fans are treated identically
in those cases.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
All boards build, "make runtests" passes.
On a multi-fan system, the EC command "faninfo" displays multiple results:
> faninfo
Fan 0 Actual: 0 rpm
Fan 0 Target: 0 rpm
Fan 0 Duty: 0%
Fan 0 Status: 0 (not spinning)
Fan 0 Mode: rpm
Fan 0 Auto: yes
Fan 0 Enable: yes
Fan 1 Actual: 0 rpm
Fan 1 Target: 0 rpm
Fan 1 Duty: 0%
Fan 1 Status: 0 (not spinning)
Fan 1 Mode: rpm
Fan 1 Auto: no
Fan 1 Enable: no
>
and the "fanduty", "fanset", and "fanauto" all require the fan number as the
first arg:
> fanduty 0 30
Setting fan 0 duty cycle to 30%
> fanset 1 2000
Setting fan 1 rpm target to 2000
> fanauto 0
> fanauto 1
On single-fan systems, there is no visible change.
Change-Id: Idb8b818122e157960d56779b2a86e5ba433bee1b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175368
Reviewed-by: Randall Spangler <rspangler@chromium.org>
All the current data buffers *are* aligned, but we should check anyway
just to avoid unpleasant surprises in the future. This matches what
we do on STM32L. On STM32F, we copy a byte at a time so alignment of
the source data doesn't matter.
BUG=chrome-os-partner:9526
BRANCH=none
TEST=manual
flasherase 0x20000 0x1000
flashwrite 0x20000 0x200 -> succeeds
flashwrite 0x20201 0x200 -> fails
Change-Id: Id1a0fd8f6871e1fcdc3f55ec25eea40f33b5214c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175532
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Fixed bug in which two different tasks reading two different ADC
channels could interfere and cause the ADC clock to get disabled
when a read is still in progress, thus causing a reboot.
Added a runtime assert to verify that developers don't sample the
same ADC channel from multiple different tasks, which could cause
hard to trace reboots.
BRANCH=none
BUG=chromium:313872
TEST=1) Added console command to continuously read an ADC channel not
read anywhere else. Verified that when running this console command
I could reproduce the bug every few minutes.
2) Wrote code in adc.c to protect the ADC clock resource.
3) Ran console command from step 1 for ~2 hours with no reboots.
Change-Id: Ic1905dde12871a4b93957702f7f31a25a2762bb4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175404
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update comments with more info, or remove if no longer applicable.
No code changes.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I5b56eeb500bc0f00e84e91ef99684f4b1b310972
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175418
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add bug links, reword, or remove as applicable.
No code changes, just comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175326
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add bug references. Remove one assert that can no longer be triggered.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I3f4d2e4f2f3343a8d0531cb0715d151eaa4d0b50
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175293
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Remove comments if no longer applicable, or assign bug numbers if they
still are. Tidy some debug output. No code changes other than the
debug output.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms, pass unit tests
Change-Id: I2277e73fbf8cc93f3b1b35ee115e0f2f52eb8cf9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Instead of just configuring fan support as yes/no, we'll use it to specify
the number of fans on the board. Undefined (not zero!) means no fan support
at all.
Syntax change only. No new functionality.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
make runtests, build all platforms, build and test on Link.
Change-Id: Iff65efa69e05f3e1a54fdc2a8da9001b4e8487ca
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175150
This looks like a lot, but it's really just moving the non-board-specific
stuff from chip/lm4/fan.c into common/fan.c, updating the appropriate
headers, and renaming functions to better match the new location.
This is entirely code refactoring and renaming. No new functionality.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
make runtests, build all platforms, build and test on Link.
Change-Id: I7dc03d6732bad83cf838a86600b42a7cff5aa7aa
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175012
All hibernate register writes must wait for the WC bit. When we're
enabling the RTC alarm, it's important to wait for the WC bit
afterwards, too, or else we could go into deep sleep before the write
to HIBIM is committed.
Also make sure that the normal hibernate() path enables the RTC alarm
if it has a timeout. This bug wasn't noticed until the low-power idle
code called system_reset_rtc_alarm(), since before then HIBIM was
initialized to 1 and just stayed there.
BUG=chrome-os-partner:23678
BRANCH=anywhere we use low power idle (wolf/leon, too)
TEST=with hacked firmware, note that HIBIM=1 just before the wfi
instruction in chip/lm4/clock.c
Change-Id: Ie01b106ac6a6c5894811f9a333715b22ef896f82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175013
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This chip returns ver/family/partno = 0x10de, as indicated by the
datasheet. Also switch the identification code to use a switch
statement rather than re-reading the DID1 register in if-then-else.
BUG=chrome-os-partner:23679
BRANCH=none (maybe haswell branches, but it's largely cosmetic)
TEST=version command on rambi identifies the chip as ti tm4e1g31h6zrb B1
Change-Id: I4a3748413de65d3116feb7c444f5a2af5953eecd
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175008
Reviewed-by: Vic Yang <victoryang@chromium.org>
On the LM4, all pwm functions are implemented through hardware "fan"
modules. This change abstracts the hardware fan stuff from the higher level
pwm and fan control logic. Those are still chip-specific at the moment, but
may be moved into common with a future CL.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
Code refactoring only, no new behavior. All tests build and pass, and I
tested on Link with some manual pwm and fan commands on the EC console.
> fanduty 30
> faninfo
Should report ~4500 RPM
> fanset 7000
> faninfo
Should report ~48% duty cycle.
> fanauto
Back to automatic control.
> kblight 0
> kblight 10
> kblight 50
> kblight 100
Keyboard backlight should glow appropriately.
Change-Id: I7558f36b2626e555fc8dabdd12660fa484a93b7f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174991
Reviewed-by: Randall Spangler <rspangler@chromium.org>
QEMU tests served us well, but it has been more and more difficult to
maintain as we now have more chips and use more functionality from each
EC chip. With emulator tests in place to test common code and hardware
test to test per-chip/per-board drivers, it's time to remove QEMU tests
to simplify our code base.
QEMU tests that are covered by other emulator tests are removed
completely; tests that are not covered are left alone for now to
preserve the test logic.
BUG=chrome-os-partner:18343
TEST=util/make_all.sh
BRANCH=None
Change-Id: I5a4dd2f5ac42f7f66f86fdce0b62dbd2c65bf66a
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174669
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To conform to our mutating naming conventions, let's rename the
chip-specific PWM header file to have the string "_chip" in it.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I6584be8e54fd24c8638559817e150c707bc0edb5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174884
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reset the DMA status after the end of the conversions,
else we will exit too early at the next call of the function and the
values before they are actually transfered.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run "adc" command several times and always see proper value for
each ADC.
Change-Id: I7ad335fffa2da34a4b715e9f0c9927bf06baef8f
Reviewed-on: https://chromium-review.googlesource.com/174397
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Changed ADC clock gating to disable the ADC module to conserve power,
and only enable it when needed. This saves about 15% of the power
consumed by the EC when the AP is running.
BUG=none
BRANCH=none
TEST=Run the ADC stress test. This runs 2000 consecutive ADC
reads of all the channels and verifies that the ADC module
successfully records the samples. Note that when running this
test make sure all other calls to read an ADC channel are
disabled because the ADC read function does not protect
against different tasks accesses.
Change-Id: I9ca3671d8cf68e09d21c9c2594856f9c08476398
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174580
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, it was really confusing whether I2C_PORT_HOST meant the
port where the EC was the master, or the port used to talk to the AP.
No functional changes, just a global find/replace and some tidying of
unused comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: Ia591ba4577d3399729556e0234ba0db3a0e3c5ea
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174546
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Device-specific headers belong in driver/ or chip/. The include/
directory should be for common interfaces.
Code should not normally need to include driver-specific headers. If
it does, it should use the full relative path from the EC project root
(for example, drivers/charger/bq24715.h).
Change-Id: Id23db37a431e2d802a74ec601db6f69b613352ba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173746
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The EC LPC implementation guarantees that the status byte will have at
least one zero bit, so there's no need to scan the parameter space as
well. Removing this unneeded check will slightly speed up ectool.
BUG=chrome-os-partner:10963
BRANCH=none
TEST=on an x86 chromebook (e.g. link), ectool hello still works
iotools io_read8 0x200 && iotools io_read8 0x204 -> not both 0xff
Change-Id: Ic02ca0ee686ab10e50093807717ec638aaa468c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174059
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
