Sometimes the toolchain tries to put a relocation which is not suitable
to access variables in a read-only section.
The nds32 gcc uses GP-relative signed 17-bit relocation to access
variables stored in .rodata (eg lwi.gp $r0, [ +gp ])
That's wrong since $gp is pointing in the middle of .data and .bss in
the SRAM, while .rodata is sitting in flash.
Since on IT8380, the flash is at 0x00000 and the SRAM is at 0x80000
(512kB further), the linker will fail trying to create the signed 17-bit
relocation (it detect that it needs to truncate it)
Force the compiler to put another relocation as a workaround for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:24378
TEST=./util/make_all.sh ; make BOARD=it8380dev
check "version" and "gpioget" on spring, link and it8380dev.
Change-Id: Ife50adf3a26be28f113292f73a1a70e8d74b5d8c
Reviewed-on: https://chromium-review.googlesource.com/176913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
When we are detecting Apple charger type, we disable TSU6721 interrupt.
This, however, doesn't create a race condition, because any pending
interrupt fires immediately after we re-enable TSU6721 interrupt, and in
turns schedules charger task. As a result, charger task gets waken right
after it finishes its current iteration.
As for overcurrent detection, the current algorithm seems to do a good
enough job.
BUG=chrome-os-partner:23743, chrome-os-partner:23744
TEST=None
BRANCH=None
Change-Id: Ib3a6d562a305020ef5413e2a493e4163a6e70954
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179303
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The "kbpress" command had a few issues if you wanted to reliably use
it for automation. Specifically it was not possible to guarantee how
much time would pass between the press of a key and the release of a
key. Sometimes you might press and release before the key was
officially "there" and sometimes you might get a press and hold of a
key.
Fix this:
1. Make it so that kbpress with no press/release parameter gives a
press and release (and guarantees that the press / release will
actually take effect).
2. Make it so that kbpress guarantees that when it finishes that the
key has actually been pressed or released.
BRANCH=pit
BUG=chrome-os-partner:24249
TEST=kbtype is (https://chromium-review.googlesource.com/178680) reliable
TEST=make -j32 BOARD=bds tests && make BOARD=bds runtests
TEST=Pick Ibe00a796bde7d06416889b621359671a2f68e162 and test.
Change-Id: Ia213ab2e8d8da273e3ac4876d97d5452df88f47d
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 247650ecc90385417f5dcb2d60bb6ae1e5cfa32f)
Reviewed-on: https://chromium-review.googlesource.com/179325
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It worked on Link because the fan number and the fan channel were both 0.
Samus has two fans, connected to different GPIOs.
In the EC's ACPI interface block, register 0x04 is used to get and set the
fan's target duty cycle, as a percentage value. Writing a 0 to this register
will set the target duty cycle to 0, writing a 100 (0x64) will set it to
100%. Writing any other value will return the fan control to the EC, rather
than driving it manually from the host.
Likewise, reading from this register returns the current fan target duty
cycle, as a percentage. If the EC is controlling the fan automatically, the
returned value will be 0xFF.
BUG=chrome-os-partner:23972
BRANCH=samus
TEST=manual
You can monitor the fan state from the EC console with the "faninfo"
command. From the host side, test this interface from a root shell.
Read fan duty:
iotools io_write8 0x66 0x80
iotools io_write8 0x62 4
iotools io_read8 0x62
Set fan duty to 100%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 100
Set fan duty to 50%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 50
Set fan duty to 0%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 0
Set fan control back to automatic:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 -1
Change-Id: I3a133b0b16e2a5e1ce04b16cb2bf035a04a83daf
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179373
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This fixes a rare problem in which the EC could shutdown due to
a false over-temperature when entering S0 on Haswell architectures.
The fix involves requiring two valid reads of the temperature
sensor (out of the last 4 readings) in order to report it.
BUG=chrome-os-partner:24204
BRANCH=none
TEST=See bug report for a patch that recreates the bug at a
significantly higher rate then it would occur on its own. Using
that patch, I implemented this fix, and made sure that there
were no false over-temperatures reported.
Change-Id: I0454eca1b96fd2fa1833b080026ed8f1caeeddc4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177963
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, per-board defines use mixed case (BOARD_pit). This causes
the presubmit script to complain because that's a style violation.
Using --no-verify to bypass that also allows other style violations to
creep in.
This change adds uppercase variants (BOARD_PIT). It also adds a CORE_
define with '-' changed to '_', since CORE_cortex-m isn't a valid
symbol but CORE_CORTEX_M is (so now we can #ifdef CORE_CORTEX_M).
This does not remove the old mixed-case defines yet, nor does it
find/replace them in the C source files. This is intentional, so this
change can be cherry-picked into branches without needing to change
files in the branch that may have picked up new #ifdefs.
I will rename the constants in the C source files and remove the old
mixed-case defines in a follow-on CL, which should not need to get
picked into existing branches.
BUG=chromium:322144
BRANCH=none (but might need it if you later cherry-pick something with
an uppercase #ifdef BOARD_FOO
TEST=Build each board with V=1 option: 'make V=1 BOARD=foo all tests'.
Check that the compile command line has both mixed-case and
uppercase defines. Check that per-board tests from test/build.mk
were built (for example, BOARD_PIT should compile kb_scan and
stress, and BOARD_SAMUS should build none of them).
Change-Id: I5eb0d1fe57f1c694d7449e5f148e2f13fb290a39
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179205
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
BRANCH=None
TEST=Manual. Run the following console commands:
g781 - verify temps and status look sane.
temps - verify local and remote values for the 781 are listed
g781 settemp 0x05 80 - verify local high alarm set to 80C
g781 setbyte 0x09 0x80 - verify config register is 1000 0000
Change-Id: Ia437647fd052295dfd8901c2ef241ff69c0d950e
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179152
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The samus lightbar uses different LEDs from Link. Adjust the per-color
current limits accordingly. Also swizzle the layout, since LEDs 0/1 and 2/3
are swapped.
BUG=chrome-os-partner:24405
BRANCH=samus
TEST=manual
The colors were ugly and weird. Now they should be pretty and Googley.
Change-Id: I19f317243ff46852628b8b28f2bf6f5e02c6e631
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179160
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This allows local and remote temp values to be added
to a board's list of temp sensors. It also adds a
'tmp432' EC console command to query temps
and set alert thresholds. Fractional degrees are not
supported. DPTF support is not addressed.
BUG=chrome-os-partner:23985
BRANCH=none
TEST=Add tmp432 support to a board with the sensor
then run the 'tmp432' and 'temps' EC console commands.
Signed-off-by: Dave Parker <dparker@chromium.org>
Change-Id: Ifee47cf4d4cf5eedef9ef2bfa2149f183f1d7a7b
Reviewed-on: https://chromium-review.googlesource.com/178688
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dave Parker <dparker@chromium.org>
Tested-by: Dave Parker <dparker@chromium.org>
This adds the driver for MEC1322 I2C controller.
BUG=chrome-os-partner:24107
TEST=Hook up TSU6721 to eval board. Do the following tests:
- 'i2cscan' and see TSU6721.
- Read device ID register and get correct value.
- Add 3 tasks randomly doing I2C read and writes. Check there is
no error.
BRANCH=None
Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178591
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Move the non-core dependent code out of core/$(CORE) directory to
common/ directory.
Put all panic printing code in common/panic_output.c
Put timer management code in common/timer.c
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23574
TEST=./util/make_all.sh
use "crash divzero" and "panicinfo" on Link.
Change-Id: Ia4e1ebc74cd53da55fe24f69e96f39f512b9336d
Reviewed-on: https://chromium-review.googlesource.com/178871
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Remove jumped_to_image check in system_run_image_copy because it's redundant.
disable_jump will be set by VbExEcDisableJump explicitly, whether the EC stays
in RO or jumps to RW.
TEST=Built and booted Peppy. Ran flashrom from user space and verified
the EC firmware was updated after reboot.
BRANCH=none
BUG=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: If1a3cf6158b3bc97c965298d2ab958b5fa7a5d7e
Reviewed-on: https://chromium-review.googlesource.com/172651
Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Add a new pin PMIC_THERM_L (PA1) since AP_RESET_L (PA15) is removed.
To force shutdown, drive PMIC_THERM_L to low (default high) for 32us.
Also rename set_pmic_pwrok() -> set_pmic_pwron(). And add a debounce time
for PMIC_PWRON_L pin.
BUG=chrome-os-partner:24206
BRANCH=nyan
TEST=Verified on the frank's rework board.
'power off' shutdowns the AP immediately.
'reboot' reboots the EC and resets the AP as well.
'sysjump RW' still keeps AP alive.
Change-Id: I8643e19081a824e1f6adc812dfad0269222db8ea
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178631
This adds the driver for PWM duty cycle based and RPM based fan control.
BUG=chrome-os-partner:24107
TEST='fanset 5000' and fan spins up.
'fanset 8000' and fan spins faster.
'fanset 0' and fan stops.
'fanduty 30' and fan spins up.
'fanduty 50' and fan spins faster.
'fanduty 30' and fan slows down.
'fanset 6000' and fan goes to ~6000 RPM.
Unplug fan power and see 'fan 0 stalled'.
Plug power back and doesn't see stall warning anymore.
BRANCH=None
Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178402
We are using EMI module instead of LPC memory transaction. This requires
a different protocol for accessing mapped memory from host. For easier
development, let's add a new comm-mec1322.c until we can switch back to
LPC memory transaction.
BUG=chrome-os-partner:24280
TEST=ectool version
TEST=util/make_all.sh
BRANCH=None
Change-Id: Id8914d0413561991d3e46bef7e3fe76c4f8b83e4
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178251
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With this, basic host command functionality is working.
We don't have the correct description of LPC memory BAR register yet, so
we have to use EMI (embedded memory interface) module for 0x800-0x9ff
region. This requires a slightly different protocol, which is in the
next CL.
BUG=chrome-os-partner:24107
TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working.
BRANCH=None
Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178250
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Nyan EC supports 2 different boards: Venice2 and Norrin. Venice2
uses 2S battery, and Norrin uses 3S battery. This CL is to support
2 different battery types (2S or 3S) automatically at init time by
reading battery's MANUF_NAME, DEVICE_NAME and DESIGN_VOLTAGE from
Smart Battery Interface to determine which battery type to use.
To workaround the problem that battery may not be attached at init
time, a patch is added to call battery_get_info() in PWR_STATE_INIT
state to get the current battery info. Note the battery info is only
determined once.
BUG=none
BRANCH=nyan
TEST=tested on Vencie2 with 2S battery and on Norrin with 3S battery
attached at init time and made sure correct battery info are
installed;
tested on Venice2 and Norrin without battery at init time, then
attached 2S or 3S battery and made sure correct battery info are
installed.
Change-Id: I135909c7fe1e1dfdb0f706e0eadba6e904b6221e
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178088
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This allows boards to detect the battery and return the correct temp
ranges, which will be needed for upcoming boards.
In the board-specific implementations, it's pretty much just moving
the fields from one const struct to another, so the impact is minor.
BUG=chrome-os-partner:24310
BRANCH=none
TEST=build all platforms; verify pit and rambi still charge
Change-Id: I7be075b3abb4039577f6362316adc1860c121d5c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178424
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Due to the way wireless_enable works this was resulting in
WLAN_OFF_L going low briefly on S0->S3->S0 transitions.
BUG=chrome-os-partner:23752
BRANCH=none
TEST=emerge-samus chromeos-coreboot-samus
Change-Id: I4bb02b6e9acf97d501af8c40c455c9f88ffe35ee
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178422
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Smart batteries can report capacity in mAh or 10mW units. We forced
the units to mAh in charge_state.c's main loop, but that doesn't
guarantee that they're actually set before the capacity is read. It's
cleaner to check the capacity reporting mode when actually reading the
capacity.
BUG=chrome-os-partner:20881
BRANCH=none
TEST=battery command reports the same capacity data before/after change
(on rambi, design=2940 mAh)
Change-Id: I4a4c80eaade72bb09627d5d65693c097e264a992
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176154
The charge state machine asks for all of this stuff at the same time
anyway. Bundling it into a single function removes a number of
redundant (and painfully slow) I2C reads.
Also refactor the battery debug command so it doesn't have so many
local variables all in one function; it was consuming considerably
more stack space than any other debug command.
Spring still needs low-level access to the smart battery, so move the
two functions it needs directly into the Spring implementation.
BUG=chrome-os-partner:20881
BRANCH=none
TEST=charge/discharge rambi, pit and spring; watch debug messages and
LED and output of 'battery' debug command. All should behave the
same as before. Then run 'taskinfo' and see that the console task
has at least 20 bytes unused.
Change-Id: I951b569542e28bbbb58853d62b57b0aaaf183e3f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177797
BSS section is usually put at the beginning of the RAM, so large
alignemnt causes the least memory usage penalty here, compared to
alignment using __attribute__((aligned(x))).
Also remove .bss.tasks and .bss.task_scratchpad, which are both not
present anymore.
BUG=chrome-os-partner:24107
TEST=Build all boards. Boot mec1322_evb.
BRANCH=None
Change-Id: Ie19b9feb76773a94f0443c2a0d39505ddef7a1df
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178274
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If CONFIG_WATCHDOG_HELP is defined, a 16-bit timer is used as an
auxiliary timer to interrupt us 50ms before the watchdog expires. When
the auxiliary timer expires, the stack trace is printed. Watchdog then
expires 50ms after and reboots the system.
BUG=chrome-os-partner:24107
TEST=Define CONFIG_WATCHDOG_HELP, and see stack trace on 'waitms 2000'.
TEST=Undefine CONFIG_WATCHDOG_HELP, and check watchdog still works
without printing stack trace.
BRANCH=None
Change-Id: I2555d3f86a15c83bb03a00c6807f77d9dddaf333
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178284
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds a PWM driver, which now generates 30KHz PWM output. Note that
this is different from fan control module driver.
BUG=chrome-os-partner:24107
TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output.
- Set to active high and 30%, see 30% duty PWM at ~29.1KHz.
- Set to active low and 20%, see 80% duty PWM at ~29.1KHz.
BRANCH=None
Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178391
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
So far we can only reliably sense a watchdog reset, but this
saving/checking reset cause will at least make 'ap-off' flag work.
BUG=chrome-os-partner:24107
TEST='waitms 2000' and see reset cause = 'watchdog'
TEST='reboot ap-off' and see reset cause includes 'ap-off'
TEST='reboot preserve' and see previous reset cause is preserved.
BRANCH=None
Change-Id: Id47a72d615489c9d9cd0b8761cfa699f08c724df
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178277
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This will be used for saving data across reboots.
BUG=chrome-os-partner:24107
TEST=Enable scratchpad command and check value is preserved across
watchdog reboot.
BRANCH=None
Change-Id: Ifd68541a3f842c466b6ff49bcc654c92df48aac6
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178276
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
DUMMY() is ugly and DUMMY_int() makes repo complain. Replace them with
explicit functions.
BUG=chrome-os-partner:24107
TEST=Build mec1322_evb
BRANCH=None
Change-Id: I155b769c12cafaf432c7f53fd46806feada3cfca
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178275
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
iRESET_OUT must be deasserted before the host can boot, and it's also
the gating source of the internal nSIO_RESET signal. There is a delay
between deasserting iRESET_OUT and nSIO_RESET inactivated, so let's
deassert iRESET_OUT as early as possible.
BUG=chrome-os-partner:24107
TEST=Boot EVB and check iRESET_OUT value
BRANCH=None
Change-Id: I6647da00567e2651c2b49e1e767adee2d5276493
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178171
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With this, we can now define and trigger interrupt on GPIO status.
BUG=chrome-os-partner:24107
TEST=Test GPIO036 with following cases:
- Pulled up and rising edge trigger. Pull down externally and
then release.
- Pulled up and falling edge trigger. Pull down externally.
- Pulled up and both edge trigger. Pull down and then release.
- Pulled up and low level trigger. Pull down externally.
BRANCH=None
Change-Id: Id9bfd2ba9dd8a75bcf2c5691ffe2aa6518076925
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177560
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This script is needed for packing EC binary into SPI flash for MEC1322.
This includes adding tag and header at appropriate location and signing
the image. Signing key, for obvious reason, is not included here until
we are sure what key we want to check in.
BUG=chrome-os-partner:24107
TEST=Build and boot on eval board
BRANCH=None
Change-Id: I92db7d2ba2c76c14a9c6611a04dbd6a2c3eb8d83
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177324
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This implements the basic watchdog support. For now, the watchdog
doesn't warn us before it expires. This functionality will be added
later using a basic timer.
BUG=chrome-os-partner:24107
TEST='waitms 700' and the EC stays alive.
TEST='waitms 1200' and the EC reboots.
BRANCH=None
Change-Id: I1cc48978ed09577ae88cc2f7a6087867e5854973
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177736
For historical reasons on LM4, we defined GPIO_INT_F_BOTH separately
from GPIO_INT_F_RISING and GPIO_INT_F_FALLING. This means that the
code has weird checks like BOTH || (RISING && FALLING), which have
propagated in error-prone ways across the other chips.
Instead, explcitly define BOTH to be RISING|FALLING.
Ideally, we would have called it GPIO_INT_EDGE to match
GPIO_INT_LEVEL, but changing that now would be a big find-replace.
Which might still be a good idea, but that is best done in its own CL.
BUG=chrome-os-partner:24204
BRANCH=none
TEST=build and boot pit, spring, and link; that covers STM32F, STM32L, and LM4.
Change-Id: I23ba05a3f41bb14b09af61dc52a178f710f5c1bb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177643
Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
The gpio table had the wrong pin assigned to
PP3300_LTE_EN. It should be D4 instead of D2.
BUG=chrome-os-partner:24201
BRANCH=None
TEST=Built and booted. Stuff shows up on lsusb, and I can confirm
3.3V on the bulk caps of the IO board.
Change-Id: I574599645ce21c175346e2ecde35b974aa0b68f7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177694
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
The worst case of the ONKEY long press timeout of AS3722 PMIC is
10.08 seconds, according to AMS. Increase of such timeout defines
to 10.2 seconds.
BUG=nvbug 1372063
BRANCH=nyan
TEST=verified on Venice2 boards that were failing to turn off power
with 9 seconds timeout
Change-Id: I65c8ebaab0523874ceff621cdbda72d8b44f4864
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/177611
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If EC_BL_OVERRIDE is low, backlight will be turned off. To allow AP to
control backlight, set EC_BL_OVERRIDE to high.
BUG=none
BRANCH=nyan
TEST=verified on nyan board 2.0 to see backlight turns on when system
boots up
Change-Id: I04e6052fbef4b17c3f9566c8c5cf691a2710b7b0
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/177553
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
These boards are unloved and unsupported. They'll never grow up to be
laptops, and hardware is increasingly hard to come by.
Comparable functionality is available in the other, more-loved boards.
Removing these boards speeds up util/make_all.sh by 40%. (If you're
not running that before every upload, you should be...)
BUG=chrome-os-partner:24062
BRANCH=none
TEST=build all remaining platforms and pass unit tests
Change-Id: I4d8a49e4d52d7393471f1b1cbef059c8db4a4f77
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177373
This adds include/dptf.h to define the DPTF interface functions.
As the first DPTF feature, it also adds a register to the EC's ACPI
interface block. Register 0x04 is used to get and set the fan's target duty
cycle, as a percentage value. Writing a 0 to this register will set the
target duty cycle to 0, writing a 100 (0x64) will set it to 100%. Writing
any other value will return the fan control to the EC, rather than driving
it manually from the host.
Likewise, reading from this register returns the current fan target duty
cycle, as a percentage. If the EC is controlling the fan automatically, the
returned value will be 0xFF.
BUG=chrome-os-partner:23972
BRANCH=none
TEST=manual
You can monitor the fan state from the EC console with the "faninfo"
command. From the host side, test this interface from a root shell.
Read fan duty:
iotools io_write8 0x66 0x80
iotools io_write8 0x62 4
iotools io_read8 0x62
Set fan duty to 100%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 100
Set fan duty to 50%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 50
Set fan duty to 0%:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 0
Set fan control back to automatic:
iotools io_write8 0x66 0x81
iotools io_write8 0x62 4
iotools io_write8 0x62 -1
Change-Id: I91ec463095cfd17adf452f0967da3944b254d558
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177423
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The rambi board has issues using the SERIRQ method
for triggering the keyboard IRQ. Namely, the current
level-shifter in place for the bidrectional SERIRQ
signal introduces delay resulting in the SERIRQ
being out of phase with the clock. Moreover, there
appears to be a mismatch of expectations with the
number of start frames on the SEIRQ line. Bay Trail
uses a fixed 8 while the TI docs suggest it only
supports 6.
BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi with keyboard working in
kernel with interrupts.
CQ-DEPEND=CL:177223
Change-Id: I05c2b113d801b3fc434a402620cebae0301839f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177189
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On certain boards it's no feasible to use the SERIRQ
method for generating the kebyboard interrupt. To that
end provide CONFIG_KEYBOARD_IRQ_GPIO option which
specifies the negative edge-triggered gpio for the
keyaboard interrupt.
BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi using this option. Keyboard
works in kernel with interrupts for i8042 device.
Change-Id: I64f7e9530841c184d2a33821126ec446c96bb0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177188
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is the initial commit of mec1322 support. This includes:
- Basic GPIO driver. Interrupt not supported yet.
- Microsecond timer
- UART driver
The script to pack the firmware binary will be checked in in
following-up CL.
BUG=chrome-os-partner:24107
TEST=Build and boot on eval board
BRANCH=None
Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175716
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Indicate when usleep() and udelay() may be called.
No code changes, just comments.
BUG=none
BRANCH=none
TEST=Build any platform. Heck, it's just comments.
Change-Id: I0182c153c29965b25d5294d838c1406c30115099
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177452
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Converting some of the boolean variables in vfnprintf() to a single
flags word reduces stack usage by 8 bytes and function size by 12
bytes. So it's slightly more efficient in both respects.
Confirmed size and stack usage improvements via 'make BOARD=rambi all
dis' and looking at the disassembly for vfnprintf()
BUG=chrome-os-partner:24148
BRANCH=none
TEST=Run taskinfo command twice and compare stack used by CONSOLE task.
Run timerinfo and charger commands and verify output looks reasonable;
those exercise binary and 64-bit number printing.
Change-Id: Ie4396bb0bc01dc155956fa2d8ca84c6630006729
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177400
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The keyscan task is short enough on stack space that turning on
keyboard debugging causes a stack overflow. This was previously not
the default, but https://chromium-review.googlesource.com/#/c/174373/
made it the default. Reverting that change just masks the problem;
enabling keyboard debugging on Spring would still cause a stack
overflow.
Rather than reverting that change, increase the stack size of the
keyscan task so that it doesn't overflow. There is sufficient space
to do this. Even after increasing the keyboard stack from 256 bytes to
320 bytes and doing a 'sysjump rw' to force jump tags to populate,
'shmem' reports 132 bytes free.
BUG=chrome-os-partner:23834
BRANCH=none
TEST=Boot Spring.
ksstate on
Bang on keyboard for a bit
taskinfo -> shows KEYSCAN task at 292/320 bytes free
sysjump rw
shmem -> shows 132 bytes free, 0 used
Change-Id: Idf9fdce5b9e6ca4d05d80a62ae9ea831ed508e3a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177355
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This gives the AP a chance to reboot, before the EC kills it by dropping rails.
BUG=chrome-os-partner:24120
BRANCH=none
TEST=on AP, write 0xe to 0xcf9; system should reboot instead of shutting down
Change-Id: I322a1193e90b4de37a4adaf547e1c6bf5be077c3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177305
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not sure why, but it doesn't seem to work consistently on my Spring.
Transmit works fine, but on some boots receive doesn't seem to pick up
received characters. Rather than churning Spring to fix this, just
disable receive DMA - which doesn't benefit Spring much anyway,
because it never downclocks its core to 1 MHz.
BUG=chrome-os-partner:24141
BRANCH=none
TEST=Boot Spring; typing into console works. After 'apshutdown', typing still
works (including arrow keys). Repeat 20 times. Repeat on Pit.
Change-Id: I5d9875b583c8e2a38b9070c4dfa31fd5a982a144
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177352
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Otherwise UART output gets garbled because there's a delay between
changing core clock and the UART divider. Fortunately, the glitch is
cosmetic and doesn't affect proper EC operation.
BUG=chrome-os-partner:23982
BRANCH=none
TEST=power on, power off on pit or nyan --> no UART glitch
Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177087
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
