When AP is off, turn off pullup on NSS, and set MISO to an input so
the SPI module won't drive it high if the last sent bit was a 1. This
reduces leakage when the AP is off.
This patch also fixes a bug where gpio_set_alternate_function() set
the wrong pins to normal-mode when func=-1; that didn't hit anything
else because that functionality wasn't used on STM32 until now.
BUG=chrome-os-partner:19304
BRANCH=none
TEST=boot pit
On EC console, with AP on, 'rw 0x40020000' returns
read 0x40020000 = 0x6569aa20 <- must have 0x____aa__
Then 'apshutdown' and 'rw 0x40020000' returns
read 0x40020000 = 0x65690020 <- must have 0x____00__
The 'power on' and AP turns back on. At u-boot prompt,
'sspi 2:0 256 9f00000000' returns
FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001
(some number of 0xFD's followed by FEEC...) This shows SPI
functionality is restored when AP is powered back on, and not
just at init time.
Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51182
Reviewed-by: Simon Glass <sjg@chromium.org>
SPI is always enabled on pit, so remove #ifdefs
SPI1_CLK was aliased to AC_STATUS, which is left over from snow and
doesn't exist on pit. That caused it to be driven high briefly during
EC boot.
Also set SPI pins for 40MHz speed so we can try faster SPI clock.
BUG=chrome-os-partner:19304
BRANCH=none
TEST=boot system; sspi 2:0 256 9f prints a bunch of FDs then FEEC010001
Change-Id: I10352cff3669d6a087939d9d8e302d70708e9ee3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51023
Reviewed-by: Doug Anderson <dianders@chromium.org>
I've simplified the SPI module, since we only ever use SPI1 (and there
were already a number of places which assumed this was true).
Somewhere along the way I fixed a number of problems keeping the code
from compiling and working on STM32L. The code isn't currently used
anywhere else, but should still work there (that is, I don't think I
broke it working on STM32F if you re-enable it on some STM32F
platform).
BUG=chrome-os-partner:19073
BRANCH=none
TEST=from u-boot console, sspi 2:0 64 9f0000
u-boot prints: FDFDFDFDFDFDFDFD
ec prints: [193.740912 HC 0x9f][193.741141 HC err 1]
[sjg: gpio optimization back in for now]
[dianders: add comment as rspangler requested; update SOBs]
Change-Id: Ib9419403e4e44dadc1f17681e48401882cb49175
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49684
1) Port needs to be open-drain. Missed this when porting from STM32F
because open-drain and alternate function are set in the same register
on STM32F and are different regs on STM32L.
2) Queue a stop condition if a transaction failed, so the clock goes
back high.
BUG=chrome-os-partner:18969
BRANCH=none
TEST=i2cscan finds both the PMU at 0x90 and the battery at 0x16
Change-Id: I708b925e4e30da9d5864b74641b1cbe90c9313fe
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49898
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Now that I2C works, we can re-enable the charging task to debug
battery charging.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=in EC log, should see battery state messages
Change-Id: I600d0152ba416c13420ce853b55206afba9f6cec
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49649
Also moves the handy i2cscan command to i2c_common. The
platform-dependent interface is now i2c_xfer().
Still more to do in follow-up CLs; for example, i2c_read_string() has
platform-dependent implementation, and the i2c/i2cread console
commands aren't common yet.
BUG=chrome-os-partner:18969
BRANCH=none
TEST=i2cscan on link, spring
Change-Id: Ia53d57beaa157bece293a4262257e20b4107589e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49492
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Daniel Erat <derat@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
I2C communication doesn't work on pit yet, so the charger task is
spewing errors to the console. This change allows the task to be
disabled cleanly on pit, and has no effect on other platforms.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build all platforms and see that charger task is still compiled
everywhere but pit
Change-Id: I788e817d5630fb1a28694819f4ef9948a503a744
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49344
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CONFIG_ macros should be set directly. Expanding the task names in the same
way made it difficult to tell what was a configuration choice and what was
due to changes in ec.tasklist
BUG=chrome-os-partner:18343
TEST=build all, run link
BRANCH=none
Change-Id: Ib82e34f974238ee2dd216f33b701b6f4c6a4f1f1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49098
Reviewed-by: Randall Spangler <rspangler@chromium.org>
STM32-based platforms now use the same lid debouncing code as
LM4-based platforms, generate lid-open / lid-closed events, and
trigger lid-change hooks.
This is needed for disabling keyboard scanning when the lid is closed,
as well as future changes to mask off wake events when the lid is
closed.
BUG=chrome-os-partner:18896
BRANCH=spring
TEST=build all platforms; check that spring boots when lid is opened
Change-Id: I09a6e91119c3739297fe49b7eacac6efda988284
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48924
Reviewed-by: Vic Yang <victoryang@chromium.org>
Pit uses GPIO PA2=TIM2_CH3 instead of Snow's PB3=TIM2_CH2. Other than
that, the timer setup is identical (STM32F and STM32L are compatible
in this respect, anyway).
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build snow, pit; no pit boards to test on yet
Change-Id: I8ba68f99641038e12c9a9c9dd29e3b64410a5eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48403
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a function which handles translation of PWROK from logical level
to physical level.
Also implement chipset_force_shutdown() in gaia_power.c, so PMU code
doesn't need to know about PWROK physical level.
BUG=chrome-os-partner:18738
BRANCH=none
TEST=build all platforms; boot spring
Change-Id: I360266ef89b6ead49a633cd57b7530f791b04c9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48251
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The latest schematics move a few signals between GPIOs. Update the
GPIO map to match.
BUG=chrome-os-partner:18657
BRANCH=pit
TEST=build pit (can't test the binary yet; no hardware)
Change-Id: I2d135412723fbe5cf4e7c1dbeb05fc68e6bb8c9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48231
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address. Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).
No code changes, just renaming macros.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
gpio_set_level() now allows setting the pin level if GPIO_LOW or
GPIO_HIGH is specified. Previously, stm32 platforms did this even
though the definition of gpio_set_level() said it wouldn't work.
Fixed gpio_set_level() not setting level after warm reboot on stm32
because it was checking the GPIO_DEFAULT flag in the wrong place.
Fixed LM4 still mucking with alternate function settings and levels
even if GPIO_DEFAULT was specified.
And checked gpio_list[] and all of the calls to gpio_set_flags() to
make sure everything still behaves the same way it did before (or
better, in the case of actual bugs).
BUG=chrome-os-partner:18718
BRANCH=none
TEST=build all platforms; boot spring and link
Change-Id: I4b84815f76060252df235ff9a37da52c54a8eac5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48058
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The MODER register is used to set (alt-func | analog | gpio-in |
gpio-out). So there's no need to force things to be normal GPIOs in
board config, since gpio_pre_init() will clear the alternate
function-ness as part of setting the GPIO direction.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build pit and test-boot on daisy
Change-Id: I82db9d9f4d8877464d62c1ff2efaef36822fc0ca
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47904
For most tests, we don't need to power the AP. Let's exclude chipset
task to save memory space.
BUG=chrome-os-partner:18598
TEST=Run pingpong test on Spring
BRANCH=none
Change-Id: I545c5b3e1c27b0067d4ffe09a7971d32b75d6039
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47833
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This only needs to be defined if CONFIG_USB_CHARGE is defined (that
is, if the board has a USB charge controller.
(Note the difference between providing power over USB vs. receiving
power over USB; the names are confusing and I'll rename one of the two
imminently.)
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I7355b4248bb2d4f5f71cc9f8d9d8f9d6c0069f2b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47658
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This changes current TASK() syntax to TASK_BASE() and TASK_NORMAL(),
where TASK_BASE is necessary for the EC to boot on a board and
TASK_NORMAL represents the task that can be removed in a test binary.
Tasks introduced by a test should be listed as TASK_TEST().
Note that this CL breaks current tests (many of them are broken anyway),
which will be fixed in up coming CLs.
BUG=chrome-os-partner:18598
TEST=Build link/bds/spring/snow/daisy/mccroskey. (mccroskey failed for
unrelated issue)
BRANCH=none
Change-Id: Ic645cdae0906ed21dc473553f1f43c2537ec4bb9
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47531
GPIO mapping is correct for current schematics.
Things to fix are #ifdef'd out with PORT_TO_PIT, but those require
changing other files (which is most tidily done in separate CLs).
BUG=chrome-os-partner:18657
BRANCH=pit
TEST=build pit (can't test the binary yet; no hardware)
Change-Id: Id1d1bb0c2925cfc0c21ee2d91666028aa6d2a707
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47599
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
