This feature is not enabled, is awkwardly written, and shouldn't
be left lying around to use as a bad example. This CL doesn't
change any compiled code.
A followup CL will add a working RBOX interrupt handler.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I5d0701f55ab9521bf1f29e7ec18994c4401d68fb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373600
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When flashing a servo v4, the function will try to initiate a cold_reset
but that interface does not exist for a servo v4. Add in a check for
cold_reset before trying an ec_reset to prevent printing the useless
error message 'No control named "cold_reset"'.
BRANCH=None
BUG=None
TEST=flashed and did not see error message anymore.
Change-Id: I6086883f002b4961807ae0663b0ee32aea4c63d8
Reviewed-on: https://chromium-review.googlesource.com/365151
Commit-Ready: Kevin Cheng <kevcheng@chromium.org>
Tested-by: Kevin Cheng <kevcheng@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Although probability is small, we still have chance to encounter the same
symptom which CPU's behavior is abnormal after wake-up from deep idle.
Apply the same bypass in task.c but not enable interrupt to solve it.
Modified sources:
1. system.c: Apply deep idle bypass for hibernate.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; test "hibernate"&"hibernate 10" on wheatley.
Change-Id: Ib00b9932ac34414d6a177d60668664ab31284a79
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/373300
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
At one time we could switch between TPM and HC protocols on the
SPI slave bus. We disabled the HC protocol long ago with commit
e4690f6152. This CL removes the spstpm command, since there's
no longer any point to having a console command to disable the
TPM protocol too (which would leave us with nothing listening to
incoming traffic on the SPI bus).
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: Ic5028dfc1631fab4ddf2584635cb48be50d05d4d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373638
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
kevin EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms. Even when hcdebug is set to off, we still
get command errors.
BRANCH=none
BUG=chrome-os-partner:56460
TEST=make buildall -j
TEST=Flash kevin EC, see that output is fairly quiet.
Change-Id: Iad974c463c8dd91960e872ec977fe0e653696701
Reviewed-on: https://chromium-review.googlesource.com/373284
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Support Rp/Rp debug accessories in the USB PD state machine
including detecting the polarity and the available type-C current.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:52592
TEST=manual, plug a Suzy-Q reworked with Rp3A0/Rp1A5 resistors
on a Kevin, and see the PD state machine is going to
PD_STATE_SNK_ACCESSORY (and leaving it on unplug).
Re-verify a few existing accessories (Rd/Rd SuzyQ, legacy RpUSB cable,
Rp3A0 power supply).
Change-Id: Icef6c90027105d7c633f2785210ab9dae74fc33c
Reviewed-on: https://chromium-review.googlesource.com/368700
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If reset was caused by reset pin, we need this reset cause
for next sequence(recovery key).
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=To assert EC WRST pin and we will get the reset cause for
both power-on and reset-pin.
Change-Id: I0361091680a148df07cbbb8f4e53635dbf48fdee
Reviewed-on: https://chromium-review.googlesource.com/371798
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:54452
TEST=1. To check appropriate register setting.
2. Measure the CC voltage by connecting USB-C to DP cable to EVB.
Default : 433mV
CONFIG_USB_PD_PULLUP_1_5A: 951mV
CONFIG_USB_PD_PULLUP_3A : 1.72V
Change-Id: Id5a36ded94121db4343c48ecea19a5a533244f43
Reviewed-on: https://chromium-review.googlesource.com/371020
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. If one i2c transaction includes timeout and done events
at the same time, the transaction result will be timeout.
Fixed: The transaction is succeed instead of timeout.
2. The interrupt of i2c will not be enabled if an i2c write transaction
is split into two or more xfer.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Console commands:'i2cscan', 'i2cxfer', and 'battery'.
2. Use two or more i2c_xfer(the first with flag 'I2C_XFER_START'
and the last with flag 'I2C_XFER_STOP') to do a i2c write
transaction and no error.
Change-Id: Ieb2cb229748ac9504cf1636a2826bbb3097aa55c
Reviewed-on: https://chromium-review.googlesource.com/360762
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On ANX7688, POWER_STATUS.VBusPresent is averaged 16 times, so its
value may not be set to 1 quickly enough during power role swap.
Therefore, we use a proprietary register to read the unfiltered VBus
value.
BRANCH=oak
BUG=chrome-os-partner:55221
TEST=LG monitor works over type-C, power role swap looks good
Change-Id: I68572c34440be65882f431bb892ed032da05bd0a
Reviewed-on: https://chromium-review.googlesource.com/364351
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With "ectool led power blue=0 green=100 red=100", LED color is changed.
But LED will turn off immediately.
To keep color with "ectool led", we need remove led turn off when
"Battery/Power LED" auto control are not enabled.
BUG=chrome-os-partner:56179
BRANCH=none
TEST=manual, run ectool command on user space.
ectool led power blue=0 red=100 green=100
ectool led power blue=100 red=0 green=100
ectool led power blue=100 red=100 green=0
ectool led power auto
Change-Id: Ifa6b426443ca800f34ba7c61cea6e2e49694fb0e
Signed-off-by: Jongpil Jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/368586
Reviewed-by: Shawn N <shawnn@chromium.org>
The version string reported through TPM_FW_VER register has become way
too long, it takes too much time to transmit at startup, especially at
i2c speeds.
Let's limit it to the essentials: header versions and hashes of the
active RO and RW sections.
BRANCH=none
BUG=chrome-os-partner:49954
TEST=verified version in the firmware log
localhost ~ # grep cr50 /sys/firmware/log
Firmware version: B2:0 RO_A:0.0.1/84e2dde7 RW_A:0.0.3/cr50_v1.1.5106-f7349c9+
Change-Id: Ic391f90673fe21c0100b776944f6efc080213ff3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372380
Reviewed-by: Scott Collyer <scollyer@chromium.org>
There is only one set LED in reef, so with charger attached, LED behave as
charging LED; without charger, as power LED.
BUG=chrome-os-partner:55492
BRANCH=none
TEST=on reef proto, verified power led behavior is correct in s0/s3/g3
Change-Id: If6b83c46fc4b8b455531698177f559ca319d241a
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/366102
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:55583
BRANCH=none
TEST=verified OBF status is cleared during idle without event which
means kernel driver waited for the BUSY bit and read the data.
Change-Id: I79357fea5483fe7a175c60f54235926e105ec832
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/373043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
stm32f446 has two types of i2c blocks, the traditional
stm i2c, and "fast mode plus" i2c, which need different drivers.
This commit adds both, muxed in i2c-stm32f4, as the ec
codebase doesn't really support multiple types of the same interface.
BUG=chromium:608039
TEST=i2c works on all 4 channels
BRANCH=None
Change-Id: I6a9ac632f44142bd809ffee5782a192ae47af1f0
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368358
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This patch introduces support for the cr50 firmware update protocol
version 3. It is described in more details in the comment in the
patch, the bottom line is that both RO and RW updates are supported,
and SPI and USB modes use the same protocol now.
The notions of PDU (protocol data unit) passed between the host and
the programming function on the CR50 is introduced, and USB mode
framing is described.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=verified that version 1 and 2 updates still work. Version 3 mode
was tested later, when the device side patches were applied.
Change-Id: If51854b6a0b140730e85853bc42039233550fe8c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371509
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In preparation to cr50 update protocol enhancements allowing to update
both RO and RW sections this patch is changing the name of the
structure containing communications endpoint information.
In the upcoming patches more fields are going to be added to this
structure, it is cleaner to change its name and existing use before
adding new features.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=make -C extra/usb_updater
Change-Id: I5ca0b6da75067a4f01ea80b6a6ca49a50e1136ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371508
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This just adds the new command line option and a help message for it.
This option will be used to signal that the RO section update is
required along with the RW section update when invoking usb_updater.
The flag indicating presence of the option will be saved in the
endpoint structure so it is available at different layers of the code.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=built usb_updater and invoked it with --help option, observed the
new option showing up in the output.
Change-Id: Ief35a553651d29ca39c42c5af7294d3aba223b02
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/369160
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
In preparation of introducing new update protocol version this patch
cleans up the existing implementation.
The receive and transmit PDU headers are separated into their own
structures and are now shared between the server and client sides.
Some comments have been added to better explain different protocol
versions' details.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=verified that it is still possible to update RW_A and RW_B on a
Kevin CR50, works using both USB and SPI.
Change-Id: Ied65b2c2a7800bae045f1d2dd64e58dd5e793d27
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368989
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Enable the SHI interrupt only after we have received and begun
processing our host command. Disable the SHI interrupt once our
transaction is complete (with either success or error status). This will
prevent the SHI interrupt from being asserted at the same time as the CS
interrupt, which can lead to the SHI interrupt being serviced first.
Also, it avoids needless, non-useful SHI interrupts during error
transactions.
BUG=chrome-os-partner:55710,chrome-os-partner:55795,chrome-os-partner:56254
BRANCH=None
TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached
(for host command spam), verify no errors encountered after 100 minutes.
Also verify host command interface functions properly after sysjump.
Change-Id: I41e3deb382897cd4286e6ac96f4f3066bf7a94a7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371510
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
BUG=chrome-os-partner:56247
BRANCH=None
TEST=Connect kevin to samus, run "pd 0 swap vconn", verify vconn state
shown by "pd 0 state" toggles. Also verify swaps instigated by samus
toggle vconn state on kevin.
Change-Id: Ieb8b7fe8b5e56a0d6fd29deba91efb2686c41ea4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371378
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Really, we only care if the chromeos-ec package fails to build and not
if the test stages fail. The test stages don't actually test aganist
our EC changes anways, so it's kind of a waste of time to run them.
Besides, that's what FAFT is for.
BUG=None
BRANCH=None
TEST=\_()_/
Change-Id: I6a1db02a05f17b276a16543ced58efa8a04fb997
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/372325
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Use EC_CMD_HOST_EVENT_GET_WAKE_MASK (already implemented on LPC
platforms) to share CONFIG_MKBP_WAKEUP_MASK with the host.
BUG=chrome-os-partner:56164
BRANCH=None
TEST=Run `ectool eventgetwakemask` on kevin, verify
CONFIG_MKBP_WAKEUP_MASK mask is printed.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I252c8d6297e3db97dd3df506b3a386a3ad777174
Reviewed-on: https://chromium-review.googlesource.com/372320
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Following steps need to be followed for SCI/SMI generation:
1. If automatic mode is being used, set SCIE/SMIE bit in HIPMIE register
during lpc_init. This step needs to be performed only once.
2. If SCI/SMI generation is required, set ST1/ST2 bit in HIPMST register
during update_host_event_status.
3. In lpc_generate_sci/smi, if automatic mode is being used, set
SCIB/SMIB bit in HIPMIC register.
BUG=chrome-os-partner:55489
BRANCH=None
TEST=lidclose behavior verified in kernel.
Change-Id: Ib6e0ee32bc06a8c51297010ac4843a7de45a99bd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/371059
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Header version fields are instrumental when determining which of the
available images is started by the RO. Let's include the header
version when reporting the RW images' version as well as RO.
BRANCH=none
BUG=none
TEST=verified that RW header information is now included in the
version command output:
> vers
Chip: g cr50 B2
Board: 0
RO_A: * 0.0.8/8755904e
RO_B: -1.-1.-1/ffffffff
RW_A: 0.0.1/cr50_v1.1.5093-751a584+
RW_B: * 0.0.1/cr50_v1.1.5093-d27f65f
Build: 0.0.1/cr50_v1.1.5093-d27f65f
...
Change-Id: I675c473a277e272f55670324fafdab8a6e6edd78
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370939
Reviewed-by: Scott Collyer <scollyer@chromium.org>
sweetberry is an stm32f446 based power monitoring
board, with 48 channels of INA current sense chips
BUG=chromium:608039
TEST=boots
BRANCH=none
Change-Id: If263bcee3a648ba3605f991999d481b7a0e2a1db
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370718
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
DIOM3 is no longer used. Remove it from gpio.inc
BUG=chrome-os-partner:55895,chrome-os-partner:55896
BRANCH=none
TEST=make buildall; test on Cr50 hardware
Change-Id: I1f7aeab8135fa97aab04945b6a450e32903e2e84
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/372405
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For some reason, chell-pre-cq is very flaky (fails in VMTest
login_CryptohomeIncognito for reasons not related to EC changes).
Since pre-submit hook forces us to compile test changes on all platforms
anyway, let's skip chell-pre-cq to unblock developers.
BRANCH=none
BUG=chromium:631640
TEST=chell-pre-cq is not run on EC changes.
Change-Id: I98cb68709bb4305069e5e67874c1847b2a891fb7
Reviewed-on: https://chromium-review.googlesource.com/372618
Reviewed-by: Yoshiki Iguchi <yoshiki@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Previously this was only done when the board version is EVT or less
and when daughter card is inserted. However board version can not
be determined at this stage of power up since the function
board_get_version() relies on reading Board ID ADC and ADCs have not
yet been initialized.
This pull up can be removed in future board versions in which the
daughter card will always be in place and an internal pull-up will
no longer be needed.
BUG=chrome-os-partner:55488 chrome-os-partner:56039
BRANCH=none
TEST=verify board has no watchdog reset when daughter baord
is not connected. Also verify from EC log timestamps that
there is no delay of approximately 1 second between
"Inits done"and "KB init state"
Change-Id: I68eff923dd795b7b2f23f88028ee14d1e845b401
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/370958
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Turn off PP3300_A, PP5000_A, and PMIC when chipset_do_shutdown is called.
BUG=chromium:54962
TEST=Press power button for 9 seconds and confirm that PP3300_A, PP5000_A,
and PPVAR_VNN are at 0 volts. Also verify that system boots from G3 when
power button is pressed.
BRANCH=None
Change-Id: Ib8347873728e3940fd588599403c94d0f264f64c
Signed-off-by: Rachel Nancollas <rachelsn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371340
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
There were a few things wrong with the way I2C pins were originally
set up:
- EC_I2C_SENSOR_SCL was moved from GPIOA0 to GPIO92.
- EC_I2C_GYRO_SCL/SDA and EC_I2C_POWER_SCL/SDA were swapped.
BUG=chrome-os-partner:53791
BRANCH=none
TEST=Motion sensors work now.
Change-Id: Id867c56b625da27e8ad82b503ae11173d7f855cc
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347754
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
This adds basic support for the stm32f446.
This consists of:
* New DMA model for stm32f4
* New clock domain support.
* MCO oscillator gpio export support.
* Flash support for irregular blocks.
BUG=chromium:608039
TEST=boots w/ correct clock, stm32f0 also boots.
BRANCH=None
Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363992
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
ble_tx now resets values that could prevent its functioning.
Since there is no NRF51 shortcut from TX->RX, it also blocks until
packet is transmitted. This prevents calling RX before TX is completed,
specifically in advertising state.
Also added timeouts to prevent possibility of freezing in case of
unexpected state.
TEST=Used function before and after CL in a more fully implemented stack.
This improved reliability.
BUG=None
BRANCH=None
Change-Id: I6a5b0b6f36e37ac0102d254bbdc9dfcd29694bb8
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/370597
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The variable rv was being returned without being initialized. Instead,
return EC_SUCCESS.
BUG=None
BRANCH=None
TEST=Build all boards successfully.
Change-Id: If37057b737e6419c1d5cc22215a7d76d920d1267
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370664
Configure the FUSB302 current source used for Rp according to the
CONFIG_USB_PD_PULLUP_xxx value.
Set the default Rp for Kevin to 1.5A.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:54452 chrome-os-partner:56110
TEST=manual: plug to Samus, enable charging on the Samus side,
measure the CC voltage with Twinkie, get 950mV instead of 450mV.
Change-Id: I98faf18132a097e49e9c0fa8e1395d230608ee9e
Reviewed-on: https://chromium-review.googlesource.com/369190
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In preparation to RW and RO cr50 updates, separate the code
transferring an image section (an RW section currently) into a
function.
This will allow to add RO transfer by invoking the same function with
different address and size parameters.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=verified that it is still possible to update to RW_A and RW_B
both over USB and SPI.
Change-Id: Ia41317e0eefe114bac41e73c7e715b1a5cb6549c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368988
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
TEST=Used function before and after CL in a more fully implemented
stack. This improved reliability and lengthened connection times.
BUG=None
BRANCH=None
Change-Id: I60680c8855d6166e4e4a6a71639ee57464fa21ce
Signed-off-by: Levi Oliver <levio@google.com>
Reviewed-on: https://chromium-review.googlesource.com/370420
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This is a mostly cosmetic change, use size_t as the type for variables
which are used to pass around number of bytes received or transmitted.
BRANCH=none
BUG=chrome-os-partner:55789
TEST=verified that usb_updater still works both over USB and SPI.
Change-Id: I2cc726315d613ee42937fb494745cf7e0ea66622
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368987
Reviewed-by: Scott Collyer <scollyer@chromium.org>
