To test drivers, we need a way to fake I2C periphrals. With this CL, a
fake peripheral can be done by declaring its own I2C read/write
functions. The fake I2C peripherals may return EC_ERROR_INVAL to
indicate it's not responding. The emulator I2C read/write call scans
through all registered I2C peripherals and uses the first response.
BUG=chrome-os-partner:19235
TEST=Pass sbs_charging test with the next CL.
BRANCH=None
Change-Id: I9380dc40e147781b42e09eb6979c864bbd9f2ac4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169511
Reviewed-by: Randall Spangler <rspangler@chromium.org>
STM32 has a single-byte mailbox for UART I/O. When the core clock
runs at 16Mhz we can service interrupts fast enough to handle 115200
baud input, but when we drop to 1MHz we drop characters. Using DMA to
receive input solves this problem.
The STM32 DMA engine can only generate interrupts when the transfer is
half-done / all-done, so we need to poll the DMA receive-head-pointer
to see if individual characters have been received. Do this in the
tick task (every 250ms). When a character is received, poll more
quickly for a bit (5 times before the next tick) so the input console
is more responsive to typing.
BUG=chrome-os-partner:20485
BRANCH=none
TEST=Console is responsive to debug commands. For example, help -> prints help
apshutdown -> shuts down AP
arrow keys -> move cursor and scroll through command history
Ctrl+Q, help, wait a second, Ctrl+S -> help output printed after Ctrl+S
Then in chip/stm32/config_chip.h, comment out #define CONFIG_UART_RX_DMA
and rebuild/reflash the EC. When the AP is up, the console works normally
but after 'apshutdown', the EC drops to 1MHz core clock, and the arrow
keys don't work. (This step confirms that adding DMA support did not
change the behavior of systems where CONFIG_UART_RX_DMA is not defined.)
Change-Id: I199448354824bd747c7b290ea7fd5ccf354c11bb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169406
Reviewed-by: Simon Glass <sjg@chromium.org>
All calls to it did
if (uart_tx_stopped())
uart_tx_start();
And that was the only use of uart_tx_stopped(). Merge the functions.
BUG=chrome-os-partner:20485
BRANCH=none
TEST=EC debug console still prints output and accepts commands.
Ctrl+Q pauses output and Ctrl+S resumes it.
Change-Id: I113c64f5fdfc6b02b63034a74b1a3c6c6a76c351
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169329
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This reduces the number of UART interrupts by a factor of 12, and
reduces the overall interrupt rate on STM32 by a factor of 2.
BUG=chrome-os-partner:20485
BRANCH=none (not required for pit branch)
TEST=Boot pit. Ctrl+Q pauses debug output; Ctrl+S resumes it.
'crash divzero' still prints a full crash dump.
And util/makeall.sh passes builds all platforms and passes tests.
Change-Id: I86993e14b436150298dcb2c6d29086cc3c9db418
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168814
This is a precursor to DMA-based UART transfers, which require
different processing for DMA vs PIO output types.
BUG=chrome-os-partner:20485
BRANCH=pit
TEST=Boot pit; verify EC console still works.
Change-Id: I6d6f55561eeebe9bd2928b2bfb25278c86f689d1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168811
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The definition of GPIO interface allows passing in multi-bit mask, and
this is what's done by gpio_config_module(). Fix STM32L's function so
that it doesn't accidentally set incorrect GPIO register values.
BUG=chrome-os-partner:22605
TEST=On Kirby, do 'led r 0' and check the value of 0x40020800 is
0x01540000.
BRANCH=None
Change-Id: I9a1c8074aab7345485a590ecf138bf99d0742997
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168739
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
This is in preparation for enabling DMA-based UART transfers, to
improve UART performance on STM32.
BUG=chrome-os-partner:20485
BRANCH=none
TEST=Boot pit. Host commands should still be received; this verifies DMA
is still operational.
Change-Id: Ibc3b2e2cd187547eb61b85e4a086704accd7f2fb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168810
BQ27541 is not a smart battery IC, and thus we cannot use existing smart
battery driver. Let's add a driver that implements a smart-battery-like
interface.
The 'battery' console command is also moved to battery.c so that it can
be reused by different battery driver.
BUG=chrome-os-partner:22048
TEST=Type 'battery' and check the reported values are sane.
TEST=Check 'battery' command works fine on Spring.
BRANCH=None
Change-Id: I5d1eaeb3f801478f3b9473fd43c1f2a2eda75859
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/66340
ADC module on STM32L is clocked by HSI oscillator, and thus we need to
switch to HSI if using MSI. After the conversion, if the system is not
in S0, clock is switched back to MSI again.
There are several register bits that can only be written when ADC is
powered down. For now, let's just power down the ADC after each
conversion.
Currently ADC watchdog is not working and is disabled on STM32L.
BUG=chrome-os-partner:22242
TEST=Try multiple all-channel and single-channel reads in S0 and S5.
BRANCH=None
Change-Id: I769dda8a9c69ac9de1eb22d6d259034eef8c1ac4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167454
If we reboots the emulator without flushing test coverage information,
the test coverage report will be incorrect. Let's fix this by flushing
it before every reboot.
BUG=chrome-os-partner:19235
TEST=Generate test coverage report and check correctness.
BRANCH=None
Change-Id: I1eb060e419b767f382325bed841366c491ba56b7
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167770
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
GPIO_INPUT is defined as 0, and any GPIO flag cannot be examined against
GPIO_INPUT. Change GPIO_INPUT to non-zero value to avoid this.
BUG=chrome-os-partner:22275
TEST=On Kirby, set a GPIO to output and pull it low, and then set it back to
input. Check it can be pull high externally.
TEST=Build all boards.
TEST=Boot link and spring.
BRANCH=None (unless this bug hits some other boards.)
Change-Id: I84b9936c24af538ac59c36129fda27ca879bf9d1
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167190
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
and when the bus seems wedged at i2c_init().
BUG=chrome-os-partner:19286
TEST=Manual test on peach pit. Tried the following wedged cases:
(1) Bit bang a transaction but only read part of the response.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 2 2
(2) Bit bang a transaction to do a "write" and stop while the other side is
acking. (Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 1
(3) Same as (1) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 6 2
(4) Same as (2) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 5
(5) Manually pull down on SCL.
(Refer to https://chromium-review.googlesource.com/#/c/66063)
All five cases successfully wedged the bus and were recovered by this change.
BRANCH=pit
[dianders: made sure we don't change SCL after SCL high, misc other bits]
Change-Id: I23f16fcaa2a76ea37025f8204ab1cdb27e9ef6d1
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/66915
Previously we could get into some pretty bad situtation around
frequency changes. Specifically:
* If the freq change code exectued during a transaction then it would
get all messed up.
* If the freq change notifier executed during a transaction then we'd
reset the bus midway through transaction. Badness.
BRANCH=pit
BUG=chrome-os-partner:22093
TEST=With all patches together:
- on AP: suspend_stress_test
- on EC: battery 10000 50
Change-Id: I24be29d459fe229a6278829a7c03c1e102358e8c
Signed-off-by: Doug Anderson <dianders@chromium.org>
Previous-Reviewed-on: https://chromium-review.googlesource.com/167102
(cherry picked from commit deab2433c13bc3b3bb75cd33c12dad633ba6a42a)
Reviewed-on: https://chromium-review.googlesource.com/167149
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Before this change drivers had no way of knowing that a frequency
change was coming. This could cause problems for some drivers (like
i2c) that need to make sure that a transaction isn't happening while a
frequency change is happening.
The PRE_FREQ_CHANGE archiecture is very simple here and we don't allow
any way to cancel it.
At the moment, we guarantee:
- We won't call PRE_FREQ_CHANGE with interrupts disabled, so acquiring
locks / sleeping is OK.
- We'll call the actual HOOK_FREQ_CHANGE after the PRE_FREQ_CHANGE.
PRE_FREQ_CHANGE and HOOK_FREQ_CHANGE should not use deferred function
calls.
BRANCH=pit
BUG=chrome-os-partner:22093
TEST=With all patches together:
- on AP: suspend_stress_test
- on EC: battery 10000 50
Change-Id: I2731a3e85d41e749fa571fdb74b5c9b12043cda6
Signed-off-by: Doug Anderson <dianders@chromium.org>
Previous-Reviewed-on: https://chromium-review.googlesource.com/167101
(cherry picked from commit d84c0dbbf7c5a72917a820e292ecfdfa698d0fb9)
Reviewed-on: https://chromium-review.googlesource.com/167148
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, the STM32L I2C driver queues the stop condition, but
doesn't actually wait for it to take effect before returning. If
another back-to-back transfer is started, this may attempt to send a
start condition before the stop condition completes. If this happens
after a slave read, this can look to the slave like just another pulse
on SCL, causing it to clock out another bit - potentially driving SDA
low and hanging the bus.
Instead, wait for the bus to go idle, then wait another clock period
(10 us) to give the slaves plenty of time to detect bus-idle before
the next start condition.
BUG=chrome-os-partner:22093
BRANCH=pit
TEST=repeatedly run the battery i2c command from the EC console while
running 'ectool i2cxfer 0 0x48 1' from a root shell. Should not hang
the I2C bus.
Change-Id: I5e65ee242537dbc801fba4ae57847a5af5104186
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/66997
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Commit-Queue: Douglas Anderson <dianders@chromium.org>
Dumping before the ADDR bit is cleared also has the effect of clearing the ADDR
bit.
BUG=chrome-os-partner:22235
TEST=Manual test on peach pit.
Keep executing the "battery" command on the EC console while busy running
flashrom on the host to read back the EC. See that there's no error produced.
BRANCH=pit
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Change-Id: I10e88a8512f4e9eb90267ef1aca1df5dd214318d
Reviewed-on: https://chromium-review.googlesource.com/66930
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Commit-Queue: Hung-ying Tyan <tyanh@chromium.org>
Tested-by: Hung-ying Tyan <tyanh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This unifies the PWM module interface for LM4 and STM32. Now PWM
channels are defined in board.h/board.c. Instead of calling functions
named pwm_set_fan_duty(x), one can now use pwm_set_duty(PWM_CH_FAN, x),
which prevents additional functions added when we have a new PWM
channel.
BUG=chrome-os-partner:18343
TEST=Limit input current on Spring.
TEST=Check power LED in S0/S3/S5 on Snow.
TEST=Check keyboard backlight functionality on Link.
TEST=Check fan speed control/detecting on Link.
BRANCH=None
Change-Id: Ibac4d79f72e65c94776d503558a7592f7db859dc
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/64450
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Problems with existing thermal control loop:
* Not multi-board friendly. thermal.c only supports Link and needs
refactoring. Temp thresholds and fan speeds are hard-coded.
* Only the PECI temp is used to determine the fan speed. Other temp sensors
are ignored.
* Has confusing data structures. Values in the CPU temp thresholds array mix
ACPI thresholds with fan step values.
With this change, the thermal task monitors all temp sensors in order to
perform two completely independent functions:
Function one: Determine if the host needs to be throttled by or informed of
any thermal events.
For thermal events, each temp sensor will have three threshold levels.
TEMP_HOST_WARN
* When any sensor goes above this level, host_throttle_cpu(1) will be called
to ask the CPU to slow itself down.
* When all sensors drop below this level, host_throttle_cpu(0) will be called.
* Exactly AT this level, nothing happens (this provides hysteresis).
TEMP_HOST_HIGH
* When any sensor goes above this level, chipset_throttle_cpu(1) will be
called to slow the CPU down whether it wants to or not.
* When all sensors drop below this level, chipset_throttle_cpu(0) will be
called.
* Exactly AT this level, nothing happens (this provides hysteresis).
TEMP_HOST_SHUTDOWN
* When any sensor is above this level, chipset_force_shutdown() will be
called to halt the CPU.
* Nothing turns the CPU back on again - the user just has to wait for things
to cool off. Pressing the power button too soon will just trigger shutdown
again as soon as the EC can read the host temp.
Function two: Determine the amount of fan cooling needed
For fan cooling, each temp sensor will have two levels.
TEMP_FAN_OFF
* At or below this temperature, no active cooling is needed.
TEMP_FAN_MAX
* At or above this temperature, active cooling should be running at maximum.
The highest level of all temp sensors will be used to request the amount of
active cooling needed. The function pwm_fan_percent_to_rpm() is invoked to
convert the amount of cooling to the target fan RPM.
The default pwm_fan_percent_to_rpm() function converts smoothly between the
configured CONFIG_PWM_FAN_RPM_MIN and CONFIG_PWM_FAN_RPM_MAX for percentages
between 1 and 100. 0% means "off".
The default function probably provide the smoothest and quietest behavior,
but individual boards can provide their own pwm_fan_percent_to_rpm() to
implement whatever curves, hysteresis, feedback, or other hackery they wish.
BUG=chrome-os-partner:20805
BRANCH=none
TEST=manual
Compile-time test with
make BOARD=falco runtests
On the EC console, the existing fan commands should work correctly:
faninfo - display the fan state
fanduty NUM - force the fan PWM to the specified percentage (0-100)
fanset RPM - force the fan to the specified RPM
fanset NUM% - force the fan to the specified percentage (0-100) between
its configured minimum and maximum speeds from board.h
(CONFIG_PWM_FAN_RPM_MIN and CONFIG_PWM_FAN_RPM_MAX)
fanauto - let the EC control the fan automatically
You can test the default pwm_fan_percent_to_rpm() with
fanset 1%
faninfo
The fan should be turning at CONFIG_PWM_FAN_RPM_MIN. Let the EC control it
automatically again with
fanauto
Also on the EC console, the thermal settings can be examined or changed:
> temps
PECI : 327 K = 54 C
ECInternal : 320 K = 47 C
G781Internal : 319 K = 46 C
G781External : 318 K = 45 C
>
> thermalget
sensor warn high shutdown fan_off fan_max name
0 373 387 383 333 363 PECI
1 0 0 0 0 0 ECInternal
2 0 0 0 0 0 G781Internal
3 0 0 0 0 0 G781External
>
> help thermalset
Usage: thermalset sensor warn [high [shutdown [fan_off [fan_max]]]]
set thermal parameters (-1 to skip)
>
> thermalset 2 -1 -1 999
sensor warn high shutdown fan_off fan_max name
0 373 387 383 333 363 PECI
1 0 0 0 0 0 ECInternal
2 0 0 999 0 0 G781Internal
3 0 0 0 0 0 G781External
>
From the host, ectool can be used to get and set these parameters with
nearly identical commands:
ectool thermalget
ectool thermalset 2 -1 -1 999
Change-Id: Idb27977278f766826045fb7d41929953ec6b1cca
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66688
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The BOOTCFG register configures a couple of important things: whether to
allow jumping into the builtin ROM bootloader at reset, and whether or not
to allow JTAG access for programing and debugging.
The default is "no" and "yes". But the BOOTCFG register can be locked so
that it can't be changed again, which means that if the wrong values are put
into it, the system is pretty much bricked.
On Link, we wrote a BOOTCFG value that allowed a GPIO to be used as a bypass
to optionally trigger the ROM bootloader, but on Slippy and its derivatives
that GPIO is not pulled up. If you program the Link values into BOOTCFG on a
Slippy, the system is stuck in the ROM bootloader more or less forever.
This change disables that GPIO, keeps JTAG enabled, and locks those settings
for all LM4 chips (it's a chip config now, not a board config). We've never
actually used the GPIO to invoke the ROM bootloader, but we have managed to
brick a number of systems just by having it enabled, so we're going to lock
it into a safe configuration now.
BUG=chrome-os-partner:19247
BRANCH=falco,peppy
TEST=manual
Reflash, boot, power cycle (actually unplug the EC from AC and battery) a
few times. It should continue to work.
Change-Id: Iaf1a81d6814104421a56425490e3d5164ea9b617
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66538
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This tests that command history is as expected. Also fix a bug that some
checks in console_edit test are skipped.
BUG=chrome-os-partner:19236
TEST=Pass console_edit test.
BRANCH=None
Change-Id: Ifbd3d1690f25b35bf5efe523e656b013aa534d26
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64837
BUG=chrome-os-partner:21847
BRANCH=peppy
TEST=Manual. Check state of GPIO_P5000_FAN_EN with lid open
and lid closed. Can also check with meter via TP109.
Change-Id: I8a64c14d53dd84a5d586c0abb04ccb71de0e78b3
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65674
Firmware development for this board is happening on the
firmware-wolf-4389.24.B branch.
BUG=chrome-os-partner:21815
BRANCH=None
TEST=Run util/make_all.sh. Verify all is made.
Change-Id: I4b58a982a87562231453f3f201024b809c6a24fb
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65514
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This fixes a confusing indication in flashinfo, where the all_now flag
is set but banks aren't shown as protected now.
BUG=chrome-os-partner:20277
BRANCH=pit
TEST=See bug for full test procedure. In short:
1) Enable physical write protect
2) flashwp enable
3) flashwp now
4) flashinfo shows all banks protected now
Change-Id: I489e80f63a33c182629d3a04fd0a9dadfb3914ab
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64980
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This just replaces all the "X - 273", "Y + 273" stuff with a macro.
BUG=none
BRANCH=falco,peppy
TEST=manual
Run the EC console command "temps". It should print human-readable things.
Change-Id: Icc4284c89fdbc0cd3b206a0faacf121973652a63
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65005
Reviewed-by: Randall Spangler <rspangler@chromium.org>
GPIO alternate functions used to be configured throughout the code,
which made it hard to tell which ones you needed to configure yourself
in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being
configured as alternate functions even if they weren't used on a given
board.
With this change, every board has a table in board.c which lists ALL
GPIOs which have alternate functions. This is now the only place
where alternate functions are configured. Each module then calls
gpio_init_module() to set up its GPIOs.
This also fixes a bug where gpio_set_flags() ignored most of the flags
passed to it (only direction and level were actually used).
On stm32f, gpio_set_alternate() does not exist, and pins are
configured via direct register writes from board.c. Rather than
attempt to change that in the same CL, I've stubbed out
gpio_set_alternate() for stm32f, and will fix the register writes in a
follow-up CL.
BUG=chrome-os-partner:21618
BRANCH=peppy (fixes I2C1 being initialized even though those pins are used
for other things)
TEST=boot link, falco, pit, spring
Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64400
It looks like a line of code was accidentally left in during
refactoring gpio_set_flags(). That line is equivalent to
gpio_set_level(signal, 0).
It's so far been harmless, because it's immediately followed by
gpio_set_level(signal, 1) - but it does mean the signal may glitch for
a few clocks at this point.
BUG=chrome-os-partner:21678
BRANCH=none (or Spring, but it seems to work fine even with this line)
TEST=boot Spring
Change-Id: Id7a48e2c9bd543f2aa6a0b710faa5dd2b482fd84
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64719
The old low-level SPI protocol provided no useful information to the
host about whether it was ready to receive or not. It also could get
stuck waiting to receive data without setting up receive DMA, if the
host did two transactions back-to-back.
Add a real state machine to the SPI module.
Add a range of byte codes the EC can return outside of a response
frame, to indicate its current state. If the AP receives one of these
codes, it can abort the transaction since it now knows the EC is
unable to determine when it can send a response frame.
This change is backwards-compatible with current AP firmware and
kernel drivers, since those only look for the framing byte and don't
care what other bytes are received in the meantime.
BUG=chrome-os-partner:20257
BRANCH=none
TEST=crosec test; passes at 70us.
Change-Id: Ia06109ead3fbc421848e01050f7baf753cbeb16c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64254
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
No functional changes; just moving file
BUG=chrome-os-partner:21612
BRANCH=none
TEST=onewire red / onewire green / onewire yellow all set the adapter LED
(tested on link, since I don't have a bolt, but the EC chip and adapter
are identical)
Change-Id: I005abf871caafa39e82e88875b515c842a12d591
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64376
Reviewed-by: Vic Yang <victoryang@chromium.org>
There's no need for it to directly access the GPIO registers. That
was only necessary at the beginning of link, when gpio_set_flags()
didn't exist.
BUG=chrome-os-partner:21612
BRANCH=none
TEST=onewire red / onewire green / onewire yellow all set the adapter LED
(tested on link, since I don't have a bolt, but the EC chip and adapter
are identical)
Change-Id: I2386962ff039bb2251be38eaadcaeae8ffd1ea7b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64375
Reviewed-by: Vic Yang <victoryang@chromium.org>
Previously, processing of arrow keys and control characters was done
in the interrupt handler itself. This increased the impact of UART
input on other interrupts and high-priority tasks. It also makes it
harder to implement DMA-based UART input on STM32L (in an imminent
CL), since the processing affected the circular UART input buffer
in-place.
This change turns uart_buffering.c back into a dumb I/O buffering
module, and puts all the command line editing and history support into
console.c.
Console history is done via a simple array of input lines instead of a
packed circular buffer of characters. This is a little less
RAM-efficient, but is easier to implement and read. History depth is
controlled via CONFIG_CONSOLE_HISTORY, and is 3 for STM32F and 8 for
other platforms. If we really need a greater history depth, we can
look into implementing a packed circular buffer again, but this time
at task time in console.c. Also added a 'history' command to print
the current console history.
BUG=chrome-os-partner:20485
BRANCH=none
TEST=console_edit unit test passes; 'history' command prints the last commands
Change-Id: I142a0be0d67718c58341e4569f4e2908f191d8b0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64363
Reviewed-by: Vic Yang <victoryang@chromium.org>
Remove support for allowing host command handlers to set the response
pointer. This is just one more thing that can break (and did, on SPI
protocol V2). No commands other than the trivial read-memory-map
command in host_command.c and flash read made use of this capability,
and the savings in performance was negligible.
BUG=chrome-os-partner:21576
BRANCH=none
TEST=boot pit; still boots
Change-Id: I0a9bcf57dbea7155318fc389d7b47d3742a1a00a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64236
We've been declaring a bunch of statically-sized arrays:
extern struct foo_t foo[FOO_COUNT];
And then initializing them like so:
struct foo_t foo[FOO_COUNT] = {
/* blah */
};
That only catches cases where we initialize with too many entries. It
doesn't catch cases where we haven't initialized enough. This change tests
for both cases like so:
extern struct foo_t foo[];
struct foo_t foo[] = {
/* blah */
};
BUILD_ASSERT(ARRAY_SIZE(foo) == FOO_COUNT);
The affected arrays are:
adc_channels[ADC_CH_COUNT]
gpio_list[GPIO_COUNT]
temp_sensors[TEMP_SENSOR_COUNT]
x86_signal_list[X86_SIGNAL_COUNT]
i2c_ports[I2C_PORTS_USED]
BUG=chrome-os-partner:18343
BRANCH=falco,peppy
TEST=build all platforms
All platforms should still build, all tests should still pass.
Change-Id: Ibb16dc3201f32df7cdc875648e89ba4ffb09f733
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63833
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Rename onewire_led to led_driver_ds2413, since we may have other LED
drivers hanging off a one-wire bus in the future.
No functional changes, just renaming config options.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I1d70b1c5778da94bda4ebef3b57f7c39bfba2322
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63273
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CONFIG_FMAP is now defined by default, because all platforms other
than the host unit tests use it.
No functional changes, just renaming config options and removing dead code.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: Ie6496310c822491068e2fa6976933486f26badb0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63271
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we are hibernating indefinitely, just exit with hibernate exit code.
If hibernating with a delay, delay for that amount of time and then
reboot.
BUG=chrome-os-partner:19235
TEST='hibernate 1' and see emulator reboot after a second with reset
flag 'hibernate'
BRANCH=None
Change-Id: If25bf2eefbcf275f2592b92a997a9d7e1ff2384d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62970
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With this, the emulator is able to reboot itself without the help of
run_host_test script. This makes it easier for development and also
speeds up the test.
BUG=chrome-os-partner:19235
TEST=Pass all tests
BRANCH=None
Change-Id: Ifa510442de19256c671ab91b6bc75fe9e8b9dc7b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62969
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To create a token by concatenating already-defined macros and new
text, it's necessary to use multiple levels of macro. We'd already
done that in several places in the code such as STM32_CAT; this now
standardizes it into a single place.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=Build all platforms; examine ec.RO.map to see that irq_*_handler and prio_* symbols
evaluated the same as before. (Other macro evaluations would simply fail to compile
if they were incorrect, since the concatenated tokens wouldn't fully expand.)
Change-Id: Ic9bf11d27881a84507fe7b6096dab6217c6c6dc7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63231
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The preliminary bolt support allows the board to boot
with all the necessary peripherals working except for the
following things:
- Not all board temp sensors are added.
- WLAN is not powered on because of inrush issues.
- USB power chargers are fixed to normal mode for now.
BUG=chrome-os-partner:20372
BRANCH=None
TEST=Built and booted
Change-Id: Iea7a39e812bb396e5731f212630b7fe97c164bf2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
No functional changes, just renaming config options.
Remove README, now that all options described in it have been moved to
config.h, and the remaining information is out of date. (Yes, we
should have a README which describes the organization of the EC
repository, but that's a matter for another CL; this one's about
cleaning up config options.)
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: Iafefbe94369f1217c698f11d358bc0ecac2bdfde
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63145
Reviewed-by: Vic Yang <victoryang@chromium.org>
All of these were defined on all but a few platforms, and those
explicitly #undef them. So define them as enabled by default in
config.h so the board.h files are cleaner.
No functional changes; just rearranging/renaming config constants.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; FEATURES=test emerge-falco chromeos-ec
Change-Id: I1201a1472ae29641e9e219c2a0347691ca64cd28
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63102
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reset flags should be set properly according to reset type. Also, on
system jump, current time should be preserved.
BUG=chrome-os-partner:19235
TEST='sysjump rw' and check time is the same.
TEST='reboot hard' and see '[Reset cause: hard]'
BRANCH=None
Change-Id: I00fd2c652d10c237f23cc6a33e0b667422bc625d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62958
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These are now described in config.h. The various BQ chargers now also
use a consistent naming for their sense resistor options.
No functional changes, just renaming, and removal of obsolete
never-defined configs.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: Ie274546fe45f5ffc6fd0f26096c4622805baf8a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62540
This adds two new fields: the ideal write size for best EC flashing
performance (e.g., page mode instead of word mode), and a flags field
with a flag to indicate whether the EC erases its bits to 0 or 1.
The EC still supports the old version 0 command, since u-boot and
flashrom expect that to work.
BUG=chrome-os-partner:20973
BRANCH=(all haswell); this will speed up flashing and software sync
TEST=ectool flashinfo
1. old EC, new ectool -> only reports version 0 info
2. new EC, old ectool -> only reports version 0 info
3. new EC, new ectool -> reports new fields
Change-Id: I484327fe22a58d2b69d7f6ac767b2d3e81b3e0b7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62378
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The curent code ends up creating a veneer for interrupt_enable/disable()
which isn't really needed (see below). By calling the interrupt code while
still running from flash we can avoid this.
I cannot see any problem with the current implementation, but it seems that
with this patch I also avoid an exception.
BUG=chrome-os-partner:20976
BRANCH=none
TEST=manual
Build EC and see code generated like this:
200029ec <iram_flash_write>:
200029ec: b538 push {r3, r4, r5, lr}
200029ee: 460d mov r5, r1
200029f0: 4604 mov r4, r0
200029f2: f000 f83d bl 20002a70 <__interrupt_disable_veneer>
...
20002a4a: f000 b809 b.w 20002a60 <__interrupt_enable_veneer>
20002a4e: bf00 nop
20002a60 <__interrupt_enable_veneer>:
20002a60: b401 push {r0}
20002a62: 4802 ldr r0, [pc, #8] ; (20002a6c <__interrupt_enable_veneer+0xc>)
20002a64: 4684 mov ip, r0
20002a66: bc01 pop {r0}
20002a68: 4760 bx ip
20002a6a: bf00 nop
20002a6c: 080007f5 .word 0x080007f5
20002a70 <__interrupt_disable_veneer>:
20002a70: b401 push {r0}
20002a72: 4802 ldr r0, [pc, #8] ; (20002a7c <__interrupt_disable_veneer+0xc>)
20002a74: 4684 mov ip, r0
20002a76: bc01 pop {r0}
20002a78: 4760 bx ip
20002a7a: bf00 nop
20002a7c: 080007f1 .word 0x080007f1
With this patch the veneers go away.
Change-Id: Idfe173b4c8d45a142914b2388bcff8ba708c657c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62243
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There's nothing LM4-specific about the switch module; it's just
checking GPIOs and updating a memory-mapped register.
No code changes; just moving a file.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=verify switch.c is compiled for link and falco, but not pit or spring
Change-Id: I186f3aac1405c7ba8d94b47bb2586c2ad191daba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61930
