One Time Programmable memory can be used to store permanent data like
serial numbers.
Reorganize the code to support writing serial number to OTP, in
addition to pstate (if using its own memory bank) or autogenerate from
unique id (hammer).
+ Add CONFIG_OTP to enable OTP code
+ Add CONFIG_SERIALNO_LEN to indicate the size of the serial number
string. Currently set to 28, when USB serial number is needed.
+ Expose flash_read|write_pstate_serial and add otp_read|write_serail,
remove more generic flash_read|write_serial.
+ Make board_read|write_serial generic, declared outside of USB subsystem.
Priority order to read|write serial string:
- board definition (like hammer)
- pstate location, if stored in its private memory bank
- otp area
If none of these methods are available, a compilation error is raised.
BUG=chromium:746471
BRANCH=none
TEST=compile
Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580289
Reviewed-by: Nick Sanders <nsanders@chromium.org>
LTE_GPS_OFF_L and LTE_BODY_SAR_L are both currently configured as
push-pull output, but they should be OD. Let's also set the default
value to high.
BRANCH=none
BUG=b:64126879
TEST=Flash poppy.
Change-Id: I2e9297c567e74f7d2656557c306337e90a4410c1
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/590908
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Turns out PCH_RTCRST is never used, and its location is either
GPIOE7 (rev 0-3), or GPIO27 (rev 4-).
- Leaving this pin configured as input (default) for rev0-3 should
be fine as there is an external pull-down.
- We still drive it low from rev4, for consistency.
Also, LED_YELLOW_C0 only moved from GPIO32 to GPIO24 (not GPIO27)
from rev5.
BRANCH=none
BUG=b:63048710
TEST=Boot poppy/soraka
Change-Id: I1c474fe8abb97c75210b81662ba1d1af0a7ee82e
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/588428
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The sysrst and ecrst commands are now protected by the RebootECAP
capability. They can print the state of the reset lines when the
capability is not allowed, but can only change the state or pulse the
reset lines when the capability is allowed.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build:
ccdoops --> reset CCD config and go to Opened state
ecrst pulse --> works
sysrst pulse --> works
ccdunlock
ecrst pulse --> access denied
sysrst pulse --> access denied
ecrst --> prints state
sysrst --> prints state
ccdoops
ccdset rebootecap unlesslocked
ccdunlock
ecrst pulse --> works
sysrst pulse --> works
Change-Id: Ia9ebe67bdc1e85129051caf94f20fb2fb84b76da
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590071
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The WP command is now controlled by CCD configuration (ccdset
wpoverride). In addition to enabling/disabling/following battery for
the current boot (counting deep sleep resume), it is also possible to
set the WP override at boot. That's needed to support persistently
disabling WP for RMA without needing to persistently remove the
battery.
Restricted console commands are now controlled by CCD configuration
(ccdset cr50fullconsole).
The old 'lock' console command has been removed, now that
ccdopen/ccdunlock/ccdlock replace it.
The old TPM vendor commands for set_lock is gone; it will be replaced
by CCD configuration TPM vendor commands in a subsequent CL. The
get_lock command still exists, but only reports the console lock
state; it will be removed too.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
ccdinfo --> State = Opened, WPOverride = default(IfOpened)
plug in battery (or jumper DIOM2 to ground on a dev board)
gpioget --> make sure GPIO_BATT_PRES_L=0
wp --> enabled, at boot follow battery
remove battery (or jumper DIOM2 to JTAG pin3 on a dev board)
gpioget --> make sure GPIO_BATT_PRES_L=1
wp --> disabled, at boot follow battery
wp enable --> forced enabled, at boot follow battery
idle d
(wait for restart)
wp --> forced enabled, at boot follow battery
reboot
wp --> disabled, at boot follow battery
plug in battery (or jumper DIOM2 to ground on a dev board)
wp --> enabled, at boot follow battery
wp disable --> forced disabled, at boot follow battery
idle d
(wait for restart)
wp --> forced disabled, at boot follow battery
reboot
wp --> enabled, at boot follow battery
wp disable atboot --> forced disabled, at boot forced disabled
reboot
wp --> forced disabled, at boot forced disabled
wp enable --> forced enabled, at boot forced disabled
idle d
(wait for restart)
wp --> forced enabled, at boot forced disabled
wp follow_batt_pres --> enabled, at boot forced disabled
wp follow_batt_pres atboot --> enabled, at boot follow battery
ccdunlock
wp disable --> access denied
help --> commands like 'crash' are disabled
ccdoops
ccdset cr50fullconsole unlesslocked
ccdset wpoverride always
ccdunlock
help --> commands like 'crash' are still enabled
ccdlock
help --> commands like 'crash' are disabled
wp disable --> forced disabled
ccdoops
Change-Id: Ic441f490bdd7a19dd646fe8338e5d608b42ce72c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575997
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
If there is a board ID mismatch and rollback is not possible Cr50
firmware will enter a limited mode which only support Cr50 firmware
upgrade. All other features must be disabled, because it is not
possible to know which features should be allowed on the mismatched
board.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build, define CONFIG_CMD_CCDDISABLE
ccdinfo --> state=opened
ccddisable --> state=locked(disabled), all capabilities disabled
ccdunlock --> access denied
ccdopen --> access denied
ccdreset --> access denied
ccdpassword --> access denied
ccdset --> access denied
ccdoops
ccdinfo --> state=opened, back to defaults
Change-Id: Idb66fb1f3d5106aa0c2cb6addf2404ea9942b0d6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/590070
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Define two bits in a long-life register to hold the current CCD state
across deep sleep. Update the bits on CCD config change, and restore
them on init.
This is necessary because Cr50 loses RAM contents on deep sleep. It
would be really inconvenient to open CCD, get a cup of coffee, and
come back to find CCD has locked again because Cr50 was idle too long.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
ccdinfo --> state=opened
idle d
ccdunlock
ccdinfo --> state=unlocked
(wait for deep sleep)
sysinfo --> reset flags = hibernate wake-pin
ccdinfo --> state=unlocked
reboot
sysinfo --> reset flags = hard
ccdinfo --> state=opened
Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575996
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This will officially kill the support for rev0 boards.
The major changes include:
1) Massive GPIO rename/reallocation
2) New power sequencing
3) Reconfigure peripherals (e.g. I2C, SPI, ADC)
4) Drop usb_charger_task
5) Remove lid switch
6) Display BL not driven by PWM
7) Move bmp280 from I2C to SPI
8) Remove SPI flash
9) Some placeholders for follow-up changes.
BUG=b:62640322, b:62269890
BRANCH=none
TEST=build scarlet
Change-Id: Idc0a854a0935089295b67da106ba1b35359f146d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/572684
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
100us is hard to measure reliably on poppy side, let's increase to
500us, and widen the range.
BRANCH=none
BUG=b:63818321
TEST=Flash staff and soraka EC, check that pulses are detected
correctly.
Change-Id: I1c29a42c70da0efa0318a619bb83e451b9f168f4
Reviewed-on: https://chromium-review.googlesource.com/581572
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit adds the GPIOs for determining the GPIOs.
Additionally, this adds some alternate functions for the PWM and ADC
pins.
BUG=b:63508740
BRANCH=None
TEST=Flash modified version on EVB and verify that it boots without any
panics or assertions.
Change-Id: I34161ad075ad88f940a21c2ee94219ea6a878d63
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/584052
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1) Don't assert prochot by default, this signal has an inverter
and driving it high is asserting prochot until it gets deasserted
during S3->S0 transition.
2) Clear PMIC power source interrupts in pmic_init in case they
were inadvertently set by misbehaving PMIC. The BATTSHORT event
that matters for PROCHOT assertion is masked so it should never
be set anyway, but I found a system where it was set. This register
does not seem to get cleared by an LDO reset so PROCHOT was stuck on
until battery cutoff.
BUG=b:63913242
BRANCH=eve
TEST=manual testing on Eve unit
Change-Id: I5c7f7ca528160972f65bd714deea98357fa43a53
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/579904
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Support a level shifter for both 1.8v and 3.3v
uarts on SBU.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail, both 1.8v and 3.3v detected.
Change-Id: I76d545b582c6ed15086941513d5de4cd6783ac16
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575595
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
hwtimer ticks at 8 * 32768 Hz rather than 250 KHz, so adjust our timing
appropriately. Also ensure that udelay() will delay for at least the
requested time, taking into account our timer precision.
BUG=b:63858553
TEST=Generate square wave with 1000us udelay between GPIO edge toggle,
verify period is 1000us + code overhead. Also verify timer behavior on
overflow with 'forcetime' command. Also verify accuracy of system clock
to 0.2% with `timerinfo` and a stopwatch.
BRANCH=None
Change-Id: I5da41bd7250db87de5143cc54ebd0bb750fb7003
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/578551
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tigertail Rev. C has a button, we'll use it to toggle
between A, B and off.
BRANCH=None
BUG=b:35849284
TEST=ran on tigertail w/rework, mux muxed.
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I2a2a9ce0ba713c47e6f1196fac62a3804a78bf94
Reviewed-on: https://chromium-review.googlesource.com/575893
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Board rev0 will lose VBAT on power cycle and therefore
cannot successfully save the reset flag state.
Implement workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:63889675
BRANCH=None
TEST=None
Change-Id: Ie79053e2e52a3a9efd9cd864808af7214989602e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579666
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using zero to represent success make it cleaner when processing return
values of this function. Also, let's report different failures using
different error values.
Note that nobody checks this function's return value yet.
BRANCH=cr50
BUG=b:63686091
TEST=none
Change-Id: If25d30e637701f6c37f3ce75e5a5d5315e0e86e9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579583
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
This adds the CCD configuration module, and the console commands to
control it. It is not wired up to any of the CCD capabilities; that's
coming in the next CL.
Briefly:
* CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to
print it.
* CCD can be Locked, Unlocked (some capabilities), or Opened
(all capabilities), using the ccdlock / ccdunlock / ccdopen commands.
* CCD config can be restricted by setting a password via ccdpass.
* Individual config capabilities can be set via ccdset. Some of those will
be used to gate access to things like write protect and UARTs. Others
affect the requirements for ccdunlock / ccdopen (for example, is physical
presenc required).
* The entire config can be reset via ccdreset. If only unlocked, config
that is restricted to Opened is not reset.
* If CR50_DEV=1, ccdoops will force-reset and open the config.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccdlock # lock, because CR50_DEV=1 builds start unlocked
ccdinfo # locked, flags=0, all capabilities default
ccdpass # access denied (we're locked)
ccdreset # access denied
ccdset flashap always # access denied
ccdunlock
ccdinfo # unlocked
ccdpass foo
ccdinfo # flags=2 (password set when unlocked)
ccdset flashap always # access denied
ccdset uartectx unlesslocked
ccdinfo # yes, uartectx permission changed
ccdlock
ccdunlock # fails without password
ccdunlock bar # wrong password
ccdunlock foo # busy
(wait 3 sec)
ccdunlock foo
ccdreset
ccdinfo # no password, flags 0, capabilities all default
ccdopen # requires physical presence; tap power or use 'pp'
ccdset uartectx unlesslocked
ccdset batterybypasspp ifopened
ccdpass baz
ccdinfo # password set, flag 0, ccdset changes worked
ccdunlock
ccdreset
ccdinfo # uartectx back to ifopened, password still set
ccdopen baz # still requires physical presence
ccdset opennolongpp always
ccdlock
ccdopen baz # no pp required
ccdset unlocknoshortpp unlesslocked
ccdlock
ccdopen baz # short pp sequence required (3 taps)
ccdlock
ccdunlock baz # short pp sequence required
ccdopen baz # pp not required
ccdset unlocknoshortpp always
ccdlock
testlab open # access denied
testlab enable # access denied
ccdunlock baz
testlab open # access denied
testlab enable # access denied
ccdopen baz
testlab enable # requires short pp
ccdinfo # flags 1
ccdreset
ccdinfo # no password, flags=1, caps all default
ccdlock
testlab open
ccdinfo # opened
testlab disable # requires short pp; let it time out
ccdinfo # still opened, flags=1
ccdlock
ccdoops # backdoor in CR50_DEV images to force-reset CCD
ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccdreset rma
ccdinfo # flags = 0x400000, everything but Cr50FullConsole always
ccdreset # back to flags=0, all default
Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9
Reviewed-on: https://chromium-review.googlesource.com/569439
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Disable reporting of EC events to the linux kernel that are not used
by kevin's kernel.
BRANCH=none
BUG=chromium:637061
TEST=make buildall passes, lid close puts AP into suspend, lid open
turns on display
Change-Id: I7841294aec0853f4820a262ec14e8ad6037e1060
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/503536
Reviewed-by: Shawn N <shawnn@chromium.org>
This will be used as part of case closed debugging configuration.
Currently, this only adds the state machine, and a test command which
is available when CR50_DEV=1. It also adds a new sleep mask flag for
physical presence detect, instead of oveloading FORCE_NO_DSLEEP.
The physical presence state machine supports both short (tap 5 times
in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes
apart) sequences. It will call a callback function at the end of the
sequence, so that multiple things can each request physical presence
in turn. This will be used by ccdopen / ccdunlock / testlab commands
for CCD V1.
Eventually, CCD config will replace the unlock sequence handling in
wp.c. But for now, we don't touch that.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual
Short sequence:
pp short
pp
pp
pp # See "Physical presence good"
Timeout
pp short
pp # 15 sec later, get timeout error
Long sequence:
pp long
pp
pp
pp
(wait 2 sec)
pp
(wait 2 sec)
pp # See "PP good"
Long sequence, presses too fast:
pp long
pp
pp
pp
pp # See "PP L too soon"
(wait 2 sec)
pp
(wait 2 sec)
pp # See "Physical presence good"
Abort:
pp short
pp abort # See "Physical presence aborted"
Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568796
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This commit adds support for the virtual wire signals over eSPI.
Additionally, the SLP_S0_L signal is added for the board and some minor
changes are made to some GPIOs.
BUG=None
BRANCH=None
TEST=flash zoombini image on npcx7 EVB with some modifications. Verify
no panics or asserts are hit.
Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/577054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In deep S3, SLP_SUS# goes low which results in power to base being
cut. For such cases, PMIC needs to be configured so that it keeps the
power to base up. Use VREN register to keep PP5000_A rail enabled in
deep S3.
BUG=b:63251418
BRANCH=None
TEST=make -j buildall. Verified that wake from base works in deep S3.
Change-Id: Ice3ba56f1a7e52275c3afa332c29b5b252dded4d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/574619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We need to add __keep to the USB descriptors, otherwise they
get thrown away.
Also, for some reason the optimized RWSIG task uses a little bit
more stack space, so account for that:
1 RWSIG 00000000 0.264350 1096/2048
BRANCH=none
BUG=b:63610290
TEST=make BOARD=hammer -j
make newsizes
build/hammer/RO/ec.RO.flat shrank by 2052 bytes: (37336 to 35284)
build/hammer/RW/ec.RW.flat shrank by 3172 bytes: (50508 to 47336)
Flash hammer, touchpad, keyboard, update all still work fine.
Change-Id: I39ffd320dae883596ce481efc4adec6e3c23000b
Reviewed-on: https://chromium-review.googlesource.com/567909
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the bd99954 charger we do not need to discharge when full,
so remove this config option and the setting of 94% for "full"
battery.
Note that this only affects the battery reporting state, the
EVT systems (board <= 4) will still discharge when full (in order
to prevent the charger noise) but they will now indicate that they
are discharging in this state instead of appearing full.
Newer boards (version > 4) will behave as expected.
This is a compile time option so it isn't something I can easily
support old boards with, but I think it is more important to do
the right thing for new boards.
BUG=b:35585628
BRANCH=eve
TEST=test charge behavior when full on board version 6
Change-Id: I3dd46ae305107b17b3bf8e3ce71578d3400b0f79
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573091
Reviewed-by: Shawn N <shawnn@chromium.org>
Eve does not use PECI so disable it and remove from the resulting binary.
BUG=b:35581264
BRANCH=eve
TEST=build EC for Eve and ensure peci module is not included
Change-Id: Ie87d789226b2b5f2162ea96cb001a5cb62359213
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/573083
Reviewed-by: Shawn N <shawnn@chromium.org>
Current LED color changes are abrupt. This CL adds a new function
which steps from one color (some RGB combo) to another gradually. When
the new or old color is white, then precomputed steps computed from
HSI space are used. Other transisions involving either just red/green
use linear steps computed dynamially based on the total change.
This CL also creates a new task for the LED code so that the color
transitions won't hold off other hook tasks for too long a period of
time. Changed the LED tick time to be 500 msec as it's no longer tied
to the hook tick.
BUG=b:35584895
BRANCH=eve
TEST=Using EC console command 'battfake', changed reported battery
charge level and verified that the LED patterns still work as
expected. In addition, had debug code which printed to the console
what the R, G, B duty cycle levels were for each transition and
verified the expected values were achieved. Visually compared version
with transitions to the previous version which changed abruptly.
Change-Id: I4e7c19556db9ed6037f2afa05cf348d19aeb18bb
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/562543
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Fix a issue that user can't use type-c adapter and type-c device at
the same time. ex. Plug in adapter in port1 and then plug in device in
port2. Port1 will stop charge.
2. Update the vbus status when AC change to correct the charge source.
3. We use the typc adapter with capacity 5V/3A, 9V/3A, 15V/3A,
20V/2.25A. Add PD_PREFER_HIGH_VOLTAGE define to request voltage to 20V.
BRANCH=None
BUG=None
TEST=Plug in type-c adapter and device to test
Signed-off-by: Cloud Lin <cloud_lin@compal.com>
Change-Id: I1927008a13651b8fa137d8d1a5000efd7db2e79f
Reviewed-on: https://chromium-review.googlesource.com/485380
Commit-Ready: Lin Cloud <cloud_lin@compal.com>
Tested-by: Lin Cloud <cloud_lin@compal.com>
Reviewed-by: Martin Roth <martinroth@chromium.org>
This patch gives EC the capability of verifying and jumping to
RW_A or RW_B. EC tries the slot stored in a persistent storage
(e.g. BBRAM). If verification fails due to invalid contents, EC
tries the other slot. AP's expectation and its reaction to the
state of the slots and the currently running image are summarized
below.
Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC
won't try to verify or jump to RW yet.
| AP expects X
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X' | reboot to B
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X' | reboot to A
----------+---------------------------
SLOT_A=X' | write X to B, reboot to B
SLOT_B=X' | write X to A, reboot to A
BUG=b:38462249
BRANCH=none
TEST=Lock the system and boot Fizz on barrel-jack and type-c.
Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/556286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The Simplo_a50 battery had voltage_max = 8750 mV, which is not correct
and it should be 8800. Since the voltage_max parameter is used with
-0.5% margin, the 8750 mV value resulted in a charger setting of 8704
and does not provide enough of a voltage delta between the charger and
the battery to fully charge packs that exceed the design capacity.
In addition, had the tables for both battery types reviewed by the HW
team and updated some of the temperature parameters.
BUG=b:62483321
BRANCH=eve
TEST=Tested with a dogood unit that was failing to reach 100% charge
and showing very long "time to full" values as the battery charge
approached 90%. After adjusting the voltage_max param, tested and
verified that the battery reached 100% charge. In addition, verified
the bd9995x 0x1A register had the correct voltage setting.
Change-Id: I40e7bc111b048986e824fcb7843e57433a1def84
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/570380
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The `brdprop` command simply returned board_properties, however,
board_properties is just a cache of the properties from init time. When
the `brdprop` command was issued, it would only return the cached value.
This commit changes the functionality of the `brdprop` command to always
query the LONG_LIFE_SCRATCH1 register.
BUG=b:63456150
BRANCH=cr50
TEST=Flash bob. Unplug and plug in battery, verify that
BOARD_WP_ASSERTED is set when running the `brdprop` command.
Change-Id: I0a7feb5e63f3e528b554ed0820924ac0705f5517
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/566240
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The LED pattern for lowest battery level is supposed to indicate that
there isn't enough battery present to boot the AP. The pattern_tbl
array had this value set to 2. However, it's better to tie this to the
constant defined in board.h so that it's consistent with when the AP
will be allowed to boot. In addition, adjusted the battery level
ranges to work correctly with the <= check.
BUG=b:35584895
BRANCH=eve
TEST=Used 'battfake' console command to verify that the patterns
changed at the expected battery charge levels.
Change-Id: Ie85a448ad4803be7e612c382b8e60fa42356d257
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/562542
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
This commit adds support for the PS8805, another Parade Tech TCPC with
integrated superspeed muxes. This also creates a generic Parade Tech
TCPC driver which supports the PS8xxx series.
The current supported TCPCs are:
- PS8751
- PS8805
BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I78383af414996e0e8d6220985d286f95267136f8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564799
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
For hammer, we do not want to require finalization in factory, so
we just protect RO whenever WP GPIO is set.
BRANCH=none
BUG=b:63378217
TEST=Enable CONFIG_FLASH_PSTATE_LOCKED, flash hammer,
check with flashinfo that RO protection matches WP status.
Change-Id: I902ee478c00a3c932277d2a7d0622c070654a5eb
Reviewed-on: https://chromium-review.googlesource.com/563217
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
GPO32 is "PU [30K] during reset, then Hi-Z", so change to GPIO27
avoiding USB-C (P0) LED shortly light up during EC reset.
BRANCH=none
BUG=b:63048710
TEST=Rework poppy board by wiring EC_CHG_LED_Y_C0 to TP38
Change-Id: I91e3dd58849ce15f9a85408aec94fd3f94acf038
Reviewed-on: https://chromium-review.googlesource.com/558785
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Tony Lin <tonycwlin@google.com>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
mux_lock is only used whenever the 2 PI3USB chips are sharing a
common I2C bus, and is only valid if mux_gpio and mux_gpio_level
are also set in the structure:
if (chip->mux_lock) {
mutex_lock(chip->mux_lock);
gpio_set_level(chip->mux_gpio, chip->mux_gpio_level);
}
Let's remove mux_lock on poppy.
BRANCH=none
BUG=chromium:740010
TEST=Flash poppy, BC1.2 charging works on both ports.
Change-Id: I76490c379efdfb3f37c590129429c163a03ae664
Reviewed-on: https://chromium-review.googlesource.com/563147
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
