Logical address selection is best done from the AP since
it depends on what kind of CEC device type we want to be.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Set address to different values and verify that it
only receives messages on that address (or broadcast)
CQ-DEPEND=CL:1030229
Change-Id: Ia5ef182b22f2345831caaa7f29cc9f009f932c99
Reviewed-on: https://chromium-review.googlesource.com/1030370
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If pulses shorter than the CEC specification allows are detected,
ignore the bus for a while. This avoids CPU stress if there is a
misbehaving device sending short pulses on the CEC bus.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=none
CQ-DEPEND=CL:1030228
Change-Id: I55819f9437a00799718e235c30f256508465bf4c
Reviewed-on: https://chromium-review.googlesource.com/1030229
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When an incoming message is complete, store it in a
internal circular buffer and notify the AP so the
message can be read out.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Write different type of messages from one EC to another EC
using ectool. Also use ectool on the second EC to verify that
they are received correctly.
CQ-DEPEND=CL:1030226
Change-Id: Ie4370b0c954befe81a055cd5dff7d7f13dbefbd0
Reviewed-on: https://chromium-review.googlesource.com/1030227
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Adds handling of incoming messages:
* Start-bit detection
* ACK incoming messages
* Broadcast handling
* Pulse-width validation
* EOM detection
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Tested in later CL when messages are plumbed all the
way back to the AP.
CQ-DEPEND=CL:1030225
Change-Id: I541072b8afa3d911b310628f09f0b665f11a0a15
Reviewed-on: https://chromium-review.googlesource.com/1030226
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The Linux kernel has enable/disable hooks in the CEC
driver API. Make it possible to use those calls on
the EC CEC implementation.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Verify with logical analyzer that nothing happens on
the bus in disable mode and it still works in enable mode.
CQ-DEPEND=CL:1030223
Change-Id: Ib5255d76427f288862740cd2e3299ba47f39d998
Reviewed-on: https://chromium-review.googlesource.com/1030224
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
According to the CEC specification, a resend must be
attempted at least once and up to five times after NAK.
This fix does it five times.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Write CEC message without sink. Verify with logical
analyzer that it resends 5 times.
CQ-DEPEND=CL:1030221
Change-Id: Id296e12b6657b9e7ca0453a2deb06e8aaf17f839
Reviewed-on: https://chromium-review.googlesource.com/1030222
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add hooks that ectool or AP will use to send CEC messages.
Messages are sent by setting a timer and flipping
a GPIO in the timer interrupt. The timer is then
recharged in inside that interrupt depending on
where it is in the CEC state-machine.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Switched on and off a TV:
ectool cecwrite 0x40 0x04
ectool cecwrite 0x40 0x36
CQ-DEPEND=CL:1030220
Change-Id: Ia640d0d035bcee9be88863046e88402c7a63c19f
Reviewed-on: https://chromium-review.googlesource.com/1030221
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add CEC stub implementation and enable it for Fizz. All
it does is print a message when the driver is initialized.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Check that "CEC initialized" is printed on the
console when the EC boots.
CQ-DEPEND=CL:1030219
Change-Id: I1cf674e664e091354e344e0c08a69bd09f415904
Reviewed-on: https://chromium-review.googlesource.com/1030220
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The kernel is only able to know the number of USB PD port through
EC_CMD_USB_PD_PORTS, but the kernel needs also to be able to know
that there is a dedicated port. Add a host command that will
return the total number of charge port (USB PD + BJ).
BRANCH=None
BUG=chromium:841944
TEST=Called command from kernel driver and checked that the port count
was the expected value.
Change-Id: I6ccd8a2dee35bbe8bb66dfbe09d1cc09c54b73a0
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-on: https://chromium-review.googlesource.com/1046593
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
When EC sees discharge current hit BAT_MAX_DISCHG_CURRENT,
we kick off a timer and ask AP to throttle.
Then EC keeps monitoring discharge current. If the current doesn't
drop below BAT_MAX_DISCHG_CURRENT - BAT_OCP_HYSTERESIS, we restart
the timer and notify AP again, which shouldn't happen unless
AP misses or ignores the first notification.
When the timer expires, which means EC hasn't seen over-current
for BAT_OCP_TIMEOUT_US, we ask AP to stop throttling.
BUG=b:74321682, chromium:838754
BRANCH=scarlet
TEST=manually test on scarlet, confirm EC sends
EC_HOST_EVENT_THROTTLE_START and EC_HOST_EVENT_THROTTLE_STOP
host events when entering/exiting OCP.
Change-Id: I1e55fc23249596d8afec52a3885655ca9c1f2151
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/994188
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Add a serial number match to allow update of servo or
other usb devices, where mutliple devices may be attached
to one system.
BRANCH=None
BUG=chromium:718688
TEST=usb_updater2 -d 18d1:501b --serial=[C1706311869|fail]
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Id6ec944139e685948433af703555fd185e91a9d4
Reviewed-on: https://chromium-review.googlesource.com/1050971
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Allow board & addr in the board file instead of channel, to make board
file creation and configuration simpler.
This is part of the efforts in the BUG to make sweetberry under chrome
os simpler to use. In that case, we allow now (with crrev.com/c/1051215) to
generate .board files using explicit pin and bank numbers (j2,j3,j4).
BRANCH=None
BUG=chromium:806148
TEST=manual test, works fine.
Change-Id: I6fd3bb1a4a5ffffee08b81625ecb190adceeb2e7
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1051212
Reviewed-by: Nick Sanders <nsanders@chromium.org>
The Fizz hardware has three pins for CEC. One GPIO is used
as a pull-up. It is always an output and always high. The
second GPIO is a data output. The third GPIO is the data
input that can also be configured as a timer input (TA1).
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Read and write the newly added GPIOs using ectool
Change-Id: Ia33b36a0cdaa40fd1a4f7aa66a092b5833bf5cf8
Reviewed-on: https://chromium-review.googlesource.com/1030219
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This patch adds an interrupt handler for a tablet switch and an init
hook to enable the interrupt.
The handler does the typical tasks for convertible devices: 1. sets
tablet mode then 2. disables peripherals if tablet mode is on.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77298177
BRANCH=none
TEST=buildall. Verify on Nami.
Change-Id: If7fb5ea15f388d2b6084d800d2bc05efafd1945e
Reviewed-on: https://chromium-review.googlesource.com/1043057
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This patch refactors motion_lid so that EC can decide to use lid angles
to set tablet mode at run time.
Then, it implements board_is_lid_angle_tablet_mode to enable the feature
for Nami and Vayne.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77298177
BRANCH=none
TEST=Verify on Nami.
Change-Id: Ib717911a16fe031aa6c6ede731e6aa722d32d022
Reviewed-on: https://chromium-review.googlesource.com/1024914
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
PD is enabled so don't need it.
BRANCH=none
BUG=b:74395451
TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests:
* Verified USB boot
* Plugged adapter to port-0/port-1/both and saw charging
* Plugged USB device to port-0/port-1/both and saw sourcing VBUS
* Plugged adapter to one port and USB device to another port
* Plugged USB disk to port-0 and booted into kernel
* When AP off, not sourcing VBUS to USB device
* Rebooting AP still works
Change-Id: Ib878960fb302d85549735a395f75cc8d045d45f2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1042621
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Port 0:
TCPC: ANX3429
PPC: SN5S330
BC1.2: PI3USB9281
Port 1:
TCPC: PS8751
Power switch (sink): NX5P3290
Power switch (source): NX20P5090
BC1.2: PI3USB9281
Charger: ISL9238
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests:
* Plugged adapter to port-0/port-1/both and saw charging
* Plugged USB device to port-0/port-1/both and saw sourcing VBUS
* Plugged adapter to one port and USB device to another port
* Plugged USB disk to port-0 and booted into kernel
* When AP off, not sourcing VBUS to USB device
* Rebooting AP still works
Change-Id: Icde5e24c2cda3d0f2046486528a210af84befcca
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969701
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
When we write a 0 to the register it actually prevents
future calls from correctly determining if the OCM is
present.
BRANCH=none
BUG=b:79123179
TEST=board with OCM still reports ocm after multiple anx_ocm 0 calls
Change-Id: I3899e8999483518fb42ddbd044d29e32fc3380f3
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047830
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Update the fingerprint match event to include the index of the template
which matched.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:77516790
TEST=on ZerbleBarn, enroll 5 fingers and do matching from the console,
see the proper finger index in the trace.
TEST=on Meowth, check unmodified biod still works for match with the
updated MCU firmware.
CQ-DEPEND=CL:*621808
Change-Id: I5be77ba65ce232989606274aba9a6c20841d533c
Reviewed-on: https://chromium-review.googlesource.com/1047267
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
In npcx5 series, there is no other chip generation and npcx's system
driver fixed the first character of revision array as 'A'. But in npcx7
series, there are two chip generations and it's better to show chip
generation information by 'version' console command.
In this CL, we used SRID_CR to distinguish the generation of npcx7
series. It also adds the support for NPCX787G in system_get_chip_name()
since it is used on the version 1 of npcx7 evb.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Verified npcx5m5g, npcx7m6g and
npcx7m7wb on evbs by 'version' console command.
Change-Id: I7572b5688b4430c6febd21c25f36c3903fb97e27
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1046689
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The ACOK_OD is a required signal of the charging state machine. EC
can't always hold it low; however, it breaks the charging state.
Make it back to EC input. There are some side-efforts, mentioned in
the bug.
BRANCH=none
BUG=b:78035750
TEST=Plugged/unplugged AC when AP is on/off.
TEST=Verified the power sequence still works.
Change-Id: I039af9cdb86cfb509f2580e6f57d82309825dac1
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1042620
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When we support the lowest power mode for Nuvoton in the next spin, we
will shed the TCPC/PPC power rail during hibernate. Before we drop the
power for the PPCs we need to ensure that Vbus is lower than the
hard-coded 6.8V dead-battery mode over-voltage threshold, otherwise we
will lock ourselves out of power.
BRANCH=none
BUG=b:79218851
TEST=verified that yorp renegotiates Vbus to 5V when entering hibernate
via ec `hibernate` cmd.
Change-Id: I4a98573eefb5757eea02dc48c64d5f9358b5e0b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047954
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Keep the timestamp of the latest power lost. Add a handler to wake
the chipset task to check if power lost stays low for a while (the
time between now and the latest power lost is longer than a period).
BRANCH=none
BUG=b:78455067
TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset
sequence and verified AP reset but not a transition S0 -> S5.
TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse
(see power_off function) to execute PMIC shutdown sequence and verified
a power-lost transition S0 -> S5.
Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028831
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising
edge interrupts to trigger a hook to call chipset_reset().
As the hook task will be preempted by the chipset task, it adds a
flag bypass_power_lost_trigger to avoid triggering to S5 as the
chipset state machines sees power lost during the reset.
So far the chipset_reset() implementation is to do a cold reset;
will be revised to a warm reset after the PMIC registers are
reprogrammed.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Ran 'reboot' on AP console which toggles the GPIO.
Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1023986
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On newer boards, FP_RST_ODL is no longer Open-Drain and has a 100k
pull-down. Drive it as push-pull.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:79277207
TEST=On ZerbleBarn, verify that the sensor comes up, has the right HWID
and can capture images.
TEST=On new boards, do the same.
Change-Id: I45e1ba41a7649e0682e3ea11dd0159f666286bba
Reviewed-on: https://chromium-review.googlesource.com/1049545
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
we need to configure EC_PROCHOT_ODL as an input because the EC isn't
driving it correctly. we changed the polarity of EC_PROCHOT for atlas
and similar boards, but the EC codebase has this hard-coded as
active-high.
this is a short-term fix until we implement a more general PROCHOT
"polarity" feature.
BUG=b:78911901,b:79266467
BRANCH=none
TEST=checked voltage drop across in-line resistor on EC_PROCHOT and
AP can now run above 400MHz
Change-Id: I8c3224c62ea7af4f386062d39c248d418e73fa53
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045556
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
the isl9238 needs to see a higher PPVAR_SYS voltage than we were using
to avoid tripping Low_VSYS. Low_VSYS is one of the terms causing the
isl9238 to assert PROCHOT. its lowest default voltage threshold is
about 6.1v which is too close to the battery "minimum" that we were
using to set PPVAR_SYS. it's better to use the "normal" battery
voltage so the running-on-AC case is similar to the running-on-battery
case.
BUG=b:78911901
BRANCH=none
TEST=examined isl9238 regs to verify it is no longer tripping Low_VSYS
Change-Id: Iafc39e988a5af668c6cc1b5485841f6d659b1e8b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1043456
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
We add a configuration option to set the minimum shared memory
size (CONFIG_SHAREDMEM_MINIMUM_SIZE), so that the link will fail
if there is not enough IRAM left.
Also, we add 2 macros around shared_mem_acquire, that check, at
build time, that the shared memory size is sufficient for the
allocation:
- SHARED_MEM_ACQUIRE_CHECK should be used instead of
shared_mem_acquire, when size is known in advance.
- SHARED_MEM_CHECK_SIZE should be used when only a maximum size
is known.
This does not account for "jump tags" that boards often add on
jump from RO to RW. Luckily, RW usually does not do verification,
and does not need as much shared memory.
BRANCH=none
BUG=chromium:739771
TEST=make buildall -j, no error
Change-Id: Ic4c72938affe65fe8f8bc17ee5111c1798fc536f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1002713
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When cr50 resumes from deep sleep term_enabled is reset to 0, but not
all of the s3 termination settings are reset. Some of them are, because
some of the gpios are defined in gpio.inc and cr50 will handle setting
those up during init, but others like the sps pulldowns aren't. At this
point, the term_enabled setting does not actually match the state of
enabled terminations.
After deep sleep reset if the AP is on, ccd update state will try to
disable the s3 terminations, but term_enabled is 0, so s3_term thinks
they're already disabled and wont do anything even though some of the
terminations are actually enabled.
This change initializes all of the s3_term stuff to disable during hook
init. This way things are reset so they won't interfere with sps_init.
This will also make sure to align the system state with term_enabled,
before the ccd hook starts getting called. It is safer to start with
disabling the terminations, because it wont interfere with tpm
communication if the AP is on. If the AP is off, ccd_update_state will
re-enable the terminations around a second after init.
BUG=b:62200096,b:79214702
BRANCH=cr50
TEST=firwmare_Cr50DeepSleepStress.reboot on bob
Change-Id: I9a90c7f7703b1406b4c494db448a8ac84d040d1c
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1043152
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It was observed on yorp that connecting AC when EC is in hibernation
does not always reliably wake the EC up. The reason for this seems to
be that USB_C0_CHARGE_ON from ANX7447 is not asserting SINK_CTRL and
PPC does not pass through ACIN and thus ACOK_OD remains low.
This change ensures that SINK_CTRL is enabled on all the ports before
EC goes into hibernate state.
BUG=b:79173959
BRANCH=None
TEST=Verified that EC wakes up from hibernate reliably with AC
insert.
Change-Id: I14ff2c89511993fec53462ac606b92e5d9438739
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1043076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
