Rename from V5A_EN to PMIC_EN.
The name V5A_EN came from Amenia where it controls both
5V_A-Rail and PMIC_EN.
Reef has a separate 5V_A-Rail control (EN_PP5000) and
an another GPIO pin for PMIC_EN.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=buildall pass
Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354767
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Board initialization function configures certain RBOX registers, but
RBOX initialization runs at the same priority as board initialization,
and as such is not guaranteed to run in time.
Reducing RBOX initialization priority guarantees that RBOX is
initialized by the time board init function needs to access it.
BRANCH=none
BUG=chrome-os-partner:49959
TEST=the AP_WP_L signal now reports the expected value:
> gpioget AP_WP_L
1 AP_WP_L
>
Change-Id: I9c29451a08fc47d3409031bda1a936de243c0c70
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358169
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since we are targeting a 45W solution, set max power to 45W.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Zinger and make sure 20V/2.25A is used instead of 20V/3A
Change-Id: Ie57a1df39f0cc642fe3644535aa1b5aa92f1ff35
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/358320
Reviewed-by: Rong Chang <rongchang@chromium.org>
In some rare instances the learn bit gets inadvertently set in the
charger which disables charging. Disable it in charger_set_mode unless
its been set intentionally.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=chrome-os-partner:51196
BUG=chrome-os-partner:54484
TEST=manual,
on Chell w/ charger attached and charging
- force learn on manually, see charging stop
i2cxfer w16 4 0x12 0x3c 0x1000
- wait a second, see charging restored
- check learn has been disabled
i2cxfer r16 4 0x12 0x3
0x0000
- set learn on explicitly
ectool chargecontrol off
- see charging remain disabled
- check learn has been enabled
i2cxfer r16 4 0x12 0x3
0x1000
ectool chargecontrol normal
Change-Id: I26f1e855dcad1aa41530d06555a9be7956fdf435
Reviewed-on: https://chromium-review.googlesource.com/353530
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch replaces a long standing stub. When the EC asserts this
signal, the CR50 must reset.
But this signal could be driven by CR50 itself as well, and in that
case the signal's assertion should not be causing the CR50 reset.
Ideally it should be possible to tell if the pin is configured as
output and ignore its assertion in that case. But there is no API for
checking the pin configuration settings at this time. An API function
is added to check if the AP Flash is being programmed, the GPIO
configuration access API is left for future enhancements.
BRANCH=none
BUG=chrome-os-partner:52366, chrome-os-partner:54982
TEST=issue 'reboot' command from the bash command line.
- verify on the cr50 console that it reboots along with the rest of
the device
- observe that reading of the NVRam spaces is still fully
functional, and Kevin can boot all the way up to the login
screen.
- try flashing AP firmware through CR50, verify that it succeed.
Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357967
Reviewed-by: Shawn N <shawnn@chromium.org>
In NPCX5m5g/NPCX5m6g, PM channel 1 can support both
PC87570-Compatible and enhcnced mode. In next generation of chip,
only enhanced mode will be supported. Set the enhanced mode as
default in the firmware to support all gereration of chips.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/357752
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Currently, it is assumed the host will sooner or later retrieve the
events from the sensor ring: It is only used by Android and the sensor
HAL is enabling the ring buffer at boot.
But if nobody processes the ring, and the ring is almost full, the EC will
generate interrupt for every new events.
This can happen with ARC, where events generated for ChromeOS
will be in the ring but nobody will process them until Android is
started.
Add a command to allow sending ring MKBP events. It will be used when
the IIO ring buffer is enabled / disabled.
It also can be used for preventing raising interrupt when the device is
about to go to sleep.
BRANCH=ryu,cyan
BUG=b:25425420,b:27849483
TEST=Check with fiforead that no events are queued when IIO ring
buffer is disabled.
Check with ectool and androsensor that interrupt generation stops.
Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356689
Allow at least 10ms for the 'version' cap to charge in order to have a
voltage on the ADC pin that reflects our voltage divider circuit.
BUG=chrome-os-partner:54768
BRANCH=None
TEST=Manual on kevin. Run 'ver', verify that rev3 board is recognized as
version 3.
Change-Id: I1f3326f4c99a165d77363834d5671aa357a89007
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357970
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
For certain board configurations, KSI2 will be stuck asserted for all
scan columns if the power button is held. We must be aware of this case
in order to correctly handle recovery mode key combinations.
BUG=chrome-os-partner:54602
BRANCH=None
TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I03d76e1121107484f79520745858388f6cae096c
Reviewed-on: https://chromium-review.googlesource.com/357590
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The fix for SPI bus base address missed the tpm test driver, this patch
fixes the issue.
BRANCH=none
BUG=chrome-os-partner:54720
TEST=tpmtest.py connects over ftdi & tests pass
Change-Id: I5a59a6e089aee5a7c25466e0d183f3647c67343a
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356556
The motion sensor drivers used to rely on #defines indicating I2C or
SPI port to tell which to use. However, these days the drivers get
that info passed in via the motion_sensor_t struct. Now this #define
simply decides whether to compile in SPI or I2C wrapper code. We
should eventually make it less confusing, but that's beyond the scope
for now.
BUG=none
BRANCH=none
TEST=reef motion sensor init works now
Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356822
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The modexp implementation occasionally produces
a result larger than the modulus, in which case a
single final reduce is required. The software
based implementation already has this check.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tpmtest.py passes
Change-Id: I0a830781e2a109963394d0702cbc2ca6457c410c
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/357010
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This handles the case where we wish to disable the mux.
Without this the "else" case will return EC_ERROR_UNIMPLEMENTED
when we transition to the PD_STATE_SRC_DISCONNECTED state, and
the EC console shows "Error setting mux port(0)."
BUG=none
BRANCH=none
TEST=no longer see "Error setting mux port(0)" on Reef EC console
Change-Id: I97f35775a5c92636ede1b32293b3a4d01e002dc0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354680
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a test that verifies RSA keygen from a fixed seed and
template from the TCG EK Credential Profile spec.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpmtest pass
Change-Id: I2f1cfb8460a0497c93079b89b9ff4e031eaff358
Reviewed-on: https://chromium-review.googlesource.com/356561
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
SHI_OBUF_VALID_OFFSET may wrap on buffer full, leaving us with an
incorrect tally of bytes transmitted. Always assume the worst case, that
SHI_OBUF_VALID_OFFSET is at maximum, when deciding to apply 256B bypass.
BUG=chrome-os-partner:54566
BRANCH=None
TEST=Manual on gru. Verify 'flashrom -p ec -r read.bin' does not produce
CRC errors.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7c0ccc1b555838854584a3be8ced50057eaea961
Reviewed-on: https://chromium-review.googlesource.com/356771
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
When verifying RW using rwsig, we need to be able to erase the RW
signature to remain in RO. This change excludes the RW signature from
the area protected by system_unsafe_to_overwrite, so flash write can be
used to overwrite the RW signature while still in the RW system image.
BUG=none
BRANCH=lucid
TEST="ectool flashwrite 0x1ff00 corrupt_sig" runs successfully, and on
reboot the EC firmware verification fails.
Change-Id: I7e234664ae564eef30a8b021ea0539b6c0ae898e
Reviewed-on: https://chromium-review.googlesource.com/356810
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To achieve higher power efficiency, we want the input voltage to be as
low as possible. If the PD source advertise several choices over
PD_MAX_POWER_MW, choose the one with the lowest voltage.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Liteon charger and make sure 15V/3A is selected
Change-Id: I6157eb94a1cb45cd537acc79c377db2cff09d922
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/356317
Reviewed-by: Rong Chang <rongchang@chromium.org>
If set_cc() is called, our toggle interrupt may still be active. Since
alert() is called from the pdcmd task and set_cc() is called from the
pd tasks, an unwanted interrupt may fire and override our desired CC
settings.
BUG=chrome-os-partner:54786
BRANCH=None
TEST=Manual on gru. Rapidly attach + detach DP dongle, verify we don't
get stuck in SNK_DISCONNECTED_DEBOUNCE.
Change-Id: Ib60123c45d9a3a78243a3347377fb2190cbdf94b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356513
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Changes were submitted for ec_commands.h but only in the braswell tree.
Merge in ToT for future reference.
BRANCH=none
BUG=chrome-os-partner:50627
TEST=compile.
Change-Id: I74f6ce3c5fd2a628879593a65506d10c44ee574d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356551
If SHI finds itself in an unexpected state, we may try to print an error
message for each IBF / IBHF interrupt, which is excessively spammy and
may even lead to EC watchdog. Avoid console spam by not duplicating IBF
/ IBHF / IBEOR error prints, if our state doesn't change.
BUG=chrome-os-partner:54502
BRANCH=None
TEST=Manual on gru. Verify only one print is seen when SHI fails due to
missed initialization.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I331c64c24fa3a68d7c17e052240691076d3532cc
Reviewed-on: https://chromium-review.googlesource.com/356239
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The CR50 RO version is identified not just by the git hash, but also
by the fuse settings and keys used for signing. The first four bytes
of the entire RO image's hash are saved in the image header. Adding
these four bytes to the version string reported to the host allows to
uniquely identify both RO and RW firmware versions.
BRANCH=none
BUG=none
TEST=verified that the appropriate string is showing up:
localhost ~ # grep cr50 /sys/firmware/log
Firmware version: RO: 97594095 RW: cr50_v1.1.4803-dcac93a-dirty
localhost ~ #
Change-Id: I30a21fad15d99523b1edfa1baa32d80b44e7d0df
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356735
Reviewed-by: Scott Collyer <scollyer@chromium.org>
If the battery is not yet ready to provide the power or battery is
not present and the charging current is set to 64mA then the charger
voltage regulation is transient. ROHM recommended 512mA of minimum
charging current for this issue, hence changed the minimum charging
current from 64mA to 512mA.
BUG=chrome-os-partner:54821
BRANCH=none
TEST=Manually tested on Amenia.
a. Until the battery is initialized from cut-off mode, charging
voltage doesn't drop below battery voltage max.
b. With 15W charger (5V, 3A) without the battery, charger voltage
is regulated to battery voltage max.
Change-Id: I44172d4e9152b699976137bf070d618097c8cef7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/356570
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added console commands for the debugging purpose
psys - Can be used to measure the system power
amonbmon - Can be used to measure AMON/BMON voltage diff, current
BUG=chrome-os-partner:54273
BRANCH=none
TEST=Manually tested on Amenia
psys - Ran fish task and observed psys value changes.
amonbmon - AMON & BMON voltage & current are same as measured
across sense resistors.
Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/353043
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The highsec jittery clock was breaking the USB peripheral, because it
would use bank values that mapped to frequencies less than 15MHz. This
change modifies stepx16 to keep the bankvalues mapped to frequencies
above 18MHz to ensure the USB peripheral can work with the high
security jittery clock.
BUG=chrome-os-partner:53952
BRANCH=none
TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin
Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the Cr50 doesn't have anything else to do and it's been a
while since anyone has communicated with it (10 seconds via UART,
1 second via SPI, and the USB bus has stopped sending SOF
packets), it enters one of three idle states:
wfi = fully powered, just waiting for an interrupt.
sleep = low power mode, but RAM is preserved. It resumes quickly.
deep sleep = hibernate. RAM is lost, resume is a warm boot
You can get/set the idle state with the "idle" console command.
BUG=chrome-os-partner:49955,chrome-os-partner:54331
BRANCH=none
TEST=make buildall
To test it:
* I've only tested on the debug board, because I need a serial
console (not serial-over-USB) to see if it's asleep or not.
* I haven't been able to knowingly force USB Suspend on my
workstation, so to fake it I just unplug the USB cables.
* Wait 10-12 seconds after typing anything on the serial console,
then press a key. If the Cr50 was asleep, the first character
will be lost. If it wasn't, you'll see the character echoed
immediately.
Change-Id: Icc213e50b0c38f8c2b16bcd9960e2e5550b43180
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356123
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
- Power up the AP automatically on initial EC power-on.
- In S0, wait for 8s power button hold before powering down.
- In S3 and lower, power down immediately on power press.
- In G3 / S5, power up on lid open.
BUG=chrome-os-partner:54582,chrome-os-partner:54511
BRANCH=None
TEST=Manual on gru. Verify the following:
- AP powers up when battery initially attached.
- `reboot` powers up AP after EC reset.
- `reboot ap-off` doesn't power up AP.
- `apshutdown` + `lidclose` + `lidopen` causes AP power-up.
- Holding power for 4s in S0 does not change power state.
- Holding power for 8s in S0 causes AP power down.
Change-Id: I588056549a972212c28b9aa6a83fe2e0b179baa9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355650
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
We need to write 0 to RBOX_WAKEUP_CLEAR after writing 1 to clear the
rbox wakeup registers.
BUG=none
BRANCH=none
TEST=after init verify 'rw .h 0x40550098' returns 0
Change-Id: Id7eda45f443300e77f293556eece72d52ca28f17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355283
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Hsiao-heng Lee <kelinlee@google.com>
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Change-Id: I5459cb587badd46c03d1c433f13fdf21a5dc63ed
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355282
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
For designs where the host SOC is responsible for setting the USB-C SS
mux, the EC must track the desired mux state and inform the host when
the desired state changes. Then, the host must ask the EC for the new
desired state and set the mux accordingly.
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75
Reviewed-on: https://chromium-review.googlesource.com/355281
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This updates the lockfile path for FHS 3.0 since powerd as well
as other pieces of software are migrating over.
BUG=chromium:616620
CQ-DEPEND=CL:351271
BRANCH=none
TEST=compiled
Change-Id: I6aa5fa30225e45039316e4a3af0e50cdef0fdf4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351345
Reviewed-by: Dan Erat <derat@chromium.org>
Created a new TPM register define at the beginning of the
vendor defined configuration register space 0xF90 - 0xFFF.
Note that this same space is defined for each locality.
In order to retrieve the FW version string, the TPM register
at offset 0xF90 needs to be written. This will initialize
a the pointer index to 0. The same register is then
read by the AP and each read will return up to 4 bytes of the
FW version string. Once Cr50 detects the string termination
character, it stops incrementing the index so that 0s continue
to be returned for each subsequent read.
In addition there is a max value of reads for the case when the
version string is corrupt and doesn't have a '\0' character.
BRANCH=none
BUG=chrome-os-partner:54723
TEST=Manual
Added a routine in /coreboot/src/drivers/spi/tpm.c tpm_init()
that does the write/read sequence described above. This test
routine produced the folloiwng AP console output:
Reading TPM EC Version!!
scollyer@ code goes here
Read 1: cr50 0x30
Read 2: _v1. 0x2e
Read 3: 1.47 0x37
Read 4: 81-1 0x31
Read 5: 3619 0x39
Read 6: 95-d 0x64
Read 7: irty 0x79
Read 7: 0x0
Cr50 FW Version: cr50_v1.1.4781-1361995-dirty
Read Count = 29
Initialized TPM device CR50 revision 0
Change-Id: I5d68a037f7a508e3109c35e841dbcb3a893ce22f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355701
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The "PC Client Protection Profile for TPM 2.0" document defines SPI
bus addresses for different localities. That definition is not honored
in the cr50 implementation, this patch fixes it: locality zero
register file is based off 0xd40000.
BRANCH=none
BUG=chrome-os-partner:54720
TEST=verified that upstream Linux driver is happy now
Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355610
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On EC reset where PMIC_EN will be pulled low,
PMIC could get into an unknown state and will
not sequence properly on sub-sequent boot.
This is a temporary workaround for Reef Proto,
a hardware change will be implemented on EVT.
BUG=chrome-os-partner:53974,chrome-os-partner:54507
BRANCH=none
TEST=Reef powers to S0 and starts coreboot after EC reset
Tested with servo cold reset button
and console reboot command
Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354762
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54503
BRANCH=none
TEST=Manually tested using console commands on both the ports.
a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is
1 when AC connected & 0 when AC disconnected.
b. Issued 'hibernate' & on plugging in the AC, device
boots to S0.
Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354721
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added mutex lock for nvmem write/move operations. In the
current implementation, there is no single entry point
for the platform specific NvMem calls. The mutex lock is
coupled with a task number so that the same task can attempt
to grab the lock without stalling itself.
In addition to the mutex lock, changed where the cache.base_ptr
variable is updated. Previously, this was done prior to the
partition being copied from flash to the shared memory area.
Now, the variable is only updated after the copy so that read
operations will always read from the correctly from either
flash or from cache memory if a write operation has been
started.
BRANCH=none
BUG=chrome-os-partner:52520
TEST=Manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353026
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
