_cpri__EccPointMultiply should check whether the provided
point is on the curve prior to doing a multiply.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=TCG test CPCTPM_TC2_4_13_01_01 passes
Change-Id: Ia92494070c62f7e03b395975138c0c8446a7284d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/341112
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This change modifies the behavior of RBOX by blocking the key0 and key1
output, when the power button is pressed. It also adds support for
printing debug statements when various RBOX interrupts are triggered.
BUG=none
BRANCH=none
TEST=On cr50 test board verify key0 and key1 out are not asserted unless
the power button is pressed.
Change-Id: I67a3c1b8009279015bdc87bcf0995cffa9ab6f03
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341470
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Setitng SYS_RST_L as an output contends with the EC setting it as an
output. We will only drive the pin when necessary.
BUG=none
BRANCH=none
TEST=power on kevin and make sure the AP is able to boot.
Change-Id: Ie40cc4932ff92d20b021765c3aa356d8902f20e1
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341326
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch adds HSE and PLL as a system clock oscillator for STM32L4.
This allows us to drive the chip at a higher frequency (up to 80 MHz),
which is necessary to big-bang GPIO ports accurately.
BUG=none
BRANCH=tot
TEST=make buildall. Verified console works on STM32L476G-Eval using HSE,
PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly
with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies
using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz.
Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a
Reviewed-on: https://chromium-review.googlesource.com/341275
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since uart_freq_change assumes we drive UARTs at system clock, we need to
set UARTs clock sources accordingly. This will allow us to clock up the
chip without worrying about prescaler values set for HCLK and PCLK or the
on/off status of HSI.
BUG=none
BRANCH=tot
TEST=make buildall. Verified LPUART on stm32l476g-eval.
Change-Id: I02898921e31b68cacbc2235a29c47a212c350afe
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341260
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CR50 does not depend on the rsa implementation
in common This change removes the corresponding
config option.
Also remove a duplicate CONFIG_SHA256 option, and add a
comment regarding CONFIG_SPS_TEST.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=compilation succeeds
Change-Id: Ie01439899042c5fa981f884a01b83eb0b3eb6e32
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340539
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Internal builds may have private*/ subdirectories cloned from
repositories that we're not (yet) allowed to share
publicly (boo). Tell git not to complain about them every time I
run "git status".
BUG=none
BRANCH=none
TEST=manual
mkdir private-foo
touch private-foo/bar.txt
git status
Observe the lack of complaints about private-foo
Change-Id: I5281e3a533f9b1a548ced6f6716a388152c58776
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341032
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a
channel active during low-power idle / deep sleep. Currently it's
supported by npcx and mec1322.
BUG=chrome-os-partner:52783
BRANCH=glados
TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify
KB backlight does not flicker during idle.
Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341002
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
A fairly detailed description of the driver is included in the
comments in the file.
As of this submission the setup is fairly brittle, as clock stretching
is not yet enabled, and there is no guarantee that the slave will
prepare the data for the master in time.
More testing will be required and enhancements will be added in the
future.
BRANCH=None
BUG=chrome-os-partner:40397
TEST=with the rest of the patches applied, an i2c app running on the
desktop allows read and write TPM registers using the
USB-FTDI-I2C cable connected to the B1 board.
Change-Id: I46b13d360ca92271702268f9088193b5ada583be
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340519
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Some debug messages were a bit ambiguous, and some just wrong, this
patch fixes the wrong one and disambiguates the other two.
BRANCH=none
BUG=none
TEST=observed the new generated message.
Change-Id: I2b58ec050816ecdfe4b20dd8410910569767830d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340536
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
GPIO console commands currently only show input voltage level,
and can only set level on predefined outputs.
This change allows GPIOs to be cycled between output, input,
and alternate function, as well as displaying the mode and
asserted level (if any) in gpioget.
This change creates CONFIG_CMD_GPIO_EXTENDED
as the internal gpio interface needs to be changed to support
this, and I can't test the other architectures. It may be
worthwhile to add this for all, or not.
This change is also necessary also for servo micro JTAG and PD
UART support, as several pins are tied together on the flex
and stm32 outputs need to be variously active or in high-z
depending on mode.
BUG=chromium:571477
TEST=gpioget <0|1|IN|A|ALT>; gpioget;
BRANCH=None
Change-Id: Iba32992db6244ee1e654db840d1c9c11dd2a0993
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338885
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The checkpatch complaints about both lines longer than 80 characters
AND character strings split between lines. Damn if you do, damn if you
don't. With this addition split character strings are not a problem
any more.
BRANCH=none
BUG=none
TEST=split character strings are not reported as a violation by the
pre-upload script.
Change-Id: I8b5919f086f8c19fe4e6e3a4b99a816111882f0d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This doesn't appear to be used anymore, and the EC3PO replacement
console doesn't support this yet. This also makes changing the UART
driver API more difficult, so let's remove it.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ia6d9cf4c89e34683f38169dbec612a417c6ba630
Reviewed-on: https://chromium-review.googlesource.com/340842
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The cr50 SPI master can control the external AP and EC SPI ROM. This
change adds support for doing spi_transactions, but does not use the SPI
transactions for anything except console commands. This support will be
used for flashing the AP and EC through CCD. For now AP and EC flash
select must be done manually using the spi_flash_select console command.
Flash select should be disabled after use, because it will prevent the
system from booting.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo,
read, erase, and write commands work properly. Select EC ROM and verify
the same commands.
Change-Id: I16c55015794f8513effe0fa5712488a84bed2627
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339844
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch adds support for console on LPUART (low power UART).
It is wired to the USB type B port on the board, which is also one of the
power sources. So, using LPUART simplifies the set up.
BUG=none
BRANCH=tot
TEST=Verified console works on stm32l476g-eval. make buildall
Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340101
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch adds initial set of files to bring up STM32L476G-Eval board.
BUG=none
BRANCH=tot
TEST=Tested console. make buildall && make tests
Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340100
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
dma_select_channel selects which stream (peripheral) to be used on a
specific channel. Some STM32 chips simply logically OR requests, thus
do not require this selection.
BUG=none
BRANCH=tot
TEST=make buildall && make tests. Verified on stm32l476g-eval.
Change-Id: I7b64b78bdec80658992f58cb4c94ade972a1081c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340107
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This add modifications for EVT, including:
- Use SPI for KX022 motion sensor on the daughterboard
- remove TMP432
- Use PF2 to control the external power of ANX7688
BRANCH=none
BUG=chrome-os-partner:52245
TEST=make BOARD=elm -j
Change-Id: I7d4021746bc8a2be0028076a5c3aeefd8736c1b0
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/337338
Reviewed-by: Rong Chang <rongchang@chromium.org>
CROS_EC_DEV_IOCRDMEM must be used on architecture where legacy IO mapped
registers are accessed inderectly via EMI. The kernel is taking care of
the translation.
TEST=Check on reks that we need to use the IOCTL.
BUG=chrome-os-partner:52550,chromium:602832
BRANCH=none
This reverts commit de45353bbd ("ectool: Remove CROS_EC_DEV_IOCRDMEM").
Change-Id: I8efad56df90c58c25bdc9ccd70a508547e629a77
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340348
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds files to support nucleo-f072rb. This board can be used as
a DUT to test STM32F072.
BUG=none
BRANCH=tot
TEST=Verified EC console works. Flashed the board by 'make flash'. User LED
brinks periodically and when user button is pressed.
make buildall && make tests
Change-Id: I628f229b62c4b06d19d8245121f79a13e17bc2e9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338461
Prime generation uses a sieve to amortize division
with small primes. Otherwise this a standard
Miller-Rabin implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/335222
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
points_mul (variable time) is only necessary for
ECDSA verification, and is not required as part of
the public dcrypto API. Replaced wih (constant time)
point_mul, and add corresponding parameter checks to
the tpm2 interface call _cpri__EccPointMultiply.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I4ec885c147755e8a645c51b9a461b81c3a3b310f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/338851
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Implement _cpri__TestKeyRSA, which computes
the modulus and private exponent given a
pair of primes, or computes the second prime
and private exponent given the modulus and
one prime.
The _cpri__TestKeyRSA call is used to determine
whether the components of an RSA key match each other.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/330466
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
AES CTR will be necessary to implement hybrid encryption
and hence needs to be a part of the dcrypto library.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I5dffe5d3a15748614db36aebdbcd50bde31bfdb2
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/339561
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches
in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when
leaving S0.
BUG=chrome-os-partner:52222,chrome-os-partner:52217
BRANCH=None
TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent
kernel / ectool patches.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812
Reviewed-on: https://chromium-review.googlesource.com/338857
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously the maximum number of deferred routines was specified by the
the default maximum number of deferred routines you had to override
this, and if you wanted fewer, you still payed the price of having the
defer_until array statically allocated to be the maximum size.
This change removes that define and instead creates the RAM state of
the deferred routine (the time to wait until to call the deferred) when
the deferred is declared.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
manually test on discovery-stm32f072
Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc
Reviewed-on: https://chromium-review.googlesource.com/335597
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
It was observed that when connecting to the CR50 console over USB,
there the line feed (LF) characters are not supplemented by carriage
return (CR), which causes weird console output.
Detailed examination has shown that uart_putc() does not do the right
thing itself and also bypasses __tx_char() used by uart_puts(), which
does the right thing.
The simplest solution is to have uart_putc() re-use all the smarts of
uart_puts().
BRANCH=none
BUG=none
TEST=verified that usb console output does not suffer from the "lost
CR" syndrome any more.
Change-Id: I2a1f84b2524c41eb6e84186141b0b9ac55e87ee0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339217
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This signal should be active low, not active high. In addition,
not only can we pull it low but so can other components. If
something else asserts it, we need to react.
This changes the polarity and sets up the interrupt handler. A
future CL will be needed to make the handler do something useful.
BUG=chrome-os-partner:52366
BRANCH=none
TEST=make buildall; test on Cr50
On the test board, short M0 to ground to trigger the interrupt.
Watch the input value with
gpioget
You can drive the output (and trigger the interrupt) with
gpioset SYS_RST_L_OUT 0
gpioset SYS_RST_L_OUT 1
Change-Id: I3556963859601f43f990fc83f26d2cea919383c6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339214
Reviewed-by: Shawn N <shawnn@chromium.org>
