USB ports are disabled after jumping between firmware copies.
We need to record USB port state and restore them after jumping.
BUG=chrome-os-partner:9692
TEST=Manual
Change-Id: Ic5cb83bdd8e49017457f732d317a1b59ced59ead
This adds a missing init hook
BUG=none
TEST=Tested on Snow
Change-Id: I4571d5bddf415b06e27e5e9eaadbb6017bde4bbe
Signed-off-by: David Hendricks <dhendrix@chromium.org>
This helps us keep track of how long vboot is taking on the EC.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9651
TEST=reboot system and look at debug log. time shouldn't start over after it jumps to image A.
Change-Id: Iad86e90d42dabf1c67b2c2be80dda1151cf9a288
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9647
TEST=hack code to put a uart_puts() immediately following uart_init()
It shouldn't crash.
Change-Id: Ia1867a631934dbd457a23183010fdf9f5c284873
It's the standard Chromium OS BSD-style license. I just copied it from
vboot_reference.
BUG=chrome-os-partner:9085
TEST=none
Change-Id: Ib8b77e9544d199fa809caaae0be9c0903c169fd5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
BUG=chrome-os-partner:7459
TEST=manual
In the chroot:
cd src/platform/ec
make BOARD=link
The firmware image (build/link/ec.bin) is signed with dev-keys. Reflash the
EC and try it, and it should verify and reboot into RW A.
Additional tests (setting USE_RO_NORMAL, poking random values into VBLOCK_A
or FW_MAIN_A to force RW B to run, etc.) are left as an exercise for the
reader. I've done them and they work, though.
Change-Id: I29a23ea69aef02a11aebd4af3b043f6864723523
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Open drain cleanup minimizes leakage and signal glitching on shared
reset/signal lines, and is tidier than explicitly switching the
signals between inputs/outputs.
Touchscreen and lightbar are powered by +5VALW so their signals need
to be dropped when +5VALW is off to avoid leakage, and so they see a
clean reset signal when they're powered up.
Moved +5VALW power-on to S5-S3 transition, to minimize power draw in
S5. This also ensures that 5VALW-powered devices get reset when the
device bounces through S5. (No effect on proto1, where 5VALW is not
under EC control.)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9172
TEST=boot and shutdown system; still works.
Change-Id: Ia4bf0703292a189c324ce283d1e79a33776ee40f
Much of the code in gpio-stmxxx.c is duplicated. Also the gpio_get_name()
function is not present in the new file.
Create a common gpio.c file to hold this function, and hopefully other
code in the future.
BUG=none
TEST=build on all platforms, boot on daisy
Change-Id: I4ab33e0e5c52843b770fabc777c917493abccffe
Signed-off-by: Simon Glass <sjg@chromium.org>
These messages are unnecessary and seem to hang the EC for a while.
Punt them for now.
BUG=none
TEST=build and boot on daisy; see that keyboard still works, and messages
do not appear
Change-Id: I62963b62eb3e7cee86162784f364d7b1da37f631
Signed-off-by: Simon Glass <sjg@chromium.org>
Some boards don't like to have every keyboard scan printed, but some
devs find this info comforting. Add a way for boards to select the
require console mask.
BUG=none
TEST=manual:
build and boot on daisy, see that key scan messages are suppressed.
build on all platforms
Change-Id: I8e6e640eaabc0a08e5427cd97f7089dda1238025
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='ch' - prints all the channels now
Change-Id: I38ebc3eed2476c44c26fc00d6ea79800ae427722
Remove the start-up debug message which otherwise ends up being the
first thing displayed on boot, ahead of the banner.
BUG=chrome-os-partner:9424
TEST=very ad-hoc:
1. build and boot on daisy, flash U-Boot with USB using
'cros_bundle_firmware -w usb', inserting daisy
USB cable when it says 'Reseting board via servo...'
2. Press cold reset, then power on, see that it powers on
3. Then hold power-on for 8 seconds and see that it power off
4. XPSHOLD function not tested yet
Change-Id: I4f057ad32c3a857851d02935286683ea87dc7cd1
Signed-off-by: Simon Glass <sjg@chromium.org>
This CL set higher temperature thresholds for CPU temperature to reduce
fan noise. Also set temperature thresholds for case temperature so that
we can adjust fan speed according to them.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8982
TEST=Manual
Change-Id: I16a74e10af4583a59065c09e8d9538232b0fb157
This saves ~70mw of power.
To make this work, I also had to stretch the power button signal to
give the system a chance to come back up when the user taps the power
button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9574
TEST=manual
For each of the following tests, wait ~15 sec after the system is
powered off to give it a chance to drop DPWROK.
1) tap power button -> system turns on
2) hold power button 1 sec -> system turns on
3) open lid -> system turns on
4) silego reset (power+refresh, or power+esc on proto1) -> system stays off
5) silego recovery (power+esc+refresh) -> system turns on
6) hold down power button and type 'reboot' on EC console -> system turns on
7) type 'powerbtn' on EC console -> system turns on
Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
This is cleaner than having x86_power explicitly know about everything
else in the system that cares about power transitions.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=boot and shutdown system; still works. Mouse powered to system is off in S5.
Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
This CL initializes the default transmit mode for I2C to CMDC_NOP.
When we introduced the protocol, we changed the default mode to send
message protocol version. This didn't take into account that U-Boot's
probe command (and probably other userspace commands) do a single-byte
read to probe. So when the probe was asking for a single byte, by
default we were sending multiple bytes for the version message.
This CL also makes the EC reset the mode to noop after each EC-to-AP
transmission. This will help ensure that the EC ends up in a known
state e.g. if the system is reset. That will require the AP to set the
mode before requesting any real data, but that's how we do things now
anyway.
BUG=chrome-os-partner:9556
TEST=Tested on Daisy.
Tested by running "i2c dev 4; i2c probe" at U-Boot prompt, booting
system, and typing on keyboard. Everything seems to work okay.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0849c94588a9a60ade657af8f941f7267553e316
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9563
TEST=manual
Measure +3VALW power before and after change with system in S5. Should drop by ~50mW.
Change-Id: I264694a80b2e558e46708de6ab1bfb146f79eb68
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9554
TEST=manual
1) Boot system. No recovery.
2) Boot system holding down Refresh+Esc. No recovery.
3) Hold down Power+Esc. System reboots and stays shut down.
4) Hold down Power+Esc+Refresh. System reboots into recovery mode.
Change-Id: I53db224b6d2a03406244e79fb64fb67851919857
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9117
TEST=version; board version should be 0 on proto1 and 1 on EVT
Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
Disable USB ports when system is down and set USB ports to standard
downstream mode when system is up or sleeping.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:9249
TEST=Plug in a phone and see it charge when system is on.
Turn off the system and see it stop charging.
Change-Id: I02850dee7051ed6589e0f176a933069203f0efdf
Implements the on-chip flash erasing and writing functions.
The actual writing is done from a routine in internal RAM (using the
special .iram.text section) with interrupt disabled as we cannot read
flash during the writing process.
The write-protect feature is only lightly tested.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=run on Daisy, from the EC console, use flasherase and flashwrite
commands and observe the results using rw command.
Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
This fixes an off-by-one error that was preventing two keys
(left and right arrow) on output 12 from being driven properly,
and causing some other weird ghosting effects.
BUG=chrome-os-partner:9516
TEST=Tested on Daisy
Pressing the right arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 40]
and pressing the left arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 80]
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ib7af21444c2d03a0787fb1a28b520a779013774d
Instead of making the STOP command synchronous, we can just have the
host-side app tell the EC to stop, then poll until it has.
BUG=chrome-os-partner:9349
TEST=manual
"make BOARD=link", then
copy build/link/util/lbplay to the host and run it.
Change-Id: I846924ae7994a498e0089197785cf239898fe2a3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
This is referenced by various files, so should be in the gpio.h header.
BUG=none
TEST=manual:
build and boot on daisy, see that USB download still works
build on all platforms
Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4
Signed-off-by: Simon Glass <sjg@chromium.org>
This just adds a single byte to the end of the RW firmware, so that we can
scan backwards from the end of the reserved block, skipping 0xff until we
find the actual firmware size. We need this so we can resign existing
firmware images without either signing a bunch of padding or forgetting to
sign a trailing 0xff that might be important.
BUG=chrome-os-partner:7459
TEST=none
Change-Id: If5cadb4d58c1bce39f66815c328ffd18cc3d444b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
In case ctl decides to put it on a separate GPIO, he'll use PC7. If
he doesn't, we can reclaim this GPIO.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_SRTCRSTn should be 1.
Change-Id: I4ca4437515d62c36d00fd28093ca41e806ce351a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9447
TEST=update from old EC 517 to this one
Change-Id: I275b5bf6c4ae1ab6e0c0a05cf9260314d644c79b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1.
Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
Mostly stolen from Daisy.
Notable differences:
- No SYSCFGEN required for external interrupts ?
- No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available
--> CODEC_INT and ENTERING_RW signals are missing
BUG=None
TEST=Tested on ADV2/Snow, able to see EC serialconsole
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
0b00 for bits 1:0 (system clock switch) indicates HSI, 0b01
indicates HSE. Also, bit 23 is reserved (maybe it was just
a copying error from earlier).
BUG=None
TEST=Compiled and run on Snow
Change-Id: Ie6891492ae6e7e3bd30e4d7b183b156de1290fe0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
These GPIOs should have been removed in fd5d6c.
BUG=Yes.
TEST=built a new image and booted Daisy-EVT1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idce4384cdbe548c2e4fe2be8b52e4275445c9f1b
This just reserves room. It doesn't actually perform any verification yet.
BUG=chrome-os-partner:7459
TEST=manual
make BOARD=link
dump_fmap build/link/ec.bin
Change-Id: I424db1d601a614be3dfe5abb200e24e8bc62e47e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Add a Jim procedure to program the Link EC image from the default
location as generated by 'emerge-link chromeos-ec'.
BUG=none
TEST=manual
. emerge-link chromeos-ec
. start openocd as described in the Link care and feeding document
. in the port 4444 terminal session type
flash_emerged_link
. observe it succeed
Change-Id: Ibfbc38060d7e82ec8c83a73e2ccadff81d633ae4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Rework to call functions in flash_common.c.
Also fixed a bug in parsing size of parse_offset_size().
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:8448
TEST=on link
(CONSOLE) flashwp set 0x3d000 0x1000
(CONSOLE) flashwp lock
(HOST) flashrom -p internal:bus=lpc --wp-status
WP: write protect is enabled
WP: write protect range: start=0x0003d000, len=0x00001000
Change-Id: I4a53735c851ebf4bb0c01a55a1d301d5b706ee0c
GPIO_KB_PWR_ON and GPIO_PMIC_PWRON are active low, so add _L to each
name to make this clearer.
BUG=chrome-os-partner:9424
TEST=very ad-hoc:
1. build and boot on daisy, flash U-Boot with USB using
'cros_bundle_firmware -w usb', inserting daisy
USB cable when it says 'Reseting board via servo...'
2. Press cold reset, then power on, see that it powers on
3. Then hold power-on for 8 seconds and see that it power off
4. XPSHOLD function not tested yet
Change-Id: Ibdc0064477c36e8658ef5605cdd5811c2283aff9
Signed-off-by: Simon Glass <sjg@chromium.org>
Add this to the GPIO API. It seems that the implementation is copied
in LM4 and STM32 so I have reluctantly done the same with this new
function.
BUG=chrome-os-partner:9424
TEST=build and boot on Daisy
Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd
Signed-off-by: Simon Glass <sjg@chromium.org>
