USB ports are disabled after jumping between firmware copies.
We need to record USB port state and restore them after jumping.
BUG=chrome-os-partner:9692
TEST=Manual
Change-Id: Ic5cb83bdd8e49017457f732d317a1b59ced59ead
This helps us keep track of how long vboot is taking on the EC.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9651
TEST=reboot system and look at debug log. time shouldn't start over after it jumps to image A.
Change-Id: Iad86e90d42dabf1c67b2c2be80dda1151cf9a288
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9647
TEST=hack code to put a uart_puts() immediately following uart_init()
It shouldn't crash.
Change-Id: Ia1867a631934dbd457a23183010fdf9f5c284873
BUG=chrome-os-partner:7459
TEST=manual
In the chroot:
cd src/platform/ec
make BOARD=link
The firmware image (build/link/ec.bin) is signed with dev-keys. Reflash the
EC and try it, and it should verify and reboot into RW A.
Additional tests (setting USE_RO_NORMAL, poking random values into VBLOCK_A
or FW_MAIN_A to force RW B to run, etc.) are left as an exercise for the
reader. I've done them and they work, though.
Change-Id: I29a23ea69aef02a11aebd4af3b043f6864723523
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Open drain cleanup minimizes leakage and signal glitching on shared
reset/signal lines, and is tidier than explicitly switching the
signals between inputs/outputs.
Touchscreen and lightbar are powered by +5VALW so their signals need
to be dropped when +5VALW is off to avoid leakage, and so they see a
clean reset signal when they're powered up.
Moved +5VALW power-on to S5-S3 transition, to minimize power draw in
S5. This also ensures that 5VALW-powered devices get reset when the
device bounces through S5. (No effect on proto1, where 5VALW is not
under EC control.)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9172
TEST=boot and shutdown system; still works.
Change-Id: Ia4bf0703292a189c324ce283d1e79a33776ee40f
Some boards don't like to have every keyboard scan printed, but some
devs find this info comforting. Add a way for boards to select the
require console mask.
BUG=none
TEST=manual:
build and boot on daisy, see that key scan messages are suppressed.
build on all platforms
Change-Id: I8e6e640eaabc0a08e5427cd97f7089dda1238025
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='ch' - prints all the channels now
Change-Id: I38ebc3eed2476c44c26fc00d6ea79800ae427722
This CL set higher temperature thresholds for CPU temperature to reduce
fan noise. Also set temperature thresholds for case temperature so that
we can adjust fan speed according to them.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8982
TEST=Manual
Change-Id: I16a74e10af4583a59065c09e8d9538232b0fb157
This saves ~70mw of power.
To make this work, I also had to stretch the power button signal to
give the system a chance to come back up when the user taps the power
button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9574
TEST=manual
For each of the following tests, wait ~15 sec after the system is
powered off to give it a chance to drop DPWROK.
1) tap power button -> system turns on
2) hold power button 1 sec -> system turns on
3) open lid -> system turns on
4) silego reset (power+refresh, or power+esc on proto1) -> system stays off
5) silego recovery (power+esc+refresh) -> system turns on
6) hold down power button and type 'reboot' on EC console -> system turns on
7) type 'powerbtn' on EC console -> system turns on
Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
This is cleaner than having x86_power explicitly know about everything
else in the system that cares about power transitions.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=boot and shutdown system; still works. Mouse powered to system is off in S5.
Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9563
TEST=manual
Measure +3VALW power before and after change with system in S5. Should drop by ~50mW.
Change-Id: I264694a80b2e558e46708de6ab1bfb146f79eb68
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9117
TEST=version; board version should be 0 on proto1 and 1 on EVT
Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
Disable USB ports when system is down and set USB ports to standard
downstream mode when system is up or sleeping.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:9249
TEST=Plug in a phone and see it charge when system is on.
Turn off the system and see it stop charging.
Change-Id: I02850dee7051ed6589e0f176a933069203f0efdf
Implements the on-chip flash erasing and writing functions.
The actual writing is done from a routine in internal RAM (using the
special .iram.text section) with interrupt disabled as we cannot read
flash during the writing process.
The write-protect feature is only lightly tested.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=run on Daisy, from the EC console, use flasherase and flashwrite
commands and observe the results using rw command.
Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
Instead of making the STOP command synchronous, we can just have the
host-side app tell the EC to stop, then poll until it has.
BUG=chrome-os-partner:9349
TEST=manual
"make BOARD=link", then
copy build/link/util/lbplay to the host and run it.
Change-Id: I846924ae7994a498e0089197785cf239898fe2a3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
This is referenced by various files, so should be in the gpio.h header.
BUG=none
TEST=manual:
build and boot on daisy, see that USB download still works
build on all platforms
Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4
Signed-off-by: Simon Glass <sjg@chromium.org>
This just adds a single byte to the end of the RW firmware, so that we can
scan backwards from the end of the reserved block, skipping 0xff until we
find the actual firmware size. We need this so we can resign existing
firmware images without either signing a bunch of padding or forgetting to
sign a trailing 0xff that might be important.
BUG=chrome-os-partner:7459
TEST=none
Change-Id: If5cadb4d58c1bce39f66815c328ffd18cc3d444b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9447
TEST=update from old EC 517 to this one
Change-Id: I275b5bf6c4ae1ab6e0c0a05cf9260314d644c79b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1.
Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
Mostly stolen from Daisy.
Notable differences:
- No SYSCFGEN required for external interrupts ?
- No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available
--> CODEC_INT and ENTERING_RW signals are missing
BUG=None
TEST=Tested on ADV2/Snow, able to see EC serialconsole
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
This just reserves room. It doesn't actually perform any verification yet.
BUG=chrome-os-partner:7459
TEST=manual
make BOARD=link
dump_fmap build/link/ec.bin
Change-Id: I424db1d601a614be3dfe5abb200e24e8bc62e47e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Rework to call functions in flash_common.c.
Also fixed a bug in parsing size of parse_offset_size().
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:8448
TEST=on link
(CONSOLE) flashwp set 0x3d000 0x1000
(CONSOLE) flashwp lock
(HOST) flashrom -p internal:bus=lpc --wp-status
WP: write protect is enabled
WP: write protect range: start=0x0003d000, len=0x00001000
Change-Id: I4a53735c851ebf4bb0c01a55a1d301d5b706ee0c
GPIO_KB_PWR_ON and GPIO_PMIC_PWRON are active low, so add _L to each
name to make this clearer.
BUG=chrome-os-partner:9424
TEST=very ad-hoc:
1. build and boot on daisy, flash U-Boot with USB using
'cros_bundle_firmware -w usb', inserting daisy
USB cable when it says 'Reseting board via servo...'
2. Press cold reset, then power on, see that it powers on
3. Then hold power-on for 8 seconds and see that it power off
4. XPSHOLD function not tested yet
Change-Id: Ibdc0064477c36e8658ef5605cdd5811c2283aff9
Signed-off-by: Simon Glass <sjg@chromium.org>
The position of jump_tags was shifted every time a new field was added
to struct jump_data. This broke the sysjump hook badly.
To make this more scalable, add a header_size field in struct jump_data.
Then the new code can always prepend (or reduce if jump_data becomes smaller)
some spaces between jump_data and jump_tags.
BUG=chrome-os-partner:9447
TEST=EC upgrade from EC 517 (2231) to this version, and keyboard keeps working.
Note that EC 526 (2235) to this version is not working because we have no way
to identify that header version change.
Change-Id: If1b506c6f7d22e5affaaf8ada15990f60d2f957a
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8982
TEST=manual
run console command 'charger'
charger option will be displayed in bin and hex output
Change-Id: I461bce347f13eeb4f2c8595b83a7ba4c7d40ea58
We need to assert PROCHOT signal at/before 68 degree-C. Let's assert it
when CPU is at 68 degree-C. Also, we lower fan speed control threshold
to max fan speed at 65 degree-C.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8982
TEST=none
Change-Id: Iec0d05308b1310f89bc0a2edb1ad632c8ca96c87
We no longer support ADV EVT0 board and Discovery reference design.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=link
Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
this fixes the build breakage on stm32-based platforms.
In the linker script, remove the ASSERT since this macro is not designed
to work in that context and this size condition is already verified by
the linker by setting the "length" of the "FLASH" memory region.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=daisy
boot on Link and Daisy
Change-Id: I08964749d44f47caa0a359bc93c303a9611e5d73
This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and
RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff.
Still, you should be able to do things like this:
flashrom -p internal:bus=lpc -r ec.bin
flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat
BUG=chrome-os-partner:8198
TEST=manual
Build the image, look for the FMAP in it.
cd src/platform/ec
make BOARD=link
dump_fmap ./build/link/ec.bin
Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
When the host reboots the EC it should be able to request the EC to
force recovery mode after reset. This is achieved by extending the
REBOOT EC command with a bitmask byte, with bit 0 dedicated to
recovery request.
So, when BIOS on the way up determines that recovery is requested, but
the EC is not running from the RO space, the BIOS would reset the EC
forcing it to run from RO and to request recovery mode through the LPC
bitmask. Then BIOS will restart itself ensuring that the system comes
up in consistent state.
Some refactoring was also done to make the code a bit more compact.
BUG=chrome-os-partner:9040
TEST=manual
. tested along with coreboot changes (test described in the coerboot CL).
Change-Id: I29801b6aec80da0901ba0e8db8e92e615cc778bd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Note: This will not work on older (0.94 boards).
- Use power button (KB_PWR_ON) to drive power sequencing events and
disable EC_PWRON. This is because EC_PWRON and KB_PWR_ON shared an
external interrupt line. Daisy v2.x will fix this so that both can
be enabled. Note: KB_PWR_ON is active low, wihle EC_PWRON is active
high.
- Relay power button state to PMIC. Also, since we are driving
PMIC_PWRON instead of PMIC_ACOK now, so updated the naming.
- Add a keyboard power button debounce period to avoid accidentally powering
the system back on after keyboard power-off.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=tested on daisy (frh@ verified behavior using a scope)
Change-Id: I5338eebe42c9b43a07af371a450db23276b2a574
The EVT boards will have an enable signal for the +5V always-on rail
connected to GPIO PK4.
Just turn it on at startup to ensure that EVT boards will run out of the
box with the current EC firmware.
(PK4 is a test point on proto-1 board, this should be harmless).
We can later implement fancier power saving scheme by enabling it only
when we enter S3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9284
TEST=boot Linux kernel on Link proto-1 and Link-1 proto-1 reworked with
+5V Always-on enable on PK4.
Change-Id: I26527480c7cd364f3fabcaabaadd079a332f9c1c
Adjust fan step thresholds:
T=55C Fan=20%/2200RPM
T=65C Fan=40%/4400RPM
T=75C Fan=60%/6600RPM
T=85C Fan=80%/8800RPM
T=95C Fan=100%/11000RPM
Also set minimum fan speed to 0 rpm.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8466
TEST=Manual test
Change-Id: I609853f2eceb9a6a43fbeb500084e82b1461f092
When PWM module detects fan stall, issue SMI warning and print warning
message to console.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:7497
TEST=Disconnect fan and power up. See warning message.
Change-Id: I4d96595f7f3cdfab5df333afc35206304bacab9d
BUG=chrome-os-partner:7839
TEST=manual
Try "lightbar help" on the EC console and "ectool lightbar help" on the
host. You should see the same commands and behavior.
Change-Id: I6e879e8bb892ef5ada7ef85a97fdf243149f4cb6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
fix small modularity issues to ensure we are able to compile all boards
in "tests" configuration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8546
TEST=make BOARD=link tests && make BOARD=bds tests
make BOARD=daisy tests && make BOARD=adv tests && make BOARD=discovery tests
Change-Id: I9eed0195af6bfd3b47ef74e3cb27966c4365c345
