Undo some of CL:1072637 so that battery_is_present() and
battery_hw_present() move back to baseboard.
battery_fuel_gauge.c now only includes code which is
directly involved with the fuel gauge.
BUG=b:109894491,b:80299100
BRANCH=none
TEST=make -j buildall
Change-Id: I8fc5be3856564601019d94514dcfc8ffb3071c2e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1097954
Commit-Ready: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
LPC and eSPI logical device configuration is mostly common.
Create common subroutines for LD configuration. Fix bugs
in LPC LD configuration for ACPI, EMI, Port80. Add work-
around for APL LRESET# changing when LPC clock is not
running.
BRANCH=none
BUG=None
TEST=Build all boards using chip mchp. Test LPC and eSPI
communication with host chipset via EC/Host UART logs.
CQ-DEPEND=CL:1053576,CL:1053827,CL:1053880,CL:1053949
Change-Id: Ie40245c20627178a0e518eafc028d194c1f176a6
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053884
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no need to add hardcoded .test suffix when determining the
base RMA key file name.
BRANCH=none
BUG=none
TEST=succeeded signing both prod and pre-pvt images.
Change-Id: I59a5eb4ff8c093110c4d29969974148c99bd62a0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1099731
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The blob includes 65 bytes of the public key and one byte of the key
ID, 66 bytes total.
BRANCH=cr50, cr50-mp
BUG=b:73296606, b:73647182
TEST=none
Change-Id: I0adf844a487776b0a93eae404f7bc74566d003fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1099730
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When a battery isn't plugged in, the current implementation of the
baseboard_tcpc_init() funciton waits a full second for the battery to be
connected. This one second is unnecessary when the battery isn't plugged
in, and results in the power button state machine going into idle before
the system can boot.
BRANCH=none
BUG=b:109944712
TEST=booted yorp without battery plugged in, also verified it still
boots with a good battery plugged in
Change-Id: I31df13207c13a523c1112be9c82c63767c1cd299
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1097234
Commit-Ready: Diana Z <dzigterman@google.com>
Tested-by: Diana Z <dzigterman@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When USB is suspended and disable remote wakeup (SUS0), we can stop
touchpad scanning to save some power.
This CL also stops sending empty touchpad HID events when there is no
finger events nor button events.
BRANCH=whiskers
BUG=b:70482333
TEST=`st_tp_stop_scan` is called on USB suspend
Signed-off-by: Wei-Han Chen <stimim@chromium.org>
Change-Id: Iebf29d7371383b7493baa1059cfa8d56bbc2589c
Reviewed-on: https://chromium-review.googlesource.com/1095119
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Chip level I2C transfer called from common was huge and
consumed 96 bytes of stack. Refactor into subfunctions
for master transmit and receive. Update I2C configuration
to program proper register values for bus clock and other
registers. Port switching modified to only switch ports
if necessary. Make port switch more robust by resetting
I2C controller clearing hardware state machines. Read
raw SCL and SDA signals using GPIO API instead of I2C
bit-bang register. I2C bit-bang only useful if I2C is
idle.
BRANCH=None
BUG=None
TEST=Configure board for port switching and I2C stress
tests.
CQ-DEPEND=CL:1053576
Change-Id: I647ecec8746dc9741c59879db15d7ad4e20e0469
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053880
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Hibernation timer was not programmed to correct value for
some cases and code was duplicated. Not all interrupt sources
were properly configured in system hibernate. Remove debug
only system pre-init board level call.
BRANCH=none
BUG=none
TEST=Build all boards using chip mchp. Test with EC UART
hibernate command.
CQ-DEPEND=CL:1053576
Change-Id: I932443fa7a4e284168babdbb7f64033a55427fb2
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053956
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Prevent WDT from firing while JTAG is attached without
having to completely remove watchdog feature. When new
chip debug feature is enabled attached a JTAG cable pulling
JTAG TRST# pin high will prevent watchdog timer from counting
down. Replacing the JTAG cable with a weak pull down will
allow WDT to operate normally.
BRANCH=None
BUG=None
TEST=Build all boards using chip mchp.
Change-Id: I54c52bd1ba2115491e63882c91a6ab4827918784
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053950
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For npcx ec, board driver needs to add GPIO_SEL_1P8V flag for SDA/SCL
pins in gpio.inc when i2c port is configured to support low-voltage
mode (1.8V). Npcx gpio driver will set the corresponding bits in
LV_GPIO_CTL register later. But if there is an i2c unwedging mechanism
occurred on those 1.8V i2c port, the bits of LV_GPIO_CTL will be cleared
unexpectedly after unweding is completed. And it also will make ec
consumes more 0.5mA current on each pin since IO is selected to 3.3V.
The root cause is the GPIO flags of SCL/SDA have been changed to
zero only after i2c unweding is done. This CL which solved this issue
includes:
1. Add GPIO_INPUT and GPIO_SEL_1P8V flag in ALTERNATE macro array which
pins belong to 1.8V i2c port.
2. Change type of flags in structure gpio_alt_func from uint16_t to
uint32_t since bit overflow.
BRANCH=none
BUG=b:109884927
TEST=No build errors for npcx7 series. Saving 3.3mW power consumption on
yorp if this patch is applied.
Change-Id: I06eadd5df36c7f69e6741f1dee13c801bac18360
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1089604
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The SPDX_LICENSE_TAG doesn't apply to the ec codebase since it would
want us to add the SPDX-License-Identifier to every file.
BRANCH=none
BUG=none
TEST=verified a new file does not need SPDX-License-Identifier tag
Change-Id: Ie7670f52ecd7a5dd825a56a0e8dc839e66ddd6f1
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1098026
Reviewed-by: Mike Frysinger <vapier@chromium.org>
With the Cortex-M7 core on STM32H7, the imprecise bus abort triggered by
the flash permission check might be propagated rather than ignored as we
might have gone through the ignore_bus_fault(0) before the exception
actually happens.
We need barriers to avoid this case, add one in flash_physical_protect_now
where I missed it in my previous patch.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75068419
TEST=On ZerbleBarn with MPU on and caches enabled, verify that
flash_physical_protect_now() no longer triggers an imprecise abort in
some builds.
Change-Id: I1b5159e6606336a196b93cb1210cc28acd47c5a4
Reviewed-on: https://chromium-review.googlesource.com/1096765
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
on the npcx7, GPIOC2 is a bit special because it has 2 alternate
modes. we want the PWM1 mode instead of I2C6, and that's selected
using a special #define.
BUG=b:94613023,b:78309559
BRANCH=none
TEST=apshutdown still works
Change-Id: Ibd8baa15640344ce6c48b2c849e0d9fe6ce4239f
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1090320
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
set the input level for the PROCHOT# signal to 1.8v. the signal is
actually pulled up to 1.0v on the board so it has always read as
0 with the default 3.3v GPIO setting
now, with the 1.8v pin configuration, it actually reads as a 1:
> gpioget ec_prochot_odl
1 EC_PROCHOT_ODL
>
BUG=b:109846359
BRANCH=none
TEST=read back gpio pin state from EC console
Change-Id: Ibd25fdb10b15e42a03e460a43c118d1bc8971281
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1090319
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The FACTORY_DISABLE vendor command could return VENDOR_RC_INTERNAL_ERROR
in which case the EC error code is included in the response payload.
Print both errors if rv is nonzero and the response size is 1.
BUG=none
BRANCH=none
TEST=run 'gsctool -a -F disable' and make sure the vc and ec errors are
printed correctly.
Change-Id: Idc75d6d809865f1f3b685ca775ffbef9f6a1d860
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1096103
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
P256 key provisioning is complete, let's move RMA unlock to p256, this
frees up 5328 bytes in the flash.
BRANCH=cr50, cr50-mp
BUG=b:73296606
TEST=verified that dev key is properly accepted by the server, prod
key will be tested when prod image is signed.
Change-Id: I7d86bb2b793c32181f47f5354ad9db603aa49881
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1095535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The alternate mode for i2c still needs to set the 1.8V flag since it is
called when configuring the port initially and when it finishes
manually unwedging the port.
BRANCH=none
BUG=b:109884927
TEST=builds
Change-Id: Iafa87d3420a3605c0ad87bf8e1f5d69c3edb167a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096020
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The alternate mode for i2c still needs to set the 1.8V flag since it is
called when configuring the port initially and when it finishes
manually unwedging the port.
BRANCH=none
BUG=b:109884927
TEST=builds
Change-Id: Iac34c413499dfa803b45ec575f0a134774951b6c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096019
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Widen the flags field from 16-bit to 32-bit to fit all of the
current GPIO_flags. Also reorder fields within struct to allow arm
compiler to use 16-bit instructions instead of 32-bit instructions when
accessing fields (which is important for kevin board, otherwise
it runs out of space)
Lastly, re-tool macros to all reordering of gpio_alt_func struct fields.
BRANCH=none
BUG=b:109884927
TEST=builds on all boards
Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096018
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Because switching a task context might change these conditions and
resulting in EC entered deep sleep mode where it shouldn't.
So we disable interrupts to avoid task scheduling during checking these
conditions.
BUG=b:80131632
BRANCH=none
TEST=Ensure EC is entering deep doze mode, and check if watchdog warning
fired after 48 hours.
Change-Id: Ie12239ecd71a3894b379c19e985d23231018ea7c
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1080567
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The point of rma_reset is to test cr50 authcode stuff. We want to make
sure that cr50 doesn't accept test key authcodes when it is using prod
keys. To test this we need to know the authcode that would be generated
with test keys. When there is a unsupported keyid print the authcode so
we can use that authcode to verify prod key cr50 wont accept test key
authcodes.
BUG=none
BRANCH=none
TEST=run rma_reset with a prod key challenge and make sure rma_reset
still prints the authcode.
Change-Id: Id1b0025ff7ab165d26be2b4e1503df7dee1d5ec7
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1091972
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Nocturne's CPU_PROCHOT is active low. Additionally, it's a 1V signal,
so enable 1.8V GPIO logic to give it a chance of reporting the right
thing.
BUG=b:109882953
BRANCH=poppy
TEST=Flash nocturne; verify that PROCHOT isn't asserted by default.
Change-Id: I90126b3e495fa6e83b03c893cc3090cad90e1d5a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1092151
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
The common x86 chipset code assumed that CPU_PROCHOT was active high,
however on some boards it's actually active low. This commit simply
adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts
the places where the signal is used.
BUG=b:109882953
BRANCH=poppy
TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted
by default.
Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1092150
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
When we try to unwedge an i2c port, we change the pin type into a
manually GPIO ODR. When we do that we should also carry over the 1.8V
flag if it exists on the original GPIO definition.
BRANCH=none
BUG=b:109884927
TEST=verified with manually-created EC console command that low voltage
register is not set when going into raw mode before this change and
correctly sets the low voltage register after this change (when going into
raw mode).
Change-Id: I87515d53cc68ace3f69ea1058b83a378ef9a281c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1093011
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Currently, the BIOS carries the table which maps (OEM,SKU) to barrel
jack adapter spec. This patch moves this table to the EC. Then, the
EC will independently manage the max voltage and current for BJ.
This would remove the dependency on AP-EC communication, thus improves
the stability
This patch also corrects the mapping between SKUs and BJ wattages.
SKU BJ(W)
* KBL-R i7 8550U 4 90
* KBL-R i5 8250U 5 90
* KBL-R i3 8130U 6 90
* KBL-U i7 7600 3 65
* KBL-U i5 7500 2 65
* KBL-U i3 7100 1 65
* KBL-U Celeron 3965 7 65
* KBL-U Celeron 3865 0 65
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:109762580
CQ-DEPEND=CL:1089370
BRANCH=none
TEST=Verify BJ adapter is set expectedly on Teemo.
Change-Id: I70c8987670e7495a32fdcbc572779fdc9362e22f
Reviewed-on: https://chromium-review.googlesource.com/1089328
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 270e3240fab531d15cddc7c50202e5820e90bb53)
Reviewed-on: https://chromium-review.googlesource.com/1091975
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
For early bringup, or failure analysis, it is sometimes useful to
be able to force enable the keyboard matrix scanning, even though
other signals (lid close, usb off) would normally disable it.
The only way to disable the scanning again is to wait for an
lid/USB event, or reboot the board, which is ok as this is
for debugging purpose only.
BRANCH=none
BUG=b:109743721
TEST=Provide power to whiskers via servo only.
ksstate force => key presses are shown
Change-Id: I3eaa9552ea52f7e3df45fdb6c8d0aa88c7b164b3
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1090350
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The signer script is checking the elf files for presence of test RMA
keys, currently hardcoded to be x25519 keys.
The algorithm (x25519 vs p256) is going to become a compile time
option, the script should be prepared to determine the type of the key
at run time, because the script could be used for signing images from
different branches, compiled with different config options.
The prod p256 key does not yet exist.
BRANCH=none
BUG=b:73296606
TEST=verified that prod signing images including x25519 keys is still
working as expected.
Change-Id: Icf48845279912ecc9ccdecec1764fcb5f85d22bd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1079698
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
- Change GPIO signals at runtime based on board version
- SYS_RESTET_L, ENTERING_RW, USB2_OTG_ID
- Add 2nd signal for 2nd USB-A port BC1.2 outbound charging
- (GPIO96) USB_A1_CHARGE_EN_L (V1) maps to EN_BRD_ID (V0) so we
can just enable the USBA port 1 signal on V0 with only a small
power drain. It is not worth the EC codebase churn to add support
for changing the number of USB-A ports at runtime (since it is a compile
time constant now)
- Yorp V0 is the only board that set USB_PORT_COUNT to 1 so we can make
common octopus code only have the 2 port case.
- Add placeholders for LED_3_L, WFCAM_VSYNC
- Updated signal name comments to match schematics
- Formatting cleanup for consistency
BRANCH=none
BUG=b:109747036,b:74388692
TEST=verified `sysjump rw` does not brown out board when only powering
with USB C1 without battery. Since GPIO_C1_EN_SNK_V0 moved, the board would
lock power out if GPIOs state was not maintained properly through
sysjump transition.
Change-Id: Ie4c72699ab23ee6f7d2fa77a78709e5b4343e46f
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1087815
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
