Instead of enabling the SOF calibration at usb_init(), enable it
only when the first SOF packet is seen following the usb_init(),
as suggested in the recommendations document linked from the bug
report.
Also fix the code to do the right thing. The original reference
code had errors.
BUG=chrome-os-partner:50800
BRANCH=none
TEST=make buildall; test on Cr50
After adding some instrumentation code, I see the SOF being
detected and the calibration started. It only happens once after
each usb_init() and only when the USB traffic begins.
Change-Id: Id2b9a41d90ce9cc9e467fb759463d69a57bb5540
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350371
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This commands makes it possible to control the PD chip (or
the interaction between EC and PD), from the AP.
- PD_SUSPEND: Suspends the PD chip: EC needs to stop talking
to PD chip. Useful at beginning of PD FW update.
- PD_RESUME: Resumes the PD chip: EC can start talking to PD
chip again. Useful at end of PD FW update.
- PD_RESET: Resets the PD chip (called at the end of the update).
- PD_CONTROL_DISABLE: Prevents further calls to this command
(for security reason, we do not want the AP to be able to
call the other subcommands after the update has been performed).
BRANCH=none
BUG=chrome-os-partner:52433
TEST=ectool pdcontrol {suspend,resume,reset,disable}
Change-Id: I7a955dd27b65086c21d195a6504aa7392eb0406d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342584
Reviewed-by: Randall Spangler <rspangler@google.com>
Also, make sure that pd_set_suspend can work asynchronously,
but looping until the status is read back as SUSPENDED.
BRANCH=none
BUG=chrome-os-partner:52433
TEST=On elm:
ectool pdcontrol reset
sleep 0.1
ectool pdcontrol suspend
i2cset -f -y 2 0x28 0x05 0x10
=> No I2C communication with ANX7688
Change-Id: Iad7b500f1af554e2bc4f64f90ee0a492f903749a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347730
This updates SMI/SCI-related config options on Reef so that
SMIs and SCIs are generated correctly.
BUG=chrome-os-partner:53726
BRANCH=none
TEST=built and booted on Reef EC, firmware seemed more stable
(stayed up longer), but still see watchdog timesouts in task 13.
Change-Id: I6717f48a7655e49207fe34e6a166957eb34a05fd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349711
Reviewed-by: Shawn N <shawnn@chromium.org>
The default mode for the LPC pins is actually LPC. Setting the
altnerate function mode makes them GPIOs.
BUG=none
BRANCH=none
TEST=build and booted on Reef EC. Didn't seem to make much of a
difference on its own but with the follow-up things seemed more
stable.
Change-Id: Ibbc62d23d8d909be48a9bec90da8acebb9905b50
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347443
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.
When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.
The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.
The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.
When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.
BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
TEST SERVO
power cycle the DUT
connect servo and check that the AP and EC consoles still work
check that both the AP and EC can be flashed using servo.
TEST SUZY Q
Attach Suzy Q
Connect to the all three consoles. Check that the cr50 console
is in read-write mode and the EC and AP consoles are read only.
Attach Servo.
Verify all of the servo functionality described above still
works with suzy q attached and ccd enabled.
Disconnect Servo.
run 'ccd uart enable' on the cr50 console and check both the AP
and EC consoles can be written to.
Check that the AP and EC can be programmed using the
raiden_debug_spi programmer.
Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
While in CCD, cr50 can be used to flash the AP and EC through USB. This
change adds an endpoint that can be used to read, erase, and write to
the AP and EC spi rom.
Currently CCD is not enabled on cr50, so usb_spi access has to be
enabled manually through the cr50 console.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=manual
On EC console run 'flash_tristate true'
On cr50 console run 'usb_spi enable'
Use 'flashrom -p raiden_debug_spi:target=EC' and
'flashrom -p raiden_debug_spi:target=AP' to interact with
the AP and EC flash
CQ-DEPEND=CL:342144
Change-Id: I9c31dab252a8bfbc498eaf64ac5c2f53ec9dde30
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342511
Update power sequencing as per Rachel's recommendation. We currently
wait for PP5000_PG and PP3300_PG before enabling the PMIC. This changes
the order so that we don't wait for PP3300_PG before setting the PMIC
enable.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=see scope shots mentioned in the BUG
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I022a9ab21c1bcb70dc72f358dbf89acb656851b8
Reviewed-on: https://chromium-review.googlesource.com/349291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Kevin uses inverted polarity (low = enable 5V output), so add a new CONFIG
to support this.
BUG=chrome-os-partner:53777
BRANCH=None
TEST=Manual on Kevin. Enable USB charger tasks, verify that VBUS is
properly detected on no-battery case.
Change-Id: Ifb3e5fa9db1973d9826435712711f0cb0fd1d3a5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349260
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds a fallback directory in case SYSTEM_LOCKFILE_DIR is
unavailable. Since this is a band-aid meant to help older systems
auto-update, the fallback path is hardcoded to "/tmp" as to avoid
polluting the overall lockfile API.
BUG=chromium:616620
BRANCH=none
TEST=Tested on veyron_jaq by removing /run/lock and seeing
mosys, flashrom, and ectool run successfully with
firmware_utility_lock in /tmp.
Change-Id: Idbe63a574474ec35a5c3b6fe2b0fb3b672941492
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348850
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
I2C is not necessarily _that_ slow, especially when using 1Mhz clock
speed, and, looking at traces from userspace, there are large gaps
(150us) between bytes (while the bytes themselves only take ~10us).
At 400kHz and higher bus speed, busy-loop for the duration of 2 bytes,
before sleeping (and yielding to other tasks) for 100us between each
attempt.
BRANCH=None
BUG=chrome-os-partner:50381
TEST=i2cget, look at Logic 16 traces: no gaps between address and bytes
Change-Id: If47f0f8e55be37002361800d35f71c945863d42d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346670
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
move PRECHARGE_TIMEOUT to config.h so that we can customize precharge time to
meet client's spec.
BUG=none
BRANCH=master
TEST=`make -j buildall`, precharge time is set to 300s in elm.
Change-Id: I5c3bf0d5c5240b9c087e6cdb7c6e97301efa9f84
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/348151
Reviewed-by: Shawn N <shawnn@chromium.org>
After the EC is powered, we are no longer concerned with the
IADP-selected current limit, so disable IADP measurement. On some
platforms, this prevents IADP from interfering with register-selected
current limits.
BUG=chrome-os-partner:53693
BRANCH=None
TEST=Verify reef selects a new input current limit when external charger
is plugged.
Change-Id: I1acadc03e3c978368dc96fd478970960106c18fb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Rachel Nancollas <rachelsn@google.com>
Add tests for RSA-1024, and created partner CRBUG/53893
to track issue discovered with 1024-bit modinv.
1024-bit RSA support being added in preparation
for a forthcoming hardware based implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53893
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I6b5aaeffc9df1cbbe403535fd21cdd377b42c38e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/348490
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Port SHA and P256 code to depend on third_party/cryptoc.
Remove config options CONFIG_SHA1, and CONFIG_SHA256 as
these are provided by third_party/cryptoc.
Also remove unused config options CONFIG_SHA384, CONFIG_SHA512.
Crypto functions prefixed by dcrypto_ (declared in internal.h ),
DCRYPTO_ (declared in dcrypto.h) are implemented under
chip/g/dcrypto, and otherwise are implemented under third_party/cryptoc.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53782
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: If7da02849aba9703573559370af5fae721d594fc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340853
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
GPIO_USB_C0_VBUS_WAKE_L is used to show VBUS status on elm.
If VBUS is present, pd sends soft reset on boot.
So it can boot without battery.
BUG=chrome-os-partner:53496
BRANCH=none
TEST=test on elm.
Remove battery and boot up successfully only with AC.
Use "sysjump rw" command and ec won't reboot by pd hard reset.
Change-Id: I1cdb12894c7b6bc41d7a16802b8c0ef14e2aa426
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/346261
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This could be a pain, but we do no want to keep any state when cr50
firmware is upgraded.
BRANCH=none
BUG=chrome-os-partner:44745, chrome-os-partner:51977
TEST=not much yet, will be tested when debugging cr50 functionality
Change-Id: Ic26d3f9f20c6edb77c76c941d04c31948f02be20
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348292
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
It is important to be able to wipe out the non-volatile memory for
various reasons. This patch adds this ability for both when NV memory
is kept in SRAM and in flash.
Also a minor clean up to eliminate some code duplication and to have
normal flow messages printed out with time stamps.
BRANCH=none
BUG=chrome-os-partner:44745
TEST=just makeall at this time.
Change-Id: I59c1909669aeaa9e8ffb3d8ef81b02fa0facb6ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348291
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change enables configs for:
CONFIG_USB_SERIALNO: a programmable serial number for servo_v4
CONFIG_CMD_GPIO_EXTENDED: ability to change GPIO functions on the command line.
BUG=chromium:571476
BRANCH=None
TEST=serialno set abcdef; serialno load; reboot; gpioget/gpioset
Change-Id: I0e871d256e41022d3bb9985e590864a6c4cdf6a4
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This change is motivated by an internal use case.
BRANCH=none
BUG=none
TEST=make buildall -j
Successfully used the exported functions on Cr50.
Change-Id: I5a54b4ea407866c7d7a4bd075d7773ac81e00930
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This moves PP5000 and PP3300 enable early into board_init() and
increases priority of board_init() so that it runs before any TCPC
or PD init hooks which communicate with the TCPCs via I2C.
This hack also makes it so we don't shut off PP3300 for the time
being, at least until we get the proper sequence down and can avoid
I2C errors.
This probably is not the permanent solution, but for now it prevents
a lot of I2C errors from occurring.
BUG=chrome-os-partner:53549
BRANCH=none
TEST=booted on reef, no longer see I2C wedge error messages
Change-Id: I87e2e99aa3e1152cd10a2bfdd749d6e0dbd981a8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Move power rail and pmic enable control to be handled at
board level due to specific board design.
Modify rsmrst where assertion is pass-through at all time
and de-assertion is only pass-through at power up.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=amenia is able to handle apreset warm/cold, pmic shutdown,
soc reset/shutdown.
Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347370
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
This fixes two race conditions that lead to a watchdog timeout:
1) ticks_to_usecs()
common/timer.c:process_timers() wraps its body in a
"while (next.val <= get_time().val)" loop meant to ensure that
it never returns after having scheduled an expired timer
(to address potential __hw_clock_event_set() overflows/underflows).
However get_time() through __hw_clock_source_read() calls ticks_to_usecs()
which "expands" the hw_rollover_count by a truncated clock_div_factor which
causes that loop condition to observe a "current time" that is up to ~15us
in the past (assuming a 24MHz clock). This race arises frequently with
workloads that repeatedly sleep for a short duration.
2) __hw_clock_event_irq()
The HW timer rollover interrupt was configured to be higher priority than
the event timer interrupt (i.e. it can preempt it) which is problematic if:
- There is a scheduled deadline soon after a "clksrc_high / .le.hi" boundary
- An earlier (before the clksrc_high rollover) event timer interrupt kicks in
- After the event timer interrupt handler gets to "now = get_time()"
in common/timer.c:process_timers() the rollover interrupt triggers
incrementing clksrc_high (i.e. the overflow case)
- The rollover interrupt handler arms the event timer to trigger at
that deadline (mentioned in the first bullet) and returns
- The original event timer interrupt handler resumes execution but finds
no events to schedule since the "timer_deadline[tskid].le.hi == now.le.hi"
clause won't evaluate to true. It will then call __hw_clock_event_clear()
before returning causing a watchdog timeout
This commit also contains a fix to properly initialize the HW timer
after a sysjump.
BRANCH=none
BUG=none
TEST=Reproduced both races and successfully tested the fix. The workload I was
using to reproduce (typically within an hour) has been running smoothly
for the past 24 hours.
Change-Id: Ic0b0958e66e701b52481fcfe506745ca1c892dd1
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347465
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the AP or EC is off, the RX line is low. Holding the UART RX line
low causes an interrupt storm. This change disables the UART TX and RX
on the peripheral when the device is powered off so the interrupts wont
be triggered.
BUG=chrome-os-partner:53514,b:28885578
BRANCH=none
TEST=run taskinfo on cr50 and make sure the IRQ count for 181 is a
reasonable number.
Change-Id: I42c779253860a2b1dd27ab41fb7097c887cc23ff
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347355
Use the power and servo connection states to enable and disable the
EC and AP UART output. Contention between the cr50 and servo
can prevent either uart from working, and possibly damage kevin or
servo. If both UARTs are enabled, then cr50 cant know if servo is
connected, so it is best if the UARTs are disabled before connecting
servo.
If servo is connected or if a device is not powered on then the UART
output wont be enabled. The two UARTs are enabled separately and one can
be enabled without the other. Any disabled UART will be monitored for a
servo connection. If servo is detected, then all UARTs will be disabled.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=manual
Power on the EC only. Check only the EC UART is enabled.
Without disabling the uarts power on the AP and verify both are
now enabled.
Turn of the AP. run 'uart enable. Verify only the EC UART is
enabled. Then attach servo and check that the AP and EC UART
are disabled.
Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342828
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Only way to set alarm previously was through
rtcalarm command on EC console. Implemented
interface through ectool so that the AP can set
it as well.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=from AP console, run ectool rtcalarm <sec>
Should see [event set 0x02000000] from EC
console in approximately <sec> seconds.
Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347493
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Used #define CONFIG_FLASH_NVMEM to have functions in
/board/tpm2/NVMem.c utlitize on chip Nvmem functions.
On chip NV Memory availability is tied to an internal nvmem
error state which itself only depends on finding at least one
valid partition.
Added nvmem_is_different and nvmem_move functions which were
needed to complete the tpm2 platform interface. In addition,
added unit tests to support these two new functions.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled CONFIG_FLASH_NVMEM and its associated configs. Added
user definitions along with buffer lengths. Added board
specific functions for sha computation and getting user
buffer lengths required by the NvMem module.
This CL does not include calls from cr50/board/tpm2/NVMem.c.
Those calls will be modified in a subsequent CL.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
The only call to any NvMem functions is nvmem_init().
Loaded code and verified via console that it boots
up properly. Also executed 'make runtests', but
that really only tests regression and not the new
board specific changes.
Change-Id: Iddc8d05703707247d26a8f22dca3ac9cc3c6ad1e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345633
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
