Commit Graph

9 Commits

Author SHA1 Message Date
Vadim Bendebury
fab26ee891 cr50: allow using ccprintf() early in the process
Attempts to use ccprinf() before both uart and usb consoles have been
initialized cause the device lock up. Luckily both console channels
are buffered (and usb console buffering is about to be greatly
improved), all what needs to be done is to hold on to the attempts to
start transmit interrupts until hardware has been initialized.

BRANCH=none
BUG=none
TEST=attempts to print something on the console early in the process
     do not cause the device to lock up any more, and the printouts
     show up where expected.

Change-Id: I16cd1fab79bceaf7c2334a955fdb6046d21ed550
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/268379
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
2015-04-30 02:31:07 +00:00
Sheng-Liang Song
bdcc496b30 cr50: added cr50 a1 chip
cr50_a1 is for cr50 Rev A1 chip.

BUG=chrome-os-partner:33432
BRANCH=none
TEST=Compile Only

Change-Id: I5490d1a5b89fa66c8e8b969cff7538a293a7d053
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/259847
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2015-03-20 23:06:53 +00:00
Bill Richardson
02013f6aa3 cr50: Separate ARM core GPIOs from pinmux configuration
This separates the configuration of the ARM core GPIOs from the
routing of internal peripherals to external pins. Both are still
described in the gpio.inc file, but are less dependent on each
other.

BUG=chrome-os-partner:33818
BRANCH=none
TEST=manual

Before this CL, running "sysjump rw" or trying to use more than 8
GPIOs caused hangs and reboots. Now it doesn't.

Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/251015
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2015-02-20 03:00:04 +00:00
Vincent Palatin
1b1c3089af g: implement GPIOs
Add a driver for the GPIO controller.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:33816
TEST=press the push buttons on the board and see the console text
message and the LEDs lighting up.

Change-Id: Idb408fe1c341beb8a97f2047ba6740e0d40cedf5
Reviewed-on: https://chromium-review.googlesource.com/233307
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
2014-12-10 22:14:07 +00:00
Vincent Palatin
a58083c421 cr50: update for 11/20 hardware release
The clock frequency has been update from 26 to 30 Mhz.
Update the register definitions.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make BOARD=cr50
load the software and see the console working.

Change-Id: I7ccb15491f582173d17739c93ea8c94b05925a6d
Reviewed-on: https://chromium-review.googlesource.com/231129
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2014-11-21 02:44:41 +00:00
Bill Richardson
806ba91ea4 Cr50: Update/refactor for new HW release
This is fairly large change set to accomodate a new hardware
release. There are enough differences to require refactoring the
registers.h file. Autogenerated constants are now in gc_regdefs.h
and all constant names begin with GC_, while register names are
defined in registers.h and begin with GR_.

Yes, I know the new header files are wider than 80 chars, but we
agreed that was okay in some cases if it makes them more readable
(see commit 3500c28).

BUG=chrome-os-partner:33423
BRANCH=none
TEST=make buildall -j

Build and run on the development board.

Change-Id: I21bd88c490f4f359ad17b5af9d17d8caca8dc9e4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230513
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
2014-11-18 23:52:08 +00:00
Bill Richardson
f154a8b95d cr50: Update TODO comments with new bug numbers
Just changing comments, no code.

BUG=chrome-os-partner:33432
BRANCH=none
TEST=make buildall -j

Change-Id: Ibffda40bff23a8c685feaef30a85e19157566245
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229860
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2014-11-14 23:56:44 +00:00
Bill Richardson
e28b6184b1 tweak: Allow "rw" command to read AND write memory.
It's really annoying to have to type two different commands. If I
want to read a location and then write it and then read it back
(which often happens when poking at hardware), then this:

  rw 0x40570008
  rw 0x40570008 14
  rw 0x40570008

is much easier to enter than this:

  rw 0x40570008
  ww 0x40570008 14
  rw 0x40570008

The "ww" command is still there, if you're really attached to it.

BUG=none
BRANCH=none
TEST=manual

Tried the example above. It worked.

Change-Id: I2302ed60df3dd3ec2224afa7c32d997bd2468ec1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229660
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2014-11-14 22:47:13 +00:00
Bill Richardson
86c7e2e90a Add initial support for cr50 SoC
The serial console works. Nothing else is implemented yet.

BUG=none
BRANCH=ToT
TEST=make buildall -j

To build,

  make BOARD=cr50 hex

Testing the result requires a development board. I have one. It
works with HW revision m3.dist_20140918_094011

Change-Id: I718d93572d315d13e96ef6f296c3c2796e928e66
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226268
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2014-10-31 22:32:50 +00:00